Light emitting display panel and light emitting display apparatus using the same

Abstract

Disclosed is a light emitting display panel and a light emitting display apparatus using the same, in which a portion of a cathode electrode overlapping a data line is patterned. The light emitting display panel includes a substrate, a first signal line along a first direction of the substrate, a first insulating film covering the first signal line, a second insulating film covering the first insulating film, an anode electrode patterned per pixel, a bank covering an end portion of the anode electrode, a first light emitting layer on the anode electrode disposed at a first side of the bank, a second light emitting layer on the anode electrode disposed at a second side of the bank, a first cathode electrode on the first light emitting layer, and a second cathode electrode on the second light emitting layer, wherein the first cathode electrode and the second cathode electrode are separated from each other on an upper surface of the bank.

Description

Technical Field

[0001] This disclosure relates to a light-emitting display panel and a light-emitting display device using the light-emitting display panel. Background Technology

[0002] A light-emitting display device is a display device that outputs light by using a light-emitting device, and a light-emitting display device includes a light-emitting display panel having a light-emitting device.

[0003] As light-emitting display panels display high resolution and the number of masks used in them decreases, the resistive-capacitive load (RC load) in the panels increases, resulting in image quality degradation due to the deterioration of the charging rate.

[0004] Specifically, when one of the two electrodes constituting the light-emitting device is formed, a parasitic capacitance is generated between the cathode electrode, which is arranged in the form of a plate on the entire light-emitting display panel, and the data line arranged along the first direction of the light-emitting display panel. As a result, the resistive-capacitive load (RC Load) in the data line and the cathode electrode increases, thereby causing image quality degradation. Summary of the Invention

[0005] This disclosure is made in view of the above-mentioned problems, and one object of this disclosure is to provide a light-emitting display panel in which the portion of the cathode electrode overlapping with the data line is patterned, and a light-emitting display device using the light-emitting display panel.

[0006] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a light-emitting display panel comprising: a substrate; a first signal line disposed along a first direction of the substrate and disposed on the substrate; a first insulating film disposed on the substrate and configured to cover the first signal line; a second insulating film configured to cover the first insulating film; an anode electrode disposed on the second insulating film, electrically connected to a driving transistor disposed on the first insulating film, and patterned according to each pixel; a dam portion disposed on the second insulating film while overlapping with the first signal line, and configured to cover the end of the anode electrode; a first light-emitting layer disposed on the anode electrode disposed on a first side of the dam portion relative to the dam portion; a second light-emitting layer disposed on the anode electrode disposed on a second side of the dam portion relative to the dam portion; a first cathode electrode disposed on the first light-emitting layer; and a second cathode electrode disposed on the second light-emitting layer, wherein the first cathode electrode and the second cathode electrode are separated from each other on the upper surface of the dam portion.

[0007] According to another aspect of this disclosure, a light-emitting display device is provided, the light-emitting display device comprising: the aforementioned light-emitting display panel; a data driver configured to provide a data voltage to a data line disposed in the light-emitting display panel; a gating driver configured to provide a gating voltage to a gating line disposed in the light-emitting display panel; and a controller configured to control the data driver and the gating driver.

[0008] In addition to the effects of this disclosure described above, those skilled in the art will clearly understand from the following description of this disclosure the additional purposes of this disclosure. Attached Figure Description

[0009] The above and other objects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A display device according to the present disclosure is illustrated, and Figure 2 An example of a pixel structure applied to a display device according to the present disclosure is shown;

[0011] Figure 3 Four pixels of a light-emitting display panel according to this disclosure are illustrated;

[0012] Figure 4A Examples are shown in the settings. Figure 3 The first panel electrode in the pixel shown;

[0013] Figure 4B Examples are shown in the settings. Figure 3 The second panel electrode in the pixel shown;

[0014] Figure 5 Examples are shown in the settings. Figure 3 The third panel electrode in the pixel shown;

[0015] Figure 6 Examples are shown in the settings. Figure 3 The separators in the pixels shown;

[0016] Figure 7 An example is shown of a cathode electrode disposed in a light-emitting display panel according to the present disclosure;

[0017] Figure 8 An example is shown of two pixels arranged in a light-emitting display panel according to the present disclosure;

[0018] Figure 9 It is along Figure 3 and Figure 8 The cross-sectional view of I-I' shown;

[0019] Figures 10A to 10F Examples are shown for manufacturing Figure 9 The method for displaying a light-emitting panel shown;

[0020] Figure 11 An example of a light-emitting display panel according to another embodiment of the present disclosure is shown; and

[0021] Figures 12A to 12D Examples are shown for manufacturing Figure 11 The method for displaying a light-emitting panel as shown. Detailed Implementation

[0022] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following description of embodiments in conjunction with the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0023] The shapes, dimensions, scales, angles, and quantities disclosed in the drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the essence of this disclosure. Where the terms “comprising,” “having,” and “including” are used in this specification, another component may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0024] When interpreting a component, although there is no explicit description, the component is interpreted as including a range of error.

[0025] When describing positional relationships, for example, when the positional relationship is described as “~above,” “~above,” “~below,” and “~side,” one or more parts may be arranged between two other parts unless “exactly” or “directly” is used.

[0026] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “exactly” or “directly” is used.

[0027] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0028] It should be understood that the term "at least one" includes all combinations relating to any one of them. For example, "at least one of the first element, the second element, and the third element" can include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0029] The features of the various embodiments of this disclosure may be connected or combined with each other in part or in whole, and may interoperate with and be technically driven by each other in various ways, as will be fully understood by those skilled in the art. The embodiments of this disclosure may be performed independently of each other or together in an interdependent relationship.

[0030] In the following, a display panel and a display device using the same, according to the present disclosure, will be described in detail with reference to the accompanying drawings. In the drawings, even when depicted in different figures, the same or similar elements are indicated by the same reference numerals.

[0031] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 An example of a display device according to the present disclosure is shown. Figure 2 An example of a pixel structure applied to a display device according to the present disclosure is shown.

[0033] The light-emitting display device according to this disclosure can be configured into various electronic devices. For example, the electronic device can be a smartphone, tablet computer, television, monitor, etc.

[0034] like Figure 1 As shown, the display device according to this disclosure includes: a light-emitting display panel 100, the light-emitting display panel 100 including a display area 120 configured to output an image and a non-display area 130 disposed around the display area; a gating driver 200 configured to provide gating signals to gating lines GL1 to GLg disposed in the display area of ​​the light-emitting display panel 100; a data driver 300 configured to provide data voltages to data lines DL1 to DLd disposed in the display panel; and a controller 400 configured to control the operation of each of the gating driver 200 and the data driver 300.

[0035] The light-emitting display panel 100 includes a display area 120 and a non-display area 130. In the display area 120, there are gate lines GL1 to Glg, data lines DL1 to DLd, and pixels 110.

[0036] like Figure 2As shown, the pixel 110 disposed in the light-emitting display panel 100 may include a light-emitting device ED, a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2. The pixel 110 includes a pixel driving circuit PDC and a light-emitting portion, and the pixel driving circuit PDC may include the switching transistor Tsw1, the storage capacitor Cst, the driving transistor Tdr, and the sensing transistor Tsw2. Furthermore, the light-emitting portion may include the light-emitting device ED.

[0037] The light-emitting device ED may include any one of an organic light-emitting layer, an inorganic light-emitting layer, and a quantum dot light-emitting layer. Alternatively, the light-emitting device ED may include a laminate or hybrid structure of an organic light-emitting layer (or an inorganic light-emitting layer) and a quantum dot light-emitting layer.

[0038] The switching transistor Tsw1, constituting the pixel driving circuit PDC, can be turned on or off by the gating signal GS provided to the gating line GL. When the switching transistor Tsw1 is on, the data voltage Vdata supplied through the data line DL is provided to the driving transistor Tdr. The first voltage EVDD can be provided to the driving transistor Tdr and the light-emitting device ED through the first voltage supply line PLA. Furthermore, the second voltage EVSS is provided to the light-emitting device ED through the second voltage supply line PLB. The sensing transistor Tsw2 can be turned on or off by the sensing control signal SS provided through the sensing control line SCL. Furthermore, the sensing line SL can be connected to the sensing transistor Tsw2. The reference voltage Vref can be provided to the pixel 110 through the sensing line SL. Sensing signals related to changes in the characteristics of the driving transistor Tdr can be transmitted to the sensing line SL through the sensing transistor Tsw2.

[0039] Although the light-emitting display panel according to this disclosure can be formed as Figure 2 The structure shown is not limited thereto. Therefore, in addition to Figure 2 In addition to the structure shown, the light-emitting display panel according to this disclosure can be changed in various types.

[0040] The light-emitting display panel 100 can form a pixel region in which pixels 110 are formed. In the light-emitting display panel 100, there are signal lines configured to provide various signals to the pixel driving circuit PDC disposed in the pixels 110 of the pixel region.

[0041] For example, in a light-emitting display panel including pixel 110, the signal lines may include a gating line GL, a data line DL, a sensing control line SCL, a first voltage supply line PLA, a second voltage supply line PLB, and a sensing line SL.

[0042] The data driver 300 can be disposed in an on-film chip attached to the light-emitting display panel 100. Furthermore, the data driver 300 can be connected to a motherboard on which the controller 400 is disposed. In this case, the wiring for electrically connecting the controller 400 / data driver 300 and the light-emitting display panel 100 can be disposed in the on-film chip. For this purpose, the wiring is electrically connected to pads disposed in the light-emitting display panel 100 and the motherboard. The motherboard is electrically connected to an external substrate on which an external system is mounted.

[0043] The data drive 300 can be directly installed on the light-emitting display panel 100 and can be electrically connected to the motherboard.

[0044] However, the data driver 300 can be integrated with the controller 400 within a single integrated circuit. Furthermore, this integrated circuit can be disposed on an on-film chip or directly mounted on the light-emitting display panel 100.

[0045] An external system performs the functions of the drive controller 400 and the electronic device. For example, when the electronic device is a smartphone, the external system can receive various voice, image, and text information via a wireless communication network and transmit the received image information to the controller 400. The image information can be input image data.

[0046] The data driver 300 can receive sensing signals related to changes in the characteristics of the driving transistor Tdr disposed in the light-emitting display panel from the light-emitting display panel, and can transmit the sensing signals to the controller 400.

[0047] Next, the gate driver 200 can be constructed of an integrated circuit and can then be integrated within the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 using a gate-in-panel (GIP) method. If the gate-in-panel (GIP) method is used, the transistors constituting the gate driver 200 can be provided in the non-display area 130 using the same process as the transistors disposed in each of the pixels 110 in the display area 120.

[0048] When a gating pulse generated in the gating driver 200 is provided to the gate of a switching transistor Tsw1 or Tsw2 disposed in pixel 110, the switching transistor is turned on. Therefore, light can be output from the pixel. When a gating cutoff signal is provided to the switching transistor Tsw1 or Tsw2, the switching transistor is turned off. Therefore, no light is output from the pixel. The gating signal GS provided to the gating line GL includes a gating pulse and a gating cutoff signal.

[0049] The controller 400 can readjust input image data transmitted from an external system using a timing synchronization signal transmitted from an external system. Additionally, the controller 400 may include: a data aligner configured to provide readjusted image data to the data driver 300; a control signal generator configured to generate a gating control signal GCS and a data control signal DCS using the timing synchronization signal; an input section configured to receive the timing synchronization signal and input image data transmitted from the external system, and to transmit the received timing synchronization signal and input image data to the data aligner and the control signal generator; and an output section configured to output the image data Data generated in the data aligner and the control signals DCS and GCS generated in the control signal generator to the data driver 300 or the gating driver 200.

[0050] The controller 400 may be embedded in or attached to the light-emitting display panel 100. Alternatively, the controller 400 may also perform the function of analyzing touch sensing signals received through the touch panel and sensing the presence and location of a touch.

[0051] In the following text, such as Figure 2 As shown, a light-emitting display panel including a light-emitting device ED is described as an example of a light-emitting display panel according to this disclosure.

[0052] Figure 3 Four pixels of a light-emitting display panel according to this disclosure are illustrated. Figure 4A Examples are shown in the settings. Figure 3 The first panel electrode in the pixel shown. Figure 4B Examples are shown in the settings. Figure 3 The second panel electrode in the pixel shown. Figure 5 Examples are shown in the settings. Figure 3 The third panel electrode in the pixel shown. Figure 6 Examples are shown in the settings. Figure 3 The separators in the pixels shown. Figure 7 An example is shown of a cathode electrode disposed in a light-emitting display panel according to the present disclosure. Figure 8 Two pixels are illustrated in a light-emitting display panel according to the present disclosure. Figure 9 It is along Figure 3 and Figure 8 The cross-sectional view of I-I' shown.

[0053] like Figures 3 to 9As shown, the light-emitting display panel according to this disclosure may include: a substrate 101; a first signal line L1 disposed along a first direction of the substrate 101 and disposed on the first substrate 101; a first insulating film 102 disposed on the substrate 101 and configured to cover the first signal line L1; a second insulating film 103 configured to cover the first insulating film 102; an anode electrode AE ​​disposed on the second insulating film 103, electrically connected to a driving transistor Tdr disposed on the first insulating film 102, and patterned according to each pixel; a dam 104 disposed on the second insulating film 103 while overlapping with the first signal line L1, and configured to cover the end of the anode electrode AE; a first light-emitting layer EL1 disposed on the anode electrode AE ​​disposed on a first side of the dam 104; a second light-emitting layer EL2 disposed on the anode electrode AE ​​disposed on a second side of the dam 104; a first cathode electrode CE1 disposed on the first light-emitting layer EL1; and a second cathode electrode CE2 disposed on the second light-emitting layer EL2. The first cathode electrode CE1 and the second cathode electrode CE2 can be disposed on the upper surface of the embankment 104 while being separated from each other.

[0054] The light-emitting display panel according to this disclosure may include a plurality of pixels 110. (See reference...) Figure 3 The diagram shows the four pixels that make up a unit pixel: a red pixel (R), a blue pixel (B), a white pixel (W), and a green pixel (G).

[0055] Each pixel may include a pixel driving circuit (PDC) and a light-emitting portion (EU). (See reference...) Figure 2 In response to Figure 3 In the pixel driving circuit PDC of each pixel shown, there is a switching transistor Tsw1, a driving transistor Tdr, and a sensing transistor Tsw2. In this case, the light-emitting portion EU can be formed by a light-emitting device ED, and the light-emitting device ED can be formed by an organic light-emitting diode, but is not limited to this type. For example, the light-emitting device can be formed by an inorganic light-emitting diode.

[0056] In each pixel, there are signal lines configured to provide various signals to the pixel driving circuit PDC. For example, a light-emitting display panel may include a data line DL, a gating line GL, a first driving voltage line PLA, a sensing line SL, and a sensing control line SCL.

[0057] The first signal line L1 can be any one of the signal lines disposed in the light-emitting display panel 100 along a first direction (e.g., the vertical direction). For example, each of the data line DL, the first driving voltage line PLA, and the sensing line SL can be the first signal line L1.

[0058] Furthermore, the second signal line L2 can be any one of the signal lines in the light-emitting display panel 100 that is disposed along a second direction (different from the first direction) of the light-emitting display panel 100. The second direction can be a horizontal direction perpendicular to the first direction. For example, each of the gate line GL and the sensing control line SCL can be the second signal line L2.

[0059] This disclosure can be implemented by patterning the cathode electrode CE in the region where the first signal line L1 and the cathode electrode CE overlap.

[0060] Among the first signal lines that overlap with the cathode electrode CE, the data line DL may be significantly affected by the overlap with the cathode electrode CE. Because the data line DL overlaps with the cathode electrode CE, parasitic capacitance may be generated between the data line DL and the cathode electrode CE. This parasitic capacitance may create a resistive-capacitive load (RC Load) in the data line DL and the cathode electrode CE, resulting in image quality defects in the light-emitting display panel 100.

[0061] In the following description, a light-emitting display panel in which the data line DL, the first driving voltage line PLA, and the sensing line SL are used as the first signal line L1 is described as an example of this disclosure.

[0062] The substrate 101 can be a glass substrate or a plastic substrate, and can be formed from various films.

[0063] like Figure 4A As shown, a first panel electrode can be formed on the substrate 101. Some of the first panel electrodes can be data lines DL used as first signal lines L1. The first signal line L1, as one of the first panel electrodes, is... Figure 4A As shown in the figure, the first signal line L1 can be the data line DL.

[0064] The data voltage Vdata generated from the data driver 300 can be supplied to the data line DL. The data voltage Vdata can also be supplied to transistors configured in the pixel driving circuit. For example, as... Figure 2 As shown, the data voltage Vdata can be supplied to the switching transistor Tsw1.

[0065] The first signal line L1 can be disposed in a first direction of the substrate 101. For example, the first signal line L1 can be along... Figure 1 The vertical orientation of the luminous display panel shown.

[0066] The first signal line L1 can be covered by the first insulating film 102.

[0067] The first insulating film 102 may include a buffer portion that contacts the first signal line L1 and a gate insulating film that covers the buffer portion.

[0068] The buffer portion can be disposed on the substrate 101 and can be disposed over the entire display area of ​​the substrate 101.

[0069] A gate insulating film can be formed on the upper surface of the buffer portion. The gate insulating film insulates the active layer of the driving transistor Tdr disposed in the pixel driving circuit PDC from the gate of the driving transistor Tdr disposed in the pixel driving circuit PDC. The gate insulating film can be configured to cover the active layer on the buffer portion. Furthermore, the gate of the driving transistor Tdr can be disposed on the gate insulating film.

[0070] The buffer layer may be formed of at least one inorganic membrane or at least one organic membrane. Alternatively, the buffer layer may be formed by stacking at least one inorganic membrane and at least one organic membrane.

[0071] The gate insulating film can be formed of at least one inorganic film or at least one organic film. Alternatively, the gate insulating film can be formed by stacking at least one inorganic film and at least one organic film. Figure 4B As shown, a second panel electrode can be formed on the first insulating film 102. The second panel electrode can be a second signal line L2, and the second signal line L2 can be a gate line GL or a sensing control line SCL.

[0072] The second insulating film 103 can cover the first insulating film 102 and the second panel electrode.

[0073] The second insulating film 103 may include a protective film configured to insulate the second panel wires from other metal wires, and a planarization film configured to planarize the upper surface of the protective film.

[0074] For example, various transistors and signal lines constituting the pixel driving circuit PDC can be disposed between the first insulating film 102 and the second insulating film 103. In this case, the various transistors and signal lines can have different thicknesses, and the thickness of the area where transistors and signal lines are disposed can be different from the thickness of the area where transistors and signal lines are not disposed.

[0075] Due to step differences, the upper surface formed by transistors and signal lines may be uneven. Therefore, the upper surface of the protective film covering transistors and signal lines may also be uneven.

[0076] A planarization film is formed on the upper surface of the protective film and is configured to planarize the uneven upper surface. The planarization film is configured to have a height greater than that of the protective film.

[0077] The protective film can be formed from at least one inorganic film.

[0078] The planarization membrane can be formed from at least one organic membrane or can be formed as a stacked structure of at least one inorganic membrane and at least one organic membrane.

[0079] like Figure 5 As shown, a third panel electrode can be formed on the second insulating film 103. Some of the third panel electrodes can form the anode electrode AE ​​of the light-emitting portion EU.

[0080] For example, the anode electrode AE ​​can be disposed on the second insulating film 103. Furthermore, the anode electrode AE ​​can be electrically connected to the driving transistor Tdr disposed on the substrate. And, the anode electrode AE ​​can be patterned for each pixel.

[0081] The anode electrode AE ​​can be one of the two electrodes constituting the light-emitting device ED. For example, if the light-emitting device ED is an organic light-emitting diode (OLED), the OLED may include a first pixel electrode, a light-emitting layer disposed on the upper surface of the first pixel electrode, and a second pixel electrode disposed on the upper end of the light-emitting layer. The first pixel electrode can be the anode electrode AE, and the second pixel electrode can be the cathode electrode CE. In this case, the anode electrode AE ​​is connected to the driving transistor Tdr.

[0082] The anode electrode AE ​​disposed on the second insulating film 103 can be electrically connected to the transistor disposed on the first insulating film 102. For example, the anode electrode AE ​​can be electrically connected to the driving transistor Tdr.

[0083] The anode electrode AE ​​can be formed from a transparent electrode of ITO or IZO, or from an opaque electrode of copper (Cu). The anode electrode AE ​​can be formed as a stacked structure of transparent and opaque electrodes.

[0084] The anode electrode AE ​​can be covered by the dam 104, which is configured to form an opening through which light output passes.

[0085] A retaining wall 104 is disposed on the second insulating film 103 and may overlap with the first signal line L1. For example, the retaining wall 104 may overlap with the first signal line L1, with the second insulating film 103 inserted therebetween. Figure 8 As shown, the embankment 104 covers the end of the anode electrode AE.

[0086] The dam 104 covers the end of the anode electrode AE, and the dam 104 includes an opening configured to expose the upper surface of the anode electrode AE. Furthermore, the dam 104 can be disposed on the display area of ​​the substrate 101. Moreover, the dam 104 can be disposed over the entire display area. The dam 104 can prevent light from overlapping between adjacent pixels.

[0087] The embankment 104 may be formed of at least one inorganic membrane or at least one organic membrane. Alternatively, the embankment 104 may be formed by stacking at least one inorganic membrane and at least one organic membrane.

[0088] Relative to the embankment 104, a first light-emitting layer EL1 can be disposed on an anode electrode AE ​​disposed on a first side of the embankment 104. Furthermore, relative to the embankment 104, a second light-emitting layer EL2 can be disposed on an anode electrode AE ​​disposed on a second side of the embankment 104. The first side of the embankment 104 can be the left side of the embankment 104, and the second side of the embankment 104 can be the right side of the embankment 104.

[0089] For example, refer to Figure 9 The first light-emitting layer EL1 can be disposed on the left side of the embankment 104, and the second light-emitting layer EL2 can be disposed on the right side of the embankment 104.

[0090] The first luminescent layer EL1 and the second luminescent layer EL2 can be formed of the same material. Each of the first luminescent layer EL1 and the second luminescent layer EL2 may include any one of an organic luminescent layer, an inorganic luminescent layer, and a quantum dot luminescent layer. Alternatively, each of the first luminescent layer EL1 and the second luminescent layer EL2 may have a deposited or stacked structure of an organic luminescent layer (or an inorganic luminescent layer) and a quantum dot luminescent layer.

[0091] The first cathode electrode CE1 can be disposed on the first light-emitting layer EL1, and the second cathode electrode CE2 can be disposed on the second light-emitting layer EL2.

[0092] The first cathode electrode CE1 and the second cathode electrode CE2 can be formed from the same material. For example, the first cathode electrode CE1 and the second cathode electrode CE2 can be formed from transparent electrodes such as ITO and IZO, and can be formed from opaque electrodes such as copper (Cu). Alternatively, the first cathode electrode CE1 and the second cathode electrode CE2 can be formed as a stacked structure of transparent and opaque electrodes.

[0093] In this invention, the first cathode electrode CE1 and the second cathode electrode CE2 are separated from each other on the embankment 104.

[0094] like Figure 6 , Figure 8 and Figure 9 As shown, a separator 105 can be additionally provided while overlapping with the first signal line L1. The first light-emitting layer EL1 and the first cathode electrode CE1 are separated from the second light-emitting layer EL2 and the second cathode electrode CE2 by the separator 105 on the upper surface of the embankment 104.

[0095] Therefore, a cathode electrode CE is not disposed in the area on the upper surface of the embankment 104 that overlaps with the first signal line L1. (Refer to...) Figure 9 The first cathode electrode CE1 and the second cathode electrode CE2 can be spaced apart from each other on the embankment 104 so as not to overlap with the first signal line L1.

[0096] Therefore, on the upper surface of the embankment 104, no parasitic capacitance due to the overlap of the first signal line L1 and the cathode electrode CE will be generated in the region where it overlaps with the first signal line L1. Thus, the RC load of the cathode voltage transmitted along the cathode electrode CE or the data voltage Vdata transmitted along the data line DL corresponding to the first signal line L1 can be reduced. The cathode voltage can be the second voltage EVSS supplied to the light-emitting device ED via the second voltage supply line PLB.

[0097] Since the cathode electrodes CE are spaced apart from each other on the upper surface of the embankment 104 to avoid overlapping with the first signal line L1, the RC load of the data line DL or the cathode electrode CE in the light-emitting display panel according to the present invention can be reduced compared to the RC load of the data line DL or the cathode electrode CE in the prior art display panel where the first signal line L1 overlaps with the cathode electrode. Therefore, in the present invention, the degradation of image quality of the light-emitting display panel due to RC load can be reduced.

[0098] As described above, the RC load increases with higher resolution and reduced mask size, potentially leading to a decrease in charging rate in existing display panels. Therefore, image quality defects due to the increased RC load may occur in existing display panels.

[0099] For example, the RC load increases due to the parasitic capacitance generated between the cathode electrode CE disposed on the upper surface of the embankment 104 and the data line DL overlapping with the cathode electrode CE. To prevent this, it is necessary to reduce the overlap area between the data line and the cathode electrode.

[0100] Therefore, in this invention, a cathode electrode CE is not disposed in the region on the upper surface of the embankment 104 that overlaps with the first signal line L1. For example, the cathode electrodes CE can be spaced apart from each other so that the cathode electrodes CE do not overlap with the first signal line L1 on the upper surface of the embankment 104.

[0101] Furthermore, in this invention, the light-emitting layers can be separated by separators 105 in the region where they overlap with the first signal line L1 on the upper surface of the embankment 104. For example, the light-emitting layers can be configured to be spaced apart by separators 105 overlapping with the first signal line L1 on the embankment 104. (See also...) Figure 9In the case of the light-emitting layer, the first light-emitting layer EL1 disposed on the anode electrode AE ​​on the first side of the embankment 104 and the second light-emitting layer EL2 disposed on the anode electrode AE ​​on the second side of the embankment 104 can be separated by using the separator 105.

[0102] Therefore, no leakage current flows from the first light-emitting layer EL1 into the second light-emitting layer EL2. Furthermore, no leakage current flows from the second light-emitting layer EL2 into the first light-emitting layer EL1. In this invention, no leakage current flows through the light-emitting layers into adjacent pixels. Therefore, the brightness of the light output from each pixel is not affected by adjacent pixels.

[0103] Reference Figure 9 The first cathode electrode CE1, the first transverse surface of the separator 105 on the first side, the second transverse surface of the separator 105 on the second side, the upper surface of the embankment 104 exposed between the first cathode electrode CE1 and the separator 105, the upper surface of the embankment 104 exposed between the second cathode electrode CE2 and the separator 105, and the second cathode electrode CE2 may be covered by the third insulating film 106.

[0104] In this case, the third insulating film 106 may not be formed on the upper end of the first lateral surface of the separator 105, the upper end of the second lateral surface of the separator 105, and the upper surface of the separator 105. Therefore, the upper end of the first lateral surface of the separator 105, the upper end of the second lateral surface of the separator 105, and the upper surface of the separator 105 are not covered by the third insulating film 106.

[0105] The width of the upper surface of the separator 105 can be greater than the width of the lower surface of the separator 105. When the width of the upper surface of the separator 105 is greater than the width of the lower surface of the separator 105, the first light-emitting layer EL1 and the first cathode electrode CE1 disposed on the first side can be easily separated from the second light-emitting layer EL2 and the second cathode electrode CE2 disposed on the second side by using the separator 105.

[0106] The third insulating film 106 can be covered by the encapsulation film 107. For example... Figure 9 As shown, the encapsulation film 107 can be formed such that the upper region of the first lateral surface of the separator 105, the upper region of the second lateral surface of the separator 105, and the upper surface of the separator 105 can be exposed. Furthermore, the encapsulation film 107 can cover the third insulating film 106. This shape can be formed by simultaneously etching the third insulating film 106 and the encapsulation film 107 during the manufacturing process of the light-emitting display panel. This will be referred to below. Figures 10A to 10F It is described in the manufacturing process specification.

[0107] The third insulating film 106, the encapsulation film 107, and the separator 105 may be covered by the fourth insulating film 108.

[0108] Each of the third insulating film 106, the encapsulation film 107, and the fourth insulating film 108 may be formed of at least one inorganic film or at least one organic film. Alternatively, each of the third insulating film 106, the encapsulation film 107, and the fourth insulating film 108 may be formed as a laminated structure of at least one inorganic film and at least one organic film.

[0109] like Figure 6 and Figure 8 As shown, the separator 105 can extend in the first direction. Figure 6 Examples are shown in the settings. Figure 3 The separators in the pixels shown.

[0110] The cathode electrode CE can be spaced apart from the spacer 105. For example, the first cathode electrode CE1 is disposed on the upper surface of the dam 104 and configured to be spaced apart from the first transverse surface of the spacer 105. Therefore, the upper surface of the dam 104 located between the first cathode electrode CE1 and the first transverse surface of the spacer 105 can be exposed. Furthermore, the exposed upper surface of the dam 104 is covered by a third insulating film 106. The second cathode electrode CE2 is disposed on the upper surface of the dam 104 and configured to be spaced apart from the second transverse surface of the spacer 105. Therefore, the upper surface of the dam 104 located between the second cathode electrode CE2 and the second transverse surface of the spacer 105 can be exposed. Furthermore, the exposed upper surface of the dam 104 is covered by a third insulating film 106. Therefore, as... Figure 7 As shown, the cathode electrodes CE disposed over the entire display area of ​​the light-emitting display panel can be patterned to be spaced apart from each other on the embankment 104. For example, the cathode electrodes CE formed in the display area of ​​the substrate can be patterned to be spaced apart from each other relative to the spacers 105 disposed in the embankment 104.

[0111] like Figure 7 As shown, the cathode electrode hole HCE can be formed in the portion of the cathode electrode CE corresponding to the spacer 105. The cathode electrode hole HCE overlaps with the spacer 105.

[0112] The separator 105 may overlap with the first signal line L1. For example, the separator 105 may overlap with the data line DL. Therefore, the cathode electrode hole HCE may overlap with the data line DL.

[0113] Figures 10A to 10F This is an example used in manufacturing Figure 9 An example diagram of a method for using a light-emitting display panel is shown. In the following description, descriptions of references are omitted or briefly omitted. Figures 1 to 9 The content described is the same or similar.

[0114] like Figure 10A As shown, a first signal line L1 (i.e., data line DL) is disposed on a substrate 101. The first signal line L1 is covered by a first insulating film 102. The first insulating film 102 is covered by a second insulating film 103. An anode electrode AE ​​is patterned on the second insulating film 103, and the end of the anode electrode AE ​​is covered by a dam 104.

[0115] The embankment 104 is formed on the second insulating film 103 and is configured to overlap with the first signal line L1.

[0116] The separator 105 is formed on the upper surface of the embankment 104 in the area where it overlaps with the first signal line L1.

[0117] Then, the material of the light-emitting layer configured to form the first light-emitting layer EL1 and the second light-emitting layer EL2 is disposed on the entire surface of the substrate 101 to cover the anode electrode AE1, the embankment 104 and the separator 105.

[0118] In this case, as described above, since the width of the upper surface of the separator 105 is greater than the width of the lower surface of the separator 105, such as Figure 10B As shown, the light-emitting layer material disposed on the upper surface of the separator 105 and the light-emitting layer material disposed on the upper surface of the embankment 104 can be separated from each other. Therefore, the first light-emitting layer EL1 and the second light-emitting layer EL2 are spaced apart from each other, and the separator 105 is located therebetween.

[0119] The cathode metal used to form the first cathode electrode CE1 and the second cathode electrode CE2 is disposed on the entire upper surface of the light-emitting layer material.

[0120] In this case, the principle is the same as that described above regarding the material of the light-emitting layer, such as... Figure 10B As shown, the cathode metal disposed on the upper surface of the separator 105 and the cathode metal disposed on the upper surface of the embankment 104 can be separated from each other. Therefore, the first cathode electrode CE1 and the second cathode electrode CE2 are spaced apart from each other, and the separator 105 is located therebetween.

[0121] Next, as Figure 10C As shown, the upper surfaces of the first cathode electrode CE1, the separator 105, and the embankment 104 exposed between the first cathode electrode CE1 and the separator 105, the upper surface of the embankment 104 exposed between the second cathode electrode CE2 and the separator 105, and the second cathode electrode CE2 are covered by a third insulating film 106.

[0122] Then, as Figure 10D As shown, the third insulating film 106 is covered by the encapsulation film 107.

[0123] Next, as Figure 10E As shown, a portion of the encapsulation layer 107 can be etched using a first etching process employing a mask and dry etching, thereby exposing the third insulating film 106 disposed on the upper surface of the separator 105. A halftone mask can be used in the first etching process.

[0124] Then, as Figure 10F As shown, the third insulating film 106 disposed on the upper surface of the separator 105, the upper end of the first lateral surface of the separator 105, and the upper end of the second lateral surface of the separator 105 can be etched using a second etching process employing a mask and dry etching, and the upper surface of the encapsulation layer 107 can also be etched. A halftone mask can be used in the second etching process.

[0125] Through a second etching process, such as Figure 9 and Figure 10F As shown, portions of the third insulating film 106 disposed on the first and second lateral surfaces of the separator 105 can be formed in a shape exposed through the encapsulation layer 107.

[0126] Finally, as the third insulating film 106, the encapsulation layer 107, and the separator 105 are covered by the fourth insulating film 108, a structure with the following characteristics can be manufactured: Figure 9 The cross-section shown is of a light-emitting display panel.

[0127] Figure 11 This is a cross-sectional view of another light-emitting display panel according to another embodiment of the present invention, and more specifically, Figure 11 Another light-emitting display panel according to the present invention is shown in conjunction with... Figure 3 The I-I' line or Figure 8 The cross section in the direction corresponding to line I-I'. In the following description, with reference to... Figures 1 to 10F Content that is identical or similar to the description is omitted or briefly described.

[0128] For reference Figures 1 to 10FThe light-emitting display panel according to this disclosure includes: a substrate 101; a first signal line L1 disposed on the substrate 101 and disposed along a first direction of the substrate 101; a first insulating film 102 disposed on the substrate 101 and configured to cover the first signal line L1; a second insulating film 103 configured to cover the first insulating film 102; an anode electrode AE ​​disposed on the second insulating film 103, electrically connected to a driving transistor Tdr disposed in the first insulating film 102 and patterned according to each pixel; and a dam 104. It is disposed on the second insulating film 103 while overlapping with the first signal line L1, and is configured to cover the end of the anode electrode AE; a first light-emitting layer EL1 is disposed on the anode electrode AE ​​disposed on the first side of the dam 104 relative to the dam 104; a second light-emitting layer EL2 is disposed on the anode electrode AE ​​disposed on the second side of the dam 104 relative to the dam 104; a first cathode electrode CE1 is disposed on the first light-emitting layer EL1; and a second cathode electrode CE2 is disposed on the second light-emitting layer EL2.

[0129] In this case, such as Figure 9 and Figure 11 As shown, the first cathode electrode CE1 and the second cathode electrode CE2 are separated from each other on the upper surface of the embankment 104.

[0130] like Figure 9 and Figure 11 As shown, the first light-emitting layer EL1 and the first cathode electrode CE1 are also separated from the second light-emitting layer EL2 and the second cathode electrode CE2 on the upper surface of the embankment 104.

[0131] The first cathode electrode CE1 and the second cathode electrode CE2 are covered by a third insulating film 106. The third insulating film 106 can be formed of at least one inorganic film or at least one organic film, and can be formed of at least one inorganic film and at least one organic film. Figure 9 and Figure 11 As shown, the third insulating film 106 is separated from each other on the upper surface of the embankment 104.

[0132] The third insulating film 106 is covered by the encapsulation layer 107. The encapsulation layer 107 can be formed of at least one inorganic film or at least one organic film, and can be formed of at least one inorganic film and at least one organic film. Figure 9 and Figure 11 As shown, the encapsulation layers 107 are separated from each other on the upper surface of the embankment 104.

[0133] Therefore, as Figure 11As shown, on the upper surface of the embankment 104, there is a separation hole DH formed by a separate encapsulation film 107, a separate third insulating film 106, a first cathode electrode CE1, a second cathode electrode CE2, a first light-emitting layer EL1, and a second light-emitting layer EL2.

[0134] In this case, the exposed surface of the upper surface of the embankment 104 exposed by the encapsulation film 107 and the encapsulation film 107 are covered by the fourth insulating film 108.

[0135] In other words, the fourth insulating film 108 covers the upper surface of the encapsulation film 107 and the separation hole DH. Specifically, the fourth insulating film 108 covers the surfaces exposed by the separation hole DH, such as a portion of the upper surface of the embankment 104, the lateral surface of the first light-emitting layer EL1, the lateral surface of the second light-emitting layer EL2, the lateral surface of the first cathode electrode CE1, the lateral surface of the second cathode electrode CE2, the lateral surface of the third insulating film 106, and the lateral surface of the encapsulation film 107.

[0136] In addition, the fourth insulating film 108 can be disposed on the entire surface of the substrate 101.

[0137] The fourth insulating film 108 may be formed from at least one inorganic film or at least one organic film, and may be formed from at least one inorganic film and at least one organic film.

[0138] The separation hole DH overlaps with the first signal line L1 located at the lower end of the embankment 104.

[0139] The first signal line L1 extends in the first direction. Therefore, the separation aperture DH can extend in the first direction.

[0140] Furthermore, the cathode electrode CE is not formed in the region used for the separation aperture DH. Therefore, as Figure 7 As shown, the cathode electrode CE disposed on the entire substrate 101 of the light-emitting display panel can be patterned.

[0141] In other words, such as Figure 7 As shown, a cathode electrode hole HCE is formed in the region corresponding to the separation hole DH in the cathode electrode CE, as follows. Figure 7 As shown, the cathode electrode hole HCE overlaps with the separation hole DH.

[0142] Furthermore, the separation hole DH overlaps with the first signal line L1 (i.e., the data line DL), thereby the cathode electrode hole HCE overlaps with the data line DL.

[0143] Therefore, a cathode electrode CE is not provided in the area on the upper surface of the embankment 104 that overlaps with the first signal line L1.

[0144] Therefore, no parasitic capacitance caused by the overlap between the first signal line L1 and the cathode electrode CE is generated in the area where the upper surface of the embankment 104 overlaps with the first signal line L1, thereby reducing the RC load of the data voltage Vdata transmitted along the data line DL corresponding to the first signal line L1 or the cathode voltage transmitted along the cathode electrode CE.

[0145] In other words, on the upper surface of the embankment 104, in the area overlapping with the first signal line L1, the first signal line L1 does not overlap with the cathode electrode CE. Therefore, compared to the RC load in each of the data lines DL and cathode electrodes CE in a prior art display panel where the cathode electrode is formed on the upper surface of the embankment 104 and overlaps with the first signal line L1, the RC load in each of the data lines DL and cathode electrodes CE in the light-emitting display panel according to this disclosure can be reduced. Therefore, in this invention, image quality defects caused by RC load can be reduced.

[0146] Furthermore, in this disclosure, the light-emitting layer is separated by the separation hole DH in the region on the upper surface of the dam 104 that overlaps with the first signal line L1. That is, the first light-emitting layer EL1 disposed on the anode electrode AE ​​disposed on the first side of the dam 104 and the second light-emitting layer EL2 disposed on the anode electrode AE ​​disposed on the second side of the dam 104 are separated from each other by the separation hole DH.

[0147] Therefore, no leakage current is generated from the first light-emitting layer EL1 to the second light-emitting layer EL2, and no leakage current is generated from the second light-emitting layer EL2 to the first light-emitting layer EL1. In other words, in this disclosure, no leakage current is generated that is transmitted through the light-emitting layer to adjacent pixels, so the brightness of the light output from each pixel is not affected by adjacent pixels.

[0148] Figures 12A to 12D This is an example used in manufacturing Figure 11 An example diagram of a method for using a light-emitting display panel is shown. In the following description, references are made to... Figures 1 to 11 Content that is identical or similar to the description is omitted or briefly described.

[0149] First, such as Figure 12A As shown, a first signal line L1 (i.e., data line DL1) is provided on a substrate 101. The first signal line L1 is covered by a first insulating film 102. The first insulating film 102 is covered by a second insulating film 103. The anode electrode AE ​​is patterned on the second insulating film 103 and the end of the anode electrode AE ​​is covered by a dam 104.

[0150] The embankment 104 is formed on the second insulating film 103 and is configured to overlap with the first signal line L1.

[0151] Then, as Figure 12B As shown, the light-emitting layer material ELM used to form the first light-emitting layer EL1 and the second light-emitting layer EL2 is disposed on the entire surface of the substrate 101 to cover the anode electrode AE ​​and the embankment 104.

[0152] The cathode metal CM forming the first cathode electrode CE1 and the second cathode electrode CE2 is formed on the entire upper surface of the light-emitting layer material ELM.

[0153] The third insulating film 106 is formed on the entire upper surface of the cathode metal CM.

[0154] The encapsulation film 107 is formed on the entire upper surface of the third insulating film 106.

[0155] Then, as Figure 12C As shown, the encapsulation film 107 corresponding to the upper surface of the embankment 104 is etched to expose the third insulating film 106.

[0156] Next, as Figure 12D As shown, the third insulating film 106, the cathode metal CM, and the light-emitting layer material ELM are etched by dry etching to form a separation hole DH, thereby forming the first light-emitting layer EL1, the second light-emitting layer EL2, the first cathode electrode CE1, and the second cathode electrode CE2. Furthermore, the third insulating film 106 and the encapsulation film 107 are also separated through the separation hole DH.

[0157] Finally, with the fourth insulating film 108 covering the upper surface of the encapsulation film 107 and the separation hole DH, it is possible to manufacture a structure having, as shown in the image, ... Figure 11 The cross-section shown is of a light-emitting display panel.

[0158] According to this disclosure, the region in the cathode electrode that overlaps with the data line is patterned, thereby reducing the parasitic capacitance between the cathode electrode and the data line.

[0159] Therefore, the image quality degradation caused by RC load in the cathode electrode and data line can be reduced in this disclosure.

[0160] The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to one embodiment. Furthermore, those skilled in the art can achieve the features, structures, and effects described in at least one embodiment of this disclosure through combinations or modifications of other embodiments. Therefore, anything associated with combinations and modifications should be understood as being within the scope of this disclosure.

[0161] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover any modifications and variations thereof that fall within the scope of the appended claims and their equivalents.

[0162] Cross-references to related applications

[0163] This application claims the benefit of Korean Patent Application No. 10-2020-0141302, filed on October 28, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A light-emitting display panel, the light-emitting display panel comprising: substrate; A first signal line is disposed along a first direction of the substrate and is disposed on the substrate; A first insulating film is disposed on the substrate and configured to cover the first signal line; A second insulating film, configured to cover the first insulating film; An anode electrode is disposed on the second insulating film, electrically connected to a driving transistor disposed on the first insulating film, and patterned according to each pixel; A dam portion, which overlaps with the first signal line, is disposed on the second insulating film and is configured to cover the end of the anode electrode; A first light-emitting layer is disposed on an anode electrode located on a first side of the embankment relative to the embankment. A second light-emitting layer is disposed on an anode electrode located on a second side of the embankment relative to the embankment. The first cathode electrode is disposed on the first light-emitting layer; The second cathode electrode is disposed on the second light-emitting layer; A separator, which overlaps with the first signal line and is disposed on the upper surface of the embankment. A third insulating film is configured to cover the first cathode electrode, a first lateral surface of the separator disposed on the first side, a second lateral surface of the separator disposed on the second side, an upper surface of the embankment exposed between the first cathode electrode and the separator, an upper surface of the embankment exposed between the second cathode electrode and the separator, and the second cathode electrode. The first light-emitting layer and the first cathode electrode are separated from the second light-emitting layer and the second cathode electrode by the separator on the upper surface of the embankment. The first cathode electrode and the second cathode electrode are separated from each other on the upper surface of the embankment.

2. The light-emitting display panel according to claim 1, wherein, The first signal line is at least one of a data line, a drive voltage line, and a sensing line.

3. The light-emitting display panel according to claim 1, wherein, The width of the upper surface of the separator is greater than the width of the lower surface of the separator.

4. The light-emitting display panel according to claim 3, wherein, The distance between the first cathode electrode and the second cathode electrode is the same as the width of the upper surface of the separator.

5. The light-emitting display panel of claim 1, further comprising an encapsulation film configured to cover the third insulating film to expose a portion of the third insulating film disposed on the first lateral surface of the separator and a portion of the third insulating film disposed on the second lateral surface of the separator.

6. The light-emitting display panel according to claim 5, further comprising a fourth insulating film configured to cover the third insulating film, the encapsulation film, and the separator.

7. The light-emitting display panel according to claim 1, wherein, The separator extends in the first direction.

8. The light-emitting display panel according to claim 1, wherein, The first cathode electrode and the second cathode electrode are spaced apart from the separator.

9. The light-emitting display panel according to claim 1, wherein, The first luminescent layer is separated from the second luminescent layer on the upper surface of the embankment.

10. The light-emitting display panel according to claim 1, further comprising a third insulating film configured to cover the first cathode electrode and the second cathode electrode. in, The third insulating film is separated from each other on the upper surface of the embankment.

11. The light-emitting display panel of claim 10, further comprising an encapsulation film configured to cover the third insulating film, wherein, The encapsulation films are separated from each other on the upper surface of the dike.

12. The light-emitting display panel of claim 11, further comprising a fourth insulating film configured to cover the exposed portion of the upper surface of the embankment exposed by the encapsulation film and the encapsulation film.

13. The light-emitting display panel according to claim 12, wherein, The exposed portion of the upper surface of the embankment overlaps with the first signal line.

14. A light-emitting display panel, the light-emitting display panel comprising: substrate; A first signal line is disposed along a first direction of the substrate and is disposed on the substrate; A first insulating film is disposed on the substrate and configured to cover the first signal line; A second insulating film, configured to cover the first insulating film; An anode electrode is disposed on the second insulating film, electrically connected to a driving transistor disposed on the first insulating film, and patterned according to each pixel; A dam portion, which overlaps with the first signal line, is disposed on the second insulating film and is configured to cover the end of the anode electrode; A first light-emitting layer is disposed on an anode electrode located on a first side of the embankment relative to the embankment. A second light-emitting layer is disposed on an anode electrode located on a second side of the embankment relative to the embankment. A cathode electrode is disposed on the entire substrate and disposed on the first light-emitting layer and the second light-emitting layer, wherein the cathode electrode includes a first cathode electrode and a second cathode electrode, the first cathode electrode is disposed on the first light-emitting layer, the second cathode electrode is disposed on the second light-emitting layer, and the first cathode electrode and the second cathode electrode are patterned to be spaced apart from each other on the embankment; A separator, which overlaps with the first signal line and is disposed on the upper surface of the embankment; A third insulating film is configured to cover the first cathode electrode on the first light-emitting layer and the second cathode electrode on the second light-emitting layer. The third insulating film is separated from each other by the separators on the upper surface of the embankment. The first light-emitting layer and the first cathode electrode are separated from the second light-emitting layer and the second cathode electrode by the separator on the upper surface of the embankment.

15. The light-emitting display panel according to claim 14, wherein, The cathode electrode includes a cathode electrode hole that overlaps with the first signal line.

16. The light-emitting display panel according to claim 15, wherein, The cathode electrode hole overlaps with the separator.

17. The light-emitting display panel according to claim 15, wherein, The cathode electrode hole extends in the first direction.

18. The light-emitting display panel according to claim 15, further comprising: An encapsulation film configured to cover the third insulating film, and A fourth insulating film, configured to cover the encapsulation film, Wherein, the encapsulating films are separated from each other on the upper surface of the dike, and The fourth insulating film is further configured to cover the exposed portion of the upper surface of the embankment that is exposed by the encapsulation film.

19. The light-emitting display panel according to claim 18, wherein, The cathode electrode hole overlaps with the exposed portion of the upper surface of the embankment.

20. A light-emitting display device, the light-emitting display device comprising: The light-emitting display panel according to any one of claims 1 to 19; A data driver configured to provide a data voltage to data lines disposed in the light-emitting display panel; A gating driver configured to provide a gating voltage to a gating line disposed in the light-emitting display panel; as well as A controller configured to control the data driver and the strobe driver.

Images