Display device

Abstract

The present application relates to a display device. The display device includes a data conductive layer disposed on a substrate, a passivation layer disposed on the data conductive layer, a via layer disposed on the passivation layer, and a pixel electrode disposed on the via layer. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data cap layer disposed on the data main metal layer, a second data cap layer disposed on the first data cap layer, and a third data cap layer disposed on the second data cap layer. The passivation layer and the via layer include a pad opening exposing a portion of the data conductive layer in a pad area. The third data cap layer has a higher etching rate than the first data cap layer and the second data cap layer for the same etchant.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] With the development of multimedia technology, display devices have become increasingly important. As a result, various display devices have been developed, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs).

[0003] Meanwhile, the display device includes a display panel capable of displaying images, such as an OLED display panel or an LCD panel. The display panel includes light-emitting elements such as light-emitting diodes (LEDs), and LEDs can be classified into OLEDs, which use organic materials as fluorescent substances, and inorganic LEDs, which use inorganic materials as fluorescent substances. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device including a novel pad electrode structure.

[0005] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of this disclosure.

[0006] According to embodiments of this disclosure, a display device may include: a substrate including a display area and a pad area; a data conductive layer disposed on the substrate; a passivation layer disposed on the data conductive layer; a via layer disposed on the passivation layer; and a pixel electrode disposed on the via layer. The data conductive layer may include: a data base layer; a data main metal layer disposed on the data base layer; a first data capping layer disposed on the data main metal layer; a second data capping layer disposed on the first data capping layer; and a third data capping layer disposed on the second data capping layer. The passivation layer and the via layer may include pad openings that expose a portion of the data conductive layer in the pad area. For the same etchant, the third data capping layer may have a higher etch rate than the first and second data capping layers, and the third data capping layer may include a pad conductive layer that does not overlap with the pad openings.

[0007] In one implementation, for the same etchant, the third data capping layer may have twice the etch rate of the first and second data capping layers.

[0008] In an implementation, the third data capping layer may include copper (Cu) or zinc indium oxide (ZIO).

[0009] In this implementation, the main data metal layer and the third data cover layer may include copper.

[0010] In an implementation, the third data capping layer may have approximately to approximately The thickness is within the range.

[0011] In an implementation, the data base layer and the first data capping layer may comprise the same material, and include at least one of titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and nickel (Ni).

[0012] In one implementation, the data base layer and the first data capping layer may include titanium.

[0013] In an implementation, the second data capping layer may include indium tin oxide (ITO).

[0014] In this implementation, the side surfaces of each of the data base layer, the main metal layer, the first data capping layer, the second data capping layer, and the third data capping layer of the data conductive layer can be aligned with each other.

[0015] In one implementation, the side surface of the passivation layer can be aligned with the corresponding side surface of the pad conductive layer.

[0016] In one implementation, the passivation layer may overlap with the pad conductive layer, and the side surface of the passivation layer protrudes outward beyond the side surface of the pad conductive layer.

[0017] According to embodiments of this disclosure, a display device may include: a substrate including a display area and a pad area; a data conductive layer disposed on the substrate; a passivation layer disposed on the data conductive layer; a via layer disposed on the passivation layer; and a pixel electrode disposed on the via layer. The data conductive layer may include: a data base layer; a data main metal layer disposed on the data base layer; a first data capping layer disposed on the data main metal layer; a second data capping layer disposed on the first data capping layer; and a third data capping layer disposed on the second data capping layer. The passivation layer and via layer may include: a first contact hole penetrating the passivation layer and via layer in the thickness direction to expose a portion of the data conductive layer in the display area; and a pad opening exposing a portion of the data conductive layer in the pad area. The data conductive layer can be divided into a first region overlapping with the passivation layer, a second region overlapping with the first contact hole, and a third region overlapping with the pad opening. A third data capping layer can be disposed in the entire first region and the entire second region of the data conductive layer, and the third data capping layer can include a pad conductive layer that does not overlap with the pad opening in the third region of the data conductive layer.

[0018] In one implementation, the third data capping layer may contact the pixel electrode in the second region of the data conductive layer.

[0019] In an embodiment, the display device may further include: a lower metal layer disposed on a substrate below a first region of the data conductive layer; and at least one insulating layer disposed between the data conductive layer and the lower metal layer.

[0020] In one embodiment, at least one insulating layer may include a contact hole that penetrates at least one insulating layer in the thickness direction to expose the underlying metal layer, and the underlying metal layer may be electrically connected to the data conductive layer through the contact hole.

[0021] In one embodiment, portions of the third data capping layer in the first and second regions of the data conductive layer and portions of the pad conductive layer in the third region of the data conductive layer may comprise the same material.

[0022] In an implementation, for the same etchant, the third data capping layer may have a higher etch rate than the first and second data capping layers.

[0023] In an implementation, the third data capping layer may include copper (Cu) or zinc indium oxide (ZIO).

[0024] In this implementation, the main data metal layer and the third data cover layer may include copper.

[0025] In an implementation, the third data capping layer may have approximately to approximately The thickness is within the range.

[0026] According to the foregoing and other embodiments of this disclosure, since the contour of the data conductive layer is improved by preventing the formation of sharp points in the data conductive layer, cracks in the passivation layer can be prevented.

[0027] Furthermore, since multiple capping layers are formed on the main conductive layer that forms the wiring pads to prevent the main conductive layer from being directly exposed to the etchant, damage to the main conductive layer can be prevented and the reliability of the main conductive layer can be improved.

[0028] Other features and embodiments will be apparent from the following detailed description, drawings and claims. Attached Figure Description

[0029] The above and other embodiments and features of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0030] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present disclosure;

[0031] Figure 2 yes Figure 1 A schematic cross-sectional view of the display device;

[0032] Figure 3 yes Figure 1 A schematic layout diagram of the circuit layer of the first display substrate of the display device;

[0033] Figure 4 yes Figure 1 A schematic equivalent circuit diagram of the pixels of a display device;

[0034] Figure 5 yes Figure 1 A schematic cross-sectional view of the first display substrate of the display device;

[0035] Figure 6 yes Figure 5 A schematic enlarged view of part A;

[0036] Figures 7 to 19 It shows how to manufacture Figure 5 A schematic cross-sectional view of the display device;

[0037] Figure 20 This is a schematic cross-sectional view of a first display substrate of a display device according to another embodiment of the present disclosure;

[0038] Figure 21 It corresponds to Figure 5 A schematic enlarged view of part A;

[0039] Figure 22 It corresponds to Figure 5 A schematic enlarged view of part A;

[0040] Figure 23 It corresponds to Figure 5 A schematic enlarged view of part A;

[0041] Figure 24 Images showing different etch degrees of data conductive layer patterns for different etch durations according to embodiments of the present disclosure;

[0042] Figure 25 An image showing a data conductive layer pattern according to an embodiment of the present disclosure; and

[0043] Figure 26 An image of wiring pads during the etching of a pixel electrode according to an embodiment of the present disclosure is shown. Detailed Implementation

[0044] The present disclosure will now be described more fully below with reference to the accompanying drawings, which illustrate embodiments thereof. However, the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art.

[0045] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on the other layer or substrate, or there may be an intervening layer. Throughout the specification, the same reference numerals indicate the same parts.

[0046] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0047] Each of the features in the various embodiments of this disclosure can be combined with each other, either partially or entirely, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other or can be implemented together in association.

[0048] For the purposes of its meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0049] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this disclosure, and shall not be interpreted in an ideal or overly formal sense unless expressly so defined herein.

[0050] Embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0051] Figure 1 This is a schematic plan view of a display device according to an embodiment.

[0052] refer to Figure 1The display device 1 can be applicable to smartphones, mobile phones, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), televisions (TVs), game consoles, watch-type electronic devices, head-mounted displays (HMDs), PC monitors, laptop computers, car navigation systems, car dashboards, digital cameras, video cameras, external billboards, electronic display panels, medical devices, examination devices, or various household appliances (such as refrigerators or washing machines). In the following description, the display device 1 will be depicted as a TV, for example, having a high resolution or ultra-high resolution (such as high definition (HD), ultra-high definition (UHD), 4K, or 8K).

[0053] Display device 1 can be classified in various ways according to the manner in which it displays images. Display device 1 can be, for example, an organic light-emitting diode (OLED) display device, an inorganic light-emitting diode (LED) display device, a quantum dot emission (QED) display device, a micron-LED display device, a nano-LED display device, a plasma display panel (PDP) device, a field emission display (FED) device, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device, or an electrophoretic display (EPD) device. Hereinafter, display device 1 will be described as, for example, an OLED display device, and OLED display device will be simply referred to as a display device unless otherwise stated. However, this disclosure is not limited thereto, and various other display devices can also be used as display device 1 without departing from the scope of this disclosure.

[0054] In the plan view, the display device 1 can have a quadrilateral shape, such as a rectangular shape. When the display device 1 is a TV, its long side can be arranged horizontally, but this disclosure is not limited thereto. As another example, the long side of the display device 1 can be arranged vertically, or the display device 1 can be rotatably mounted such that its long side can be arranged horizontally or vertically.

[0055] Display device 1 may include a display area DPA and a non-display area NDA. The display area DPA may be an effective area in which an image is displayed. The display area DPA may have a shape similar to that of display device 1 in a plan view, such as a rectangular shape, but this disclosure is not limited thereto.

[0056] The display area DPA may include pixels PX. Pixels PX may be arranged in both row and column directions. Pixels PX may have a rectangular or square shape in a planar view, but this disclosure is not limited thereto. As another example, pixels PX may have a rhomboid shape with sides inclined relative to the sides of the display device 1. Pixels PX may include pixels PX of various colors. In an example, pixels PX may include first-color pixels PX (e.g., red pixels), second-color pixels PX (e.g., green pixels), and third-color pixels PX (e.g., blue pixels). The first-color pixels PX, second-color pixels PX, and third-color pixels PX may be arranged in stripes or... The arrangement is alternating.

[0057] A non-display area NDA may be disposed around a display area DPA. The non-display area NDA may surround at least a portion or the entire display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be disposed adjacent to the four sides of the display area DPA. The non-display area NDA may form the border of the display device 1.

[0058] In the non-display area NDA, a driving circuit or component for driving the display area DPA can be provided. In the example, in the first and second long sides of the display device 1 (e.g., ...), Figure 1 In the first and second non-display areas adjacent to the bottom and top sides of the display device 1, pad portions can be provided on the display substrate, and external devices (EXDs) can be mounted on the pad electrodes of the pad portions. Examples of external devices (EXDs) may include connection films, printed circuit boards (PCBs), driver integrated circuits (DICs), connectors, and wiring connection films. In the example, in the first short side (e.g., the bottom and top sides of the display device 1), pad portions can be provided on the display substrate of the display device 1, and external devices (EXDs) can be mounted on the pad electrodes of the pad portions. Figure 1 In the third non-display area NDA adjacent to the left side of the display device 1, a scan driver SDR can be set. The scan driver SDR can be directly formed on the display substrate of the display device 1.

[0059] Figure 2 yes Figure 1 A schematic cross-sectional view of the display device.

[0060] Figure 2 The display device 1 shown is a top-emitting display device that emits light L in a direction away from the first substrate 110 on which the light-emitting layer EML is formed (e.g., towards the second substrate 210), but this disclosure is not limited thereto. As another example, the display device 1 may be a bottom-emitting display device that emits light L in the direction towards the first substrate 110, or a dual-emitting display device that emits light L in both the direction towards the first substrate 110 and the direction towards the second substrate 210.

[0061] refer to Figure 2 The display device 1 may include a first display substrate 100, a second display substrate 200 facing the first display substrate 100, and a fill layer 300 combining the first display substrate 100 and the second display substrate 200.

[0062] The first display substrate 100 may include a first substrate 110. The first substrate 110 may be an insulating substrate. The first substrate 110 may include a transparent material. In an example, the first substrate 110 may include a transparent insulating material, such as glass or quartz. The first substrate 110 may be a rigid substrate. However, this disclosure is not limited thereto. In an example, the first substrate 110 may include a plastic such as polyimide, or may be flexible (or bendable, foldable, or rollable).

[0063] Pixel electrodes PXE can be disposed on the first substrate 110. Pixel electrodes PXE can be disposed within their respective pixels PX. The pixel electrodes PXE of adjacent pixels PX can be separated from each other. A circuit layer CCL driving the pixels PX can be disposed on the first substrate 110. The circuit layer CCL can be disposed between the first substrate 110 and the pixel electrodes PXE. The circuit layer CCL will be described below.

[0064] The pixel electrode (PXE) can be the first electrode of an LED, such as the anode electrode. The pixel electrode PXE can have a structure in which layers of high work function materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In₂O₃)) and layers of reflective materials (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof) are stacked. The high work function layer can be disposed above the reflective layer and close to the light-emitting layer (EML). The pixel electrode PXE can have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but this disclosure is not limited thereto.

[0065] A pixel defining layer (PDL) may be disposed on the surface of the first substrate 110 along the boundary of each of the pixels (PX). The PDL may be disposed on the pixel electrode (PXE) and may include openings exposing the pixel electrode (PXE). An emitting region (EMA) and a non-emitting region (NEM) may be defined by the PDL and the openings in the PDL. The PDL may comprise an organic insulating material, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The PDL may also comprise an inorganic material.

[0066] The light-emitting layer (EML) can be disposed on the portion of the pixel electrode (PXE) exposed by the pixel-defining layer (PDL). In the case that the display device 1 is an OLED display device, the light-emitting layer (EML) may include an organic layer comprising organic materials. The organic layer may include an organic light-emitting layer, and may also include a hole injection layer, a hole transport layer, an electron transport layer, and / or an electron injection layer as auxiliary layers to aid in light emission. As another example, in the case that the display device 1 is a micron-LED or nanon-LED display device, the light-emitting layer (EML) of the display device 1 may include inorganic materials, such as inorganic semiconductors.

[0067] In some implementations, the emissive layer (EML) may have a tandem structure comprising organic light-emitting layers stacked in the thickness direction and charge-generating layers disposed between the organic light-emitting layers. The organic light-emitting layers may emit light of the same or different wavelengths. At least some of the multiple layers in each of the emissive layers (EML) may be separated from each other between adjacent pixels (PX).

[0068] In this example, the wavelength of light emitted by the emissive layer EML can be the same for each pixel PX. In this example, the emissive layer EML can emit either blue or ultraviolet (UV) light, and the color control structure, as described below, can include a wavelength conversion layer WCL. In this example, different color pixels PX can display different colors.

[0069] In the example, the wavelength of the light emitted by the emissive layer EML can vary from one pixel PX to another. For instance, the emissive layer EML of the first color pixel PX can emit light of the first color, the emissive layer EML of the second color pixel PX can emit light of the second color, and the emissive layer EML of the third color pixel PX can emit light of the third color.

[0070] The common electrode CME can be disposed on the emissive layer EML. The common electrode CME can contact not only the emissive layer EML, but also the top surface of the pixel defining layer PDL.

[0071] The common electrode CME can be connected across multiple pixels PX. The common electrode CME can be a full electrode disposed on the entire surface of the first substrate 110 regardless of the differences between pixels PX. The common electrode CME can be a second electrode of the LED, such as a cathode electrode.

[0072] The common electrode CME may include a layer (or low work function layer) of a low work function material, including materials such as Li, Ca, lithium fluoride (LiF), aluminum (Al), Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, barium fluoride (BaF), barium (Ba), or compounds or mixtures thereof (e.g., mixtures of Ag and Mg), or materials with a multilayer structure such as LiF / Ca or LiF / Al. The common electrode CME may also include a transparent metal oxide layer disposed on the low work function layer.

[0073] A pixel electrode (PXE), an emissive layer (EML), and a common electrode (CME) can form a light-emitting element (e.g., an OLED). Light emitted by the emissive layer (EML) can pass through the common electrode (CME) and be emitted in an upward direction.

[0074] The thin-film encapsulation structure 170 can be disposed on the common electrode CME. The thin-film encapsulation structure 170 may include one or more thin-film encapsulation layers. In an example, the thin-film encapsulation layers may include a first inorganic layer 171, an organic layer 172, and a second inorganic layer 173. The first inorganic layer 171 and the second inorganic layer 173 may include silicon nitride (SiN). x ), silicon oxide (SiO) x ) or silicon nitride oxide (SiO) x N y Organic layer 172 may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, or BCB.

[0075] The second display substrate 200 may be disposed above the thin-film encapsulation structure 170 to face the thin-film encapsulation structure 170. The second substrate 210 of the second display substrate 200 may include a transparent material. The second substrate 210 may include a transparent insulating material, such as glass or quartz. The second substrate 210 may be a rigid substrate. However, this disclosure is not limited thereto. As another example, the second substrate 210 may include a plastic such as polyimide, or may be flexible (or bendable, foldable, or rollable).

[0076] The second substrate 210 and the first substrate 110 can be the same, or the second substrate 210 can differ from the first substrate 110 in terms of material, thickness, and transmittance. In the example, the second substrate 210 can have a higher transmittance than the first substrate 110. The second substrate 210 can be thicker or thinner than the first substrate 110.

[0077] A light-blocking member (BML) may be disposed along the boundary of each of the pixels (PX) on the surface of the second substrate 210 facing the first substrate 110. The light-blocking member (BML) may overlap with the pixel defining layer (PDL) of the first display substrate 100 and may be disposed in the non-emitting region (NEM). The light-blocking member (BML) may include openings that expose portions of the surface of the second substrate 210 that overlap with the emitting region (EMA). The light-blocking member (BML) may be formed in a grid shape in a plan view.

[0078] The light-blocking component (BML) can comprise organic materials. The BML absorbs external light, thereby reducing color distortion that may be caused by reflection of external light. The BML prevents light emitted by the emissive layer (EML) of pixel PX from penetrating into adjacent pixels PX.

[0079] In this example, the light-blocking component BML can absorb light of all visible wavelengths. The light-blocking component BML may include a light-absorbing material. In this example, the light-blocking component BML may be formed of a material that can be used as a black matrix in the display device 1.

[0080] In the example, the light-blocking component BML can absorb light of a specific visible wavelength and allow light of another specific visible wavelength to pass through it. The light-blocking component BML and the color filter layer CFL can comprise the same material. Specifically, the light-blocking component BML and the blue color filter layer (see...) Figure 2 The third color filter layer (CFL3) may include the same material. In some embodiments, the light-blocking member (BML) may be integral with the third color filter layer (CFL3). In some embodiments, the light-blocking member (BML) may not be provided.

[0081] The color filter layer CFL can be disposed on the surface of the second substrate 210 where the light blocking member BML is disposed. The color filter layer CFL can be disposed on the portion of the surface of the second substrate 210 exposed by the opening of the light blocking member BML. The color filter layer CFL can even be disposed on the light blocking member BML.

[0082] The color filter layer CFL may include a first color filter layer CFL1 disposed in a first color pixel PX, a second color filter layer CFL2 disposed in a second color pixel PX, and a third color filter layer CFL3 disposed in a third color pixel PX. The color filter layer CFL may include a colorant, such as a pigment or dye capable of absorbing all wavelengths of light except for a specific specified wavelength (or predetermined wavelength). The first color filter layer CFL1 may be a red (R) color filter layer, the second color filter layer CFL2 may be a green (G) color filter layer, and the third color filter layer CFL3 may be a blue (B) color filter layer. The color filter layers CFL are shown as being disposed on a light-blocking member BML spaced apart from each other, but in embodiments, they may at least partially overlap each other on the light-blocking member BML.

[0083] A first capping layer 220 may be disposed on the color filter layer CFL. The first capping layer 220 can prevent the color filter layer CFL from being damaged or contaminated by external impurities (such as moisture or air). The first capping layer 220 can prevent the colorant of the color filter layer CFL from diffusing into other components.

[0084] The first capping layer 220 can directly contact the surface of the color filter layer CFL (e.g., Figure 2 (The bottom surface of the substrate). The first capping layer 220 may be formed of an inorganic material. In an example, the first capping layer 220 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, or silicon oxynitride.

[0085] The partition wall PTL can be disposed on the first capping layer 220. The partition wall PTL can be disposed in the non-emissive region (NEM). The partition wall PTL can overlap with the light-blocking member (BML). The partition wall PTL can include openings exposing the area overlapping with the color filter layer (CFL). The partition wall PTL can include a photosensitive organic material, but this disclosure is not limited thereto. The partition wall PTL can also include a light-blocking material.

[0086] The wavelength conversion layer (WCL) and the light transmission layer (TPL) can be disposed in the space exposed by the opening of the partition wall (PTL). The wavelength conversion layer (WCL) and the light transmission layer (TPL) can be formed using the partition wall (PTL) as a dam via an inkjet printing process, but this disclosure is not limited thereto.

[0087] When the emissive layer EML of pixel PX emits light of a third color, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 and a second wavelength conversion pattern WCL2 respectively disposed in the first color pixel PX and the second color pixel PX. The light transmission layer TPL may be disposed in the third color pixel PX.

[0088] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 disposed in the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 disposed in the second base resin BRS2. The light transmission layer TPL may include a third base resin BRS3 and a scatterer material (or scatterer) SCP disposed in the third base resin BRS3.

[0089] The first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may comprise transparent organic materials. In examples, the first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may comprise epoxy resin, acrylic resin, cardo resin, or imide resin. The first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may comprise the same materials, but this disclosure is not limited thereto.

[0090] The scattering SCP can be particles of metal oxides or organic materials. The metal oxides can be titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and the organic materials can be acrylic resins or polyurethane resins.

[0091] The first wavelength conversion material WCP1 can be a material that converts a third color into a first color, and the second wavelength conversion material WCP2 can be a material that converts a third color into a second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 can be quantum dots, quantum rods, phosphors, etc. Quantum dots can include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or combinations thereof. The first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 can also include a scatterer SCP.

[0092] A light-transmitting layer (TPL) disposed in the third-color pixel PX allows third-color light incident from the emissive layer (EML) of the third-color pixel PX to pass through it while maintaining the wavelength of the incident light. The scattering component (SCP) of the light-transmitting layer TPL can control the path of the light output through the light-transmitting layer TPL. The light-transmitting layer TPL may not include wavelength conversion material.

[0093] The second capping layer 230 may be disposed on the wavelength conversion layer WCL, the light transmission layer TPL, and the partition wall PTL. The second capping layer 230 may be formed of an inorganic material. The second capping layer 230 may include a material selected from the materials of the aforementioned first capping layer 220. The second capping layer 230 and the first capping layer 220 may be formed of the same material, but this disclosure is not limited thereto.

[0094] A filler layer 300 may be disposed between the first display substrate 100 and the second display substrate 200. The filler layer 300 may fill the space between the first display substrate 100 and the second display substrate 200, and may bond and connect the first display substrate 100 and the second display substrate 200. The filler layer 300 may be disposed between the thin-film encapsulation structure 170 and the second capping layer 230 of the second display substrate 200. The filler layer 300 may be formed of a silicon (Si)-based organic material or an epoxy-based organic material, but this disclosure is not limited thereto.

[0095] The circuit layer CCL of display device 1 will be described below.

[0096] Figure 3 This is a schematic layout diagram of the circuit layer of the first display substrate of the display device according to an embodiment.

[0097] refer to Figure 3 Lines may be disposed on the first substrate 110. The lines may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, and a first power supply line ELVDL.

[0098] The scan line SCL and the sensing signal line SSL can extend on the first direction DR1. The scan line SCL and the sensing signal line SSL can be electrically connected to the scan driver SDR. The scan driver SDR can include driving circuitry formed as a circuit layer CCL. The scan driver SDR can be disposed on the first substrate 110 in a third non-display area NDA, but this disclosure is not limited thereto. As another example, the scan driver SDR can be disposed in a fourth non-display area NDA, or in both the third and fourth non-display areas NDA. The scan driver SDR can be electrically connected to a signal connection line CWL, and at least one end of the signal connection line CWL can form a pad WPD_CW in the first and / or second non-display areas NDA, and can be electrically connected to Figure 1 External device EXD.

[0099] The data line DTL and the reference voltage line RVL may extend along a second direction DR2 intersecting the first direction DR1. The first power line ELVDL may include a portion extending along the second direction DR2. The first power line ELVDL may also include a portion extending along the first direction DR1. The first power line ELVDL may have a mesh structure, but this disclosure is not limited thereto.

[0100] The routing pad WPD can be located at at least one end of each of the data line DTL, the reference voltage line RVL, and the first power line ELVDL. The routing pad WPD can be located in the pad area PDA of the non-display area NDA. The routing pad WPD_DT of the data line DTL (hereinafter referred to as the data pad WPD_DT) can be located in the pad area PDA of the first non-display area NDA, and the routing pad WPD_RV of the reference voltage line RVL (hereinafter referred to as the reference voltage pad WPD_RV) and the routing pad WPD_ELVD of the first power line ELVDL (hereinafter referred to as the first power pad WPD_ELVD) can be located in the pad area PDA of the second non-display area NDA. As another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power pad WPD_ELVD can all be located in the same area, such as the first non-display area NDA. Figure 1 The external device EXD can be mounted on the wiring pad WPD. The external device EXD can be mounted on the wiring pad WPD via anisotropic conductive film or ultrasonic bonding.

[0101] Pixels PX on the first substrate 110 may include pixel driving circuitry. Lines may pass through the pixels PX to apply driving signals to the pixel driving circuitry. Each pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may vary. Hereinafter, the pixel driving circuit will be described as having a “3T1C” structure comprising three transistors and one capacitor, but this disclosure is not limited thereto. As another example, various modified pixel structures (such as “2T1C”, “7T1C”, or “6T1C” structures) may be applied to the pixel driving circuitry.

[0102] Figure 4 This is a schematic diagram of the equivalent circuit of a pixel in a display device according to an embodiment.

[0103] refer to Figure 4 The pixel PX of the display device 1 may include a light-emitting element EMD, and may also include three transistors (e.g., a driving transistor DTR, a first switching transistor STR1 and a second switching transistor STR2) and a storage capacitor CST.

[0104] The light-emitting element (EMD) can emit light according to the current applied to it via the driving transistor (DTR). The light-emitting element (EMD) can be implemented as an OLED, a micron LED, or a nano LED.

[0105] The first electrode (e.g., anode electrode) of the light-emitting element EMD can be electrically connected to the source electrode of the driving transistor DTR, and the second electrode (e.g., cathode electrode) of the light-emitting element EMD can be electrically connected to the second power line ELVSL, wherein a low potential voltage (or second power supply voltage) lower than the high potential voltage (or first power supply voltage) from the first power line ELVDL is applied to the second power line ELVSL.

[0106] The driving transistor DTR can control the current flowing from the first power line ELVDL, to which a first power supply voltage is applied, to the light-emitting element EMD based on the voltage difference between its gate electrode and source electrode. The gate electrode of the driving transistor DTR can be electrically connected to the first source / drain electrode of the first switching transistor STR1, the source electrode of the driving transistor DTR can be electrically connected to the first electrode of the light-emitting element EMD, and the drain electrode of the driving transistor DTR can be electrically connected to the first power line ELVDL, to which the first power supply voltage is applied.

[0107] The first switching transistor STR1 can be turned on by a scan signal from the scan line SCL, and electrically connects the data line DTL to the gate electrode of the driving transistor DTR. The gate electrode of the first switching transistor STR1 can be electrically connected to the scan line SCL, the first source / drain electrode of the first switching transistor STR1 can be electrically connected to the gate electrode of the driving transistor DTR, and the second source / drain electrode of the first switching transistor STR1 can be electrically connected to the data line DTL.

[0108] The second switching transistor STR2 can be turned on by a sensing signal from the sensing signal line SSL, and electrically connects the reference voltage line RVL to the source electrode of the driving transistor DTR. The gate electrode of the second switching transistor STR2 can be electrically connected to the sensing signal line SSL, the first source / drain electrode of the second switching transistor STR2 can be electrically connected to the reference voltage line RVL, and the second source / drain electrode of the second switching transistor STR2 can be electrically connected to the source electrode of the driving transistor DTR.

[0109] The first source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be source electrodes, and the second source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be drain electrodes. However, this disclosure is not limited thereto. As another example, the first source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be drain electrodes, and the second source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be source electrodes.

[0110] A storage capacitor CST can be formed between the gate and source electrodes of the driving transistor DTR. The storage capacitor CST can store a differential voltage corresponding to the difference between the gate voltage and the source voltage of the driving transistor DTR.

[0111] The driving transistor DTR, the first switching transistor STR1, and the second switching transistor STR2 can be formed as a thin-film transistor (TFT). Figure 3 The driving transistor DTR, the first switching transistor STR1, and the second switching transistor STR2 are shown to be N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but this disclosure is not limited thereto. As another example, the driving transistor DTR, the first switching transistor STR1, and the second switching transistor STR2 may be P-type MOSFETs. As yet another example, some of the driving transistor DTR, the first switching transistor STR1, and the second switching transistor STR2 may be N-type MOSFETs, while the other(s) may be P-type MOSFETs.

[0112] Figure 5 This is a schematic cross-sectional view of the first display substrate of the display device according to an embodiment. Figure 6 yes Figure 5 A schematic enlarged view of part A.

[0113] Figure 5 A portion of the display area DPA and a portion of the non-display area NDA are shown. Figure 5 The transistor region TRR and capacitor region CPR of pixel PX are shown as part of the display region DPA, and the pad region PDA is shown as part of the non-display region NDA. Figure 5 The transistor region TRR can be the region of one of the three transistors (specifically, the driving transistor DTR) in which the pixel PX is set. For convenience, Figure 5 The diagram primarily shows the circuit layer CCL of the first display substrate 100, extending up to the pixel defining layer PDL. Figure 6 The setting is shown Figure 5 The wiring pads (WPD) in the pad area of ​​the PDA.

[0114] refer to Figure 5 The circuit layer CCL may include a semiconductor layer 150, a conductive layer, and an insulating layer disposed on the first substrate 110. The semiconductor layer 150 may include an oxide semiconductor. The conductive layer may include a lower metal layer 120, a gate conductive layer GCL, a data conductive layer DCL, and a pixel electrode PXE. The insulating layer may include a buffer layer 161, a gate insulating layer 162, an interlayer insulating layer 163, a passivation layer 164, and a via layer 165.

[0115] Specifically, a lower metal layer 120 may be disposed on the first substrate 110. The lower metal layer 120 may be a light-shielding layer capable of protecting the semiconductor layer 150 from light originating from below or within the circuit layer CCL. The lower metal layer 120 may have a patterned shape. The lower metal layer 120 may be disposed within the transistor region TRR. The lower metal layer 120 may overlap with the semiconductor layer 150 disposed above it, and may cover or overlap the semiconductor layer 150 from below. The lower metal layer 120 may cover or overlap at least one channel region of the semiconductor layer 150 from below, or cover or overlap the entire semiconductor layer 150. The lower metal layer 120 may be electrically connected to the source electrode SEL of the driving transistor DTR through a first contact hole CNT1, and may suppress voltage variations in the driving transistor DTR. The lower metal layer 120 may be formed of a low-reflection material capable of reducing light reflection. In the example, the lower metal layer 120 can be formed as a titanium (Ti) / copper (Cu) bilayer, wherein Ti layers and Cu layers are stacked, but this disclosure is not limited thereto. In the example, the lower metal layer 120 can be formed as a Ti / Cu / Ti trilayer or a Cu monolayer.

[0116] A buffer layer 161 may be disposed on the lower metal layer 120. The buffer layer 161 may cover or overlap the entire surface of the first substrate 110 on which the lower metal layer 120 is formed. The buffer layer 161 may comprise silicon nitride, silicon oxide, or silicon oxynitride. In an example, the buffer layer 161 may comprise SiN. x / SiO x The double layer.

[0117] Semiconductor layer 150 may be disposed on buffer layer 161. Semiconductor layer 150 may be disposed in transistor region TRR and may include channel region for driving transistor DTR. Semiconductor layer 150 may include oxide semiconductor, and oxide semiconductor may include, for example, binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), Ti, Al, hafnium (Hf), zirconium (Zr) or Mg. x ), ternary compounds (AB) x C y) or quaternary compounds (AB) x C y D z In one embodiment, the semiconductor layer 150 may include indium gallium zinc oxide (IGZO).

[0118] A gate insulating layer 162 may be disposed on a buffer layer 161. The gate insulating layer 162 and the gate conductive layer GCL may be formed with the same pattern, as will be described below. The gate insulating layer 162 disposed in the transistor region TRR may be disposed on the semiconductor layer 150, and the gate insulating layer 162 disposed in the capacitor region CPR may be disposed on the buffer layer 161. The sidewalls of the gate insulating layer 162 may be generally aligned with the sidewalls of the gate conductive layer GCL (e.g., the sidewalls of the gate electrode GEL or the first electrode CEL1), but this disclosure is not limited thereto. The gate insulating layer 162 may comprise a silicon compound or a metal oxide. For example, the gate insulating layer 162 may comprise silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. In an example, the gate insulating layer 162 may comprise SiO2. x The present disclosure is not limited to this. In an example, the gate insulating layer 162 may include SiO2. x / SiN x The double layer.

[0119] A gate conductive layer (GCL) may be disposed on the gate insulating layer 162. The gate conductive layer GCL may include the gate electrode GEL in the transistor region TRR and the first electrode CEL1 (or lower electrode) of the capacitor in the capacitor region CPR. The gate conductive layer GCL may include... Figure 3 The scan line SCL and the sensing signal line SSL. The gate conductive layer GCL may not overlap with the data conductive layer DCL in the pad area of ​​the PDA, as will be described below.

[0120] The gate conductive layer (GCL) can be formed as a single layer or as multiple layers. In one embodiment, the gate conductive layer (GCL) may include a gate metal layer 130 having a gate main metal layer 130a and a gate base layer 130b disposed below the gate main metal layer 130a. Both the gate main metal layer 130a and the gate base layer 130b can be formed of a conductive material. No insulating layer may be inserted between the multiple layers of the gate conductive layer (GCL) that overlap each other in the thickness direction. The gate main metal layer 130a and the gate base layer 130b can be etched and patterned together using a single mask process.

[0121] A gate base layer 130b may be disposed below the gate main metal layer 130a. The gate base layer 130b may improve the properties of layers forming adhesive layers such as the gate main metal layer 130a, or may prevent reactive material from the gate insulating layer 162 from penetrating into the gate main metal layer 130a. The gate base layer 130b may also prevent material (e.g., Cu) from the gate main metal layer 130a from diffusing into adjacent lower layers. The gate base layer 130b may include materials such as Ti, tantalum (Ta), Ca, Cr, Mg, or Ni, but this disclosure is not limited thereto.

[0122] The gate main metal layer 130a can primarily transmit signals and can be formed of a low-resistance material. The gate main metal layer 130a can be thicker than the gate base layer 130b and can be formed of a material having a lower resistance than the gate base layer 130b. The gate main metal layer 130a can include materials such as Cu, molybdenum (Mo), Al, or Ag, but this disclosure is not limited thereto.

[0123] Although not specifically shown, the gate metal layer 130 may also include a gate capping layer disposed on the gate main metal layer 130a. The gate capping layer may cover (or overlap with) the gate main metal layer 130a from above and protect the gate main metal layer 130a from above. The gate capping layer may be in direct contact with the gate main metal layer 130a, but this disclosure is not limited thereto. The gate capping layer may be thinner than the gate main metal layer 130a and may be formed of a material having a higher resistance than the gate main metal layer 130a. The gate capping layer may protect the gate main metal layer 130a from etchants or other chemicals used during the manufacture of the layer above the gate conductive layer GCL or the display device 1. The gate capping layer may prevent material of the gate main metal layer 130a (e.g., Cu) from diffusing into adjacent upper layers.

[0124] An interlayer insulating layer 163 may be disposed on the gate conductive layer GCL. The interlayer insulating layer 163 may be disposed on the gate conductive layer GCL, a portion of the semiconductor layer 150 exposed by the gate conductive layer GCL, and a portion of the buffer layer 161 exposed by the gate conductive layer GCL and the semiconductor layer 150. The interlayer insulating layer 163 may comprise an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. In this example, the interlayer insulating layer 163 may comprise SiON.

[0125] For convenience, Figure 5An interlayer insulating layer 163 formed of inorganic material is shown to have a flat top surface in the display area DPA, but the interlayer insulating layer 163 may have a surface shape that reflects any height difference below. The thickness of multiple portions of the interlayer insulating layer 163 can be compared with the same flat reference surface (e.g., the top surface of the buffer layer 161) on which there is no height difference.

[0126] The data conductive layer (DCL) can be disposed on the interlayer insulating layer 163. The data conductive layer (DCL) may include the source electrode (SEL) and drain electrode (DEL) in the transistor region (TRR), the second electrode (CEL2) (or upper electrode) of the capacitor in the capacitor region (CPR), and the wiring pad (WPD) in the pad region (PDA).

[0127] The source electrode SEL and drain electrode DEL can be electrically connected to the semiconductor layer 150 through the second contact hole CNT2 penetrating the interlayer insulating layer 163. The source electrode SEL can be electrically connected to the lower metal layer 120 through the first contact hole CNT1 penetrating the interlayer insulating layer 163 and the buffer layer 161. The data conductive layer DCL may also include Figure 3 The data line DTL, the reference voltage line RVL, and the first power line ELVDL.

[0128] refer to Figure 5 and Figure 6 The data conductive layer (DCL) may include a data conductive metal layer 141, a first data capping layer 142 disposed on the data conductive metal layer 141, a second data capping layer 143 disposed on the first data capping layer 142, and a third data capping layer 144 disposed on the second data capping layer 143.

[0129] The data conductive metal layer 141 can be formed as a single layer or multiple layers. In the example, the data conductive metal layer 141 may include a main data metal layer 141a and a data base layer 141b disposed below the main data metal layer 141a.

[0130] The data base layer 141b, the main data metal layer 141a, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 can all be formed of conductive material. No insulating layers may be inserted between the multiple layers of the data conductive layer DCL. The data base layer 141b, the main data metal layer 141a, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 can all be etched and patterned together using a single mask process. The process for forming the stacked structure of the data conductive layer DCL will be described below.

[0131] Similar to the gate base layer 130b, the data base layer 141b can improve the properties of the formed layer, such as the adhesion of the data main metal layer 141a, or can prevent reactive material from the interlayer insulating layer 163 from penetrating into the data main metal layer 141a. The data base layer 141b may include at least one selected from Ti, Ta, Ca, Cr, Mg, and Ni, but this disclosure is not limited thereto. In an example, the data base layer 141b may be formed of Ti.

[0132] The main data metal layer 141a can primarily transmit signals and can be formed of a low-resistance material. The main data metal layer 141a can be thicker than the data base layer 141b, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144. The main data metal layer 141a can be formed of a material having a lower resistance than the first data capping layer 142 directly disposed on the main data metal layer 141a and the data base layer 141b directly disposed below the main data metal layer 141a. The main data metal layer 141a can include at least one selected from Cu, Al, Ag, and Mo, but this disclosure is not limited thereto. In an example, the main data metal layer 141a can be formed of Cu.

[0133] The first data capping layer 142 can cover (or overlap with) the data main metal layer 141a from above and protect the data main metal layer 141a from above. The first data capping layer 142 can protect the data main metal layer 141a from the effects of etchants or other chemicals used during each manufacturing process after the formation of the data conductive layer DCL (e.g., during the formation of the pixel electrode PXE), even if the second data capping layer 143 is exposed and etched away by such etchants or chemicals. The first data capping layer 142 can prevent the material (e.g., Cu) of the data main metal layer 141a from diffusing into adjacent upper layers. The first data capping layer 142 can directly contact the data main metal layer 141a.

[0134] The first data capping layer 142 may include Ti, indium zinc oxide (ZIO), or IZO. In examples, the first data capping layer 142 may be formed as a single layer or multiple layers including at least one of a Ti layer, a ZIO layer, and an IZO layer. In embodiments, the first data capping layer 142 may be formed as, for example, a Ti single layer.

[0135] A second data capping layer 143 may be disposed on the first data capping layer 142. The second data capping layer 143 can protect the first data capping layer 142 from the effects of dry etching that can be performed during each manufacturing process after the formation of the data conductive layer DCL (e.g., during the formation of the third contact hole CNT3 and pad opening PDOP). The second data capping layer 143 can prevent the first data capping layer 142 from being over-etched by such dry etching, and thus may reduce the thickness of the first data capping layer 142.

[0136] The second data capping layer 143 may include a material that is not consumed by dry etching. The second data capping layer 143 may include ITO or IZO. The second data capping layer 143 may be formed as a single layer or multiple layers, for example, including at least one of ITO and IZO layers, but this disclosure is not limited thereto. In an example, the second data capping layer 143 may be formed as a single ITO layer.

[0137] A third data capping layer 144 may be disposed on the second data capping layer 143. The third data capping layer 144 may comprise a material having a higher etch rate for the same etchant than the first data capping layer 142 and the second data capping layer 143. In an example, the third data capping layer 144 may comprise a material whose etch rate for the same etchant is twice that of the first data capping layer 142 and the second data capping layer 143. If the first data capping layer 142 comprises Ti and the second data capping layer 143 comprises ITO, the third data capping layer 144 may comprise Cu or ZIO.

[0138] In cases where the third data capping layer 144 comprises a material having a higher etch rate for the same etchant than the first data capping layer 142 and the second data capping layer 143, the third data capping layer 144 can prevent the formation of tips during the formation of the data conductive layer DCL, which are protrusions of the first data capping layer 142 and the second data capping layer 143 that protrude further outward than the main data metal layer 141a. This will be described in detail below.

[0139] Any sharp points of the first data capping layer 142 and the second data capping layer 143 disposed on the data main metal layer 141a may lead to cracking due to step-covering defects during the deposition of the passivation layer 164, which will be described below. For example, since the third data capping layer 144 comprises a material having a higher etch rate for the same etchant than the first data capping layer 142 and the second data capping layer 143, the materials of the multiple layers of the data conductive layer DCL can have different etch rates than each other, and this can prevent the formation of sharp points on the top surface of the data main metal layer 141a during the formation of the conductive pattern of the data conductive layer DCL. Therefore, the reliability of the circuit layer CCL can be improved.

[0140] By preventing the formation of the tips of the first data capping layer 142 and the second data capping layer 143, the pattern profile of the data conductive layer DCL can be improved, and the taper angle of the data conductive layer DCL can be reduced, thereby improving the step coverage of the layer to be formed (e.g., passivation layer 164).

[0141] Because a third data capping layer 144 is used, which comprises a material whose etching rate is twice that of the first data capping layer 142 and the second data capping layer 143 for the same etchant, the fluorine (F) content in the etchant does not need to be increased to improve the etching rate. Therefore, damage that may be caused by F diffusing into the interlayer insulating layer 163 can be reduced.

[0142] In the example, the data conductive layer (DCL) may include a Ti-containing data base layer 141b, a Cu-containing data main metal layer 141a, a Ti-containing first data capping layer 142, an ITO-containing second data capping layer 143, and a Cu-containing third data capping layer 144. For example, the DCL may include five layers of Ti / Cu / Ti / ITO / Cu. The sides (or sidewalls) of the data base layer 141b, the data main metal layer 141a, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 may be aligned with each other. For example, in the DCL, the side surfaces of each pair of adjacent element layers that are in contact with each other may be aligned without protruding from each other. In an embodiment, the third data capping layer 144 may be formed of ZIO, and the DCL may have a Ti / Cu / Ti / ITO / ZIO stacked structure.

[0143] refer to Figure 6 The main data metal layer 141a, the data base layer 141b, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 can have different thicknesses. The thicknesses T1, T2, T3, T4, and T5 of the main data metal layer 141a, the data base layer 141b, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 can be defined as the distances from the bottom surface of the main data metal layer 141a, the data base layer 141b, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 to the top surface of the main data metal layer 141a, the data base layer 141b, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144, respectively.

[0144] In the example, the thickness T1 of the main data metal layer 141a can be greater than the thickness T2 of the base data layer 141b, the thickness T3 of the first data capping layer 142, the thickness T4 of the second data capping layer 143, and the thickness T5 of the third data capping layer 144. The base data layer 141b and the first data capping layer 142, which directly contact and protect the main data metal layer 141a from below and above, respectively, can be sufficiently thick. The third data capping layer 144, which does not directly contact the main data metal layer 141a, does not need to be as thick as the base data layer 141b, the first data capping layer 142, or the second data capping layer 143.

[0145] In the example, when the data conductive layer DCL is a five-layer structure of Ti / Cu / Ti / ITO / Cu, the data main metal layer 141a can have approximately to approximately With a thickness T1, the data base layer 141b can have approximately to approximately The thickness T2, the first data capping layer 142 can have approximately to approximately The thickness T3, the second data capping layer 143 can have approximately to approximately The thickness T4, and the thickness T5 of the third data capping layer 144 can be approximately Or smaller. In an embodiment, the thickness T5 of the third data capping layer 144 can be approximately to approximately The viscosity of the etchant used in the etching process for forming the pixel electrode material layer (or pixel electrode layer) can be high. If the thickness T5 of the third data capping layer 144 exposed by the pad opening PDOP is approximately... Or smaller, so as to prevent etchant from penetrating to the interface between the third data capping layer 144 and the passivation layer 164, and thus prevent the third data capping layer 144 and the passivation layer 164 from peeling off from each other.

[0146] Refer again Figure 5 Along the structure of the third data capping layer 144 disposed at the topmost layer of the data conductive layer DCL and / or along the layer in contact with the top surface of the third data capping layer 144, the data conductive layer DCL may include a first region 140A, a second region 140B and a third region 140C.

[0147] The third data capping layer 144 of the data conductive layer DCL can have a different structure, or the layers of the data conductive layer DCL that are in contact with the top surface of the third data capping layer 144 can be different. The first region 140A, the second region 140B, and the third region 140C of the data conductive layer DCL will be described below.

[0148] Passivation layer 164 may be disposed on data conductive layer DCL. Passivation layer 164 may cover and protect data conductive layer DCL. Passivation layer 164 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide.

[0149] The passivation layer 164 may be formed throughout the entire display area DPA, but may not be formed in at least a portion of the non-display area NDA. In the pad area PDA included in the non-display area NDA, the passivation layer 164 may not be provided in at least a portion of the third region 140C of the data conductive layer DCL (or on at least a portion of the wiring pad WPD).

[0150] A via layer 165 may be disposed on the passivation layer 164. The via layer 165 may cover the top surface of the passivation layer 164 and may expose the side surface of the end portion of the passivation layer 164 in the pad area PDA.

[0151] The via layer 165 may include a pad opening PDOP that exposes at least a portion of the third region 140C of the data conductive layer DCL in the pad region PDA. The via layer 165 forming the inner sidewall of the pad opening PDOP may expose the side surface of the end portion of the passivation layer 164 in the pad region PDA, but this disclosure is not limited thereto. For example, the pad opening PDOP may be formed by portions of the passivation layer 164 and the via layer 165 in the pad region PDA, and the inner sidewall of said portion of the passivation layer 164 may be aligned with the inner sidewall of said portion of the via layer 165. The via layer 165 may cover the side surface of the end portion of the passivation layer 164 in the pad region PDA to form the inner sidewall of the pad opening PDOP.

[0152] The through-hole layer 165 may include an organic insulating material, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, or BCB. The through-hole layer 165 may also include a photosensitive material, but this disclosure is not limited thereto. In an example, the through-hole layer 165 may include polyimide.

[0153] The pixel electrode (PXE) can be disposed on the via layer 165. The material of the pixel electrode (PXE) is as described in the reference above. Figure 2As described. In the example, the pixel electrode PXE can include three layers of ITO / Ag / ITO.

[0154] The pixel electrode PXE can be disposed in the display area DPA, but may not be disposed in the non-display area NDA. The pixel electrode PXE may overlap with the transistor area TRR and capacitor area CPR of the display area DPA, but this disclosure is not limited thereto. The pixel electrode PXE can be electrically connected to the source electrode SEL of the driving transistor DTR through a third contact hole CNT3 passing through the via layer 165 and the passivation layer 164.

[0155] The pixel confinement layer (PDL) can be deposited on the pixel electrode (PXE). The material for the PDL is as described in the reference above. Figure 2 As described. In the example, the pixel-defined layer (PDL) may include polyimide.

[0156] The pixel definition layer (PDL) can be disposed in the display area (DPA), but may not be disposed in the non-display area (NDA). The PDL can overlap with the edge of the pixel electrode (PXE). The PDL can be uniformly disposed on the portion of the via layer 165 where the pixel electrode (PXE) is not formed.

[0157] The first region 140A, the second region 140B, and the third region 140C of the data conductive layer DCL will be described in detail below.

[0158] The data conductive layer (DCL) may include a first region 140A overlapping with the third contact hole (CNT3), a second region 140B substantially covered by the passivation layer 164, and a third region 140C exposed by the pad opening (PDOP). The first region 140A and the second region 140B of the data conductive layer DCL may be disposed in the display area (DPA), and the third region 140C of the data conductive layer DCL may be disposed in the non-display area (NDA).

[0159] The first region 140A of the data conductive layer DCL can be disposed in the transistor region TRR. The source electrode SEL of the driving transistor DTR can be formed as the first region 140A of the data conductive layer DCL disposed in the transistor region TRR. The second region 140B of the data conductive layer DCL can be disposed in the transistor region TRR and / or capacitor region CPR of the display region DPA. The drain electrode DEL or the second electrode CEL2 of the driving transistor DTR can be formed by the second region 140B of the data conductive layer DCL.

[0160] The third data capping layer 144 can cover the entire top surface of the second data capping layer 143 in the first region 140A and the second region 140B of the data conductive layer DCL in the display area DPA. For example, portions of the second data capping layer 143 in the first region 140A and the second region 140B of the data conductive layer DCL can be covered by the third data capping layer 144 without being exposed.

[0161] The first region 140A of the data conductive layer DCL can be electrically connected to the pixel electrode PXE through the third contact hole CNT3. Specifically, the passivation layer 164 and the pixel electrode PXE can be disposed on the top surface of the third data capping layer 144 in the first region 140A of the data conductive layer DCL. At least a portion of the top surface of the third data capping layer 144 in the first region 140A of the data conductive layer DCL that overlaps with the third contact hole CNT3 can contact the pixel electrode PXE, and the remaining portion of the top surface of the third data capping layer 144 in the first region 140A of the data conductive layer DCL can contact the passivation layer 164. The pixel electrode PXE can fill the third contact hole CNT3 and can contact and be electrically connected to the portion of the top surface of the third data capping layer 144 in the first region 140A of the data conductive layer DCL.

[0162] A passivation layer 164 can be disposed on the top surface of the second region 140B of the data conductive layer DCL. Specifically, the top surface of the third data capping layer 144 can contact the passivation layer 164 in the second region 140B of the data conductive layer DCL. The passivation layer 164 can be disposed on the entire top surface of the third data capping layer 144 in the second region 140B of the data conductive layer DCL to cover the entire second region 140B of the data conductive layer DCL.

[0163] The third region 140C of the data conductive layer DCL can be set in the pad area PDA. The wiring pads WPD in the pad area PDA can be formed by the setting of the third region 140C of the data conductive layer DCL in the pad area PDA.

[0164] In the third region 140C of the non-display region NDA, where the data conductive layer DCL is disposed, the third data capping layer 144 may not overlap with at least a portion of the second data capping layer 143. The portion of the third data capping layer 144 in the third region 140C of the data conductive layer DCL will hereinafter be referred to as the pad conductive layer 145, to distinguish it from the portions of the third data capping layer 144 in the first region 140A and the second region 140B.

[0165] The pad conductive layer 145 in the third region 140C of the data conductive layer DCL can at least partially expose the top surface of the portion of the second data capping layer 143 in the third region 140C of the data conductive layer DCL. The pad conductive layer 145 in the third region 140C of the data conductive layer DCL may not overlap with the pad opening PDOP. Therefore, the top surface of the portion of the second data capping layer 143 in the third region 140C of the data conductive layer DCL can be exposed by the pad opening PDOP.

[0166] The pad conductive layer 145 in the third region 140C of the data conductive layer DCL may include an inner surface disposed in the pad opening PDOP and an outer surface positioned opposite the inner surface. In an example, the inner surface of the pad conductive layer 145 in the third region 140C of the data conductive layer DCL may be aligned with the inner sidewall of the passivation layer 164 forming the pad opening PDOP, but this disclosure is not limited thereto. As another example, the inner surface of the pad conductive layer 145 in the third region 140C of the data conductive layer DCL may not be aligned with the inner sidewall of the passivation layer 164 forming the pad opening PDOP. As described above, the outer surface of the pad conductive layer 145 in the third region 140C of the data conductive layer DCL may be aligned with the side surface of a portion of the second data capping layer 143 below the pad conductive layer 145.

[0167] The manufacturing process will be described below. Figure 5 Methods for displaying devices.

[0168] Figures 7 to 19 It shows how to manufacture Figure 5 A schematic cross-sectional view of the display device. Figures 12 to 14 yes Figure 11 A schematic enlarged cross-sectional view of region B.

[0169] refer to Figure 7 A patterned lower metal layer 120 can be formed on the first substrate 110. The lower metal layer 120 can be formed by a mask process. In this example, the lower metal layer 120 can be formed by depositing a material layer for the lower metal layer on the entire surface of the first substrate 110 and patterning the material layer for the lower metal layer by photolithography.

[0170] refer to Figure 8 A buffer layer 161 can be formed on the entire surface of a first substrate 110 on which a lower metal layer 120 is formed. A semiconductor layer 150 can be formed on the buffer layer 161. The semiconductor layer 150 can be formed by a mask process. In this example, the semiconductor layer 150 can be formed by depositing an oxide semiconductor on the entire surface of the buffer layer 161 and patterning the oxide semiconductor by photolithography.

[0171] refer to Figure 9 A patterned gate insulating layer 162 and a gate conductive layer GCL can be formed on a buffer layer 161 on which a semiconductor layer 150 is formed. The patterned gate insulating layer 162 and the gate conductive layer GCL can be formed by a single mask process.

[0172] Specifically, a material layer for the gate insulating layer can be deposited on the entire surface of the buffer layer 161 on which the semiconductor layer 150 is formed. A material layer for the gate base layer and a material layer for the gate main metal layer can be sequentially deposited on the material layer for the gate insulating layer. A photoresist pattern can be formed by applying a photoresist layer to the material layer for the gate main metal layer and subjecting the photoresist layer to exposure and development. The photoresist pattern can be used as an etching mask to sequentially etch the material layer for the gate main metal layer, the material layer for the gate base layer, and the material layer for the gate insulating layer. The gate conductive layer GCL, including the gate electrode GEL and the first electrode CEL1, can be formed by stripping or ashing to remove the photoresist pattern.

[0173] The photoresist pattern has been described above as being used as an etch mask until the gate insulating layer 162 is patterned; however, each patterned upper layer can be used as a hard mask for etching the lower layers disposed beneath it. The photoresist pattern can be used together with the hard mask as an etch mask. As another example, the photoresist pattern can be removed after the hard mask is formed, and the hard mask can be used as an etch mask to etch the layers beneath it.

[0174] refer to Figure 10An interlayer insulating layer 163 can be deposited on a buffer layer 161 on which a gate conductive layer GCL is formed, and a first contact hole CNT1 exposing a portion of the lower metal layer 120 and a second contact hole CNT2 exposing a portion of the semiconductor layer 150 (e.g., source and drain regions) can be formed. The first contact hole CNT1 and the second contact hole CNT2 can be formed by a mask process. The first contact hole CNT1 and the second contact hole CNT2 can be formed sequentially using different masks. For example, a material layer for the interlayer insulating layer (or insulating film) can be deposited on the entire surface of the buffer layer 161 on which the gate conductive layer GCL is formed. A first photoresist pattern for exposing a portion of the lower metal layer 120 can be formed on the material layer for the interlayer insulating layer, and the first contact hole CNT1 exposing a portion of the lower metal layer 120 can be formed by etching the material layer for the interlayer insulating layer and the buffer layer 161 using the first photoresist pattern as an etching mask. The first photoresist pattern can be removed, and a second photoresist pattern for exposing a portion of the semiconductor layer 150 can be formed on the material layer used for the interlayer insulating layer. The second contact hole CNT2 can be formed by etching the material layer used for the interlayer insulating layer using the second photoresist pattern as an etching mask.

[0175] The first contact hole CNT1 and the second contact hole CNT2 can be formed using the same mask. The semiconductor layer 150 can be exposed to the etchant during the etching buffer layer 161 to form the first contact hole CNT1. As described above, if the first contact hole CNT1 is formed first and the second contact hole CNT2 is formed using a separate mask, damage to the surface of the semiconductor layer 150 exposed by the second contact hole CNT2 can be suppressed.

[0176] refer to Figure 11 A patterned data conductive layer (DCL) can be formed on the interlayer insulating layer 163. The data conductive layer DCL can be formed using a mask process. In this example, material layers for a data conductive metal layer, a material layer for a first data capping layer, a material layer for a second data capping layer, and a material layer for a third data capping layer can be sequentially deposited on the entire surface of the interlayer insulating layer 163. The material layer for the data conductive metal layer may include a material layer for a data base layer and a material layer for a data main metal layer.

[0177] In the example, when the data conductive layer DCL is formed as a five-layer structure of Ti / Cu / Ti / ITO / Cu, the material layer containing Ti for the data base layer, the material layer containing Cu for the data main metal layer, the material layer containing Ti for the first data capping layer, the material layer containing ITO for the second data capping layer, and the material layer containing Cu for the third data capping layer can be formed by physical vapor deposition (PVD) (e.g., sputtering). In this process, the material layers for the data conductive metal layer, the material layer for the first data capping layer, the material layer for the second data capping layer, and / or the material layer for the third data capping layer can be deposited on the inside of the first contact hole CNT1 and the second contact hole CNT2, and thus can be electrically connected to the lower metal layer 120 and the semiconductor layer 150.

[0178] A photoresist pattern can be formed by applying a photoresist layer to a material layer used for a third data capping layer and subjecting the photoresist layer to exposure and development. This photoresist pattern can then be used as an etching mask to etch the material layers used for the first, second, and third data capping layers, as well as the material layer used for the data conductive metal layer. The photoresist pattern can be removed by stripping or ashing, and as... Figure 11 As shown, a data conductive layer DCL can be formed, including the source electrode SEL and drain electrode DEL in the transistor region TRR, the second electrode CEL2 in the capacitor region CPR, and the wiring pad WPD in the pad region PDA.

[0179] refer to Figure 11 The source electrode SEL and drain electrode DEL in the transistor region TRR, the second electrode CEL2 in the capacitor region CPR, and the wiring pad WPD in the pad region PDA can be formed as a structure in which the data base layer 141b, the main data metal layer 141a, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 are stacked sequentially. The sidewalls of the data base layer 141b, the main data metal layer 141a, the first data capping layer 142, the second data capping layer 143, and the third data capping layer 144 can be aligned with each other.

[0180] In the example, the third data capping layer 144 can be formed of a material whose etch rate with the same etchant is twice that of the first data capping layer 142 and the second data capping layer 143, and thus the formation of sharp points in the first data capping layer 142 and the second data capping layer 143 can be prevented. Reference will be made below. Figures 12 to 14 Describe in detail the etching of the data conductive layer (DCL).

[0181] refer to Figure 12A photoresist pattern PR can be formed on the material layer 144' used for the third data capping layer, and the material layer 144' used for the third data capping layer can be etched using an etchant and the photoresist pattern PR as an etch mask. First, the material layer 144' used for the third data capping layer can be etched, and then the material layers 143' used for the second data capping layer, 142' used for the first data capping layer, and 141a' used for the data main metal layer exposed by the etched material layer 144' used for the third data capping layer can be etched sequentially. Although not shown in the figures, the material layer used for the data base layer can also be etched.

[0182] Because the third data capping layer 144 is formed of a material with a higher etching rate for the same etchant than the first data capping layer 142 and the second data capping layer 143, the sidewalls of the material layer 144' for the third data capping layer can be etched inward rapidly. The material layer 143' for the second data capping layer and the material layer 142' for the first data capping layer can be etched sequentially. If the sidewalls of the material layer 144' for the third data capping layer are etched inward rapidly, the top surface and sidewalls of the material layer 143' for the second data capping layer, which is located below the material layer 144' for the third data capping layer, can be exposed to the etchant. Because both the top surface and sidewalls of the material layer 143' for the second data capping layer are etched, the material layer 143' for the second data capping layer can be etched faster than if only the sidewalls of the material layer 143' for the second data capping layer are etched.

[0183] refer to Figure 13 Since the material layer 143' for the second data capping layer and the material layer 142' for the first data capping layer have similar etching rates with the same etchant, they can be etched at similar speeds, and their sidewalls are aligned with each other. Because the material layer 141a' for the main data metal layer located below the material layer 142' for the first data capping layer is formed of the same material as the material layer 144' for the third data capping layer and has the same etching rate with the same etchant, the bottom surface of the material layer 142' for the first data capping layer can be exposed and etched by the etchant.

[0184] Since the top surface of the material layer 143' used for the second data capping layer, the side surface of the material layer 143' used for the second data capping layer, the side surface of the material layer 142' used for the first data capping layer, and the bottom surface of the material layer 142' used for the first data capping layer are etched simultaneously, the material layer 143' used for the second data capping layer and the material layer 142' used for the first data capping layer can be etched rapidly.

[0185] like Figure 14 As shown, the sidewalls of the first data cover layer 142 and the second data cover layer 143 can be aligned with the sidewalls of the main data metal layer 141a, and thus the formation of sharp points can be prevented.

[0186] As described above, even if the material layer 141a' for the data master metal layer includes Cu, the material layer 142' for the first data capping layer includes Ti with a lower etch rate than Cu for the same etchant, and the material layer 143' for the second data capping layer includes ITO with a lower etch rate than Cu for the same etchant, if the material layer 144' for the third data capping layer includes a material (e.g., Cu) with a higher etch rate for the same etchant than the materials (e.g., Ti and ITO) of the materials (e.g., the materials for the first data capping layer and the material layer 143' for the second data capping layer), the sidewalls of the multiple layers in the data conductive layer DCL can be etched to align with each other. Therefore, since the material layer 144' used for the third data capping layer includes a material that has a higher etch rate for the same etchant than the material layer 142' used for the first data capping layer and the material layer 143' used for the second data capping layer, the formation of tips in the first data capping layer 142 and the second data capping layer 143 that may be caused by differences in etch rates between the materials of the multiple layers of the data conductive layer DCL can be prevented.

[0187] refer to Figure 15 A passivation layer 164 can be formed on the interlayer insulating layer 163 on which the data conductive layer DCL is formed, and a photoresist pattern can be formed on the passivation layer 164.

[0188] Specifically, a material layer for a passivation layer can be deposited on the entire surface of the interlayer insulating layer 163 on which the data conductive layer DCL is formed. A photoresist pattern can be formed by forming a photoresist layer on the material layer for the passivation layer and subjecting the photoresist layer to exposure and development. The photoresist pattern may include a first photoresist opening and a second photoresist opening corresponding to a first opening OP1 and a second opening OP2 to be formed in the passivation layer 164, where the first opening OP1 exposes the source electrode SEL in the transistor region TRR, and the second opening OP2 exposes the wiring pad WPD in the pad region PDA. In this example, the width of the first opening OP1 may be less than or equal to the width of the source electrode SEL, and the width of the second opening OP2 may be less than or equal to the width of the wiring pad WPD in the pad region PDA. However, this disclosure is not limited to this example.

[0189] A photoresist pattern can be used as an etching mask to etch the material layer used for the passivation layer. A portion of the material layer used for the passivation layer exposed by a first photoresist opening can be etched to form a contact hole to expose the source electrode SEL in the transistor region TRR. A portion of the material layer used for the passivation layer exposed by a second photoresist opening can be removed to expose a portion of the uppermost layer of the wiring pad WPD (e.g., the third data capping layer 144). For example, the passivation layer 164 may not be disposed on at least a portion of the wiring pad WPD in the pad region PDA, and at least a portion of the wiring pad WPD in the pad region PDA may not overlap with the passivation layer 164 in the thickness direction.

[0190] refer to Figure 16 A patterned via layer 165 can be formed on the passivation layer 164. The patterned via layer 165 may include a third opening OP3 exposing a first opening OP1 formed in the passivation layer 164, and a fourth opening OP4 exposing at least a portion of the wiring pads WPD in the pad region PDA. The third opening OP3 may form a third contact via CNT3 together with the first opening OP1 exposing the source electrode SEL. The fourth opening OP4 may form a pad opening PDOP.

[0191] In the example, the width of the third opening OP3 can be greater than the width of the first opening OP1, and the width of the fourth opening OP4 can be greater than the width of the second opening OP2, which is based on the above reference. Figure 15 The process described herein is used to form the passivation layer 164. Therefore, in the pad region PDA, the via layer 165 may cover or overlap at least a portion of the top surface of the passivation layer 164 in the pad region PDA. The via layer 165 may expose the side surface of the end portion of the passivation layer 164 in the pad region PDA.

[0192] The via layer 165 may include, for example, an organic material comprising a photosensitive material. The via layer 165 can be formed by applying an organic material layer for the via layer and subjecting the organic material layer to exposure and development to form a third opening OP3 and a fourth opening OP4. Although not specifically shown, the via layer 165 may have different heights in different regions and may be formed using a halftone mask or a slot mask.

[0193] refer to Figure 17 and Figure 18 Patterned pixel electrodes (PXEs) can be formed on the via layer 165. The pixel electrodes (PXEs) can be formed using a mask process.

[0194] refer to Figure 17 A pixel electrode material layer (or pixel electrode layer) can be deposited on the entire surface of the via layer 165. The pixel electrode material layer can be uniformly deposited on the inside of the third contact hole CNT3 to electrically connect to the source electrode SEL, or it can be uniformly deposited on the inside of the pad opening PDOP to be uniformly placed on a portion of the wiring pad WPD exposed by the pad opening PDOP in the pad region PDA. The pixel electrode material layer can contact at least a portion of the top surface of the third data capping layer 144 disposed on the uppermost side of the first region 140A of the data conductive layer DCL. The pixel electrode material layer can contact at least a portion of the top surface of the third data capping layer 144 disposed on the uppermost side of the wiring pad WPD in the pad region PDA of the data conductive layer DCL.

[0195] A photoresist pattern PR having the same pattern shape as the pixel electrode PXE can be formed by applying a photoresist layer to the pixel electrode material layer and subjecting the photoresist layer to exposure and development. The photoresist pattern PR can be used as an etching mask to etch the pixel electrode material layer. The pixel electrode material layer can be etched by wet etching, but this disclosure is not limited thereto.

[0196] The portion of the pixel electrode material layer with the photoresist pattern PR can be patterned by wet etching, thereby forming the pixel electrode PXE. A portion of the pixel electrode layer on the wiring pads WPD in the pad area PDA (where no photoresist pattern PR is provided) of the data conductive layer DCL may be exposed to the etchant used in the etching of the pixel electrode material layer and damaged by it. As a result, at least a portion of the third data capping layer 144 on the uppermost side of the wiring pads WPD in the pad area PDA of the data conductive layer DCL can be exposed by the pad opening PDOP and can be removed by exposure to the etchant used in the etching of the pixel electrode material layer. In this way, a pixel electrode PXE can be formed. Figure 5The conductive layer 145 of the pads. The photoresist pattern PR can be removed by peeling or ashing.

[0197] refer to Figure 19 A patterned pixel-defining layer (PDL) can be formed on a via layer 165 on which pixel electrodes (PXEs) are formed. The pixel-defining layer (PDL) may include, for example, an organic material comprising a photosensitive material. The pixel-defining layer (PDL) can be formed by applying an organic material layer for the pixel-defining layer and subjecting the organic material layer for the pixel-defining layer to exposure and development.

[0198] The pixel defining layer PDL can be formed along the boundary of each pixel PX and can partially overlap with the pixel electrode PXE. The pixel defining layer PDL can be formed to overlap with the third contact hole CNT3. Although not specifically shown, the pixel defining layer PDL can fill a portion of the via layer 165 with a relatively small height, and thus can compensate for the height difference with the rest of the via layer 165.

[0199] Since the third data capping layer 144 is formed together with the data conductive metal layer 141 through a single mask process, the formation of tips in the first data capping layer 142 and the second data capping layer 143 can be prevented, and a portion of the second data capping layer 143 exposed by the pad conductive layer 145 can be used as a contact electrode for the wiring pad WPD. Therefore, since the formation of tips in the data conductive layer DCL can be prevented, cracks in the multiple insulating layers disposed on the data conductive layer DCL can be prevented. Since no additional mask process is required for forming the contact electrodes of the wiring pad WPD, process efficiency can be improved.

[0200] The following description will depict display devices according to other embodiments, primarily focusing on those related to... Figure 5 The differences in display devices. Repeated descriptions of features or elements that are the same as those already described will be omitted or simplified.

[0201] Figure 20 This is a schematic cross-sectional view of the first display substrate of the display device according to an embodiment.

[0202] Figure 20 The implementation may differ at least in the stacked structure or profile structure of the via layer 165 in the pad area of ​​the PDA. Figure 5 The implementation method.

[0203] refer to Figure 20The via layer 165 may include a pad opening PDOP together with a passivation layer 164 disposed below the via layer 165, which exposes a third region 140C of the data conductive layer DCL in the pad region PDA. The sidewalls of the passivation layer 164 forming the inner sidewall of the pad opening PDOP and the sidewalls of the via layer 165 may be aligned with each other. The inner sidewall of the pad opening PDOP may be aligned with the inner sidewall of the pad conductive layer 145 of the data conductive layer DCL. For example, the sidewalls of the passivation layer 164 forming the inner sidewall of the pad opening PDOP and the sidewalls of the via layer 165 may be aligned with the inner sidewall of the pad conductive layer 145 of the data conductive layer DCL.

[0204] When the passivation layer 164 and the via layer 165 are etched using a single mask pattern, the sidewalls of the passivation layer 164 and the via layer 165 that form the inner sidewalls of the pad opening PDOP can be aligned with the inner sidewalls of the pad conductive layer 145 of the data conductive layer DCL.

[0205] Figure 21 This is part A corresponding to the display device according to the embodiment (see [reference]). Figure 5 A schematic enlarged view of part ).

[0206] Figure 21 The third region 140C of the data conductive layer DCL in the pad area PDA is shown.

[0207] Figure 21 Implementation methods and Figure 5 The difference in the implementation may be at least that, in the third region 140C of the data conductive layer DCL, the sidewall of the pad conductive layer 145 is not aligned with the corresponding sidewall of the passivation layer 164.

[0208] refer to Figure 21 In the third region 140C of the data conductive layer DCL, a portion of the passivation layer 164 may cover or overlap the top surface of the pad conductive layer 145, and a portion of the passivation layer 164 may protrude outward beyond the pad conductive layer 145. Therefore, in the region overlapping with the second data capping layer 143, at least a portion of the bottom surface of the outwardly protruding portion of the passivation layer 164 beyond the pad conductive layer 145 may face the top surface of the second data capping layer 143.

[0209] Figure 21The display device can be obtained by etching a portion of the pixel electrode material layer in the pad region PDA during the etching process used to form the pixel electrode PXE, such that a third data capping layer of the data conductive layer DCL in the pad region PDA is exposed to the etchant used in the etching process. In the example, if the third data capping layer is formed of a material with a relatively high etching rate (such as Cu), the third data capping layer can be etched more inward than the sidewalls of the passivation layer 164 disposed on the data conductive layer DCL, and therefore can be formed more inward than the pad conductive layer 145.

[0210] Figure 22 This is part A corresponding to the display device according to the embodiment (see [reference]). Figure 5 A schematic enlarged view of part ).

[0211] Figure 22 The third region 140C of the data conductive layer DCL in the pad area PDA is shown. Figure 22 Implementation methods and Figure 5 The difference in the implementation may be at least that, in the third region 140C of the pad region PDA where the data conductive layer DCL is disposed, the second data capping layer 143 includes surface steps of different thicknesses.

[0212] refer to Figure 22 In the third region 140C of the data conductive layer DCL, the second data capping layer 143 may include a first segment 143A and a second segment 143B, which is thinner than the first segment 143A, in the region overlapping with the passivation layer 164. The second segment 143B may be located in the region exposed by the pad opening PDOP. Therefore, the side surface of the first segment 143A may be aligned with the corresponding side surface of the passivation layer 164 and the corresponding side surface of the pad conductive layer 145, thereby forming the pad opening PDOP in the pad region PDA.

[0213] Figure 22 The display device can be obtained by etching a portion of the pixel electrode material layer in the pad region PDA and a third data capping layer disposed on the entire surface of the second data capping layer 143 during an etching process for forming the pixel electrode PXE, such that the second data capping layer 143 is exposed to the etchant used in the etching process. In the example, while the pixel electrode material layer and the third data capping layer are being etched, at least a portion of the second data capping layer 143 can be etched. If the second data capping layer 143 is formed of an ITO-containing material having a relatively low etch rate and being sufficiently thick, it can be as follows: Figure 22As shown, only a portion of the second data capping layer 143 is etched. Even in this case, the first data capping layer 142 disposed on the main data metal layer 141a can remain on the main data metal layer 141a and thus can cover (or overlap with) the top surface of the main data metal layer 141a and protect the top surface of the main data metal layer 141a.

[0214] Figure 23 This is part A corresponding to the display device according to the embodiment (see [reference]). Figure 5 A schematic enlarged view of part ).

[0215] Figure 23 The third region 140C of the data conductive layer DCL in the pad area PDA is shown.

[0216] Figure 23 Implementation methods and Figure 5 The difference in the implementation may be at least that the third region 140C of the data conductive layer DCL in the pad region PDA does not include the pad conductive layer.

[0217] refer to Figure 23 In the third region 140C of the data conductive layer DCL, the pad conductive layer may not be disposed on a portion of the second data capping layer 143. The passivation layer 164 may be disposed on at least a portion of the top surface of the second data capping layer 143. Therefore, a portion of the top surface of the second data capping layer 143 overlapping with the passivation layer 164 may be exposed. A space SP, close to the sidewall of the pad opening PDOP, may be formed between the passivation layer 164 and the second data capping layer 143 in the thickness direction.

[0218] Figure 23The display device can be obtained when different material layers of the sequentially stacked data conductive layer DCL have different etch rates during the patterning of the data conductive layer DCL. In the example, if the material layer used for the third data capping layer has a higher etch rate with the same etchant than other material layers of the data conductive layer DCL, the material layer used for the third data capping layer can be etched faster than other layers of the data conductive layer DCL. The material layer used for the third data capping layer can be etched more than other layers of the data conductive layer DCL, and the material layer used for the third data capping layer can be completely etched away during the etching of the data conductive layer DCL. In the example, after the patterned data conductive layer DCL is formed, the passivation layer 164, the via layer 165, and the pixel electrode PXE can be formed sequentially. During the etching process for forming the patterned pixel electrode PXE, the material layer used for the third data capping layer exposed by the pad opening PDOP can be completely removed by the etchant. Therefore, a space SP close to the sidewall of the pad opening PDOP can be formed between the passivation layer 164 and the second data capping layer 143 in the thickness direction.

[0219] Figure 24 Images showing different degrees of etching over time for different etching durations of the data conductive layer pattern, according to an embodiment, are illustrated. Figure 25 An image of a data conductive layer pattern according to an embodiment is shown. Figure 26 An image of wiring pads during the etching of pixel electrodes, according to an embodiment, is shown.

[0220] Specifically, Figure 24 and Figure 25 The above references are shown. Figures 12 to 14 The described process is illustrated by scanning electron microscope (SEM) images (or vertical SEM images (V-SEM)). Figure 26 The above references are shown. Figure 18 SEM images of the described process.

[0221] refer to Figures 12 to 14 and Figure 24 If a photoresist pattern PR is formed on the material layer 144' used for the third data capping layer, and the material layer 144' used for the third data capping layer is etched using an etchant and the photoresist pattern PR as an etch mask, then the material layer 144' used for the third data capping layer can be etched first (20 seconds).

[0222] Material layer 143' for the second data capping layer and material layer 142' for the first data capping layer can be etched at similar speeds while their sidewalls are aligned with each other. Because the top surface of material layer 143' for the second data capping layer, the sidewalls of material layer 143' for the second data capping layer, the sidewalls of material layer 142' for the first data capping layer, and the bottom surface of material layer 142' for the first data capping layer are etched together, material layers 143' for the second data capping layer and material layer 142' for the first data capping layer can be etched rapidly (25 seconds).

[0223] As etching continues, the sidewalls of the material layer 142' for the first data capping layer, the material layer 143' for the second data capping layer, and the material layer 144' for the third data capping layer are aligned with the corresponding (multiple) sidewalls of the main data metal layer 141a (30 seconds), and a data conductive layer pattern with improved contours can be created (35 seconds).

[0224] Specifically, such as Figure 25 As shown in the diagram, the data conductive layer pattern can have an improved profile and prevent the formation of sharp points.

[0225] refer to Figure 18 and Figure 26 When the material layer 144' for the third data capping layer is etched with an etchant during the etching of the pixel electrode material layer, the material layer 143' for the second data capping layer may be exposed to the etchant. If the material layer 143' for the second data capping layer is formed of ITO, the etchant can penetrate into the material layer 142' for the first data capping layer through pinholes present in the material layer 143' for the second data capping layer. However, the penetration of the etchant into the material layer 142' for the first data capping layer can be prevented, and thus the data main metal layer 141a can be prevented from being damaged by the etchant.

[0226] like Figure 26 As shown in the figure, it can be seen that the data conductive layer DCL, including the data main metal layer 141a, is not damaged by the etchant.

[0227] In closing, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of this disclosure. Therefore, the embodiments of this disclosure are used in a general and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, comprising: The substrate includes the display area and the pad area; A data conductive layer is disposed on the substrate; A passivation layer is disposed on the data conductive layer; A via layer is disposed on the passivation layer; as well as Pixel electrodes are disposed on the via layer, wherein, The data conductive layer includes: Data infrastructure layer; A main data metal layer is disposed on the data base layer; A first data cover layer is disposed on the main data metal layer; A second data capping layer is disposed on the first data capping layer; and A third data capping layer is disposed on top of the second data capping layer. The passivation layer and the via layer include pad openings that expose a portion of the data conductive layer in the pad region. The third data capping layer comprises a material having a higher etch rate for the same etchant than the first and second data capping layers, and the third data capping layer comprises a pad conductive layer that exposes the second data capping layer through the pad opening.

2. The display device according to claim 1, wherein, For the same etchant, the third data capping layer has twice the etch rate of the first and second data capping layers.

3. The display device according to claim 2, wherein, The third data capping layer comprises copper or zinc indium oxide.

4. The display device according to claim 3, wherein, The main data metal layer and the third data capping layer comprise copper.

5. The display device according to claim 3, wherein, The third data capping layer has a thickness in the range of 10 Å to 100 Å.

6. The display device according to claim 3, wherein, The data base layer and the first data capping layer comprise the same material, and include at least one of titanium, tantalum, calcium, chromium, magnesium, and nickel.

7. The display device according to claim 6, wherein, The data base layer and the first data capping layer comprise titanium.

8. The display device according to claim 3, wherein, The second data capping layer includes indium tin oxide.

9. The display device according to claim 1, wherein, The side surfaces of each of the data base layer, the data main metal layer, the first data capping layer, the second data capping layer, and the third data capping layer of the data conductive layer are aligned with each other.

10. The display device according to claim 1, wherein, The side surface of the passivation layer is aligned with the corresponding side surface of the pad conductive layer.

11. The display device according to claim 1, wherein, The passivation layer overlaps with the conductive layer of the pad, and The side surface of the passivation layer protrudes outward beyond the side surface of the pad conductive layer.

12. A display device, comprising: The substrate includes the display area and the pad area; A data conductive layer is disposed on the substrate; A passivation layer is disposed on the data conductive layer; A via layer is disposed on the passivation layer; as well as Pixel electrodes are disposed on the via layer, wherein, The data conductive layer includes: Data infrastructure layer; A main data metal layer is disposed on the data base layer; A first data cover layer is disposed on the main data metal layer; A second data capping layer is disposed on the first data capping layer; and A third data capping layer is disposed on top of the second data capping layer. The passivation layer and the via layer include: A first contact hole penetrates the passivation layer and the via layer in the thickness direction to expose a portion of the data conductive layer in the display area; and The pad opening exposes a portion of the data conductive layer within the pad area. The data conductive layer is divided into: The first region overlaps with the passivation layer; The second region overlaps with the first contact hole; and The third region overlaps with the pad opening. The third data capping layer is disposed in the entire first region and the entire second region of the data conductive layer, and The third data capping layer includes a pad conductive layer in the third region of the data conductive layer that does not overlap with the pad opening.

13. The display device according to claim 12, wherein, The third data capping layer contacts the pixel electrode in the second region of the data conductive layer.

14. The display device according to claim 12, further comprising: A lower metal layer is disposed on the substrate below the first region of the data conductive layer; as well as At least one insulating layer is disposed between the data conductive layer and the lower metal layer.

15. The display device according to claim 14, wherein, The at least one insulating layer includes a contact hole that penetrates the at least one insulating layer in the thickness direction to expose the underlying metal layer, and The lower metal layer is electrically connected to the data conductive layer through the contact hole.

16. The display device according to claim 12, wherein, The portions of the third data capping layer in the first and second regions of the data conductive layer and the portions of the pad conductive layer in the third region of the data conductive layer comprise the same material.

17. The display device according to claim 12, wherein, For the same etchant, the third data capping layer has a higher etch rate than the first and second data capping layers.

18. The display device according to claim 17, wherein, The third data capping layer comprises copper or zinc indium oxide.

19. The display device according to claim 18, wherein, The main data metal layer and the third data capping layer comprise copper.

20. The display device according to claim 18, wherein, The third data capping layer has a thickness in the range of 10 Å to 100 Å.

21. The display device according to claim 12, wherein, The third data capping layer includes a pad conductive layer that exposes the second data capping layer through the pad openings.

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