Display panel and display device using the same

Abstract

This invention relates to a display panel and a display device using the display panel. The display panel includes: a first metal layer; a first insulating layer covering the first metal layer; a semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering the semiconductor layer; and a second metal layer disposed on the second insulating layer, wherein the first metal layer includes a bottom gate of a driving element, wherein the second metal layer includes a top gate of the driving element, the top gate being connected to the bottom gate through a first contact hole penetrating the second insulating layer and the first insulating layer, and wherein the semiconductor layer includes a semiconductor channel of the driving element, the semiconductor channel overlapping the top gate and the bottom gate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0150906, filed on November 12, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to a display panel and a display device using the display panel. Background Technology

[0004] Depending on the material of the light-emitting layer, electroluminescent display devices can be broadly classified into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and possess advantages such as fast response speed, high luminous efficiency, high brightness, and wide viewing angle. In organic light-emitting display devices, organic light-emitting diodes (OLEDs) are formed in each pixel. Organic light-emitting display devices have a fast response speed, excellent performance in luminous efficiency, brightness, and viewing angle, and provide superior contrast and color reproduction due to their ability to display black grayscale with full black.

[0005] Organic light-emitting display devices do not require a backlight unit and can be implemented on flexible materials such as plastic substrates, thin glass substrates, or metal substrates. Therefore, flexible displays can be realized as organic light-emitting display devices.

[0006] Each pixel in an organic light-emitting display device includes a driving element for driving the light-emitting element. The driving element supplies current to the light-emitting element according to the gate-source voltage Vgs. Various methods are being explored to increase the current capability of the driving element.

[0007] Crosstalk can occur due to parasitic capacitance between signal / power lines formed in the pixel array.

[0008] A pixel circuit can be formed in each pixel. The pixel circuit has a structure in which multiple thin film layers, including metal layers and insulating layers, are stacked on top of each other. Because of the large number of contact holes that penetrate the insulating layer and connect the metal layer or metal and semiconductor layers at major nodes, it is difficult to design a pixel circuit that can increase the pixel aperture ratio. Summary of the Invention

[0009] Therefore, the present invention aims to solve the above-mentioned needs and / or problems.

[0010] The present invention provides a display panel that can improve the current capability of the driving element, prevent crosstalk, and reduce the number of required contact holes, as well as a display device using the display panel.

[0011] The present invention is not limited to the above objectives, and other objectives of the present invention will be apparent to those skilled in the art from the following description.

[0012] A display panel according to one aspect of the present invention includes: a first metal layer; a first insulating layer covering the first metal layer; a semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering the semiconductor layer; and a second metal layer disposed on the second insulating layer, wherein the first metal layer includes a bottom gate of a driving element, wherein the second metal layer includes a top gate of the driving element, the top gate being connected to the bottom gate through a first contact hole penetrating the second insulating layer and the first insulating layer, wherein the semiconductor layer includes a semiconductor channel of the driving element, the semiconductor channel overlapping the top gate and the bottom gate.

[0013] According to another aspect of the present invention, a display panel includes: a driving element configured to provide current to a light-emitting element; a first switching element configured to connect a data line to the gate of the driving element in response to a gate signal from a gate line; a second switching element configured to apply a reference voltage to the source of the driving element in response to the gate signal; and a capacitor connected between the gate of the driving element and the source of the driving element, wherein the gate of the driving element includes a top gate and a bottom gate and a semiconductor layer, wherein the semiconductor layer includes a semiconductor channel interposed between the top gate and the bottom gate, the top gate overlapping the bottom gate, wherein the top gate contacts the bottom gate through a first contact hole, the first contact hole penetrating a first insulating layer located between the bottom gate and the semiconductor layer and a second insulating layer located between the top gate and the semiconductor layer, wherein the anode of the light-emitting element contacts the semiconductor layer through a second contact hole, the second contact hole penetrating a third insulating layer and a planarization layer disposed on the third insulating layer, the third insulating layer covering the driving element and the first switching element and the second switching element.

[0014] According to another aspect of the present invention, a display device includes: a display panel, wherein a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of first power lines for applying a pixel driving voltage, a plurality of second power lines for applying a reference voltage, and a plurality of pixels are arranged therein; a data driver configured to provide a data voltage for pixel data via the data lines; and a gate driver configured to provide a gate signal via the gate lines, wherein each pixel includes: a driving element configured to provide current to a light-emitting element; a first switching element configured to connect a data line for applying the data voltage to a gate of the driving element in response to a gate signal from the gate lines; and a second switching element configured to apply a reference voltage lower than the pixel driving voltage to a light-emitting element in response to the gate signal. The source of the driving element; and a capacitor connected between the gate of the driving element and the source of the driving element, wherein the gate of the driving element includes a top gate and a bottom gate and a semiconductor layer, wherein the semiconductor layer includes a semiconductor channel inserted between the top gate and the bottom gate, the top gate overlapping the bottom gate, wherein the top gate contacts the bottom gate through a first contact hole, the first contact hole penetrating a first insulating layer located between the bottom gate and the semiconductor layer and a second insulating layer located between the top gate and the semiconductor layer, wherein the anode of the light-emitting element contacts the semiconductor layer through a second contact hole, the second contact hole penetrating a third insulating layer and a planarization layer disposed on the third insulating layer, the third insulating layer covering the driving element and the first switching element and the second switching element.

[0015] This invention improves the current-carrying capability of the driving element by implementing the gate of the driving element used to drive the light-emitting element as a dual-gate structure.

[0016] In this invention, by optimizing the planar and cross-sectional structure of the pixel circuit, the number of contact holes used to connect the main nodes of the pixel circuit can be reduced. As a result, this invention can reduce the aperture ratio loss caused by the contact holes arranged in the pixel circuit.

[0017] In this invention, a slit covered by an anode is formed between the bottom gate and the data line of the driving element to eliminate parasitic capacitance between adjacent bottom gates and data lines and prevent crosstalk.

[0018] In this invention, a slit is formed between the bottom gate and the data line of the driving element, thereby preventing short circuits between adjacent bottom gates and data lines and eliminating parasitic capacitance.

[0019] The effects achievable by this invention are not limited to those described above. In other words, other objectives not mentioned will be readily understood by those skilled in the art based on the following description. Attached Figure Description

[0020] The above and other objects, features, and advantages of the present invention will become more apparent to those skilled in the art from the exemplary aspects described in detail with reference to the accompanying drawings. In the drawings:

[0021] Figure 1 This is a block diagram schematically illustrating a display device according to one aspect of the present invention;

[0022] Figure 2 This is a circuit diagram showing an example of a pixel circuit;

[0023] Figure 3 This is a schematic cross-sectional view illustrating the cross-sectional structure of a pixel circuit in a display device according to one aspect of the present invention.

[0024] Figure 4 This is a plan view showing the pixel circuit of a sub-pixel in a display panel according to one aspect of the present invention;

[0025] Figure 5 It is a diagram along Figure 4 A cross-sectional view of the pixel circuit structure cut by line I-I'.

[0026] Figure 6 It is a diagram Figure 3 A plan view of the pattern of the first metal layer shown;

[0027] Figure 7 It is a diagram Figure 5 A plan view showing the patterns of the semiconductor layer and the third metal layer;

[0028] Figure 8 It is a diagram Figure 3 A plan view of the pattern of the second metal layer shown;

[0029] Figure 9 It is a diagram Figure 4 A plan view of the anode of the light-emitting element shown;

[0030] Figure 10 This is a plan view illustrating the pixel circuit of a sub-pixel in a display panel according to another aspect of the present invention;

[0031] Figure 11 It is a diagram along Figure 10 A cross-sectional view of the pixel circuit structure taken from line II-II';

[0032] Figure 12 It is a diagram Figure 10 The diagram shows a plan view of the pattern of the first metal layer. Detailed Implementation

[0033] The advantages and features of the invention and its implementation will become clearer from the various aspects described below with reference to the accompanying drawings. However, the invention is not limited to these aspects and can be implemented in various different forms. These various aspects of the invention will complete the disclosure of the invention and give full understanding of the scope of the invention to those skilled in the art. The invention is limited only to the scope of the appended claims.

[0034] The shapes, dimensions, proportions, angles, quantities, etc., shown in the accompanying drawings for the purpose of describing various aspects of the invention are merely examples, and the invention is not limited thereto. Similar reference numerals generally denote similar elements throughout the specification. Furthermore, in describing the invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the invention.

[0035] Terms such as “including,” “contains,” and “have” used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.”

[0036] Even if not explicitly described, the components are interpreted as including the usual range of error.

[0037] When using terms such as “on top of,” “above,” “below,” and “after” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately following” or “directly.”

[0038] Components may be distinguished from each other using terms such as "first" and "second," but the function or structure of a component is not limited by the serial number or component name preceding it.

[0039] Throughout this application, the same reference numerals denote substantially the same elements.

[0040] The following aspects may be combined or integrated with each other, either partially or entirely, and may be technically related and operated in various ways. These aspects may be implemented independently of each other or in relation to each other.

[0041] In the display device of the present invention, the pixel circuit may include at least one of an n-channel transistor and a p-channel transistor. The transistor may be implemented as an oxide thin-film transistor (oxide TFT) including oxide semiconductor, a low-temperature polycrystalline silicon (LTPS) TFT including low-temperature polycrystalline silicon, etc. Furthermore, each transistor may be implemented as a p-channel TFT or an n-channel TFT. In various aspects, descriptions will be given based on examples of implementing the transistors of the pixel circuit as p-channel TFTs, but the present invention is not limited thereto.

[0042] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode where charge carriers are applied to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode where charge carriers flow out of the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. The current in an n-channel transistor flows from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor (PMOS)), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the present invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0043] The gate signal oscillates between the gate-on voltage and the gate-off voltage. The gate-on voltage is set to a voltage higher than the transistor's threshold voltage, and the gate-off voltage is set to a voltage lower than the transistor's threshold voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be the gate high voltage VGH, and the gate-off voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage can be the gate low voltage VGL, and the gate-off voltage can be the gate high voltage VGH.

[0044] The driving elements of a pixel circuit can be implemented as transistors. Although the electrical characteristics between pixels should be consistent across all pixels, differences may exist due to process variations and device characteristic variations. The electrical characteristics of pixels may degrade over time. To compensate for these inter-pixel electrical characteristic variations, the display device of this invention may include an external compensation circuit. The external compensation circuit senses the threshold voltage and / or mobility of the driving device via a sensing switch element located in each pixel circuit and a REF line (or sensing line) connected to the sensing switch element, and transmits this information to an external compensator. The compensator compensates for the inter-pixel electrical characteristic variations and degradation by modulating pixel data of the input image based on the sensing results of each sub-pixel.

[0045] The various aspects of the present invention will now be described in detail with reference to the accompanying drawings.

[0046] Reference Figure 1 and Figure 2 The display device of the present invention includes a display panel 10 and a display panel driver for writing pixel data to pixels of the display panel 10.

[0047] The display panel driver includes a data driver 12, a gate driver 13, and a timing controller 11.

[0048] The screen of the display panel 10 includes a pixel array AA on which an input image is displayed. The pixel array AA includes multiple data lines DL, multiple gate lines GL intersecting the data lines DL, multiple REF lines RL parallel to the data lines DL, and multiple pixels P arranged in a matrix.

[0049] Each pixel P can be divided into red, green, and blue sub-pixels to represent color. Each pixel may further include a white sub-pixel. Each sub-pixel may include... Figure 2 The pixel circuit shown.

[0050] Each sub-pixel is connected to one of the data lines DL that provides the data voltage, one of the REF lines RL that provides the reference voltage REF, and one of the gate lines GL. Additionally, each sub-pixel is connected to the VDD line PL that provides the pixel drive voltage EVDD, and is supplied with a low-potential power supply voltage EVSS through the VSS electrode.

[0051] The data driver 12 includes: a data channel unit 20 for providing data voltage to the data line DL of the display panel 10; and a sensing channel unit 30 connected to the pixel circuit of each sub-pixel to sense the driving characteristics of the pixel circuit in real time.

[0052] Data channel unit 20 includes multiple digital-to-analog converters (hereinafter referred to as "DACs") disposed on each channel. In display mode, the DACs of data channel unit 20 convert pixel data DATA input from timing controller 11 into gamma compensation voltages for each grayscale level to output data voltage Vdata. In sensing mode, data channel unit 20 outputs data voltage Vdata for sensing under the control of timing controller 11. The data voltage Vdata output from each channel of data channel unit 20 can be directly applied to data line DL, or it can be applied to data line DL through switching unit 40.

[0053] The display panel 10 may further include a switching unit 40. The switching unit 40 may include a demultiplexer DEMUX connected between the channel from which data voltage is output from the data channel unit 20 and the data lines DL. The demultiplexer reduces the number of channels in the data channel unit 20 by distributing the data voltage output from each channel of the data channel unit 20 to two or more data lines DL in a time-division manner.

[0054] The sensing channel unit 30 includes: a sampling circuit and an integrator connected to the REF line RL; and an analog-to-digital converter (hereinafter referred to as "ADC") that converts the output voltage of the integrator into sensing data (digital data). The sensing data is transmitted to a compensation unit of the timing controller 11.

[0055] The gate driver 13 can be implemented as an in-panel gate (GIP) circuit formed directly on the bezel area of ​​the display panel 10 along with the TFT array of the pixel array. Under the control of the timing controller 11, the gate driver 13 outputs a gate signal to the gate line GL. The gate driver 13 can shift the gate signal using a shift register to sequentially provide signals to the gate line GL. The voltage of the gate signal oscillates between a gate cutoff voltage and a gate on voltage. The gate driver 13 can be disposed on each of the left and right bezels of the display panel 10 to provide the gate signal to the gate line GL according to a double-feeding scheme. In the double-feeding scheme, the gate drivers 13 located on both sides can be synchronized under the control of the timing controller 11, so that the gate signal can be applied simultaneously to both ends of a gate line. Alternatively, the gate driver 13 can be disposed on one of the left and right bezels of the display panel 10 to provide the gate signal to the gate line GL according to a single-feeding scheme.

[0056] The timing controller 11 modulates the pixel data of the input image based on the sensing data received from the sensing channel unit 30, transmits it to the data channel unit 20 of the data driver 12, and controls the data channel unit 20 and the gate driver 13.

[0057] The timing controller 11 receives pixel data DATA of the input image and timing signals synchronized with the pixel data from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock DCLK, and a data enable signal DE. One cycle of the vertical synchronization signal Vsync is one frame period. One cycle of the horizontal synchronization signal Hsync and the data enable signal DE is one horizontal period (1H). The pulse of the data enable signal DE is synchronized with one row of data in the pixels to be written to that pixel row. Since the frame period and horizontal period can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0058] The timing controller 11 can multiply the input frame rate (Hz) by i (where i is a positive integer greater than 0) to generate control signals (DDC and GDC) whose frame rate is set to input frame rate × i (Hz), used to control the operating timing of the data driver 12, gate driver 13, and switching unit 40. The input frame rate is 60Hz in the National Television Standards Committee (NTSC) system and 50Hz in the Phase Inverter (PAL) system. The timing controller 11 can reduce the frame rate to a frequency between 1Hz and 30Hz to reduce the pixel refresh rate in low-speed drive mode.

[0059] The voltage level of the gate timing control signal output from the timing controller 11 can be shifted by a level shifter (not shown). The gate timing signal may include a start pulse, a shift clock, etc. The level shifter can convert a low-level voltage of the gate timing control signal to a gate low voltage, and can convert a high-level voltage of the gate timing control signal to a gate high voltage. The shift register of the gate driver 13 receives the gate timing control signal, generates a gate signal, and shifts the gate signal.

[0060] The timing controller 11 controls a sensing mode for sensing the electrical characteristics of the driving element DT at each sub-pixel and updating the compensation value accordingly, and the timing controller 11 controls a display mode for displaying pixel data of the input image reflecting the compensation value. The timing controller 11 controls the data driver 12, the gate driver 13, and the switching unit 40 to separate the sensing mode and the display mode according to a predetermined sequence, but the invention is not limited thereto. For example, the sensing mode may be executed during the vertical blank period of the display mode in which the input image is displayed on the pixels, during the power-on sequence period when power is first applied to the display device, or during the power-off sequence period after the display device is powered off and before the power is completely discharged. The vertical blank period is the period during which pixel data DATA of the input image is not written to the pixels. The vertical blank period is allocated between vertically active periods in which a frame of pixel data DATA is written. The power-on sequence period includes a transition period after power is first applied to the display device and before the input image is displayed on the pixel array AA. The power-off sequence includes the transition period after the pixel data addressing is completed and before the power to the display device is completely cut off.

[0061] The compensation unit of the timing controller 11 may include a lookup table (or compensation lookup table) for compensation. This lookup table stores compensation values ​​for the threshold voltage Vth and mobility μ of the driving element DT for each sub-pixel. In order to compensate for the electrical characteristic variation of the driving element DT at each sub-pixel, the compensation unit inputs the sensing data received from the ADC of the sensing channel unit 30 to the compensation lookup table, and modulates the pixel data of the input image by adding or multiplying the compensation value output from the compensation lookup table with the pixel data.

[0062] The data driver 12 and gate driver 13 can operate in a low-speed drive mode under the control of the timing controller 11. In the low-speed drive mode, when the input image remains unchanged for a preset time as a result of analyzing input data, the power consumption of the display device can be reduced. In the low-speed drive mode, when a still image is input for a preset time or longer, the pixel refresh rate is reduced to control the pixel data write cycle for a longer period, thereby reducing power consumption. The low-speed drive mode is not limited to the input of a still image. For example, the display panel driver can operate in the low-speed drive mode when the display device is operating in standby mode or when a user command or input image has not been input to the display panel driver for a preset time or longer.

[0063] The host system can be one of the following: a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, or a vehicle system.

[0064] The display device further includes a power supply 50. The power supply 50 may include a charge pump, regulator, buck converter, boost converter, programmable gamma IC, etc. The power supply 50 regulates the DC input voltage from the host system to generate the power required to drive the display panel driver and display panel 10. The power supply 50 may output DC voltages such as a gamma reference voltage, gate low voltage, gate high voltage, pixel drive voltage EVDD, low-level power supply voltage EVSS, or reference voltage REF. Pulses of the gate signal oscillate between gate high voltage and gate low voltage. The gamma reference voltage is applied to a voltage divider circuit of the data channel unit 20. The voltage divider circuit divides the gamma reference voltage to output a gamma compensation voltage for each grayscale level. The gamma compensation voltage for each grayscale level is provided to the DAC of the data channel unit 20. The programmable gamma IC can change the voltage level of each gamma reference voltage according to register settings.

[0065] like Figure 2 As shown, the pixel circuit is connected to the data line DL, which provides the data voltage for pixel data DATA; the REF line RL, which provides the reference voltage REF; and the gate line GL, which provides the gate signal SCAN. The reference voltage REF can be set to a DC voltage that is lower than the pixel drive voltage EVDD and lower than or equal to the low-potential supply voltage EVSS.

[0066] The pixel circuit includes an OLED light-emitting element, a driving element DT, a first switching element ST1, a second switching element ST2, and a storage capacitor Cst. Each of the driving element DT and the switching elements ST1 and ST2 can be implemented using a transistor.

[0067] OLEDs can be implemented using an OLED comprising an organic compound layer formed between the anode and cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The OLED is connected between a third node Ns, which is connected to the source of the driving element DT, and a VSS electrode to which a low-potential power supply voltage EVSS is applied. The OLED is driven by the current generated by the gate-source voltage Vgs of the driving element DT to emit light.

[0068] The driving element DT includes a gate connected to a first node Ng, a drain connected to a second node Nd, and a source connected to a third node Ns. The source of the driving element DT is connected to the anode of the light-emitting element OLED through the third node Ns. The driving element DT drives the light-emitting element OLED by controlling the amount of current applied to the light-emitting element OLED according to the gate-source voltage Vgs. The pixel driving voltage EVDD can be applied to the drain of the driving element DT.

[0069] The first switching element ST1 includes a gate connected to the gate line GL, a drain connected to the data line DL, and a source connected to the first node Ng. The first switching element ST1 is turned on in response to a pulse of the gate signal SCAN from the gate line GL. When the first switching element ST1 is turned on, the data line DL, to which the data voltage of the pixel data DATA is applied, is connected to the first node Ng, and the data voltage is applied to the gate of the driving element DT and the storage capacitor Cst.

[0070] The second switching element ST2 includes a gate connected to the gate line GL, a drain connected to the EFR line RL, and a source connected to the third node Ns. The second switching element ST2 is turned on in response to a pulse of the gate signal SCAN from the gate line GL and connects the EFR line RL and the third node Ns. When the second switching element ST2 is on, a reference voltage REF is applied to the third node Ns. When the second switching element ST2 is on in sensing mode, the electrical characteristics of the driving element DT can be sensed by the current flowing through the third node Ns. The REF line RL is connected to the sensing channel unit 30, and the current flowing through the third node Ns is provided to the sensing channel unit 30.

[0071] The storage capacitor Cst is connected between the first node Ng and the third node Ns, and maintains the gate-source voltage Vgs of the driving element DT during the light-emitting period of pixel P. As the gate-source voltage Vgs increases, the current flowing through the light-emitting element OLED increases, thereby increasing the brightness of pixel P. The brightness of pixel P is proportional to the magnitude of the voltage applied to the first node Ng (i.e., the data voltage Vdata).

[0072] The gate of the driving element DT can be implemented as a dual-gate structure. In a transistor with a dual-gate structure, the carrier mobility is increased as carriers flow across the semiconductor channel. The driving element DT operates in the saturation region and supplies current to the light-emitting element OLED. When the driving element DT is implemented as a dual-gate structure, the current flowing between the drain and source of the driving element DT can be increased by approximately three times compared to a single-gate structure when operating in the saturation region.

[0073] Switching elements ST1 and ST2 can be implemented as single-gate or dual-gate structures. Switching elements ST1 and ST2 operate in the linear region. When switching elements ST1 and ST2 are implemented as dual-gate structures, the mobility of carriers flowing through the semiconductor channel is increased. Due to the linear operation of switching elements ST1 and ST2, the current increases by approximately 1.5 times.

[0074] When the switching elements ST1 and ST2 on the display panel 10 are manufactured as a dual-gate structure, the parasitic capacitances connected to the gate lines and switching elements ST1 and ST2 can be increased, making the gate lines and switching elements ST1 and ST2 more susceptible to linewidth distribution variations or critical dimension (CD) variations during the manufacturing process. Therefore, considering the improved current capability of switching elements ST1 and ST2, the non-uniformity of the gate-drain parasitic capacitance Cgd between pixels due to linewidth variations, and the gate-source parasitic capacitance Cgs, switching elements ST1 and ST2 can be designed as a single-gate or dual-gate structure.

[0075] Figure 3 This is a schematic cross-sectional view illustrating the cross-sectional structure of a pixel circuit in a display device according to one aspect of the present invention.

[0076] Reference Figure 3 The cross-sectional structure of the pixel circuit includes: a first metal layer ML1 disposed on the substrate of the display panel 10; a buffer layer BUF covering the first metal layer ML1; a semiconductor layer ACT disposed on the buffer layer BUF; a gate insulating layer GI disposed on the buffer layer BUF and covering the semiconductor layer ACT; and a second metal layer ML2 disposed on the gate insulating layer GI.

[0077] The buffer layer (BUF) and the gate insulating layer (GI) are made of insulating materials such as SiO2 or SiN. x An insulating layer made of inorganic insulating materials such as inorganic insulating materials.

[0078] The first metal layer ML1 includes the data line DL, the bottom gate GE2 of the transistor TFT, the lower electrode CE1 of the capacitor Cst, the VDD line PL, the REF line RL, etc. Figure 3 In this example, the power lines PL and RL are omitted.

[0079] The bottom gate GE2 of the transistor TFT is located below the semiconductor channel of the transistor TFT and also serves as a light-shielding layer to block external light so that light does not shine into the semiconductor channel.

[0080] The top gate GE1 of the transistor TFT can be formed by patterning a metal pattern separated from the second metal layer ML2 located on the gate insulating layer GI. Here, the transistor TFT located on the bottom gate GE2 can be... Figure 2The driving element DT is shown. The gate of each of the first switching element ST1 and the second switching element ST2 (omitted in the figure) may be formed from a metal pattern patterned from a second metal layer. The gate of the transistor TFT may include a top gate GE1, a bottom gate GE2, and a semiconductor layer including a semiconductor channel interposed between the top gate GE1 and the bottom gate GE2, with the top gate GE1 overlapping the bottom gate GE2.

[0081] The second metal layer ML2 further includes a gate line GL connected to the gates of switching elements ST1 and ST2. The second metal layer ML2 may further include the upper electrode CE3 of the storage capacitor Cst.

[0082] The semiconductor layer ACT includes the source (SE) and drain (DE) of the transistor TFT, the semiconductor channel of the transistor TFT, and the intermediate electrode (CE2) of the storage capacitor Cst. The semiconductor layer ACT may be metallized in at least some portions, such as the source and drain of the transistor TFT, the portion connected to the second metal layer pattern, and the intermediate electrode portion of the storage capacitor Cst. The semiconductor layer ACT is not metallized in the semiconductor channel defined below the gate (GE1) of the transistor TFT.

[0083] In the case of indium gallium zinc oxide (IGZO) as a representative oxide semiconductor, the conductivity changes depending on the oxygen content. When the oxygen content decreases, the conductivity of the oxide semiconductor (IGZO) increases, and it is metallized. Plasma treatment can be used as a method to reduce the oxygen content of the oxide semiconductor (IGZO). For example, when the oxide semiconductor is exposed to plasma (metallization process), the oxygen contained in the oxide semiconductor is removed, and the resistance of the oxide semiconductor (IGZO) decreases, thereby allowing the oxide semiconductor to be metallized. Plasma treatment is a method of generating plasma discharge in helium (He), hydrogen (H2), or argon (Ar). In the dry etching process of the thin film layer located on the semiconductor layer ACT, the exposed portion of the semiconductor layer ACT can be metallized.

[0084] Third metal layer ( Figure 5 The MA can be partially formed on the semiconductor layer ACT. The third metal layer formed on the semiconductor layer ACT and the top gate GE1 of the transistor are used as masks in the metallization process of the semiconductor layer ACT, so that the semiconductor layer ACT located below the third metal layer and the gate GE1 is not metallized. The third metal layer is in contact with the semiconductor layer ACT located between the first metal layer ML1 and the second metal layer ML2.

[0085] When the semiconductor layer ACT and the third metal layer are stacked on the buffer layer BUF, the semiconductor layer ACT and the third metal layer can be patterned together in a photolithography process (hereinafter referred to as "optical process") using a halftone mask to form on the same row.

[0086] The source and drain electrodes of the transistor TFT, as well as the intermediate electrode CE2 of the storage capacitor Cst, can be formed from the metallized portion of the semiconductor layer ACT or the third metal layer as described above. The storage capacitor Cst may include: a first capacitor Cst1 located between the lower electrode CE1 and the intermediate electrode CE2; and a second capacitor Cst2 located between the intermediate electrode CE2 and the upper electrode CE3. Thus, the storage capacitor Cst can have an increased capacitance by utilizing the two capacitors Cst1 and Cst2. The size of the electrodes of the storage capacitor Cst can be reduced without decreasing the required capacitance of the storage capacitor Cst. Therefore, as the size of the storage capacitor Cst decreases, the pixel P's resizing rate can be improved.

[0087] Figure 4 This is a plan view showing the pixel circuit of a sub-pixel in a display device according to aspects of the present invention. Figure 5 It is a diagram along Figure 4 A cross-sectional view of the pixel circuit structure cut by line I-I'.

[0088] Reference Figure 4 and Figure 5 Each sub-pixel includes a light-emitting section EA and a circuit section CA.

[0089] The light-emitting segment EA includes a light-emitting element (OLED). A color filter can be disposed in the light-emitting segment EA. Light from the OLED is emitted to the outside through the light-emitting region in the light-emitting segment EA. The light-emitting region is defined by a pixel-defining layer BNK. The pixel-defining layer BNK covers the edge of the anode AND of the OLED. Simultaneously, the planar shape of the anode AND can be formed to match... Figure 9 The same pattern is shown, but not limited to this. Figure 4 In the image, only a portion of the light-emitting segment EA, which is adjacent to the circuit segment CA, is shown.

[0090] The circuit section CA includes a driving element DT, a first switching element ST1, a second switching element ST2, and a storage capacitor Cst for driving the light-emitting element OLED. The light-emitting element OLED is driven by the pixel circuit implemented in the circuit section CA.

[0091] When viewed from the cross-sectional structure of the pixel circuit, as Figure 5As shown, a first metal layer is disposed on the substrate SUBS of the display panel 10. A buffer layer BUF is disposed on the substrate SUBS to cover the first metal layer. The buffer layer BUF may be formed from an inorganic insulating material, such as an oxide film like SiO2, but is not limited thereto. The first metal layer may be formed from a copper / molybdenum titanium (Cu / MoTi) layer in which copper (Cu) and molybdenum titanium (MoTi) are stacked, but is not limited thereto.

[0092] The first metal layer includes a data line DL, a first VDD line PLV, a REF line RL, a bottom gate GE2, and the lower electrode CE1 of a storage capacitor Cst. The first VDD line PLV is a power line 1-1 disposed along a first direction y parallel to the data line DL and the REF line RL. The first VDD line PLV intersects with a second VDD line PLH, and a buffer layer BUF is interposed between the first VDD line PLV and the second VDD line PLH. The REF line RL... Figure 4 and Figure 5 Omitted in .

[0093] The bottom gate GE2 and the lower electrode CE1 of the storage capacitor Cst can be a single, integral metal pattern. The bottom gate GE2 is disposed on the driving element DT and the storage capacitor Cst so as to overlap with the semiconductor channel of the top gate GE1 and the driving element DT. Alternatively, the light-shielding portion of the bottom gate GE2 and the lower electrode CE1 of the storage capacitor Cst can be formed by an island pattern separate from the first metal layer.

[0094] A semiconductor layer ACT is disposed on a buffer layer BUF. The semiconductor layer ACT includes the semiconductor channels of transistors DT, ST1, and ST2, i.e., the active layer. The semiconductor channels of transistors DT, ST1, and ST2 are not metallized. The semiconductor channel of the driving element DT is disposed between the gate insulating layer GI and the buffer layer BUF, and overlaps with the top gate GE1 and the bottom gate GE2. The semiconductor layer ACT extends toward the storage capacitor Cst to include the intermediate electrode CE2 of the storage capacitor Cst (or to make the intermediate electrode CE2 of the storage capacitor Cst a part thereof). The intermediate electrode CE2 may be formed by a metallized portion of the semiconductor layer ACT or by a third metal layer MA formed on the semiconductor layer ACT.

[0095] The semiconductor layer ACT may include: the source and drain of transistors DT, ST1, and ST2; portions connecting the electrodes of transistors DT, ST1, and ST2; a metallized portion at the intermediate electrode CE2 of the storage capacitor Cst; and a second VDD line PLH that applies the pixel driving voltage EVDD to the driving element DT. The second VDD line PLH is a first-second power supply line disposed along a second direction x parallel to the gate line GL. The second VDD line PLH can be connected to the first VDD line PLV via a contact hole (omitted in the figure). Therefore, the pixel driving voltage EVDD applied to the first VDD line PLV is transmitted to the pixel circuit of the sub-pixel through the second VDD line PLH.

[0096] A third metal layer MA can be formed on the semiconductor layer ACT. The semiconductor layer ACT can be formed of IGZO, but is not limited to this; the metal layer MA can be formed of MoTi, but is not limited to this. The third metal layer MA is in direct contact with the semiconductor layer ACT at the portions of the semiconductor ACT that need to be metallized. The source and drain of transistors DT, ST1, and ST2 can be formed by the third metal layer MA on the semiconductor layer ACT. In this case, the semiconductor layer below the source and drain is not metallized.

[0097] The gate insulating layer GI covers the semiconductor layer ACT. The gate insulating layer GI can be an oxide film such as silicon dioxide (SiO2), but is not limited to it. In the optical process, the gate insulating layer GI is patterned to remain below the pattern of the second metal layer. Therefore, the gate insulating layer GI is disposed between the electrodes and semiconductor channels of transistors DT, ST1, and ST2.

[0098] A second metal layer is disposed on the gate insulating layer GI and is patterned in the optical process. The second metal layer includes: the gates of transistors DT, ST1, and ST2; the upper electrode CE3 of the storage capacitor Cst; and the gate line GL. Therefore, the top gate GE1 of the driving element DT is formed by the pattern of the second metal layer disposed on the gate insulating layer GI.

[0099] The gates of transistors DT, ST1, and ST2 disposed on the semiconductor layer ACT are masked beneath the semiconductor layer during the metallization process of the semiconductor layer ACT. Therefore, the semiconductor channels of transistors DT, ST1, and ST2 are defined by their gates.

[0100] The top gate GE1 and bottom gate GE2 of the driving element DT are connected through a first contact hole CH1, thereby realizing a dual-gate structure. The first contact hole CH1 penetrates the gate insulating layer GI and the buffer layer BUF to expose the bottom gate GE2. The buffer layer BUF, the semiconductor layer ACT, and the gate insulating layer GI are stacked between the top gate GE1 and the bottom gate GE2.

[0101] The passivation layer PAS is an insulating layer disposed on the buffer layer BUF to cover the second metal layer and the semiconductor layer ACT. The passivation layer PAS can be formed from an inorganic insulating material, such as an oxide film like SiO2, but is not limited thereto. The planarization layer OC is disposed on the passivation layer PAS. The planarization layer OC covers the driving element DT, switching elements ST1 and ST2, and storage capacitor Cst of the circuit segment CA to planarize the surface. The planarization layer OC can be formed from organic materials, such as polyimide, benzocyclobutene series resins, or acrylates, but is not limited thereto.

[0102] The light-emitting segment EA is disposed on the planarization layer OC. The anode AND of the light-emitting element OLED contacts the metallized portion of the semiconductor layer ACT or the third metal layer MA through a second contact hole CH2 that penetrates the passivation layer PAS and the planarization layer OC. The second contact hole CH2 penetrates the planarization layer OC and the passivation layer PAS to expose the metallized portion of the semiconductor layer ACT or the third metal layer MA.

[0103] The anode AND of the light-emitting element OLED is connected to the source of the driving element DT, the intermediate electrode CE2 of the storage capacitor Cst, and the source of the second switching element ST2 through the metallized portion of the semiconductor layer ACT or the third metal layer MA.

[0104] When viewed in the direction of pixel emission, the display panel 10 can be implemented as a bottom-emitting method. In this case, the anode AND can be formed as a transparent electrode on the planarization layer OC. For example, the anode AND can be made of a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

[0105] The pixel-defining layer BNK, which defines the luminescent area of ​​each sub-pixel, is set on the planarization layer OC to cover the anode AND.

[0106] Pixel-limited layer BNK is formed in Figure 4 and Figure 5 The organic compound layer and cathode are omitted in the diagram. The organic compound layer is separated between adjacent sub-pixels by a pixel defining layer (BNK), thereby defining a light-emitting area for each sub-pixel. The cathode of the OLED light-emitting element is disposed on the organic compound layer. The cathode can be formed on the entire pixel array (AA) and can be connected together between the sub-pixels. In the bottom-emitting method, the cathode can be implemented as a metal electrode with high light reflectivity. For example, the cathode can be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or alloys thereof with low work function.

[0107] The pixel circuit of this invention includes two contact holes CH1 and CH2. In this pixel circuit, it is not necessary to use [a specific method / mechanism] for [something related to contact holes]. Figure 2The contact hole at the first node Ng connects the semiconductor layer and the second metal layer pattern, and at... Figure 2 The third node Ns connects the semiconductor layer and the second metal layer pattern via a contact hole. Therefore, this invention can reduce aperture ratio loss caused by the large number of contact holes arranged in the pixel circuit.

[0108] Figures 6 to 9 It shows in detail the relationship with Figure 4 The cross-sectional structure of the pixel circuit shown is a plan view of the pattern shape of the main thin film layers separated. Figure 6 It is a diagram Figure 3 The diagram shows a plan view of the pattern of the first metal layer ML1. Figure 7 It is a diagram Figure 5 The diagram shows a plan view of the semiconductor layer ACT and the third metal layer MA. Figure 8 It is a diagram Figure 3 A plan view of the pattern of the second metal layer ML2 shown. Figure 9 It is a diagram Figure 4 The diagram shows a plan view of the anode AND of the OLED light-emitting element.

[0109] like Figure 6 As shown, the first metal layer ML1 includes a VDD line pattern M11, a bottom gate pattern M12, a data line pattern M13, etc. The bottom gate pattern M12 includes the bottom gate GE2 of the driving element DT and the lower electrode CE1 of the storage capacitor Cst. The bottom gate pattern M12 overlaps with the first contact hole CH1 and is exposed at the first contact hole CH1.

[0110] like Figure 7 As shown, the semiconductor layer ACT includes a first semiconductor pattern A1 and a second semiconductor pattern A2.

[0111] The first semiconductor pattern A1 includes a semiconductor channel of the driving element DT, a source of the driving element DT, a drain of the driving element DT, a semiconductor channel of the second switching element ST2, a source of the second switching element ST2, a drain of the second switching element ST2, an intermediate electrode of the storage capacitor Cst, and a second VDD line PLH.

[0112] At the semiconductor channel portions of the driving element DT and the second switching element ST2, the first semiconductor pattern A1 is not metallized. In the first semiconductor pattern A1, the source and drain of the driving element DT and the second switching element ST2 may be metallized, and a third metal layer may be formed on the semiconductor layer ACT. At the intermediate electrode CE2 of the storage capacitor Cst and the second VDD line PLH, the first semiconductor pattern A1 may be metallized, or a third metal layer may be formed on the first semiconductor pattern A1.

[0113] The drain of the second switching element ST2 is connected to a branch (omitted in the figure). The branch is connected to the REF line RL via a contact hole (omitted in the figure). At least a portion of the branch, such as a portion passing through the light-emitting region, may be formed by a metallized semiconductor layer pattern without a third metal layer, in order to improve the aperture ratio and transmittance of the light-emitting region. Therefore, the drain of the second switching element ST2 is connected to the REF line RL via the branch.

[0114] The first semiconductor pattern A1 overlaps with the second contact hole CH2 and is exposed at the second contact hole CH2. The anode AND of the light-emitting element OLED is connected to the first semiconductor pattern A1 through the second contact hole CH2, which overlaps with the first semiconductor pattern A1. A portion of the first semiconductor pattern A1 connected to the anode AND at the second contact hole CH2 is a metallized portion of the semiconductor layer ACT, or a third metal layer MA formed on the semiconductor layer.

[0115] The second semiconductor pattern A2 includes a semiconductor channel of the first switching element ST1, the source of the first switching element ST1, and the drain of the first switching element ST1. At the semiconductor channel portion of the first switching element ST1, the second semiconductor pattern A2 is not metallized. The drain of the first switching element ST1 is connected to the data line DL through a contact hole (omitted in the figure). In the second semiconductor pattern A2, the source and drain of the first switching element ST1 are metallized, or include a third metal layer formed on the semiconductor layer ACT.

[0116] The second semiconductor pattern A2 overlaps with the first contact hole CH1 and is exposed at the first contact hole CH1. At the first contact hole CH1, the exposed second semiconductor pattern A2 can be metallized, or a third metal layer can be formed on the second semiconductor pattern A2.

[0117] like Figure 8 As shown, the second metal layer ML2 includes a top gate pattern M21 and a gate line pattern M22. The top gate pattern M21 includes the top gate GE1 of the driving element DT and the upper electrode CE3 of the storage capacitor Cst. The top gate pattern M21 includes a C-shaped or... The top gate GE1 of the drive element DT and the upper electrode CE3 of the storage capacitor Cst are connected in a pattern that avoids the source of the drive element DT.

[0118] The top gate pattern M21 overlaps with the first contact hole CH1, and contacts the bottom gate pattern M12 and the second semiconductor pattern A2 through the second contact hole CH2.

[0119] Figure 10 This is a plan view illustrating the pixel circuit of a sub-pixel in a display panel according to another aspect of the present invention. Figure 11It is a diagram along Figure 10 A cross-sectional view of the pixel circuit structure taken from line II-II'. Figure 12 It is a diagram Figure 10 A plan view of the pattern of the first metal layer is shown. Figures 10 to 12 In this drawing, components that are substantially the same as those in the above aspects are indicated by the same reference numerals, and their detailed descriptions will be omitted.

[0120] Reference Figure 10 and Figure 11 The pixel circuit may further include a first slit SL1 and a second slit SL2.

[0121] A first slit SL1 is formed between the bottom gate GE2 and the data line DL to block parasitic capacitances that could cause crosstalk between them. The first slit SL1 is also formed between a long side LS1 adjacent to the bottom gate GE2 and the data line DL. Figure 10 and Figure 12 As shown, the length L1 of the first slit SL1 can be set to be substantially equal to the length L1 of one long side LS1 of the bottom gate pattern M12 (including the lower electrode CE1 of the storage capacitor Cst and the bottom gate GE2).

[0122] In the first slit SL1, all insulating layers, such as the planarization layer OS, passivation layer PAS, gate insulating layer GI, and buffer layer BUF, are removed and deeply etched during the etching process. The anode AND covers the sidewalls (or side surfaces) and bottom surface inside the first slit SL1, thereby minimizing the parasitic capacitance between the bottom gate GE2 and the data line DL.

[0123] A second slit SL2 is formed between the bottom gate GE2 and the first VDD line PLV to prevent short circuits and reduce parasitic capacitance. The second slit SL2 is also formed between the other long side LS2 adjacent to the bottom gate GE2 and the first VDD line PLV. Figure 10 and Figure 12 As shown, the length L2 of the second slit SL2 can be set to be substantially equal to the length L2 of the other long side LS2 of the bottom gate pattern M12.

[0124] The length L2 of the other long side LS2 of the bottom gate pattern M12 can be set to be less than the length L1 of one long side LS1. In the second slit SL2, insulating layers such as the gate insulating layer GI and the buffer layer BUF are removed in the etching process. The passivation layer PAS covers the side and bottom surfaces of the second slit SL2, and the planarization layer OC covers it, thus making it flat.

[0125] The objectives of the present invention, the manner in which these objectives are achieved, and the effects of the invention as described above do not specify the essential features of the claims; therefore, the scope of the claims is not limited to these specific descriptions of the invention.

[0126] Although various aspects of the invention have been described in more detail with reference to the accompanying drawings, the invention is not limited thereto, and may be implemented in many different forms without departing from the inventive concept. Therefore, the aspects disclosed in the invention are provided for illustrative purposes only and are not intended to limit the inventive concept. The scope of the inventive concept is not limited thereto. Therefore, it should be understood that the foregoing aspects are illustrative in all respects and do not limit the invention. The scope of protection of the invention should be interpreted based on the appended claims, and all inventive concepts within the equivalent scope should be interpreted as falling within the scope of the invention.

Claims

1. A display panel, comprising: First metal layer; A first insulating layer covering the first metal layer; A semiconductor layer disposed on the first insulating layer; An intermediate electrode is disposed above the semiconductor layer, the intermediate electrode is coupled to a driving element, and is separated from the semiconductor layer to form a capacitor with the first electrode and the second electrode; A second insulating layer is disposed on the first insulating layer and covers the semiconductor layer and the intermediate electrode; as well as A second metal layer disposed on the second insulating layer, The first metal layer includes: a bottom gate of the driving element; a first electrode of the capacitor for the driving element overlapping with the intermediate electrode; and a data line disposed on the same layer as the bottom gate. The second metal layer includes: a top gate of the driving element, the top gate being connected to the bottom gate through a first contact hole penetrating the second insulating layer and the first insulating layer; and a second electrode of the capacitor for the driving element overlapping the intermediate electrode. The first electrode and the second electrode of the capacitor are directly coupled through the first contact hole, and The semiconductor layer includes a semiconductor channel of the driving element, which overlaps with the top gate and the bottom gate.

2. The display panel according to claim 1, further comprising: A pixel circuit, the pixel circuit being connected to the data line providing the data voltage, the gate line providing the gate signal, the VDD line providing the pixel drive voltage, and the REF line providing the reference voltage.

3. The display panel according to claim 2, wherein the pixel circuit comprises: A first switching element is configured to apply the data voltage to the top and bottom gates of the driving element in response to the gate signal; A second switching element is configured to apply the reference voltage to the source of the driving element in response to the gate signal; as well as The light-emitting element driven by the driving element The pixel driving voltage is applied to the drain of the driving element.

4. The display panel according to claim 3, wherein the first metal layer comprises: The first-1 power line pattern for applying the pixel driving voltage; Bottom gate pattern, the bottom gate pattern including the bottom gate of the driving element and the lower electrode of the capacitor connected to the bottom gate; as well as Including the data cable pattern of the data cable, The second metal layer includes: A top gate pattern, the top gate pattern including the top gate of the driving element and the first electrode of the capacitor connected to the top gate; as well as The gate line pattern includes the gate line.

5. The display panel according to claim 4, wherein the semiconductor layer comprises: A first semiconductor pattern, comprising a semiconductor channel of the driving element, an intermediate electrode of a capacitor connected to the semiconductor channel of the driving element, a source and a drain of the driving element, a semiconductor channel of the second switching element, a source and a drain of the second switching element, and a first-second power line for applying the pixel driving voltage, wherein the first semiconductor pattern overlaps with a second contact hole. as well as The second semiconductor pattern includes the semiconductor channel of the first switching element and the source and drain of the first switching element, and the second semiconductor pattern overlaps with the first contact hole. The first-1 power line pattern and the first-2 power line intersect each other, and the first insulating layer is inserted between the first-1 power line pattern and the first-2 power line.

6. The display panel according to claim 5, further comprising: A third insulating layer is disposed on the first insulating layer and covers the second metal layer and the semiconductor layer; as well as A planarization layer disposed on the third insulating layer The anode of the light-emitting element is connected to the first semiconductor pattern through the second contact hole. The second contact hole penetrates the planarization layer and the third insulating layer to expose the first semiconductor pattern. A portion of the first semiconductor pattern connected to the anode within the second contact hole is a metallized portion of the semiconductor layer, or a metal layer formed on the semiconductor layer.

7. The display panel according to claim 6, further comprising: A first slit is located between one long side of the bottom gate pattern and the data line pattern, wherein the planarization layer, the third insulating layer, the second insulating layer, and the first insulating layer are removed from the first slit. The anode of the light-emitting element covers the side and bottom surfaces of the first slit.

8. The display panel of claim 7, wherein the length of the first slit is substantially equal to the length of one long side of the bottom gate pattern.

9. The display panel of claim 8, further comprising a second slit located between another long side of the bottom gate pattern and the first-1 power line pattern, wherein the first insulating layer and the second insulating layer are removed from the second slit, and wherein the third insulating layer covers the side surface and bottom surface of the second slit.

10. The display panel of claim 9, wherein the length of the second slit is substantially equal to the length of the other long side of the bottom gate pattern.

11. A display panel, comprising: A driving element configured to supply current to a light-emitting element; A first switching element is configured to connect a data line to the gate of the driving element in response to a gate signal from a gate line; A second switching element is configured to apply a reference voltage to the source of the driving element in response to the gate signal; as well as A capacitor, wherein the capacitor is connected between the gate of the driving element and the source of the driving element. The gate of the driving element includes a top gate and a bottom gate, and a semiconductor layer, wherein the semiconductor layer includes a semiconductor channel interposed between the top gate and the bottom gate, and the top gate overlaps with the bottom gate. The top gate contacts the bottom gate through a first contact hole, the first contact hole penetrating a first insulating layer located between the bottom gate and the semiconductor layer, and a second insulating layer located between the top gate and the semiconductor layer. The anode of the light-emitting element is in contact with the semiconductor layer through a second contact hole. The second contact hole penetrates a third insulating layer and a planarization layer disposed on the third insulating layer. The third insulating layer covers the driving element, the first switching element, and the second switching element. The bottom gate and the data line are disposed on the same layer. The capacitor described herein has: a top electrode disposed on the same layer as the top gate; and a bottom electrode disposed on the same layer as the bottom gate; and an intermediate electrode disposed between the top electrode and the bottom electrode, and the intermediate electrode being connected to the source electrode of the driving element, and The top electrode and the bottom electrode of the capacitor are directly coupled through the first contact hole, and each of the top electrode and the bottom electrode of the capacitor forms a capacitance with the intermediate electrode.

12. The display panel according to claim 11, further comprising: A first slit is located between the bottom gate and the data line, wherein the planarization layer, the third insulating layer, the second insulating layer, and the first insulating layer are removed from the first slit. The anode of the light-emitting element covers the side and bottom surfaces of the first slit.

13. The display panel according to claim 12, further comprising: The power line that applies the pixel driving voltage; as well as A second slit is located between the bottom gate pattern and the power line, wherein the first insulating layer and the second insulating layer are removed from the second slit. The third insulating layer covers the side and bottom surfaces of the second slit.

14. A display device, comprising: The display panel includes a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of first power lines for applying pixel driving voltage, a plurality of second power lines for applying reference voltage, and a plurality of pixels. A data driver configured to provide a data voltage for pixel data via the data line; as well as A gate driver configured to provide a gate signal via the gate line. Each pixel includes: A driving element configured to supply current to a light-emitting element; A first switching element is configured to connect a data line to which the data voltage is applied to the gate of the driving element in response to a gate signal from the gate line. A second switching element, configured to: apply a reference voltage lower than the pixel driving voltage to the source of the driving element in response to the gate signal; and A capacitor, wherein the capacitor is connected between the gate of the driving element and the source of the driving element. The gate of the driving element includes a top gate and a bottom gate, and a semiconductor layer, wherein the semiconductor layer includes a semiconductor channel interposed between the top gate and the bottom gate, and the top gate overlaps with the bottom gate. The top gate contacts the bottom gate through a first contact hole, the first contact hole penetrating a first insulating layer located between the bottom gate and the semiconductor layer, and a second insulating layer located between the top gate and the semiconductor layer. The anode of the light-emitting element is in contact with the semiconductor layer through a second contact hole. The second contact hole penetrates a third insulating layer and a planarization layer disposed on the third insulating layer. The third insulating layer covers the driving element, the first switching element, and the second switching element. The bottom gate and the data line are disposed on the same layer. The capacitor comprises: a top electrode disposed on the same layer as the top gate; a bottom electrode disposed on the same layer as the bottom gate; and an intermediate electrode disposed between the top electrode and the bottom electrode, wherein the intermediate electrode is connected to the source electrode of the driving element. The top electrode and the bottom electrode of the capacitor are directly coupled through the first contact hole, and each of the top electrode and the bottom electrode of the capacitor forms a capacitance with the intermediate electrode.

15. The display device according to claim 14, further comprising: A first slit is located between the bottom gate and the data line, wherein the planarization layer, the third insulating layer, the second insulating layer and the first insulating layer are removed from the first slit, wherein the anode of the light-emitting element covers the side surface and the bottom surface of the first slit.

16. The display device according to claim 15, further comprising: A second slit is located between the bottom gate and the first power line, wherein the first insulating layer and the second insulating layer are removed from the second slit. The third insulating layer covers the side and bottom surfaces of the second slit.

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