High electron mobility transistor device and method of testing the same

Abstract

The present disclosure provides a high electron mobility transistor device and a testing method, the device comprising: a source electrode (6) connected with a source electrode testing electrode layout (13); a drain electrode (7) connected with a drain electrode testing electrode layout (14); a gate electrode (8) located between the source electrode (6) and the drain electrode (7) and connected with a gate electrode testing electrode layout (15); a field plate (10) located between the gate electrode (8) and the drain electrode (7) and connected with a field plate testing electrode layout (16); wherein the source electrode testing electrode layout (13), the drain electrode testing electrode layout (14), the gate electrode testing electrode layout (15) and the field plate testing electrode layout (16) are electrically insulated from each other. The device can separately add bias to radio frequency signals and direct current signals to improve the power efficiency characteristics of the device; in addition, the field plate bias has different suppression effects on the electric field under the gate in different states, which improves the working voltage of the device and further realizes high power application.

Description

Technical Field

[0001] This disclosure relates to the field of electronic information technology, and more specifically to a high electron mobility transistor device and a testing method thereof. Background Technology

[0002] GaN-based high electron mobility transistors (HEMTs) are core components of power amplifiers. Currently, GaN-based devices have entered the millimeter-wave band of research, further expanding their application areas and placing higher demands on device performance. One of the challenges facing GaN-based HEMTs is the impact of high electric field strength. Especially with the advancement of millimeter-wave applications, the source-drain spacing is further shortened, and the increased peak electric field at the gate pin severely limits the high-voltage, high-power applications of these devices. Conventional methods to suppress electric field strength include introducing field-plate structures. However, for millimeter-wave devices, the introduction of field-plate structures introduces significant parasitic capacitance, severely affecting the device's frequency characteristics and hindering the realization of high-frequency, high-power devices. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] In view of the above-mentioned technical problems, the main objective of this disclosure is to provide a high electron mobility transistor device to solve at least one of the above-mentioned technical problems.

[0005] (II) Technical Solution

[0006] To achieve the above objectives, this disclosure provides a high electron mobility transistor device, comprising,

[0007] The source electrode is connected to the source electrode test electrode layout (Pad);

[0008] Drain electrode, which is connected to the drain test pad;

[0009] The gate, located between the source and drain, is connected to the gate test pad.

[0010] The field plate, located between the gate and drain, is connected to the field plate test pad.

[0011] Among them, the source test pad, drain test pad, gate test pad and field plate test pad are electrically isolated from each other.

[0012] Optionally, the device further includes a second semiconductor layer, on which the source, drain, gate, and field plate are grown.

[0013] Optionally, the device further includes a second semiconductor layer, with a passivation layer deposited between the source and drain, and a field plate disposed on the passivation layer.

[0014] Optionally, the passivation layer is etched to form a groove, and the field plate is located on the groove, the depth of which is 0–120 nm.

[0015] Optionally, the field plate can be a Γ-shaped field plate, a T-shaped field plate, or a vertical field plate.

[0016] Optionally, the Γ-shaped field plate includes a first part and a second part that are interconnected. The second part is located on the side of the first part away from the second semiconductor layer and forms an angle with the first part. The second part and the side of the first part away from the second semiconductor layer have a common first surface. The third sidewall of the second part near the gate and the second sidewall of the first part near the gate are located on the same boundary line. The second part at least covers the portion between the second sidewall of the first part and the first sidewall of the first part near the drain. There is a first air gap between the first sidewall and the surface of the second part near the drain and the surface of the drain away from the second semiconductor layer.

[0017] Optionally, the length of the second portion along the direction from the gate to the drain is less than or equal to the distance between the gate and the drain.

[0018] Optionally, the field plate grid foot structure can be right-angled, U-shaped, or V-shaped.

[0019] Optionally, the length of the field plate test pad is greater than or equal to 50 μm, and its width is greater than or equal to 50 μm.

[0020] Another aspect of this disclosure provides a testing method for a high electron mobility transistor device, comprising: S1, connecting the source, drain, gate, and field plate to corresponding test pads respectively; S2, performing radio frequency testing on the device by applying a DC signal to the field plate and an radio frequency signal to the gate; S3, performing DC testing on the device by applying a DC signal to the field plate and applying a preset voltage or not applying a voltage to the field plate as required for testing.

[0021] (III) Beneficial Effects

[0022] The high electron mobility transistor device disclosed herein has the following advantages:

[0023] (1) By adding a field board test pad and connecting the field board lead to the field board test pad separately, during RF testing, RF bias is added to the gate and DC bias is added to the field board, thus realizing the separate addition of RF signal and DC signal and improving the efficiency of the device.

[0024] (2) By adjusting the different bias states of the field plate, the electric field distribution at the edge of the gate foot can be well suppressed, the breakdown characteristics of the device can be improved, and an enhancement device can be realized. Attached Figure Description

[0025] Figure 1 A schematic top view of the HEMT device structure proposed in an embodiment of this disclosure is shown.

[0026] Figure 2 A HEMT device according to an embodiment of the present disclosure is schematically illustrated, wherein Figure 2 for Figure 1 A cross-sectional view of the portion within the dashed line along the AA direction;

[0027] Figure 3 A HEMT device according to another embodiment of this disclosure is schematically shown, wherein Figure 3 for Figure 1 A cross-sectional view of the portion within the dashed line along the AA direction;

[0028] Figure 4 A HEMT device according to yet another embodiment of this disclosure is schematically shown, wherein Figure 4 for Figure 1 A cross-sectional view of the portion within the dashed line along the AA direction;

[0029] Figure 5 The diagram shows the simulated distribution of the electric field intensity under the gate of the HEMT device of this disclosure and the HEMT device in the prior art during DC signal testing, with the field plate biased under different conditions.

[0030] Figure 6 for Figure 5 Enlarged view of the area indicated by the dashed line;

[0031] Figure 7 The simulation results of DC transfer for HEMT devices in the prior art under different barrier layer thicknesses are shown.

[0032] Figure 8 The simulation results of DC transfer of the HEMT device proposed in this disclosure under different barrier layer thicknesses are shown.

[0033] Figure 9 A flowchart illustrating the HEMT device fabrication method proposed in this disclosure is shown schematically.

[0034] Figure 10 A flowchart illustrating the HEMT device testing method proposed in an embodiment of this disclosure is shown schematically.

[0035] Explanation of reference numerals in the attached figures

[0036] 1-Substrate; 2-First semiconductor layer; 3-Insertion layer; 4-Second semiconductor layer; 5-Cap layer; 6-Source; 7-Drain; 8-Gate; 9-Passivation layer; 10-Field plate; 11-Groove; 12-Nucleation layer; 13-Source test pad; 14-Drain test pad; 15-Gate test pad; 16-Field plate test pad; 101-First part of Γ-type field plate; 102-Second part of Γ-type field plate; 110-First air gap. Detailed Implementation

[0037] To make the purpose, technical solution and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific details and with reference to the accompanying drawings.

[0038] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0039] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0040] As introduced in the background section, the field plate structure introduced by existing HEMT devices to suppress electric field strength will bring about a large parasitic capacitance, which will seriously affect the frequency characteristics of the device. This is detrimental to the realization of high-frequency and high-power devices. Therefore, it is very important to optimize the field plate structure of millimeter-wave devices to suppress the electric field while reducing its impact on the frequency characteristics of the device.

[0041] To address the aforementioned issues, this application has discovered through research that dual-gate structures offer significant advantages in improving device power efficiency. By separating the RF signal and DC signal for biasing, the operating voltage, power, and efficiency of the device can be effectively increased. Therefore, designing a rationally designed and standardized field plate structure and peripheral test pads is crucial to both meet testing requirements and minimize parasitic effects from the test pads. Based on this, this application proposes a HEMT device.

[0042] Figure 1 A schematic top view of a HEMT device according to an embodiment of this disclosure is shown, such as... Figure 1As shown, the HEMT device includes a source 6 connected to a source test pad 13; a drain 7 connected to a drain test pad 14; a gate 8 located between the source 6 and the drain 7 and connected to a gate test pad 15; and a field plate 10 located between the gate 8 and the drain 7 and connected to a field plate test pad 16. The source test pad 13, drain test pad 14, gate test pad 15, and field plate test pad 16 are electrically isolated from each other.

[0043] In this disclosure, the source 6 and drain 7 are formed by stacking titanium, aluminum, nickel and gold layers, the gate 8 is formed by stacking nickel and gold layers, and the field plate 10 can be formed by stacking nickel and gold layers or by stacking titanium and gold layers.

[0044] Furthermore, for ease of testing, the field plate test pad 16 of the HEMT device disclosed herein has a length greater than or equal to 50 μm and a width greater than or equal to 50 μm. The materials and dimensions of the field plate test pad and other test pads in this disclosure can be selected according to actual testing needs, as long as the testing requirements are met.

[0045] In the aforementioned HEMT device, by adding a field plate test pad 16 and connecting the field plate 10 to the field plate test pad 16 with a separate lead, the following effects can be achieved: On the one hand, during RF testing of the device, a DC bias can be added to the field plate 10 and an RF bias can be added to the gate 8, achieving separation of RF and DC signals and improving device efficiency. On the other hand, during DC testing of the device, any bias that meets the test requirements can be added to the field plate 10 according to the test performance requirements, which can effectively suppress the electric field strength at the edge of the gate 8 pin, increase the operating voltage of the device, and achieve enhancement-mode device earlier.

[0046] In embodiments of this disclosure, a HEMT device is provided, such as... Figure 2As shown, the HEMT device further includes a substrate 1, a first semiconductor layer 2, and a second semiconductor layer 4. The first semiconductor layer 2 is grown on the surface of the substrate 1, and the second semiconductor layer 4 is grown on the surface of the first semiconductor layer 2 away from the substrate 1. The first semiconductor layer 2 and the second semiconductor layer 4 form a heterojunction, and a two-dimensional electron gas (2-DEG) is generated between the first semiconductor layer 2 and the second semiconductor layer 4. The source electrode 6, the drain electrode 7, the gate electrode 8, and the field plate 10 are grown on the surface of the second semiconductor layer 4 away from the first semiconductor layer 2. The gate electrode 8 is located between the source electrode 6 and the drain electrode 7, and the field plate 10 is located between the gate electrode 8 and the drain electrode 7. The source electrode 6, the drain electrode 7, the gate electrode 8, and the field plate 10 are respectively connected to the corresponding test pads, that is, the source electrode 6 is connected to the source test pad 13, the drain electrode 7 is connected to the drain test pad 14, the gate electrode 8 is connected to the gate test pad 15, and the field plate 10 is connected to the field plate test pad 16.

[0047] In this disclosure, the substrate material includes silicon carbide, and the materials of the first semiconductor layer and the second semiconductor layer can be any two semiconductor materials in the prior art capable of forming a two-dimensional electron gas. Those skilled in the art can select appropriate materials to form the first and second semiconductor layers according to the actual situation. In the embodiments of this disclosure, the material of the first semiconductor layer includes GaN, and the material of the second semiconductor layer includes AlGaN.

[0048] In another embodiment of this disclosure, such as Figure 3 As shown, the HEMT device further includes a passivation layer 9 deposited between the source 6 and the drain 7, with the field plate 10 disposed on the passivation layer 9. The passivation layer 9 covers the exposed surfaces of the second semiconductor layer 4 and the gate 8, thereby suppressing current collapse and further protecting the device. The passivation layer material in this disclosure can be any conventional insulating dielectric material in the semiconductor field, such as silicon nitride, aluminum nitride, or aluminum oxide, as long as it can suppress current collapse.

[0049] Furthermore, in embodiments of this disclosure, such as Figure 3 As shown, the passivation layer 9 can also be etched to form a groove 11, and the field plate 10 can be disposed on the groove 11, wherein the depth of the groove is 0 to 120 nm.

[0050] In the aforementioned HEMT device, the field plate 10 is disposed on the groove 11 etched in the passivation layer 9, and the passivation layer 9 below the field plate has a relatively small thickness. The field plate 10 can also penetrate the passivation layer 9 and directly contact the second semiconductor layer 4. By etching the groove 11 on the passivation layer 9, the distance between the field plate 10 and the channel carriers is shortened in the vertical direction. This effectively reduces the electric field strength at the gate edge, thereby further improving the breakdown voltage of the device, i.e., increasing the operating voltage of the device and increasing the output power of the device. The passivation layer 9 can also better protect the gate 8 and other structures, further ensuring the reliability of the device.

[0051] In yet another embodiment of this disclosure, such as Figure 4 As shown, the HEMT device further includes: an insertion layer 3, a cap layer 5, and a nucleation layer 12. The insertion layer 3 is located between the first semiconductor layer 2 and the second semiconductor layer 4 to improve the thresholding capability of the two-dimensional electron gas (2-DEG). The cap layer 5 is disposed on the surface of the second semiconductor layer 4 away from the first semiconductor layer 1 to protect the interface of the second semiconductor layer 4. The nucleation layer 12 is located between the substrate 1 and the first semiconductor layer 2 to improve the nucleation quality of the first semiconductor layer 2.

[0052] The insertion layer, cap layer, and nucleation layer in this disclosure can be made of appropriate materials according to the actual situation, as long as they can achieve the above functions. For example, the material of the insertion layer may include AlN, the material of the cap layer may include GaN, and the material of the nucleation layer may include AlN.

[0053] In this embodiment of the disclosure, when the field plate 10 is disposed on the groove 11, the etching depth of the groove 11 needs to take into account the distance between the field plate 10 and the gate 8 and the drain 7, as well as the length of the field plate 10 in the direction from the gate 8 to the drain 7. For example, when the etching depth of the groove 11 is greater than or equal to 80nm, the peak electric field strength of the field plate gate foot may exceed the peak electric field strength of the gate foot due to the deep etching depth. In this case, the field plate 10 needs to be extended to a certain distance in the direction from the gate 8 to the drain 7. This can suppress or avoid the electric field strength at the edge of the field plate gate foot caused by the introduction of the field plate.

[0054] In this embodiment, the position of the field plate 10 between the gate 8 and the drain 7 affects its suppression effect on the gate foot electric field strength. For example, when the field plate 10 is close to the gate 8, the field plate 10 has a strong suppression effect on the gate foot electric field strength, while when the field plate 10 is close to the drain 7, the suppression effect on the gate foot electric field strength is not obvious.

[0055] The field plate 10 described in this disclosure can be any structure, and those skilled in the art can select a gate with a suitable structure according to the actual situation.

[0056] In this embodiment of the disclosure, the field plate 10 structure of the HEMT device can be a Γ-shaped field plate, a T-shaped field plate, or a vertical field plate. Further, the gate pin structure of the field plate 10 can be right-angled, U-shaped, V-shaped, or other suitable structures.

[0057] like Figures 2-4 As shown, the Γ-type field plate structure 10 of this disclosure includes a first portion 101 and a second portion 102 interconnected. The second portion 102 is located on the side of the first portion 101 away from the second semiconductor layer 4 and forms an angle with the first portion 101. The second portion 102 and the side of the first portion 101 away from the second semiconductor layer 4 share a common first surface. The third sidewall of the second portion 102 near the gate 8 and the second sidewall of the first portion 101 near the gate 8 are located on the same boundary line. The second portion 102 at least covers the portion between the second sidewall of the first portion 101 and the first sidewall of the first portion 101 near the drain 7. A first air gap 110 exists between the first sidewall and the surface of the second portion 102 near the drain 7 and the surface of the drain 7 away from the second semiconductor layer 4.

[0058] In this embodiment of the disclosure, the first part 101 and the second part 102 may be formed by a plane or a curved surface (e.g., an S-shaped curved surface), or they may be formed by a curved surface and a plane. The included angle between the first part 101 and the second part 102 may be an acute angle or a right angle, or other suitable included angles.

[0059] The first air gap in this disclosure is not limited to those described above. Figures 2-4 The form in the middle can also be other forms.

[0060] Furthermore, in this embodiment of the present disclosure, the length of the second portion 102 along the direction from the gate 8 to the drain 7 is less than or equal to the distance between the gate 8 and the drain 7. This design can effectively suppress or avoid the influence of the electric field strength at the edge of the field plate gate due to the introduction of the field plate when the field plate etching depth is deep (e.g., etching depth greater than or equal to 80 nm).

[0061] In this embodiment, the T-shaped field plate structure differs from the aforementioned Γ-shaped field plate structure in that the second portion of the T-shaped field plate structure, which is connected to the first portion, extends a certain distance in the direction from the drain 7 to the gate 8, and a second air gap exists between the surface of the extended portion of the second portion of the T-shaped field plate structure near the gate 8 and the surface of the gate 8 away from the second semiconductor layer 4. Other features of the T-shaped field plate structure are the same as those of the Γ-shaped field plate structure and will not be repeated here.

[0062] In this embodiment, the vertical field plate structure differs from the above-described Γ-shaped field plate structure in that the vertical field plate does not have a second part. Other features are the same as those of the above-described Γ-shaped field plate structure, and will not be repeated here.

[0063] In another embodiment of this disclosure, a method for fabricating a high electron mobility transistor device is provided, the process of which is as follows: Figure 9 As shown, the preparation method specifically includes:

[0064] S1, a source, a drain, and a gate are grown on the second semiconductor layer, wherein the gate is located between the source and the drain, and the source and the drain form an ohmic contact;

[0065] S2, a passivation layer is deposited between the source and the drain using plasma-enhanced chemistry vapor deposition.

[0066] S3, using the dry ICP method, a groove is etched on the passivation layer to form a groove;

[0067] S4, a field plate structure is formed on the above-mentioned groove using multilayer photoresist lithography, and then the metal is evaporated and peeled off to obtain the field plate structure;

[0068] S5 uses a Ti / Ni / Ti / Au / Ti metal stack to form the peripheral pad layout, and brings out the source, drain, gate and field plate for testing.

[0069] In yet another embodiment of this disclosure, a testing method for high electron mobility transistor devices is also provided, the process of which is as follows: Figure 10 As shown, it specifically includes:

[0070] S1, connect the source 6, drain 7, gate 8, and field plate 10 to the corresponding test pads respectively;

[0071] S2, perform RF testing on the device, add a DC signal to the field board 10 and an RF signal to the gate 8;

[0072] S3, perform DC testing on the device, add a DC signal to the field board 10, and apply a preset voltage or no voltage to the field board 10 as required by the test.

[0073] S4, End of test.

[0074] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions of this disclosure will be described below in conjunction with specific embodiments.

[0075] Example

[0076] The structure of HEMT devices is as follows: Figure 4As shown, specifically, it includes a substrate 1, a first semiconductor layer 2, an insertion layer 3, a second semiconductor layer 4, a cap layer 5, a source 6, a drain 7, a gate 8, a passivation layer 9, a field plate 10, a groove 11, a nucleation layer 12, a source test pad 13, a drain test pad 14, a gate test pad 15, and a field plate test pad 16.

[0077] Specifically, the substrate 1 is a SiC substrate, the first semiconductor layer 2 is a GaN layer with a thickness of 2.5 μm, the insertion layer 3 is an AlN layer with a thickness of 1 nm, the second semiconductor layer 4 is an AlGaN layer with a thickness of 20 nm, and the cap layer 5 is a GaN layer with a thickness of 1 nm; the source 6 and the drain 7 are formed by stacking titanium, aluminum, nickel, and gold layers, and the distance between the source 6 and the drain 7 is 2.4 μm; the gate 8 is formed by stacking nickel and gold layers, the gate 8 has a vertical width of 200 nm, a height of 450 nm, and a horizontal width of 600 nm, and the distance between the gate 8 and the drain is 1.4 μm; the passivation layer 9 is a silicon nitride layer and has a groove 11 with a groove width of 400 nm, a passivation layer thickness of 30 nm below the groove 11, a passivation layer thickness of 120 nm at other locations, and a distance of 300 nm between the side of the groove 11 closest to the gate and the gate 8.

[0078] The field plate 10 is formed by stacking titanium and gold layers. The field plate 10 is a U-shaped field plate, comprising a first part 101 and a second part 102. The first part is a vertical structure with a width of 200 nm and a height of 450 nm. The second part is a horizontal structure with a right angle between the first and second parts. The second part covers the portion between the second sidewall of the first part 101 and the first sidewall of the first part 101 near the drain 7, and has a length of 400 nm. The first part is located in the groove 11 formed by etching the passivation layer 9. A first air gap 110 exists between the first sidewall and the surface of the second part 102 near the drain 7 and the surface of the drain 7 away from the second semiconductor 4. The nucleation layer 12 is an AlN layer with a thickness of 2 nm. The source test pad 13, drain test pad 14, gate test pad 15, and field plate test pad 16 are formed by stacking Ti / Ni / Ti / Au / Ti metals.

[0079] During the testing of the HEMT device, voltages were applied to the field plate 10 and the gate 8 according to the experimental requirements. A DC signal was applied to the field plate 10 and an RF signal was applied to the gate 8.

[0080] Comparative Example

[0081] The difference from the embodiment is that the HEMT device does not include the field plate test Pad 16 and the field plate 10. The gate 8 is connected to the gate test Pad 15 through a lead. During the test, a voltage is applied to the gate 8 according to the experimental requirements. DC signal and radio frequency signal are added to the gate 8 according to the test requirements.

[0082] Figure 5 This is a diagram showing the distribution of the electric field intensity under the gate of the HEMT device in the off-state state when the gate voltage, source voltage, and no voltage are applied, respectively, during DC signal testing of the simulated comparative and embodiment examples. Figure 6 for Figure 5 Enlarged view of the area indicated by the dashed line. The gate voltage Vgs = -6V, and the source is grounded.

[0083] Depend on Figure 5 and Figure 6 It can be clearly seen that: (1) Under the same bias (Vgs=-6V), the HEMT device in this embodiment has a more significant suppression effect on the gate peak electric field compared with the HEMT device in the prior art; (2) The field plate bias has different suppression effects on the gate electric field under different states; (3) The relationship between the field plate bias condition and the strength of the suppressed electric field is: field plate bias with gate voltage > field plate bias with source voltage > no voltage applied to the field plate.

[0084] Figure 7 and Figure 8 The simulation results curves show the DC transfer of HEMT devices in the comparative and example embodiments under different barrier layer thicknesses. The device drain voltage Vds = 10V, gate bias voltage Vgs: -6 to 2V, field plate voltage Vgs2 = 0V, and source grounded.

[0085] Depend on Figure 7 and Figure 8 The comparison shows that: (1) as the barrier layer thickness decreases, the threshold voltage of the HEMT device in this embodiment drifts positively, and the enhancement-mode device is gradually realized; (2) under the same barrier layer thickness, the HEMT device in this embodiment can realize the enhancement-mode device earlier than the HEMT device in the comparative example.

[0086] In summary, this disclosure provides a high electron mobility transistor device. By adding a field plate test pad and connecting the field plate lead separately to the test pad, on the one hand, during RF testing, RF bias is applied to the gate and DC bias is applied to the field plate, achieving separate application of RF and DC signals and improving device efficiency. On the other hand, by adjusting different bias states of the field plate, the electric field distribution at the gate edge can be effectively suppressed, improving the breakdown characteristics of the device and realizing an enhancement-mode device.

[0087] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A high electron mobility transistor device, characterized in that, include: Source electrode (6), which is connected to the source electrode test electrode layout (13); Drain (7), which is connected to the drain test electrode layout (14); The gate (8) is located between the source (6) and the drain (7) and is connected to the gate test electrode layout (15); A field plate (10) is located between the gate (8) and the drain (7) and is connected to the field plate test electrode layout (16). The field plate (10) is a Γ-type field plate, which includes a first part (101) and a second part (102) that are connected to each other. The high electron mobility transistor device also includes: A second semiconductor layer (4) has a passivation layer (9) deposited between the source (6) and the drain (7). A field plate (10) is disposed on the passivation layer (9). A groove (11) is etched on the passivation layer (9). The field plate (10) is located on the groove (11). The depth of the groove (11) is 0~120nm. The second portion (102) is located on the side of the first portion (101) away from the second semiconductor layer (4) and forms an angle with the first portion (101). The second portion (102) and the side of the first portion (101) away from the second semiconductor layer (4) share a common first surface. The third sidewall of the second portion (102) near the gate (8) and the second sidewall of the first portion (101) near the gate (8) are located on the same boundary line. The second portion (102) at least covers the portion between the second sidewall of the first portion (101) and the first sidewall of the first portion (101) near the drain (7). A first air gap (110) exists between the first sidewall and the surface of the second portion (102) near the drain (7) and the surface of the drain (7) away from the second semiconductor layer (4). The source test electrode layout (13), the drain test electrode layout (14), the gate test electrode layout (15) and the field plate test electrode layout (16) are electrically insulated from each other; The field plate (10) is configured such that when the depth of the groove (11) is greater than or equal to 80 nm, the field plate (10) extends to a specified distance along the direction from the gate (8) to the drain (7).

2. The high electron mobility transistor device according to claim 1, characterized in that, The source (6), the drain (7), the gate (8) and the field plate (10) are grown on the second semiconductor layer (4).

3. The high electron mobility transistor device according to any one of claims 1 to 2, characterized in that, The field plate (10) also includes a T-shaped field plate or a vertical field plate.

4. The high electron mobility transistor device according to claim 1, characterized in that, The length of the second part (102) along the direction from the gate (8) to the drain (7) is less than or equal to the distance between the gate (8) and the drain (7).

5. The high electron mobility transistor device according to claim 1, characterized in that, The field plate (10) has a right-angle, U-shaped, or V-shaped grid foot structure.

6. The high electron mobility transistor device according to claim 1, characterized in that, The length of the field plate test electrode layout (16) is greater than or equal to 50 μm, and its width is greater than or equal to 50 μm.

7. A testing method for a high electron mobility transistor device, used to test the high electron mobility transistor device as described in any one of claims 1 to 6, characterized in that, include: S1, connect the source (6), drain (7), gate (8), and field plate (10) to the corresponding test electrode layout respectively; S2, perform radio frequency testing on the device, add a DC signal to the field plate (10), and add a radio frequency signal to the gate (8); S3, perform a DC test on the device, add a DC signal to the field plate (10), and apply a preset voltage or no voltage to the field plate (10) as required by the test.

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