Isolation power chip based on dead zone control symmetrical class-d oscillator

Abstract

The present disclosure provides an isolated power supply chip based on dead zone control symmetrical class-D oscillator, comprising: a transmitting stage oscillator circuit connected to a power supply and a ground, the transmitting stage oscillator circuit being used for inverting an input DC voltage into a differential high-frequency oscillation power signal and inputting the differential high-frequency oscillation power signal to a primary coil of a subsequent transformer; a rectifier circuit connected to a secondary coil of the transformer, the rectifier circuit being used for rectifying the differential high-frequency oscillation power signal to output a DC voltage signal; and a feedback control circuit connected to the rectifier circuit, the feedback control circuit being used for feeding back the DC voltage signal to the transmitting stage oscillator circuit to modulate and stabilize the DC voltage signal; wherein the transmitting stage oscillator circuit comprises a dead zone control module, and a symmetrically arranged NMOS tube group and a PMOS tube group connected to the dead zone control module, the dead zone control module being used for controlling the on-off of the NMOS tube group and the PMOS tube group to eliminate a short-circuit current between the power supply and the ground.

Description

Technical Field

[0001] This disclosure belongs to the field of isolated power supply technology, and particularly relates to an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator. Background Technology

[0002] Isolated power supply chips are widely used in automotive electronics, biomedical, defense electronic systems, and communication systems. They play a crucial role in ensuring the safety and reliability of noise-sensitive equipment operating under extreme conditions. As isolated power supply chips become smaller, the frequency and power density of internal power oscillation signals also increase. This often makes the isolated power supply chip a source of radiation, interfering with other electronic devices and causing electromagnetic interference (EMI). This radiation includes unilateral radiation and dipole radiation. Unilateral radiation can generally be addressed by using bypass capacitors on both sides of the isolated power supply. The main problem with isolated power supply chips is the difficulty in eliminating dipole radiation from input to output. EMI testing is a crucial certification process for electronic devices before they become finished products. However, traditional methods for reducing EMI with isolated power supply chips focus on the application level, using at least four layers of interconnected capacitors and ferrite beads on the PCB. This significantly increases design costs and fails to fundamentally solve the EMI radiation problem, while also resulting in low conversion efficiency. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] To address the aforementioned issues, this disclosure provides an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator, thereby alleviating the difficulty of effectively and cost-effectively solving technical problems such as EMI radiation in existing isolated power supply chips.

[0005] (II) Technical Solution

[0006] This disclosure provides an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator, comprising: an emitter oscillator circuit connected to a power supply and ground, the emitter oscillator circuit being used to invert an input DC voltage into a differential high-frequency oscillation power signal and input it to the primary coil of a subsequent transformer; a rectifier circuit connected to the secondary coil of the transformer, used to rectify the differential high-frequency oscillation power signal to output a DC voltage signal; and a feedback control circuit connected to the rectifier circuit, used to feed back the DC voltage signal to the emitter oscillator circuit, thereby modulating and stabilizing the DC voltage signal; wherein, the emitter oscillator circuit includes: a dead-time control module, and symmetrically arranged NMOS transistor groups and PMOS transistor groups connected to the dead-time control module, the dead-time control module eliminating the short-circuit current between the power supply and ground by controlling the on / off state of the NMOS transistor groups and PMOS transistor groups.

[0007] According to an embodiment of this disclosure, the dead-time control module controls the on / off state of the NMOS transistor group and the PMOS transistor group based on the high-frequency oscillation power signal at both ends of the primary coil of the sampling transformer to achieve dead-time control.

[0008] According to an embodiment of this disclosure, the dead-time control module outputs a control voltage signal based on the high-frequency oscillation power signal at both ends of the primary coil of the sampling transformer to control the on / off state of each power transistor in the NMOS and PMOS transistor groups to achieve dead-time control.

[0009] According to embodiments of this disclosure, the NMOS transistor group includes a first NMOS transistor and a second NMOS transistor; the PMOS transistor group includes a first PMOS transistor and a second PMOS transistor.

[0010] According to an embodiment of this disclosure, the isolated power supply chip further includes: a switch, one end of which is grounded or powered, and the other end of which is connected to the emitter oscillator circuit. The switch is used to control whether the emitter oscillator circuit oscillates by switching on and off according to the DC voltage signal fed back by the feedback control circuit.

[0011] According to an embodiment of this disclosure, the emitter-stage oscillator circuit includes the following states:

[0012] State 1: The second NMOS transistor and the first PMOS transistor are turned on, and the inductor current I... L It is a negative value;

[0013] State 2: The second NMOS transistor and the first PMOS transistor are turned on, and the inductor current I... L It is a positive value;

[0014] State 3: The second NMOS transistor and the first PMOS transistor are turned off first, and the voltage V output by the dead-time control module is... GN2 and V GP1 Reaching V respectively THN and V DD -|VTHP At this point, a dead time occurs, all four power transistors are turned off, and the inductor current I... L Continuous streaming;

[0015] State 4: The first NMOS transistor and the second PMOS transistor are turned on, and the inductor current I... L It is a positive value;

[0016] State 5: The first NMOS transistor and the second PMOS transistor are turned on, and the inductor current I... L It is a negative value;

[0017] State 6: The first NMOS transistor and the second PMOS transistor are turned off first, and the voltage V output by the dead-time control module is... GN1 and V GP2 Reaching V respectively THN and V DD -|V THP At this point, a dead time occurs, all four power transistors are turned off, and the inductor current I... L Continuous streaming;

[0018] The threshold voltage of the NMOS transistor group is V. THN The threshold voltage of the PMOS transistor group is V. THP This corresponds to the high-frequency oscillating power signal V at the first end of the primary coil of the transformer. PP This corresponds to the high-frequency oscillating power signal V at the second terminal of the primary coil of the transformer. PN The inductor current generated by the primary coil of the transformer is I. L The voltage of the power supply is V. DD V GN1 V is the gate voltage of the first NMOS transistor output by the dead-time control module. GN2 V is the gate voltage of the second NMOS transistor output by the dead-time control module. GP1 V is the gate voltage of the first PMOS transistor output by the dead-time control module. GP2 This is the gate voltage of the second PMOS transistor output by the dead-time control module.

[0019] According to an embodiment of this disclosure, the dead-time control module includes a first bias voltage, a second bias voltage, a first bias resistor, a second bias resistor, a third bias resistor, a fourth bias resistor, a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, and a fourth coupling capacitor.

[0020] According to an embodiment of this disclosure, the gate of the first NMOS transistor is connected to the drain of the second NMOS transistor through a first coupling capacitor, the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor through a second coupling capacitor, the gate of the first PMOS transistor is connected to the drain of the second PMOS transistor through a third coupling capacitor, and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor through a fourth coupling capacitor.

[0021] According to an embodiment of this disclosure, a first bias voltage is connected to the gate of a first NMOS transistor through a first bias resistor and to the gate of a second NMOS transistor through a second bias resistor; a second bias voltage is connected to the gate of a first PMOS transistor through a third bias resistor and to the gate of a second PMOS transistor through a fourth bias resistor.

[0022] According to embodiments of this disclosure, the common-mode voltage of an NMOS transistor group or a PMOS transistor group is adjusted using a first bias voltage or a second bias voltage to achieve dead-time control.

[0023] (III) Beneficial Effects

[0024] As can be seen from the above technical solution, the isolation power supply chip based on the dead-time control symmetrical Class D oscillator disclosed herein has at least one or a portion of the following beneficial effects:

[0025] (1) Suppress common-mode current to reduce dipole radiation, and achieve a low EMI radiation solution at the device level;

[0026] (2) It effectively eliminates the short-circuit current of the complementary Class D oscillator, improves the conversion efficiency of the oscillator, does not affect the original symmetrical topology, and improves the service life of the power transistor.

[0027] (3) No high-voltage LDMOS is required; only low-voltage MOS transistors are needed. Low-voltage MOS transistors have lower on-resistance, which effectively improves the conversion efficiency of the oscillator and reduces the process cost. Attached Figure Description

[0028] Figure 1 This is a block diagram of an isolated power supply chip system based on a traditional cross-coupled LC oscillator.

[0029] Figure 2 This is a block diagram of an isolated power supply chip system based on a traditional complementary Class D oscillator.

[0030] Figure 3 This is a schematic diagram of the short-circuit current generation mechanism in a traditional complementary Class D oscillator.

[0031] Figure 4 This is a block diagram of an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator, according to an embodiment of this disclosure.

[0032] Figure 5 This is a schematic diagram of the state and waveforms of the transmitter oscillator circuit in an embodiment of this disclosure.

[0033] Figure 6 This is a block diagram showing the specific composition of an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator according to an embodiment of this disclosure.

[0034] Figure 7a The differential high-frequency oscillation power signal V in this embodiment of the disclosure PN A schematic diagram of dead zone control during the descent process.

[0035] Figure 7b The differential high-frequency oscillation power signal V in this embodiment of the disclosure PP A schematic diagram of dead zone control during the ascent process.

[0036] Figure label:

[0037] 100-Oscillator;

[0038] 200 - Transformer;

[0039] 10-Emitter stage oscillator circuit;

[0040] 20 - Transformer;

[0041] 30 - Rectifier circuit;

[0042] 40 - Feedback control circuit;

[0043] 101-Dead Zone Control Module;

[0044] 102 - Switch. Detailed Implementation

[0045] This disclosure provides an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator. By setting the turn-on and turn-off sequence of the power transistor through the oscillator (or oscillation circuit) topology, short-circuit current is avoided, thereby improving the power conversion efficiency and reliability of the oscillator.

[0046] An isolated power supply chip typically consists of three parts: a DC-AC inverter circuit at the transmitter, an AC-AC power transmission isolation barrier using a transformer, and an AC-DC rectifier circuit at the receiver. Reducing EMI radiation at the device level while improving converter efficiency is a significant technical challenge for isolated power supply chips. Dipole radiation is a radiation source formed by high common-mode current generated on distributed parasitic capacitances due to the large swing of common-mode voltage across the primary and secondary windings of a transformer. Based on this, this disclosure proposes a transmitter topology of a symmetrical Class D oscillator with dead-time control to address dipole radiation, the main radiation source in isolated power supply chips. By using a fully symmetrical structure at the transmitter of the isolated power supply, the common-mode current of the system is reduced at the chip level. Reducing EMI radiation is the main technical problem this disclosure aims to solve. For example, in a complementary Class D oscillator, when the differential oscillation signal flips, all four power transistors are turned on simultaneously, resulting in a momentary short-circuit current flowing from the power supply to ground through the power transistors. This causes additional losses, reducing the oscillator's power conversion efficiency, and can also damage the power transistors, causing the chip to fail. Based on this, this disclosure proposes a dead-time control method for short-circuit current cancellation technology to address the short-circuit current problem in complementary Class D oscillators. By setting the turn-on and turn-off sequence of the power transistors through the proposed oscillator topology, short-circuit current is avoided, thereby improving the oscillator's power conversion efficiency and reliability.

[0047] Dipole radiation is the primary radiation generated by isolated power supplies. This radiation is produced because the current on the isolation barrier cannot form a loop and radiates through an equivalent dipole antenna. Since there is no actual physical loop between the two reference grounds, it can only radiate outwards as electromagnetic waves, making this radiation source difficult to eliminate. When the common-mode voltage generated by the oscillator at the transmitting end passes through the isolation barrier, a common-mode current I is generated due to the distributed parasitic capacitance between the primary and secondary coils of the transformer. CM This results in dipole radiation from input to output. In this case, the transformer can be regarded as a dipole antenna, and the dipole radiation power can be expressed as:

[0048] P rad ∝(L ant f CM I CM ) 2 (1);

[0049] Where L ant f CM and I CM These represent the length of the dipole antenna, the common-mode current frequency, and the amplitude, respectively. Common-mode current I CM The formula for calculating the primary and secondary common-mode voltage is:

[0050]

[0051]

[0052] Where C ISO V is the parasitic capacitance between the primary and secondary coils of the transformer. pri_CM and V sec_CM These are the common-mode voltages of the primary and secondary windings, respectively. According to formula (2), the common-mode current I can be reduced by decreasing the rate of change of the common-mode voltage between the primary and secondary windings. CM .

[0053] EMI radiation is assessed by measuring the electric field strength of the received radiation source using a spectrum analyzer or EMI receiver. The electric field strength quantifies the magnitude of the interference voltage of the radiation source. As mentioned above, the dipole radiation source is determined by the magnitude of the common-mode current. Therefore, the spectrum of the common-mode current is used to characterize the intensity of EMI radiation within a certain frequency range. The spectrum of the common-mode current can be obtained through circuit analysis and simulation, which is an effective method for designing and optimizing EMI.

[0054] Traditional isolated power supply chips require application-level PCB layout design and adjustments to meet CISPR22 Class A or Class B restrictions. For example, adding an external shielding layer makes the system bulkier and leads to heat dissipation difficulties. Adding a safety high-voltage capacitor between the two ground planes can effectively reduce EMI radiation caused by common-mode current, but it is very expensive. Using a spliced ​​capacitor formed by the intermediate layers of at least four PCBs to form a low-resistance path between the two ground planes, and using a large-area parallel plate capacitor formed by two intermediate layers of the PCB to suppress dipole EMI radiation, application-level PCB design always adds some extra cost to the system and is not conducive to fundamentally passing EMI standard tests.

[0055] In the process of realizing this disclosure, the inventors discovered that the DC-to-AC power conversion efficiency of the transmitter module in the isolated power supply chip directly affects the conversion efficiency of the entire system, and the asymmetry of the power stage topology of the transmitter module leads to significant EMI radiation. Traditional isolated power supplies use cross-coupled LC oscillators for DC-AC inverter schemes, such as... Figure 1 As shown, the cross-coupled LC oscillator 100 generates a signal with an amplitude of π times VDD on the primary side of the transformer 200. Therefore, a high-voltage LDMOS is required to fabricate the power transistor. However, the high-voltage LDMOS has a larger on-resistance than the low-voltage MOS transistor, and a pair of voltage divider capacitors C are also required. C1 and C C2 Let power transistor M N1 and M N2The gate oscillation amplitude remains at a low swing (LDMOS gate-source voltage is not high-voltage resistant), thus increasing the conduction loss of the power transistors and limiting the DC-AC conversion efficiency of the cross-coupled LC oscillator. On the other hand, the two power transistors of oscillator 100 conduct alternately (0 to πVDD), resulting in a high-frequency common-mode voltage V0 on the primary side of the transformer with a swing from 0 to πVDD / 2. PRI_CM Due to the distributed parasitic capacitance between the primary and secondary coils of transformer 200, a large common-mode current is generated, resulting in output-to-output dipole radiation.

[0056] like Figure 2 As shown, a complementary Class D oscillator 100 composed of a pair of NMOS and PMOS transistors generates a 0-V voltage across the primary coil of the transformer 200 by the alternating charging and discharging of the two sets of NMOS and PMOS transistors. DD The swing signal stabilizes at V on the primary side of the transformer. DD / 2 common-mode voltage V PRI_CM As can be seen from equation (2), the symmetrical topology can greatly compress the common-mode current, thereby reducing EMI radiation. However, this structure has a significant problem, such as... Figure 3 As shown, the complementary Class D oscillator operates on a differential oscillation signal V. PN In V THN To V DD -|V THP Within the range, M N1 and M P1 Simultaneously conduction, similarly V PP In V THN To V DD -|V THP |Within the range (V) THN and |V THP | are the threshold voltages of NMOS and PMOS respectively, M N2 and M P2 If both are turned on, then within these two intervals, there will be a power supply V. DD The short-circuit current to ground, and the short-circuit current passing through the power transistor, will not only generate additional losses that will significantly reduce the power conversion efficiency of the oscillator, but will also burn out the power transistor and cause the chip to fail.

[0057] As described above, a cross-coupled LC oscillator generates a common-mode voltage with an amplitude of πVDD / 2 and a frequency twice the resonant frequency on the primary side of the transformer, thus producing very large dipole radiation. The output voltage swing of a cross-coupled LC oscillator is πVDD, requiring a high-voltage LDMOS, increasing conduction losses, reducing efficiency, and necessitating high-voltage BCD technology. Using a complementary Class D oscillator results in all four power transistors conducting simultaneously at the moment the oscillation signal flips, generating a short-circuit current from VDD to ground that significantly reduces efficiency and damages the power transistors. Therefore, addressing the EMI radiation problem of isolated power supplies at the device level and improving conversion efficiency can greatly reduce product development costs and shorten design cycles, thus requiring a low-cost and high-efficiency isolated power supply transmitter power stage topology.

[0058] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0059] Figure 4 This is a block diagram of an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator, according to an embodiment of this disclosure. Figure 6 This is a block diagram showing the specific composition of an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator according to an embodiment of this disclosure.

[0060] In this embodiment of the disclosure, an isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator is provided, combined with Figure 4 and Figure 6 As shown, the isolated power supply chip includes:

[0061] The emitter oscillator circuit 10 is connected to the power supply V. DD And ground GND1, the transmitter oscillator circuit is used to invert the input DC voltage into a differential high-frequency oscillation power signal and input it to the primary coil L of the subsequently connected transformer 20. P ;

[0062] A rectifier circuit, connected to the secondary coil of the transformer, is used to rectify the differential high-frequency oscillating power signal to output a DC voltage signal; and

[0063] A feedback control circuit, connected to the rectifier circuit, is used to feed back the DC voltage signal to the transmitter oscillator circuit, thereby modulating and stabilizing the DC voltage signal.

[0064] The emitter oscillator circuit includes a dead-time control module and symmetrically arranged NMOS transistor groups and PMOS transistor groups connected to the dead-time control module. The dead-time control module eliminates the short-circuit current between the power supply and ground by controlling the switching on and off of the NMOS transistor groups and PMOS transistor groups.

[0065] In the embodiments disclosed herein, such as Figure 4 and Figure 6 As shown, transformer 20 It is an isolation device used to transmit AC power, consisting of a primary coil L P and secondary coil L S Composition; the upper end of the primary coil of transformer 20 is TX P The lower end is TX N The upper end of the secondary coil is RX. P The lower end is RX N Emitter-stage oscillator circuit 10 Used to convert the input DC voltage V DD Inverted into a differential high-frequency oscillating power signal V PP and V PN and from TX P and TX N The port output is connected to the primary coil L of the miniature transformer 20. P ; Rectifier circuit 30 Used to communicate via port RX P and RX N Receives the secondary coil L generated by the transmitter oscillator circuit 10 and transmitted to the transformer 20. S The high-frequency oscillating power signal is rectified into an output DC voltage signal; feedback control circuit 40 It is used to provide feedback on the output voltage signal and to modulate and stabilize the output voltage V. ISO .

[0066] According to an embodiment of this disclosure, the NMOS transistor group includes a first NMOS transistor M. N1 Second NMOS transistor M N2 The PMOS transistor group includes a first PMOS transistor M. P1 Second PMOS transistor M P2 The voltage node V of the transmitter oscillator circuit 10 PP TX of transformer 20 P Port, voltage node V PN TX of transformer 20 N port.

[0067] According to an embodiment of this disclosure, the dead-time control module 101 controls the on / off state of the NMOS transistor group and the PMOS transistor group based on the high-frequency oscillation power signal at both ends of the primary coil of the sampling transformer to achieve dead-time control;

[0068] According to an embodiment of this disclosure, the dead-time control module outputs a control voltage signal based on the high-frequency oscillation power signal across the primary coil of the sampling transformer to control the on / off state of each power transistor in the NMOS and PMOS transistor groups, thereby achieving dead-time control. For example, the dead-time control module 101 samples the oscillation signal V... PP and V PN Output four voltages V GN1 V GN2 and V GP1 V GP1 Control the four power transistors M respectively N1 M N2 M P1 M P2 .

[0069] According to an embodiment of this disclosure, the dead-time control module 101 is used to configure the turn-on and turn-off sequence of the aforementioned NMOS transistor group and PMOS transistor group, via the primary coil L of the sampling transformer 20. P Oscillating signal V at both ends PP and V PN To control the gate voltage V of the four MOSFETs GN1 V GN2 and V GP1 V GP1 To achieve dead zone control;

[0070] According to an embodiment of this disclosure, the isolated power supply chip further includes a switch 102. One end of the switch 102 is grounded or powered, and the other end is connected to the emitter oscillator circuit. The switch is used to control the oscillation of the emitter oscillator circuit by switching it on or off based on the DC voltage signal fed back from the feedback control circuit. For example, one end of the switch 102 can be connected not only to M... N1 and M N2 One end is the source terminal, and the other end is grounded to GND1. This switch can also be converted into two, each with one end connected to M. N1 The gate and M N2 The gate is connected to ground at the other end, and M is controlled by... N1 and M N2 The high and low levels of the gate are used to control the switching of the oscillator, or the switch can be converted into two, each with one end connected to M. P1 The gate and M P2 The gate of the device, and the other end connected to V. DD By controlling M P1 and M P2 The high and low levels of the gate are used to control the switching of the oscillator.

[0071] According to embodiments of this disclosure, such as Figure 5 As shown, the emitter-stage oscillator circuit includes the following states:

[0072] State 1 (①): The second NMOS transistor and the first PMOS transistor are turned on, and the inductor current I... L A negative value indicates that the flow originates from GND1 and flows to V. DD And it gradually decreases, V PP Greater than V DD V PN Less than 0;

[0073] State 2(②): The second NMOS transistor and the first PMOS transistor are turned on, and the inductor current I L It is a positive value, that is, it is determined by V. DD Flowing towards GND1 and gradually increasing, V PP Less than V DD V PN Greater than 0;

[0074] State 3(③): To avoid short-circuit current, the second NMOS transistor and the first PMOS transistor are turned off first, and the voltage V output by the dead-time control module is... GN2 and V GP1 Reaching V respectively THN and V DD -|V THP At this point, a dead time occurs, all four power transistors are turned off, and the inductor current I... L Continuous streaming;

[0075] State 4(④): The first NMOS transistor and the second PMOS transistor are turned on, and the inductor current I... L It is a positive value, meaning it flows from GND1 to V. DD And it gradually decreases, V PN Greater than V DD V PP Less than 0;

[0076] State 5(⑤): The first NMOS transistor and the second PMOS transistor are turned on, and the inductor current I... L It is a negative value, that is, it is determined by V. DD Flowing towards GND1 and gradually increasing, V PN Less than V DD V PP Greater than 0;

[0077] State 6(⑥): To avoid short-circuit current, the first NMOS transistor and the second PMOS transistor are turned off first, and the voltage V output by the dead-time control module is... GN1 and V GP2 Reaching V respectively THN and V DD -|V THP At this point, a dead time occurs, all four power transistors are turned off, and the inductor current I... L Continuous streaming;

[0078] The threshold voltage of the NMOS transistor group is V.THN The threshold voltage of the PMOS transistor group is V. THP This corresponds to the first terminal (TX) in the primary coil of the transformer. P High-frequency oscillation power signal V (end) PP This corresponds to the second terminal (TX) in the primary coil of the transformer. N High-frequency oscillation power signal V (end) PN The inductor current generated by the primary coil of the transformer is I. L The voltage of the power supply is V. DD V GN1 V is the gate voltage of the first NMOS transistor output by the dead-time control module. GN2 V is the gate voltage of the second NMOS transistor output by the dead-time control module. GP1 V is the gate voltage of the first PMOS transistor output by the dead-time control module. GP2 This is the gate voltage of the second PMOS transistor output by the dead-time control module.

[0079] According to embodiments of this disclosure, in conjunction with Figure 4 and Figure 6 As shown, the dead-time control module includes a first bias voltage V. BN Second bias voltage V BP First bias resistor R B1 The second bias resistor R B2 The third bias resistor R B3 Fourth bias resistor R B4 First coupling capacitor C C1 The second coupling capacitor C C2 The third coupling capacitor C C3 The fourth coupling capacitor C C4 .

[0080] Among them, the first NMOS transistor M N1 The gate is connected through the first coupling capacitor C C1 Connected to the second NMOS transistor M N2 The drain of the second NMOS transistor M N2 The gate is coupled through the second coupling capacitor C C2 Connected to the first NMOS transistor M N1 The drain of the first PMOS transistor M P1 The gate is connected to the third coupling capacitor C C3 Connected to the second PMOS transistor M P2 The drain of the second PMOS transistor M P2 The gate is coupled through the fourth coupling capacitor C C4 Connected to the first PMOS transistor M P1 The missing level.

[0081] First bias voltage V BNThrough the first bias resistor R B1 Connected to the first NMOS transistor M N1 gate V GN1 Simultaneously through the second bias resistor R B2 Connected to the second NMOS transistor M N2 gate V GN2 Second bias voltage V BP Through the third bias resistor R B3 Connected to the first PMOS transistor M P1 gate V GP1 Simultaneously through the fourth bias resistor R B4 Connected to the second PMOS transistor M P2 Gate M GP2 .

[0082] First NMOS transistor M N1 Second NMOS transistor M N2 The source of the transistor is connected to one end of the switch, and the other end of the switch is grounded. The first PMOS transistor M... P1 Second PMOS transistor M P2 The source stage is connected to the power supply V. DD ; First NMOS transistor M N1 Second PMOS transistor M P2 The drain terminal is connected to the primary coil L of transformer 20. P port TX P The second NMOS transistor M N2 Second PMOS transistor M P2 The drain terminal is connected to the primary coil L of transformer 20. P port TX N .

[0083] Furthermore, in the oscillator circuit 10 provided in this disclosure, one end of the switch 102 can be connected not only to the first NMOS transistor M N1 Second NMOS transistor M N2 One end is the source terminal, and the other end is grounded to GND1. This switch can also be converted into two, each with one end connected to the first NMOS transistor M. N1 The gate and the second NMOS transistor M N2 One end is the gate, and the other end is grounded. By controlling the first NMOS transistor M N1 Second NMOS transistor M N2 The gate high and low levels are used to control the switching of the oscillator, or the switch can be converted into two, each with one end connected to the first PMOS transistor M. P1 The gate and the second PMOS transistor M P2 The gate of the device, and the other end connected to V. DD By controlling the first PMOS transistor M P1 Second PMOS transistor MP2 The high and low levels of the gate are used to control the switching of the oscillator.

[0084] like Figure 6 As shown, the present disclosure proposes a symmetrical type D oscillator with dead-time control via a coupling capacitor C. C1-4 The differential high-frequency oscillation power signal V generated by the oscillator is respectively... PP and V PN Coupled to MOSFET M N1 M N2 M P1 and M P2 gate V GN1，2 and V GP1，2 The coupling capacitance value is related to the gate parasitic capacitance C of the MOSFET. Gs The ratio determines the swing of the gate voltage signal of the MOS transistor.

[0085] Bias DC voltage V BN and V BP Through bias resistor R B1-4 Set the gate common-mode voltage values ​​for the NMOS and PMOS transistor groups in the Class D oscillator respectively, without referencing V. BN and V BP At that time, the gate common-mode voltage of both the NMOS and PMOS transistor groups is V. DD / 2, referencing V BN and V BP Afterwards, the gate common-mode voltages of the NMOS and PMOS transistor groups are V respectively. BN and V BP In order to effectively control the dead time of the switching transistors, it is necessary to set the turn-on and turn-off sequence of the NMOS transistor group and the PMOS transistor group.

[0086] Figure 7a The differential high-frequency oscillation power signal V in this embodiment of the disclosure PN A schematic diagram of dead zone control during the descent process. Figure 7b The differential high-frequency oscillation power signal V in this embodiment of the disclosure PP A schematic diagram of dead zone control during the ascent process.

[0087] According to embodiments of this disclosure, in conjunction with Figure 6 , Figure 7a and Figure 7b As shown, the differential high-frequency oscillation power signal V PN During the descent process, the bias voltage V is used. BN Pull down the NMOS transistor group (M) N1 and M N2 The gate common-mode voltage to V BN Using bias voltage V BP Raise the PMOS transistor group (MP1 and M P2 The gate common-mode voltage to V BP ,contrast Figure 3 It can be seen that M originally N1 The breakpoint P1 is at V PN For V THN At that time, now M N1 The gate-source voltage is V THN When, corresponding to V PN If point P2 is the point, then M N1 The cutoff point is moved from point P1 to point P2 (V PN，P2 =V THN +(V DD / 2-V BN Originally M P1 The starting point P3 is in V PN For V DD -|V THP |At that time, now M P1 The source-gate voltage is |V THP | when, corresponding to V PN The point is P4(V) PN，P4 =V DD -|V THP |-(V BP -V DD / 2)), then M P1 The starting point is moved from point P3 to point P4; if point P2 is earlier than point P4 (V PN，P4 >V PN，P2 ), and derived the conditional formula (4) for the generation of dead time, then M N1 First turn it off, then M P1 Then it is turned on again, so the interval from P2 to P4 is M. N1 and M P1 If all are closed, then V DD The short-circuit current to ground was effectively eliminated.

[0088] V BP -V BN >V DD -|V THP |-V THN (4);

[0089] Similarly, the differential high-frequency oscillation power signal V PP During the signal rise process, M N2 The starting point is moved from point P5 to point P6, M P2 The cutoff point is moved from point P7 to point P8. If point P8 is earlier than point P6 (V PP，P6 >V PP，P8 Similarly, the conditional formula (4) for the generation of dead time can be derived, then MP2 First turn it off, then M N2 Restart. Combine. Figure 5 As shown, V PP and V PN The differential high-frequency oscillation power signal across transformer 20, when V PN When M is high N1 and M P2 When the circuit is turned on, the direction of the inductor current in the previous state is from TX. P To TX N Furthermore, the inductor current cannot change abruptly; the inductor current I... L Through M N1 and M P2 Flowing from GND1 to V DD Then V PN Voltage exceeding V DD V PP The voltage will drop below 0 because of M N1 and M P2 The on-resistance exists, V PN It will gradually decrease and V PP It will gradually rise, when V PN For V DD Time V PP When the current is 0, the inductor current is zero until the condition M in the aforementioned dead-time control is reached. N1 Shut down, then M Pl Open, then V PN When the voltage is pulled down, the Class D oscillator enters the next state, V. PP The same principle applies to the case where the voltage is high, thus offsetting the short-circuit current between the power supply and ground generated in states 3 and 6. Moreover, the above dead-time control method does not affect the symmetry of the proposed Class D oscillator, and the common-mode voltage generated across the primary coil LP of transformer 20 remains V. DD / 2, therefore this topology has the effect of suppressing common-mode current and thus reducing EMI radiation.

[0090] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0091] Based on the above description, those skilled in the art should have a clear understanding of the isolated power supply chip based on the dead-time controlled symmetrical Class D oscillator disclosed herein.

[0092] In summary, this disclosure provides an isolated power supply chip based on a dead-time controlled symmetrical Class-D oscillator. By utilizing the symmetrical Class-D oscillator topology, common-mode current is suppressed, thereby reducing dipole radiation, enabling a low-EMI radiation solution at the device level. The oscillation amplitude of the employed symmetrical Class-D oscillator is limited to the power supply voltage V. DD Therefore, high-voltage LDMOS is unnecessary; low-voltage MOS transistors are sufficient. Low-voltage MOS transistors have lower on-resistance, effectively improving the oscillator's conversion efficiency and reducing manufacturing costs. The proposed symmetrical Class D oscillator effectively solves the problem of instantaneous short-circuit current in traditional complementary Class D oscillators. A dead-time control technique is proposed to effectively eliminate the short-circuit current in complementary Class D oscillators, improving the oscillator's conversion efficiency without affecting the original symmetrical topology and extending the lifespan of the power transistor.

[0093] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. Furthermore, the shapes and dimensions of the components in the drawings do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0094] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0095] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0096] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. An isolated power supply chip based on a dead-time controlled symmetrical Class D oscillator, comprising: The transmitter oscillator circuit, connected to the power supply and ground, is used to invert the input DC voltage into a differential high-frequency oscillation power signal and input it to the primary coil of the transformer connected thereafter. A rectifier circuit, connected to the secondary coil of the transformer, is used to rectify the differential high-frequency oscillation power signal to output a DC voltage signal; as well as A feedback control circuit, connected to the rectifier circuit, is used to feed back the DC voltage signal to the transmitter oscillator circuit, thereby modulating and stabilizing the DC voltage signal. The emitter oscillator circuit includes: a dead-time control module, and symmetrically arranged NMOS transistor groups and PMOS transistor groups connected to the dead-time control module; the emitter oscillator circuit includes the following states: State 1: the second NMOS transistor and the first PMOS transistor are turned on, and the inductor current I... L The value is negative; State 2: The second NMOS transistor and the first PMOS transistor are turned on, and the inductor current I... L The value is positive; State 3: The second NMOS transistor and the first PMOS transistor are turned off first, and the voltage V output by the dead-time control module is positive. GN2 and V GP1 Reaching V respectively THN and V DD -|V THP At this point, a dead time occurs, all four power transistors are turned off, and the inductor current I... L Freewheeling; State 4: First NMOS transistor and second PMOS transistor are turned on, inductor current I L It is positive; State 5: The first NMOS transistor and the second PMOS transistor are turned on, and the inductor current I L The value is negative; State 6: The first NMOS transistor and the second PMOS transistor are turned off first, and the voltage V output by the dead-time control module is negative. GN1 and V GP2 Reaching V respectively THN and V DD -|V THP At this point, a dead time occurs, all four power transistors are turned off, and the inductor current I... L Freewheeling; where the threshold voltage of the NMOS transistor group is V THN The threshold voltage of the PMOS transistor group is V. THP These correspond to the high-frequency oscillation power signal V at the first end of the primary coil of the transformer. PP The high-frequency oscillation power signal V at the second end PN The inductor current generated by the primary coil of the transformer is I. L The voltage of the power supply is V. DD V GN1 V is the gate voltage of the first NMOS transistor output by the dead-time control module. GN2 V is the gate voltage of the second NMOS transistor output by the dead-time control module. GP1 V is the gate voltage of the first PMOS transistor output by the dead-time control module. GP2 The second PMOS gate voltage is output by the dead-time control module. The dead-time control module eliminates the short-circuit current between the power supply and ground by controlling the switching on and off of the NMOS and PMOS transistor groups.

2. The isolated power supply chip according to claim 1, wherein the dead-time control module controls the on / off state of the NMOS transistor group and the PMOS transistor group based on the high-frequency oscillation power signal at both ends of the primary coil of the sampling transformer to achieve dead-time control.

3. The isolated power supply chip according to claim 2, wherein the dead-time control module outputs a control voltage signal based on the high-frequency oscillation power signal at both ends of the primary coil of the sampling transformer to control the on / off state of each power transistor in the NMOS transistor group and PMOS transistor group to achieve dead-time control.

4. The isolated power supply chip according to claim 3, wherein, The NMOS transistor group includes a first NMOS transistor and a second NMOS transistor; The PMOS transistor group includes a first PMOS transistor and a second PMOS transistor.

5. The isolated power supply chip according to claim 4, further comprising: A switch, with one end grounded or connected to a power source, and the other end connected to the transmitter oscillator circuit, is used to control whether the transmitter oscillator circuit oscillates by switching on and off based on the DC voltage signal fed back by the feedback control circuit.

6. The isolated power supply chip according to claim 4, wherein the dead-time control module includes a first bias voltage, a second bias voltage, a first bias resistor, a second bias resistor, a third bias resistor, a fourth bias resistor, a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, and a fourth coupling capacitor.

7. The isolated power supply chip according to claim 6, wherein the gate of the first NMOS transistor is connected to the drain of the second NMOS transistor through a first coupling capacitor, the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor through a second coupling capacitor, the gate of the first PMOS transistor is connected to the drain of the second PMOS transistor through a third coupling capacitor, and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor through a fourth coupling capacitor.

8. The isolated power supply chip according to claim 6, wherein the first bias voltage is connected to the gate of the first NMOS transistor through a first bias resistor and simultaneously connected to the gate of the second NMOS transistor through a second bias resistor; the second bias voltage is connected to the gate of the first PMOS transistor through a third bias resistor and simultaneously connected to the gate of the second PMOS transistor through a fourth bias resistor.

9. The isolated power supply chip according to claim 8, wherein the common-mode voltage of the NMOS transistor group or the PMOS transistor group is adjusted by the first bias voltage or the second bias voltage to achieve dead-time control.

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