Single pulse low level signal synchronization circuit

Abstract

The application discloses a single-pulse low-level signal synchronization circuit, and specifically comprises: a single-pulse low-level signal synchronization module connected with a first AND gate, used for synchronously converting an externally input synchronization signal from a first clock domain to a second clock domain; a single-pulse low-level signal compensation module connected with the first AND gate, used for providing a compensation correction signal; the first AND gate is connected with the single-pulse low-level signal synchronization module, the single-pulse low-level signal compensation circuit and a first inverter respectively, used for performing AND logic selection on a synchronization signal of the second clock domain combined with the compensation correction signal and transmitting the signal to the first inverter; and the first inverter is used for outputting a single-pulse low-level synchronization signal synchronously converted from the first clock domain to the second clock domain. The application realizes the transmission of a single clock cycle signal across clock domains and outputs the signal in the form of a single-pulse low-level synchronization signal, and solves the problem of abnormal signals in the transmission process across clock domains by setting a compensation correction signal.

Description

Technical Field

[0001] This invention relates to the field of circuit design, specifically to a single-pulse low-level signal synchronization circuit. Background Technology

[0002] In chip design, signals from multiple clock domains are often present. When multiple clock domain signals exist, chip design needs to involve the transfer of signals between different clock domains. Currently, the most common method for handling cross-clock domain signal transfer is register pacing. While this method is simple, it has significant limitations. In particular, for single-pulse low-level signal synchronization circuits, current single-pulse low-level signal synchronization circuits are mainly used to synchronize the low level of the signal in the first time domain of a single clock cycle to the second time domain. They cannot synchronize the signal from the fast clock domain to the slow clock domain. Furthermore, during the cross-clock domain signal synchronization process, this circuit suffers from abnormal low-level signal output due to abnormal reset signal levels. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a single-pulse low-level signal synchronization circuit. This circuit transmits a single clock cycle signal from a first clock domain to a second clock domain, satisfying both the requirement for synchronization signals to be transmitted from a fast clock domain to a slow clock domain and vice versa. Furthermore, by setting a compensation correction signal, the problem of abnormal signals occurring during cross-clock domain transmission is resolved, ultimately achieving a single-pulse low-level signal output across clock domains. The specific technical solution of this invention is as follows:

[0004] A single-pulse low-level signal synchronization circuit specifically includes: a single-pulse low-level signal synchronization module connected to a first AND gate, used to synchronously convert an externally input synchronization signal from a first clock domain to a second clock domain; a single-pulse low-level signal compensation module connected to the first AND gate, used to provide a compensation correction signal for the abnormal low-level synchronization signal output by the single-pulse low-level signal synchronization module; a first AND gate connected to the single-pulse low-level signal synchronization module, the single-pulse low-level signal compensation module, and a first inverter, respectively, used to perform AND logic selection on the synchronization signal in the second clock domain output by the single-pulse low-level signal synchronization module combined with the compensation correction signal output by the single-pulse low-level signal compensation module, and transmit the selected synchronization signal to the first inverter; and a first inverter connected to the first AND gate, used to invert the selected synchronization signal by the first AND gate, and output a single-pulse low-level synchronization signal synchronously converted from the first clock domain to the second clock domain.

[0005] Furthermore, the single-pulse low-level signal synchronization module specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, and a second inverter; wherein, the output terminal of the second AND gate is connected to the reset signal input terminal of the first register, the output terminal of the third register is connected to the input terminal of the second inverter, and the second inverter is connected to the first input terminal of the third AND gate.

[0006] Furthermore, in the single-pulse low-level signal synchronization module, the first input terminal of the second AND gate is used to receive the low-level signal of the first clock domain input from the outside, and the second input terminal of the second AND gate is used to receive the inverted reset signal input from the outside.

[0007] Furthermore, in the single-pulse low-level signal synchronization module, the first register, the second register, and the third register are connected in series; wherein, the output terminal of the first register is connected to the first input terminal of the second register, and the output terminal of the second register is connected to the first input terminal of the third register.

[0008] Furthermore, the output of the second register in the single-pulse low-level signal synchronization module is also connected to the second input of the third AND gate.

[0009] Furthermore, the single-pulse low-level signal compensation module specifically includes: a fourth register, a fifth register, a sixth register, a third inverter, a fourth inverter, and a fourth AND gate; wherein, the output terminal of the fourth register is connected to the first input terminal of the fifth register, the output terminal of the fifth register is connected to the first input terminal of the sixth register, the output terminal of the sixth register is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the fourth AND gate, and the output terminal of the fourth AND gate is connected to the input terminal of the fourth inverter.

[0010] Furthermore, the output of the fifth register in the single-pulse low-level signal compensation module is also connected to the second input of the fourth AND gate.

[0011] Furthermore, the connection of the first AND gate to the single-pulse low-level signal synchronization module, the single-pulse low-level signal compensation circuit, and the first inverter specifically means that the first input terminal of the first AND gate is connected to the output terminal of the third AND gate in the single-pulse low-level signal synchronization module, the second input terminal of the first AND gate is connected to the output terminal of the fourth inverter in the single-pulse low-level signal compensation module, and the output terminal of the first AND gate is connected to the input terminal of the first inverter.

[0012] Furthermore, the reset signal input terminals of the second register, the third register, the fourth register, the fifth register, the sixth register, and the second input terminal of the second AND gate are respectively used to receive inverted reset signals from external input.

[0013] Furthermore, the clock signal input terminals of the first register, the second register, the third register, the fourth register, the fifth register, and the sixth register are respectively used to receive the clock signal of the second clock domain.

[0014] Furthermore, the input terminal of the single-pulse low-level signal synchronization module is the input terminal of the single-pulse low-level signal synchronization circuit, and the output terminal of the first inverter is the output terminal of the single-pulse low-level signal synchronization circuit; wherein, the input terminal of the single-pulse low-level signal synchronization module includes the first input terminal of the second AND gate and the second input terminal of the second AND gate.

[0015] This invention enables the synchronous transmission of a single-clock-cycle synchronization signal from the first clock domain to the second clock domain through the single-pulse low-level signal synchronization module, and compensates and corrects abnormal single-pulse low-level signals when the single-pulse low-level signal synchronization module outputs abnormal single-pulse low-level signals based on the single-pulse low-level signal compensation module, so as to ensure that the single-pulse low-level signal synchronization circuit outputs a normal single-pulse low-level synchronization signal transmitted from the first clock domain to the second clock domain. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the single-pulse low-level signal synchronization circuit according to the first embodiment of the present invention.

[0017] Figure 2 This is a circuit diagram of the single-pulse low-level signal synchronization module according to the second embodiment of the present invention.

[0018] Figure 3 This is a circuit diagram of the single-pulse low-level signal compensation module according to the third embodiment of the present invention.

[0019] Figure 4 This is a circuit diagram of the single-pulse low-level signal synchronization circuit according to the fourth embodiment of the present invention.

[0020] Figure 5 This is a waveform diagram of a single-pulse low-level synchronization circuit according to an embodiment of the present invention.

[0021] Figure 6This is a waveform diagram illustrating the compensation and correction function provided by the single-pulse low-level signal compensation module according to an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described below are merely illustrative of the invention and are not intended to limit the invention. Furthermore, it should be understood that for those skilled in the art, modifications to the design, manufacturing, or production processes disclosed in this invention are merely conventional technical means and should not be construed as insufficient disclosure of the invention.

[0023] Unless otherwise defined, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” etc., used in this application do not indicate quantity limitation and may represent singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof, used in this application, are intended to cover non-exclusive inclusion, such as: a process, method, system product, or device that includes a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules not listed, or may also include other steps or units inherent to these processes, methods, products, or devices. The terms “first,” “second,” “third,” etc., used in this application are merely used to distinguish similar correspondences and do not represent a specific ordering of objects.

[0024] As a preferred embodiment of the present invention, the first embodiment of the present invention provides a single-pulse low-level signal synchronization circuit, such as... Figure 1 As shown, the single-pulse low-level signal synchronization circuit specifically includes: a single-pulse low-level signal synchronization module, a single-pulse low-level signal compensation module, a first AND gate, and a first inverter. The single-pulse low-level signal synchronization module is used to synchronously convert an externally input synchronization signal from a first clock domain to a second clock domain. The single-pulse low-level signal compensation module is used to provide a compensation correction signal for abnormal low-level signals output by the single-pulse low-level signal synchronization module. The first AND gate is used to perform an AND logic selection on the synchronization signal in the second clock domain output by the single-pulse low-level signal synchronization module combined with the compensation correction signal output by the single-pulse low-level signal compensation module, and transmits the selected synchronization signal to the first inverter. The first inverter is used to invert the synchronization signal selected by the first AND gate, outputting a single-pulse low-level synchronization signal synchronously converted from the first clock domain to the second clock domain.

[0025] Specifically, the input terminal of the single-pulse low-level signal synchronization module is used to receive externally input signals, the output terminal of the single-pulse low-level signal synchronization module is connected to the first input terminal of the first AND gate, the output terminal of the single-pulse low-level signal compensation module is connected to the second input terminal of the first AND gate, the output terminal of the first AND gate is connected to the input terminal of the first inverter, and the output terminal of the first inverter is used to output a single-pulse low-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain.

[0026] It should be noted that the first clock domain and the second clock domain are different clock domains. The first clock domain can be either the aclk clock domain or the bclk clock domain, and the second clock domain can be either the aclk clock domain or the bclk clock domain. It should also be noted that when the first clock domain is the aclk clock domain, the second clock domain cannot be the aclk clock domain; when the first clock domain is the bclk clock domain, the second clock domain cannot be the bclk clock domain.

[0027] This embodiment uses the single-pulse low-level signal synchronization module to synchronously transmit a synchronization signal of a single clock cycle from the first clock domain to the second clock domain, and uses the single-pulse low-level signal compensation module to compensate and correct for abnormal single-pulse low-level signals output by the single-pulse low-level signal synchronization module, so as to ensure that the single-pulse low-level signal synchronization circuit outputs a normal single-pulse low-level synchronization signal transmitted from the first clock domain to the second clock domain.

[0028] Based on the above embodiments, as a preferred embodiment of the present invention, such as... Figure 2 As shown, the single-pulse low-level signal synchronization module in the second embodiment of the present invention specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, and a second inverter; wherein, the output terminal of the second AND gate is connected to the reset signal input terminal of the first register, the output terminal of the third register is connected to the input terminal of the second inverter, and the second inverter is connected to the first input terminal of the third AND gate.

[0029] Preferably, in the single-pulse low-level signal synchronization module, the first input terminal of the second AND gate is used to receive a low-level signal from the first clock domain input externally, and the second input terminal of the second AND gate is used to receive an inverted reset signal input externally.

[0030] Preferably, in the single-pulse low-level signal synchronization module, the first register, the second register, and the third register are connected in series; wherein, the output terminal of the first register is connected to the first input terminal of the second register, and the output terminal of the second register is connected to the first input terminal of the third register. This embodiment achieves the pulse transmission of the synchronization signal in the first clock domain by connecting three registers in series, thereby enabling the transmission of the synchronization signal from the first clock domain to the second clock domain.

[0031] Preferably, the output of the second register in the single-pulse low-level signal synchronization module is also connected to the second input of the third AND gate.

[0032] Based on the above embodiments, as a preferred embodiment of the present invention, such as... Figure 3 As shown, the single-pulse low-level signal compensation module in the third embodiment of the present invention specifically includes: a fourth register, a fifth register, a sixth register, a third inverter, a fourth inverter, and a fourth AND gate; wherein, the output terminal of the fourth register is connected to the first input terminal of the fifth register, the output terminal of the fifth register is connected to the first input terminal of the sixth register, the output terminal of the sixth register is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the fourth AND gate, and the output terminal of the fourth AND gate is connected to the input terminal of the fourth inverter.

[0033] Preferably, the output of the fifth register in the single-pulse low-level signal compensation module is also connected to the second input of the fourth AND gate.

[0034] It should be noted that the reset values ​​of the first register and the fourth register are high-level signals, while the reset values ​​of the second register, the third register, the fifth register, and the sixth register are low-level signals.

[0035] For example Figure 5 As shown, Figure 5 The diagram shows the output signal waveforms of the single-pulse low-level signal synchronization circuit when the compensation module does not perform its compensation function. In the diagram, signal_in refers to the synchronization signal in the first time domain input to the single-pulse low-level synchronization module, and signal_out refers to the synchronization signal in the second time domain output by the single-pulse low-level synchronization circuit.

[0036] like Figure 6 As shown, Figure 6The diagram shows the output signal waveforms of the single-pulse low-level signal compensation module and its compensation effect on the single-pulse low-level synchronization module in the single-pulse low-level synchronization circuit. In the diagram, signal_in refers to the synchronization signal in the first time domain input to the single-pulse low-level synchronization module, and signal_out refers to the synchronization signal in the second time domain output by the single-pulse low-level synchronization circuit. When an abnormal synchronization signal is generated in the single-pulse low-level synchronization module, the fourth AND gate of the single-pulse low-level signal compensation module outputs a compensation correction signal to compensate for and correct the abnormal synchronization signal. Figure 6 As shown, the inverted reset signal outputs an abnormally low-level signal, causing the second AND gate output signal to be affected by the abnormally low-level signal output by the inverted reset signal and output an abnormally low-level signal. The timing of the first register, the second register, and the third register is unaffected. The third AND gate output signal is affected by the abnormally low-level signal output by the second AND gate and outputs an abnormally high-level signal. Under the compensation of the fourth inverter output signal in the single-pulse high-level signal compensation module, the single-pulse low-level synchronization circuit is not affected by the abnormally low-level signal, ensuring the accuracy of the synchronization signal output by the single-pulse low-level signal synchronization circuit.

[0037] Based on the above embodiments, as a preferred embodiment of the present invention, such as... Figure 4 As shown, in the fourth embodiment of the present invention, the first input terminal of the first AND gate in the single-pulse low-level signal synchronization circuit is connected to the output terminal of the third AND gate in the single-pulse low-level signal synchronization module, the second input terminal of the first AND gate is connected to the output terminal of the fourth inverter in the single-pulse low-level signal compensation module, and the output terminal of the first AND gate is connected to the input terminal of the first inverter, thereby realizing the connection of the first AND gate to the single-pulse low-level signal synchronization module, the single-pulse low-level signal compensation circuit and the first inverter respectively.

[0038] Preferably, the reset signal input terminals of the second register, the third register, the fourth register, the fifth register, the sixth register, and the second input terminal of the second AND gate are respectively used to receive inverted reset signals from external input.

[0039] Preferably, the clock signal input terminals of the first register, the second register, the third register, the fourth register, the fifth register, and the sixth register are respectively used to receive the clock signal of the second clock domain.

[0040] Preferably, the input terminal of the single-pulse low-level signal synchronization module is the input terminal of the single-pulse low-level signal synchronization circuit, and the output terminal of the first inverter is the output terminal of the single-pulse low-level signal synchronization circuit; wherein, the input terminal of the single-pulse low-level signal synchronization module includes the first input terminal of the second AND gate and the second input terminal of the second AND gate.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single-pulse low-level signal synchronization circuit, characterized in that, The single-pulse low-level signal synchronization circuit specifically includes: A single-pulse low-level signal synchronization module, connected to the first AND gate, is used to synchronously convert the externally input synchronization signal from the first clock domain to the second clock domain. The single-pulse low-level signal compensation module is connected to the first AND gate and is used to provide a compensation and correction signal for the abnormal low-level synchronization signal output by the single-pulse low-level signal synchronization module. The first AND gate is connected to the single-pulse low-level signal synchronization module, the single-pulse low-level signal compensation module, and the first inverter, respectively. It is used to perform AND logic selection on the synchronization signal of the second clock domain output by the single-pulse low-level signal synchronization module and the compensation correction signal output by the single-pulse low-level signal compensation module, and transmit the selected synchronization signal to the first inverter. The first inverter, whose input is connected to the output of the first AND gate, is used to invert the synchronization signal selected by the first AND gate and output a single-pulse low-level synchronization signal that is synchronized from the first clock domain to the second clock domain. The single-pulse low-level signal synchronization module specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, and a second inverter; wherein the output of the second AND gate is connected to the reset signal input of the first register, the output of the third register is connected to the input of the second inverter, and the output of the second inverter is connected to the first input of the third AND gate; the first input of the second AND gate is used to receive a synchronization signal from an externally input first clock domain, and the reset signal inputs of the second register, the third register, and the second AND gate are respectively used to receive an externally input inverted reset signal; the output of the third AND gate is connected to the first input of the first AND gate. The first register, the second register, and the third register are connected in series; the output of the first register is connected to the first input of the second register, and the output of the second register is connected to the first input of the third register; the output of the second register is also connected to the second input of the third AND gate; the clock signal inputs of the first register, the second register, and the third register are respectively used to receive clock signals from the second clock domain. Wherein, the input terminal of the single-pulse low-level signal synchronization module is the input terminal of the single-pulse low-level signal synchronization circuit, and the output terminal of the first inverter is the output terminal of the single-pulse low-level signal synchronization circuit; the input terminal of the single-pulse low-level signal synchronization module includes the first input terminal of the second AND gate and the second input terminal of the second AND gate.

2. The single-pulse low-level signal synchronization circuit according to claim 1, characterized in that, The single-pulse low-level signal compensation module specifically includes: a fourth register, a fifth register, a sixth register, a third inverter, a fourth inverter, and a fourth AND gate; wherein, the output terminal of the fourth register is connected to the first input terminal of the fifth register, the output terminal of the fifth register is connected to the first input terminal of the sixth register, the output terminal of the sixth register is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the fourth AND gate, and the output terminal of the fourth AND gate is connected to the input terminal of the fourth inverter; the output terminal of the fourth inverter is connected to the second input terminal of the first AND gate. The output of the fifth register is also connected to the second input of the fourth AND gate; the reset signal input of the fourth register, the reset signal input of the fifth register, and the reset signal input of the sixth register are respectively used to receive an inverted reset signal from an external input; the clock signal input of the fourth register, the clock signal input of the fifth register, and the clock signal input of the sixth register are respectively used to receive a clock signal from the second clock domain.

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