Digital driver, feedback circuit for an analog-to-digital converter, digital-to-analog converter

Abstract

The embodiment of the present application provides a kind of digital driver, comprising: input terminal, output terminal, first, second, third, fourth PMOS tube, first, second, third and fourth NMOS tube;Input terminal, first PMOS tube and first NMOS tube are connected;First PMOS tube, first NMOS tube, second PMOS tube and second NMOS tube are connected to first node;Second PMOS tube, second NMOS tube, third PMOS tube and third NMOS tube are connected to second node;Third PMOS tube, third NMOS tube, fourth PMOS tube and fourth NMOS tube are connected to third node;Fourth PMOS tube, fourth NMOS tube and output terminal are connected;The width of each PMOS tube, each NMOS tube is determined according to mobility and preset reduction factor.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a digital driver, a feedback circuit for an analog-to-digital converter, and a digital-to-analog converter. Background Technology

[0002] Traditional successive approximation register analog-to-digital converters (SAR ADCs) consist of a track-and-hold circuit (T / H), a comparator, SAR logic circuitry, and a capacitive digital-to-analog converter (DAC). This traditional structure offers advantages such as low complexity, low power consumption, and energy-efficient topology that allows for miniaturization in manufacturing processes, making it widely applicable in high-speed applications. For example, it can be used in time-interleaved successive approximation SAR ADCs. Some existing schemes have accelerated SAR ADC conversion by improving the one-bit-per-cycle topology, such as using multi-bit SAR per cycle and N-bit N-comparator SAR structures. However, the traditional one-bit-per-cycle topology still has significant advantages in terms of low complexity, fewer parasitics, and less offset. Therefore, most high-speed TI-SAR ADCs still prefer the traditional one-bit-per-cycle structure. Using a redundant bit architecture in high-speed SAR ADCs allows for very short DAC settling times. However, due to the limitation of the logical delay time of digital SAR per cycle, slow speed remains the main bottleneck of traditional SAR ADC architecture. Summary of the Invention

[0003] To address the aforementioned technical problems, embodiments of this application provide a digital driver, a feedback circuit for an analog-to-digital converter, a digital-to-analog converter, and an electronic device.

[0004] In a first aspect, embodiments of this application provide an analog-to-digital converter, including:

[0005] Input terminal, output terminal, first PMOS transistor, second PMOS transistor, third PMOS transistor, fourth PMOS transistor, first NMOS transistor, second NMOS transistor, third NMOS transistor and fourth NMOS transistor;

[0006] The input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor.

[0007] The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the gate of the second NMOS transistor are connected to the first node.

[0008] The drain of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor are connected to the second node;

[0009] The drain of the third PMOS transistor, the drain of the third NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor are connected to the third node.

[0010] The drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the output terminal are connected; wherein, the widths of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are determined according to the mobility of the PMOS transistor, the mobility of the NMOS transistor, and a preset shrinkage factor, wherein the preset shrinkage factor has a value range of (0, 1).

[0011] Secondly, embodiments of this application provide a feedback circuit for an analog-to-digital converter, the feedback circuit for the analog-to-digital converter comprising:

[0012] Capacitor-type DAC, comparator circuit, asynchronous logic control circuit, and DAC switching control circuit;

[0013] The capacitive DAC includes multiple capacitors and multiple digital drivers, each of which is the digital driver provided in the first aspect;

[0014] The asynchronous logic control circuit and the DAC switch control circuit each include multiple flip-flops;

[0015] Each capacitor is connected to the input terminal of the corresponding digital driver, and the output terminal of the capacitive DAC is connected to the input terminal of the comparator circuit.

[0016] The output of the comparator circuit is connected to the input of each flip-flop in the asynchronous logic control circuit.

[0017] The output terminals of each flip-flop in the asynchronous logic control circuit are connected to the input terminals of the corresponding flip-flops in the DAC switch control circuit.

[0018] The output terminals of each flip-flop in the DAC switch control circuit are connected to the input terminals of the corresponding digital drivers.

[0019] Thirdly, embodiments of this application provide an analog-to-digital converter, including the feedback circuit for the analog-to-digital converter provided in the second aspect.

[0020] Fourthly, embodiments of this application provide an electronic device including the analog-to-digital converter provided in the third aspect.

[0021] The digital driver, feedback circuit for analog-to-digital converter, digital-to-analog converter, and electronic device provided in this application reduce delay time and power consumption by adjusting the size of NMOS transistors and PMOS transistors using a preset scaling factor. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation on the scope of protection of this application. In the various drawings, similar components are numbered similarly.

[0023] Figure 1 A schematic diagram of the structure of a digital driver provided in an embodiment of this application is shown;

[0024] Figure 2 This illustration shows a time delay comparison diagram provided by an embodiment of this application;

[0025] Figure 3 A schematic diagram of a simulation result of a digital driver provided in an embodiment of this application is shown;

[0026] Figure 4A Another schematic diagram of the feedback circuit for an analog-to-digital converter provided in an embodiment of this application is shown;

[0027] Figure 4B This illustration shows a signal change diagram provided in an embodiment of this application;

[0028] Figure 5A Another schematic diagram of the feedback circuit for an analog-to-digital converter provided in an embodiment of this application is shown;

[0029] Figure 5B This illustration shows another signal change diagram provided in an embodiment of this application;

[0030] Figure 6 A simulation diagram of the trigger provided in an embodiment of this application is shown. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0032] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0034] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0035] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0036] Example 1

[0037] This disclosure provides a digital driver.

[0038] For details, see Figure 1 , Figure 1 The diagram shows a schematic of a digital driver 10, which includes an input terminal IN, an output terminal OUT, and a first P-type metal-oxide-semiconductor (PMOS) transistor M. P1 The second PMOS transistor M P2 The third PMOS transistor M P3 The fourth PMOS transistor M P4The first N-type metal-oxide-semiconductor (NMOS) transistor M N1 The second NMOS transistor M N2 The third NMOS transistor M N3 and the fourth NMOS transistor M N4 ;

[0039] The input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor.

[0040] The first PMOS transistor M P1 The drain of the first NMOS transistor M N1 The drain of the second PMOS transistor M P2 The gate and the second NMOS transistor M N2 The gate is connected to the first node A;

[0041] The second PMOS transistor M P2 The drain of the second NMOS transistor M N2 The drain of the third PMOS transistor, the gate of the third NMOS transistor, and the gate of the third NMOS transistor are connected to the second node B.

[0042] The third PMOS transistor M P3 The drain of the third NMOS transistor M N3 The drain of the fourth PMOS transistor M P4 The gate and the fourth NMOS transistor M N4 The gate is connected to the third node C;

[0043] The fourth PMOS transistor M P4 The drain of the fourth NMOS transistor M N4 The drain of the first PMOS transistor is connected to the output terminal; wherein the first PMOS transistor M P1 The second PMOS transistor M P2 The third PMOS transistor M P3 The fourth PMOS transistor M P4 The first NMOS transistor M N1 The second NMOS transistor M N2 The third NMOS transistor M N3 The fourth NMOS transistor M N4 The width is determined based on the mobility of the PMOS transistor, the mobility of the NMOS transistor, and a preset shrinkage factor, wherein the preset shrinkage factor has a value range of (0, 1).

[0044] In this embodiment, the NMOS transistor and PMOS transistor can be simply referred to as NMOS transistor and PMOS transistor, respectively. Due to the introduction of the preset scaling factor, the digital driver 10 can be understood as an unbalanced driver. In conventional digital drivers, the width-to-length ratio of the NMOS transistor and PMOS transistor is approximately equal to the ratio of the mobility of the NMOS transistor to the mobility of the PMOS transistor. For example, Figure 1 When the digital driver 10 shown does not use the preset scaling factor provided in this embodiment, the second PMOS transistor M P2 The second NMOS transistor M N2 The following relationship exists between the widths: Among them, W P2 Indicates the second PMOS transistor M P2 Width, W N2 Indicates the second NMOS transistor M N2 Width, μ p The mobility μ of a PMOS transistor is represented by this value. n This represents the mobility of the NMOS transistor. The third PMOS transistor M... P3 The third NMOS transistor M N3 The following relationship exists between the widths: Among them, W N3 Indicates the third NMOS transistor M N3 Width, W P3 Indicates the third PMOS transistor W P3 Width, μ p The mobility μ of a PMOS transistor is represented by this value. n This represents the mobility of an NMOS transistor.

[0045] In this embodiment, the width of the corresponding NMOS and PMOS transistors is reduced by employing a preset scaling factor. For example, in Figure 1 In the middle, the second PMOS transistor M P2 The second NMOS transistor M N2 The width is determined by the following formula 1, wherein the third PMOS transistor M P3 The third NMOS transistor M N3 The width is determined by the following formula 2.

[0046] Formula 1:

[0047] Among them, W P2 Indicates the second PMOS transistor M P2 Width, W N2 Indicates the second NMOS transistor M N2 Width, μ pThe mobility μ of a PMOS transistor is represented by this value. n α represents the mobility of the NMOS transistor; α represents the preset scaling factor.

[0048] Formula 2:

[0049] Among them, W N3 Indicates the third NMOS transistor M N3 Width, W P3 Indicates the third PMOS transistor W P3 Width, μ p The mobility μ of a PMOS transistor is represented by this value. n α represents the mobility of the NMOS transistor; α represents the preset scaling factor.

[0050] It should be noted that the first NMOS transistor M N1 and the first PMOS transistor M P1 The width ratio between them is approximately equal to The fourth PMOS transistor M P4 and the fourth NMOS transistor M N4 The width ratio between them is approximately equal to

[0051] Combination Figure 1 If the digital driver 10 does not use the preset reduction factor provided in this embodiment, the delay time for the input terminal IN to pull the first node A from low level to high level based on the edge direction in the first node A is determined by the following formula 3.

[0052] The delay time for pulling the second node B from high level to low level from the first node A to the second node B is determined by the following formula 4.

[0053] Formula 3: t pLH,A ≈0.69R eqP,A C L,A ;

[0054] Among them, R eqP,A It is the first PMOS transistor M P1 The equivalent on-resistance, L indicates the first PMOS transistor M P1 The length of W represents the mobility of the PMOS transistor. P1 Indicates the first PMOS transistor M P1 width; C L,A C is the equivalent load capacitance of the first node A. L,A ∝(W N2 +W P2 L, W N2Indicates the second NMOS transistor M N2 Width, W P2 Indicates the second PMOS transistor M P2 The width, L, represents the width of the second NMOS transistor M. N2 The length of the second PMOS transistor M P2 Length; t pLH,A This indicates the delay time during which the input terminal IN pulls the first node A from a low level to a high level.

[0055] Formula 4: t pHL,B ≈0.69R eqN,B C L,B ;

[0056] Among them, R eqN,B It is the first PMOS transistor M P1 The equivalent on-resistance, L represents the second NMOS transistor M. N2 Length, μ N W represents the mobility of an NMOS transistor. N2 Indicates the second NMOS transistor M N2 width; C L,B C is the equivalent load capacitance of node B at node E. L,B ∝(W N3 +W P3 L, W N3 Indicates the third NMOS transistor M N3 Width, W P3 Indicates the third PMOS transistor M P3 The width, L, represents the third NMOS transistor M. N3 The length of the third PMOS transistor M P3 Length; t pHL,B This represents the delay time during which node A pulls node B from a high level to a low level.

[0057] Therefore, for Figure 1 If the digital driver 10 does not use the preset reduction factor provided in this embodiment, the corresponding delay time can be determined by the following formula 5.

[0058] Formula 5:

[0059] Among them, T delay-regular express Figure 1 The digital driver 10 shown has a time delay when the preset scaling factor provided in this embodiment is not used; t pLH,A This represents the delay time during which the input terminal IN pulls the first node A from a low level to a high level; tpHL,B This represents the delay time during which node A pulls node B from a high level to a low level; W in Formula 5 P1 W P2 W P3 W N2 W N3 μ P μ N The meaning is the same as before, and will not be repeated here.

[0060] for Figure 1 If the digital driver 10 does not use the preset scaling factor provided in this embodiment, the corresponding power consumption can be determined by the following formula 6.

[0061] Formula 6: P regular ∝[(W N2 +W P2 )+(W N3 +W P3 )];

[0062] Among them, P regular express Figure 1 The power consumption of the digital driver 10 when the preset scaling factor provided in this embodiment is not used. P2 W P3 W N2 W N3 The meaning is the same as before, and will not be repeated here.

[0063] This embodiment employs a preset scaling factor, and the second PMOS transistor M... P2 The second PMOS transistor M was reduced by a preset shrinkage factor α. P2 Width W P2 This reduces C L,A ,thereby Figure 1 After the digital driver 10 shown is subjected to a preset scaling factor α, the delay time of the digital driver 10 can be determined according to the following formula 7.

[0064] Formula 7:

[0065] Among them, T delay-proposed This indicates that the digital driver 10 uses a delay time after a preset scaling factor α, T delay-regular This indicates the delay time when the digital driver 10 is not using the preset scaling factor α. α represents the preset scaling factor.

[0066] It should be further noted that the delay time of the digital driver 10 after applying a preset scaling factor α is positively correlated with the preset scaling factor. Specifically, as shown in Formula 7, the larger the preset scaling factor α, the larger the delay time after applying it; conversely, the smaller the preset scaling factor α, the smaller the delay time. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 The diagram shown illustrates the delay of a digital driver. Figure 2 In the middle, T delay-proposed This indicates that the digital driver 10 uses a delay time after a preset scaling factor α, T delay-regular This represents the delay time when the digital driver 10 does not use a preset scaling factor α, where T delay-proposed Less than T delay-regular .

[0067] also, Figure 1 After the digital driver 10 shown is subjected to a preset reduction factor α, the power of the digital driver 10 can be determined according to the following formula 8.

[0068] Formula 8:

[0069] Among them, P proposed This indicates that the digital driver 10 uses power after a preset reduction factor α; P regular This indicates the power of the digital driver 10 when the preset scaling factor α is not used; α represents the preset scaling factor.

[0070] Please see Figure 3 , Figure 3 The image shown is a schematic diagram of the simulation results. If the preset scaling factor α = 0.25, as shown... Figure 3 As shown in the bar chart, the actual circuit delay time was reduced by 31.3% in the post-simulation of the layout. Furthermore, the load capacitance and power consumption of each node in the logic transmission path also decreased by (1+α) / 2.

[0071] It should be noted that this approach of using unbalanced NMOS and PMOS transistor sizes to reduce delay and power consumption can also be extended to other digital logic circuits, such as NAND gates, NOR gates, and logic gates in flip-flops (DFFs).

[0072] The digital driver provided in this embodiment uses a preset scaling factor to adjust the size of NMOS transistors and PMOS transistors, which can reduce latency and power consumption.

[0073] Example 2

[0074] This disclosure also provides a feedback circuit for an analog-to-digital converter.

[0075] For details, see Figure 4A , Figure 4A The diagram shows a structural schematic of a feedback circuit for an analog-to-digital converter. The feedback circuit 40 for the analog-to-digital converter includes:

[0076] The DAC consists of a capacitor-type DAC 401, a comparator circuit 402, an asynchronous logic control circuit 403, and a DAC switch control circuit 404.

[0077] The capacitive DAC includes multiple capacitors C1, C2, ..., C i ... and multiple digital drivers 4011, each of which is a digital driver provided in Embodiment 1;

[0078] The asynchronous logic control circuit 403 includes multiple flip-flops (DFFs). A The DAC switch control circuit 404 includes multiple flip-flops (DFFs). D ;

[0079] Each capacitor C i The output of the capacitive DAC 401 is connected to the input terminal of the corresponding digital driver 4011, and the output terminal of the comparator circuit 402 is connected to the input terminal of the comparator circuit 402.

[0080] The output of the comparator circuit 402 is connected to each of the flip-flops (DFFs) of the asynchronous logic control circuit 403. A The input terminal is connected;

[0081] Each flip-flop (DFF) of the asynchronous logic control circuit 403 A The output terminal is connected to the corresponding trigger DFF of the DAC switch control circuit 404. D The input terminal is connected;

[0082] Each flip-flop (DFF) of the DAC switch control circuit 404 D The output terminal is connected to the input terminal of the corresponding digital driver 4011.

[0083] In this embodiment, each of the digital drivers 4011 is the digital driver provided in Embodiment 1, possessing the structure and advantages of the digital driver in Embodiment 1. The digital driver 4011 is composed of unbalanced NMOS transistors and PMOS transistors. The widths of the NMOS transistors and PMOS transistors are adjusted according to a preset shrinkage factor to reduce SAR logic delay and overcome the speed bottleneck of the single-pass SAR ADC.

[0084] In this embodiment, the analog-to-digital converter (ADC) can be a monotonic capacitor-switched SAR ADC. A monotonic capacitor-switched SAR ADC has the characteristic of switching only in a unidirectional switching DAC. By adjusting the size of the NMOS and PMOS transistors of the logic gates on one side, the delay from the comparator to the DAC can be reduced. The digital driver in this embodiment uses a preset scaling factor, proposes unbalanced NMOS and PMOS transistor sizes, improves the logic speed on critical edge transitions, and reduces the transistor size in non-critical edge directions.

[0085] This approach improves speed while simultaneously reducing the power consumption and area of ​​the SAR ADC, thus overcoming the limitation of SAR ADCs having to compromise between power consumption and latency. More importantly, this scheme does not change the classic one-bit-per-cycle structure, retaining all the advantages of traditional architectures. Implementing the 10-bit 550MS / s SAR ADC of this embodiment in a CMOS process, at a speed of 550MS / s, the SAR ADC achieved a signal-to-noise ratio (SNDR) of 56.0dB at the Nyquist input signal frequency, with a corresponding power consumption of 1.37mW, resulting in a Walden figure of merit (FoM) of 4.78fJ / conv-step (femtojoule per conversion).

[0086] The following is combined with Figure 4A The usage of the feedback circuit for the analog-to-digital converter is explained.

[0087] During the sampling phase, each digital driver 4011 converts the capacitors C of the capacitive DAC 401. i The bottom plate is reset to VDD. Then, based on the digital output (OUT) of comparator circuit 402... P / OUT N ) and the corresponding SAR logic clock (CLK) i ) Capacitor C for each bit i The bottom electrode plate can be switched to GND (critical edge direction) or kept unchanged at VDD (non-critical edge direction). For example... Figure 1 As shown, for the i-th capacitor C i The bottom plate, whose critical speed edge is always a falling edge, corresponds to the DAC switching control signal (DAC). i The critical speed edge of the SAR is always a rising edge. Similarly, the asynchronous control SAR logic clock (CLK) i The corresponding critical speed edge is always a rising edge, and all DFFs applied to asynchronous control logic are... A Reset during the sampling phase. Based on the above analysis, it can be concluded that from capacitor C... iThe DAC switching control signal (DAC) output from the bottom plate to the digital driver 4011 and the DAC switching control circuit 404. i ), the SAR logic clock (CLK) output by the asynchronous logic control circuit 403 i The critical velocity edge is always fixed and is in a single direction.

[0088] In most cases, transconductance (g) is used. m A balanced N / P-MOS digital buffer is used to drive the switching of the capacitive DAC to ensure that the digital buffer has essentially symmetrical rising and falling edges and similar N / P delay times. However, for the logic driver of the monotonic capacitive DAC switch, it is unidirectional in each cycle of each SAR transition. This means that critical data transmission only needs to be optimized in a single direction. Figure 4A The digital driver 4011 in the embodiment is the digital driver provided in embodiment 1, combined with Figure 1 As shown in the digital driver 10, the digital driver is composed of unbalanced N / P-MOS transistors. During the conversion phase, capacitor C acts as a capacitor. i The bottom plate node "OUT" is switched to GND or remains unchanged. Therefore, the critical edges in the output terminal OUT, the third node C, the second node B, and the first node A are always falling / rising / falling / rising edges, respectively. Figure 4A The structure and implementation principle of the digital driver 4011 can be found in the relevant description of the digital driver 10 in Embodiment 1, and will not be repeated here.

[0089] Please refer to it again. Figure 4A The comparison circuit 402 includes a comparator 4021, a NOR gate 4022, and a first inverter 4023. The input terminal of the comparator 4021 is connected to the output terminal of the capacitive DAC 401, the output terminal of the comparator 4021 is connected to the input terminal of the NOR gate 4022, the output terminal of the NOR gate 4022 is connected to the input terminal of the first inverter 4023, and the output terminal of the first inverter 4023 is connected to the input terminals of each flip-flop of the asynchronous logic control circuit 403.

[0090] Please see Figure 4B OUT P / OUT N These represent the two corresponding output signals of the fully differential comparator, with the Ready signal indicating the valid signal in the asynchronous SAR logic conversion. Φ comp CLK represents the clock signal of the comparator. i CLK represents the asynchronous control clock for SAR logic. i Its function is to indicate that the i-th SAR period is being converted. DAC iThis represents the digital-to-analog conversion information of the i-th DAC. Figure 4B In the diagram, curve 41 and curve 42 represent the subsequent rising / falling edge being triggered by the previous rising / falling edge. First arrow segment 43 represents the rising edge, and second arrow segment 44 represents the falling edge.

[0091] Please see Figure 5A , Figure 5A The feedback circuit shown for the analog-to-digital converter and Figure 4A The difference in the feedback circuit for the analog-to-digital converter shown is that the comparator circuit 402 further includes a second inverter 4024 and a NAND gate 4025. The first and second input terminals of the NAND gate are respectively connected to the output terminal of the NOR gate 4022 and the output terminal of the second inverter 4024. The output terminal of the NAND gate 4025 is connected to the control terminal of the comparator 4021. The input terminal of the second inverter 4024 is used to receive the sampled signal.

[0092] In one embodiment, each flip-flop (DFF) of the asynchronous logic control circuit 403 A Including digital drivers and various triggers (DFFs) A The digital driver is the digital driver provided in Example 1.

[0093] Thus, each trigger DFF A The digital driver is the digital driver provided in Example 1, and each flip-flop (DFF) A Correspondingly, each flip-flop (DFF) possesses the structure and advantages of the digital driver in Embodiment 1. A The digital driver consists of unbalanced NMOS transistors and PMOS transistors. The width of the NMOS transistors and PMOS transistors is adjusted according to a preset shrinkage factor to reduce SAR logic delay and overcome the speed bottleneck of single-pass SAR ADC.

[0094] In one embodiment, each flip-flop (DFF) of the DAC switch control circuit 404 D Including digital drivers and various triggers (DFFs) D The digital driver is the digital driver provided in Example 1.

[0095] Thus, each trigger DFF D The digital driver is the digital driver provided in Example 1, and each flip-flop (DFF) D Correspondingly, each flip-flop (DFF) possesses the structure and advantages of the digital driver in Embodiment 1. DThe digital driver consists of unbalanced NMOS transistors and PMOS transistors. The width of the NMOS transistors and PMOS transistors is adjusted according to a preset shrinkage factor to reduce SAR logic delay and overcome the speed bottleneck of single-pass SAR ADC.

[0096] In one embodiment, the preset reduction factor of each digital driver of the capacitive DAC401 ranges from [0.25, 0.5].

[0097] In one embodiment, the preset scaling factor of the digital driver for each trigger ranges from [0.1, 0.25].

[0098] The following is combined with Figure 5A The range of values ​​for the preset reduction factor is explained.

[0099] For SAR ADCs, the value of the preset reduction factor α is set according to the different positions of the logic gates in the feedback path. For example... Figure 5A As shown, the feedback loop of the SAR ADC is divided into three key delay paths: path 1, path 2, and path 3. Path 1 shows the selection and reset path of the comparator module 402 during the conversion stage. In path 1, since the rising and falling edges control the reset and selection of the comparator respectively, and both are critical to the overall conversion rate, conventional big.LITTLE logic, such as NAND gates and NOR gates, is used in this path 1 to ensure similar rising and falling edges. Path 2 shows the path between comparator 4021, asynchronous logic control circuit 403, and DAC switch control circuit 404, from the "Ready" signal generated by the output of comparator 4021 to the asynchronously controlled SAR logic clock CLK. i Path 3 shows the path from the DAC switch control circuit 404 to the digital driver 4011, from the DAC switch control logic DAC... i To capacitor C i Between the bottom plates.

[0100] Please see Figure 5B , Φ S The SAR conversion represents the clock used for signal sampling; the SAR conversion represents the clock used for successive approximation conversion of the obtained signal after sampling; Φ comp The comparator clock signal is represented by the Ready signal, indicating a valid signal in the asynchronous logic control circuit. CLK1 represents the first SAR clock generated by the asynchronous control logic during the successive approximation transition; DAC1 represents the digital-to-analog converter (DAC) signal corresponding to the first clock cycle generated by the asynchronous control logic during the successive approximation transition. Similarly, CLK... iThe DAC represents the i-th SAR clock generated by the asynchronous control logic during the successive approximation transition process. i This represents the digital-to-analog converter (DAC) signal corresponding to the i-th clock cycle generated by the asynchronous control logic during the successive approximation conversion process. For this example, the directionality of the key edges shown in the figure is universal, such as CLK. i and DAC i The critical edge is always the rising edge.

[0101] In this embodiment, non-critical edges are placed in the sampling phase, while critical edges are placed in the SAR conversion phase. The SAR logic clock CLK is controlled asynchronously. i For example, without affecting the performance of the ADC, CLK i There is a time allotted for non-critical edge transitions (resets) that exceeds the entire sampling phase. Therefore, the preset scaling factor α on path 2 can be as small as possible; for example, the preset scaling factor α can be selected between 0.1 and 0.25.

[0102] In SAR logic feedback loops, registers such as the DFF (Distributed Front-End Gate) typically account for a major portion of the delay time and power consumption. The DFF can be redesigned and optimized using unbalanced N / P-MOS transistors. This reduces the number of logic gates required for the critical propagation path in the DFF. Furthermore, using unbalanced N / P-MOS logic gates further reduces the critical path delay. (See also...) Figure 6 Compared to traditional triggers, the trigger (DFF) provided in this embodiment reduces the post-simulation delay time of the layout by more than 77%. For path 3, special attention needs to be paid to capacitor C during one-sided optimization. i The reset status. In fact, capacitor C... i A slow reset will affect the sampling accuracy of the ADC. In this solution, if... Figure 5A As shown, a sampling clock φ is used. S Directly reset DAC switch control signal DAC i In path 3, the preset shrinkage factor α can be selected between 0.25 and 0.5 to improve unidirectional high-speed propagation during the conversion stage, while maintaining a moderate reset capability of the DAC during the sampling stage. Furthermore, the unbalanced N / P-MOS size adjustment method not only reduces the load capacitance of each node on the critical path but also significantly reduces the number of buffers required to drive them, thereby further reducing logic latency and power consumption.

[0103] Using the feedback circuit for the analog-to-digital converter provided in this embodiment, a 10-bit SAR ADC was fabricated in a 28nm CMOS process, with an effective area of ​​0.0023mm². 2This 10-bit SAR ADC has 11 cycles, including 1 bit of redundancy. The first two Most Significant Bits (MSBs) use a split monotonic switched capacitor structure, while the remaining bits use a pure monotonic switched capacitor structure. A custom-designed metal-oxide-metal (MOM) capacitor array is used as the input capacitor for the SAR ADC, with a single-sided input capacitance of 180fF, enabling the integral nonlinearity (INL) to reach -0.51 / +0.60 Least Significant Bits (LSBs) in the 10-bit configuration. Tested at a 0.9V supply voltage, operating at 550MS / s, the SAR ADC exhibits a Nyquist signal-to-noise ratio (SNDR) of 56.0dB and a spurious-free dynamic range (SFDR) of 71.5dB.

[0104] The SAR ADC provided in this embodiment breaks through the physical velocity limitation of single-channel 10b SAR, achieving a higher f-value than working models with similar Walden figure of merit (FOMW) without any calibration. snyq At the same time, compared to all f snyq FOM operating at >501MHz W At least 2x / 1.8x lower. Additionally, it should be noted that the feedback circuit for the analog-to-digital converter provided in this embodiment is fully applicable to many SAR variants, such as time-interleaved SAR (TI-SAR), pipelined SAR, and noise-shaping SAR.

[0105] Example 3

[0106] Furthermore, this disclosure provides an analog-to-digital converter that includes the feedback circuit for the analog-to-digital converter provided in Embodiment 2.

[0107] The analog-to-digital converter provided in this embodiment includes the feedback circuit for the analog-to-digital converter provided in Embodiment 2. Therefore, it has the corresponding structure, function and beneficial effects of the feedback circuit for the analog-to-digital converter provided in Embodiment 2. To avoid repetition, it will not be described in detail here.

[0108] Example 4

[0109] Furthermore, this disclosure provides an electronic device that includes the analog-to-digital converter provided in Embodiment 3.

[0110] The electronic device provided in this embodiment includes the analog-to-digital converter provided in embodiment 3, and therefore has the corresponding structure, function and beneficial effects of the analog-to-digital converter provided in embodiment 3. To avoid repetition, it will not be described in detail here.

[0111] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A digital driver, characterized in that, include: Input terminal, output terminal, first PMOS transistor, second PMOS transistor, third PMOS transistor, fourth PMOS transistor, first NMOS transistor, second NMOS transistor, third NMOS transistor and fourth NMOS transistor; The input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor. The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the gate of the second NMOS transistor are connected to the first node. The drain of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor are connected to the second node; The drain of the third PMOS transistor, the drain of the third NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor are connected to the third node. The drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the output terminal are connected; wherein, the widths of the first PMOS transistor, the second NMOS transistor, the third PMOS transistor, and the fourth NMOS transistor are determined according to the load that the digital driver needs to drive; the widths of the second PMOS transistor, the fourth PMOS transistor, the first NMOS transistor, and the third NMOS transistor are determined according to the mobility of the PMOS transistor, the mobility of the NMOS transistor, and a preset shrinkage factor, wherein the preset shrinkage factor has a value range of (0, 1); The first NMOS transistor M N1 The width is equal to the preset shrinkage factor and the width of the first PMOS transistor M. P1 The quotient is obtained by dividing the width of the PMOS transistor and the mobility of the NMOS transistor by the mobility of the PMOS transistor, and the product of the three values. The second PMOS transistor M P2 The width is equal to the preset shrinkage factor and the second NMOS transistor M. N2 The quotient is obtained by dividing the width of the NMOS transistor and the mobility of the PMOS transistor by the mobility of the PMOS transistor, and the product of the three values. The third NMOS transistor M N3 The width is equal to the preset shrinkage factor and the third PMOS transistor M. P3 The product of the width of the transistor, the quotient obtained by dividing the mobility of the PMOS transistor by the mobility of the NMOS transistor, and the three values. The fourth PMOS transistor M P4 The width is equal to the preset shrinkage factor, the width of the fourth NMOS transistor MN4, and the quotient obtained by dividing the mobility of the NMOS transistor by the mobility of the PMOS transistor, and the product of the three. The delay time of the digital driver is positively correlated with the preset reduction factor.

2. A feedback circuit for an analog-to-digital converter, characterized in that, include: Capacitor-type DAC, comparator circuit, asynchronous logic control circuit, and DAC switching control circuit; The capacitive DAC includes multiple capacitors and multiple digital drivers, each of which is the digital driver as described in claim 1; The asynchronous logic control circuit and the DAC switch control circuit each include multiple flip-flops; Each capacitor is connected to the input terminal of the corresponding digital driver, and the output terminal of the capacitive DAC is connected to the input terminal of the comparator circuit. The output of the comparator circuit is connected to the input of each flip-flop in the asynchronous logic control circuit. The output terminals of each flip-flop in the asynchronous logic control circuit are connected to the input terminals of the corresponding flip-flops in the DAC switch control circuit. The output terminals of each flip-flop in the DAC switch control circuit are connected to the input terminals of the corresponding digital drivers.

3. The feedback circuit for an analog-to-digital converter according to claim 2, characterized in that, The comparison circuit includes a comparator, a NOR gate, and a first inverter. The input of the comparator is connected to the output of the capacitive DAC, the output of the comparator is connected to the input of the NOR gate, the output of the NOR gate is connected to the input of the first inverter, and the output of the first inverter is connected to the input of each flip-flop of the asynchronous logic control circuit.

4. The feedback circuit for an analog-to-digital converter according to claim 3, characterized in that, The comparison circuit further includes a second inverter and a NAND gate. The first and second input terminals of the NAND gate are respectively connected to the output terminal of the NOR gate and the output terminal of the second inverter. The output terminal of the NAND gate is connected to the control terminal of the comparator. The input terminal of the second inverter is used to receive the sampling signal.

5. The feedback circuit for an analog-to-digital converter according to claim 2, characterized in that, Each trigger includes a digital driver, and the digital driver of each trigger is the digital driver as described in claim 1.

6. The feedback circuit for an analog-to-digital converter according to claim 2, characterized in that, The preset reduction factor of each digital driver of the capacitive DAC ranges from [0.25, 0.5].

7. The feedback circuit for an analog-to-digital converter according to claim 5, characterized in that, The preset scaling factor of each trigger digital driver ranges from [0.1, 0.25].

8. An analog-to-digital converter, characterized in that, Includes a feedback circuit for an analog-to-digital converter as described in any one of claims 2-7.

9. An electronic device, characterized in that, Includes the analog-to-digital converter as described in claim 8.

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