Three-dimensional NAND memory devices and methods of forming the same

Abstract

According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes one or more bottom select gate (BSG) layers located over a substrate, a plurality of word line layers located over the one or more BSG layers, and a plurality of insulating layers located on the substrate. The plurality of insulating layers are disposed on a surface of the substrate, the one or more BSG layers, and the plurality of word line layers. The semiconductor device includes a first dielectric structure extending from the substrate and through the one or more BSG layers, and a second dielectric structure extending from the first dielectric structure and through the plurality of word line layers.

Description

Background Technology

[0001] As the critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been searching for techniques to stack multiple memory cell planes to achieve greater storage capacity and lower cost per bit. 3D NAND memory devices are exemplary devices for stacking multiple memory cell planes to achieve greater storage capacity and lower cost per bit. A 3D NAND memory device may include a stack of alternating insulating layers and word line layers above a substrate, wherein one or more of the bottommost word line layers in the stack can serve as bottom select gate (BSG) layers. Multiple dummy channel structures can extend from the substrate and through the insulating layers and word line layers to support the stack. Furthermore, multiple BSG dicing structures can be formed to separate the BSG layers into sub-BSG layers. Summary of the Invention

[0002] This disclosure describes embodiments generally related to a dummy channel structure in a 3D NAND memory device, the dummy channel structure including a bottom portion in a BSG layer and a top portion extending from the bottom portion. The bottom portion of the dummy channel structure includes a stop layer to improve the fabrication process window of the dummy channel structure.

[0003] According to one aspect of this disclosure, a semiconductor device is provided. The semiconductor device may include one or more bottom select gate (BSG) layers above a substrate, a plurality of word line layers above the one or more BSG layers, and a plurality of insulating layers on the substrate. The plurality of insulating layers may be disposed on the surfaces of the substrate, the one or more BSG layers, and the plurality of word line layers. The semiconductor device may include a first dielectric structure extending from the substrate and through the one or more BSG layers, and a second dielectric structure extending from the first dielectric structure and through the plurality of word line layers.

[0004] In some embodiments, the first dielectric structure may further include: spacers formed above the sidewalls and bottom of the first dielectric structure, and filler located in and in contact with the spacers.

[0005] In the semiconductor device, the critical dimension (CD) of the top surface of the filler of the first dielectric structure may be greater than the CD of the bottom surface of the second dielectric structure. The CD of the bottom surface of the first dielectric structure may be greater than the CD of the bottom surface of the second dielectric structure.

[0006] In some embodiments, the filler may include one of polysilicon and a dielectric material. The filler may be configured as an etch stop layer to prevent the second dielectric structure from extending through the first dielectric structure. Therefore, the second dielectric structure can extend from the filler, and the bottom portion of the second dielectric structure may also contact the spacer.

[0007] In some embodiments, the cross-section of the first dielectric structure obtained along a direction parallel to the substrate may include one of a circular shape and an elliptical shape. The cross-section of the second dielectric structure obtained along the direction parallel to the substrate may also include one of a circular shape and an elliptical shape.

[0008] The semiconductor device may include a first slot structure extending through the one or more BSG layers and the plurality of word line layers and further into the substrate. The first slot structure may further extend along a horizontal direction parallel to the substrate. The semiconductor device may include a second slot structure extending through the one or more BSG layers and the plurality of word line layers and further into the substrate. The second slot structure may be positioned in the horizontal direction along the same line as the first slot structure. The semiconductor device may also include a partition structure extending through the one or more BSG layers and further into the substrate, wherein the partition structure may further be located between the first slot structure and the second slot structure and extend in the horizontal direction.

[0009] In some embodiments, the spacer structure may include a dielectric layer, wherein the dielectric layer is formed together with the spacer of the first dielectric structure based on a deposition process.

[0010] In some embodiments, the first dielectric structure may be further positioned adjacent to and in contact with the separating structure.

[0011] In some embodiments, the partition structure may further include: a dielectric layer formed along the sidewalls and bottom of the partition structure; and a polycrystalline silicon layer located in and in contact with the dielectric layer.

[0012] In some embodiments, the dielectric layer of the separator structure and the spacer of the first dielectric structure may be formed based on a first deposition process, and the polysilicon layer of the separator structure and the filler of the first dielectric structure may be formed based on a second deposition process.

[0013] The semiconductor device may include a dummy channel structure, which includes the first dielectric structure and the second dielectric structure. The semiconductor device may also include a three-dimensional NAND flash memory device.

[0014] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided. In this method, one or more sacrificial BSG layers may be formed over a substrate, and a plurality of first insulating layers may be formed on the surfaces of the substrate and the one or more sacrificial BSG layers. A first opening extending through the one or more sacrificial BSG layers and the plurality of first insulating layers and further into the substrate may be formed by a first etching process. The first opening may include sidewalls and a bottom extending into the substrate. A first dielectric structure may then be formed in the first opening. A plurality of sacrificial word line layers and a plurality of second insulating layers may be formed in an alternating stack over the one or more sacrificial BSG layers. A second dielectric structure extending from the first dielectric structure and through the plurality of sacrificial word line layers and the plurality of second insulating layers may be formed.

[0015] To form the first dielectric structure in the first opening, a dielectric material can be conformally deposited using a first deposition process to form spacers along the sidewalls of the first opening and above the bottom of the first opening. A second deposition process can be used to deposit polycrystalline silicon over the spacers in the first opening to form a filler.

[0016] In some embodiments, the critical dimension (CD) of the top surface of the filler of the first dielectric structure may be greater than the CD of the bottom surface of the second dielectric structure, and the CD of the bottom surface of the first dielectric structure may be greater than the CD of the bottom surface of the second dielectric structure.

[0017] To form the second dielectric structure, a second opening may be formed extending through the plurality of sacrificial word lines and the plurality of second insulating layers and further into the filler. The filler may be removed to form a third opening, wherein the third opening may include a bottom portion in contact with the spacer and a top portion in contact with the plurality of sacrificial word lines and the plurality of second insulating layers. The third opening may be filled to form the second dielectric structure in the top portion of the third opening.

[0018] In the method, trench openings can be formed using the first etching process. The trench openings can be formed to extend through the one or more sacrificial BSG layers and further extend in a horizontal direction parallel to the substrate. The trench openings may include sidewalls and a bottom extending into the substrate. The dielectric material can be conformally deposited using the first deposition process to form a dielectric layer along the sidewalls of the trench openings and above the bottom of the trench openings. The polysilicon can be deposited over the dielectric layer in the trench openings using the second deposition process to form a separation structure.

[0019] To form the second dielectric structure, a second etching process can be performed to form a second opening. The second opening can extend through the plurality of sacrificial word lines and the plurality of second insulating layers to expose the filler. The second etching process can further remove a portion of the filler. A dielectric material can be used to fill the second opening to form the second dielectric structure, such that the second dielectric structure extends from the filler and the bottom portion of the second dielectric structure contacts the spacer.

[0020] In some embodiments, the filler may be configured as an etch stop layer to prevent the second etch process from extending through the first dielectric structure.

[0021] In the method, trench openings can be formed by the first etching process. The trench openings can extend through the one or more sacrificial BSG layers and the plurality of first insulating layers and into the substrate. The trench openings can be filled with the dielectric material by the first deposition process to form a separation structure.

[0022] In this method, a first slot structure may be formed extending through the one or more sacrificial BSG layers and the sacrificial word line layers into the substrate. The first slot structure may further extend horizontally. A second slot structure may be formed extending through the one or more sacrificial BSG layers and the sacrificial word line layers into the substrate, wherein the second slot structure may be positioned horizontally along the same line as the first slot structure. Therefore, the separating structure may extend through the one or more sacrificial BSG layers and the plurality of first insulating layers. The separating structure may be located between the first slot structure and the second slot structure and further extend horizontally.

[0023] In some embodiments, the one or more sacrificial BSG layers and the plurality of sacrificial word line layers may be replaced with a conductive material to form one or more BSG layers and the plurality of word line layers.

[0024] According to another aspect of this disclosure, a memory system device is provided. The memory system device may include control circuitry coupled to the memory device. The memory device may include one or more bottom select gate (BSG) layers located above a substrate, and a plurality of word line layers located above the one or more BSG layers. The memory device may include a plurality of insulating layers located above the substrate and disposed on the surfaces of the substrate, the one or more BSG layers, and the plurality of word line layers. The memory device may include a first dielectric structure extending from the substrate and through the one or more BSG layers, and a second dielectric structure extending from the first dielectric structure and through the plurality of word line layers. Attached Figure Description

[0025] The various aspects of this disclosure can be understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

[0026] Figure 1 This is a top view of a 3D NAND memory device in a relevant example of an exemplary embodiment of the present disclosure.

[0027] Figure 2A This is a top view of a first 3D NAND memory device according to an exemplary embodiment of the present disclosure.

[0028] Figure 2B This is a top view of a second 3D NAND memory device according to an exemplary embodiment of the present disclosure.

[0029] Figure 3 This is a cross-sectional view of a first 3D NAND memory device according to an exemplary embodiment of the present disclosure.

[0030] Figure 4 This is a cross-sectional view of a second 3D NAND memory device according to an exemplary embodiment of the present disclosure.

[0031] Figure 5-11 This is a cross-sectional view of the various intermediate steps in the manufacture of a first 3D NAND memory device according to an exemplary embodiment of the present disclosure.

[0032] Figure 12-22 These are cross-sectional and top views of various intermediate steps in the manufacture of a second 3D NAND memory device according to exemplary embodiments of the present disclosure.

[0033] Figure 23This is a flowchart illustrating a process for manufacturing a 3D NAND memory device according to an exemplary embodiment of the present disclosure.

[0034] Figure 24 This is a block diagram of a memory system device according to exemplary embodiments of the present disclosure. Detailed Implementation

[0035] The following disclosure provides numerous different embodiments or examples to facilitate the implementation of various features of the provided object. Specific examples of components and apparatus are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples within this disclosure. Such repetition is merely for simplicity and clarity, and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0036] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” etc., are used herein to describe the relationship of an element or feature as shown in the figures to one or more other elements or features. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0037] In relevant 3D NAND memory devices, alternating stacks of insulating layers and word line layers can be formed over a substrate, wherein one or more lowest word line layers in the stack can serve as bottom select gate (BSG) layers. Furthermore, multiple BSG cleaving structures can be formed to separate the BSG layers into sub-BSG layers. The stack can include array regions and stepped regions. Multiple channel structures can extend from the substrate and through the insulating layers and word line layers in the array regions to form multiple strings of memory cells. Multiple dummy channel structures can extend from the substrate and through the insulating layers and word line layers in the stepped regions. The dummy channel structures can further extend into the substrate and serve as support members to support the stepped regions and / or array regions when the sacrificial layer is removed to form the word line layers.

[0038] To form a dummy channel structure, an etching process can be performed to create dummy channel openings that extend through the insulating layer and word line layer in the stepped region and further into the substrate. However, as 3D NAND memory devices shift towards higher storage densities and incorporate more and more word line layers into the 3D NAND memory devices, underetching may occur at the bottom of the dummy channel openings. Additionally, the depth of the grooves (or gouging) into the substrate by the dummy channel openings may be uneven. Furthermore, the bottom portion of the dummy channel structure may deform due to a smaller bottom critical dimension (CD).

[0039] In this disclosure, the dummy channel structure can be formed from multiple portions. These different portions may include a bottom portion located in the BSG layer and a top portion extending from the bottom portion. In one embodiment, the bottom portion of the dummy channel structure may be formed together with a BSG dicing structure. For example, the formation of the bottom portion of the dummy channel structure and the BSG dicing structure may share photolithography, etching, deposition processes, etc., or combinations thereof, to save process time and cost. In another embodiment, different processes may be used to fabricate the bottom portion of the dummy channel structure and the BSG dicing structure. The bottom portion may have a larger CD compared to the CD of the dummy channel structure in the related examples. A larger CD can prevent under-etching and improve the bottom profile of the dummy channel structure, which in turn can improve the support strength of the dummy channel structure and improve the uniformity of the trench. The bottom portion may also include a stop layer (e.g., a polysilicon layer) to improve the formation process window of the dummy channel structure.

[0040] Figure 1 A top view of a 3D NAND memory device (or device) 100 in a related example is shown. Device 100 may include one or more BSG layers above a substrate, a plurality of word line layers above the one or more BSG layers, and a plurality of insulating layers alternately disposed between the one or more BSG layers and the plurality of word line layers. For example, it may be possible to... Figure 1The device 100 provides an uppermost insulating layer 106 among a plurality of insulating layers. The device 100 may include a plurality of dummy channel structures 104 extending from the substrate and further through the one or more BSG layers, the plurality of word line layers, and the plurality of insulating layers. The device 100 may also include a plurality of slot structures (e.g., 108a-108c) extending from the substrate and further through the one or more BSG layers, the plurality of word line layers, and the plurality of insulating layers. These slot structures may further extend along a horizontal direction parallel to the substrate (e.g., the X direction). A plurality of BSG cleaving structures extending from the substrate and further through the one or more BSG layers may be formed (e.g., in regions 102a-102b) to divide the one or more BSG layers into a plurality of sub-BSG layers. Each of these sub-BSG layers may receive a corresponding operating voltage via word line contacts (not shown) coupled to the sub-BSG layer.

[0041] In some embodiments, a post-gate fabrication technique is used to form device 100. A slot structure is formed to help remove the sacrificial word line layer and form the true gate (or word line layer). In some embodiments, the slot structure may be made of a conductive material and located on an array common source (ACS) region (not shown) to serve as a contact, wherein the ACS region is formed in the substrate to serve as a common source. In some embodiments, the slot structure may be made of a dielectric material to serve as a separation structure.

[0042] Still referencing Figure 1 Each of the plurality of BSG dicing structures (e.g., in regions 102a-102b) can be arranged between two corresponding slot structures of the plurality of slot structures. For example, BSG dicing structure 102a can be located between slot structures 108a and 108b. In some embodiments, end portions of the slot structures can extend further into the BSG dicing structure to form overlapping regions. For example, end portions of slot structures 108a and 108b can extend into BSG dicing structure 102a to form overlapping regions 110 and 112, respectively. In device 100, to form the dummy channel structure 104, a plurality of dummy channel openings can be formed extending through one or more BSG layers, insulating layers, and word line layers and further into the substrate. As 3D NAND memory devices move toward higher storage densities and more and more word line layers are incorporated into device 100, under-etching may occur at the bottom of the dummy channel openings. Additionally, the groove depth (or slotting) of the dummy channel openings into the substrate may be uneven. In addition, the bottom portion of the dummy channel structure may deform due to the smaller bottom CD.

[0043] Figure 2AThis is a top view of a 3D NAND memory device (or device) 200A according to an embodiment of this disclosure. Figure 2A As shown, device 200A may have a configuration similar to device 100. For example, device 200A may have multiple slot structures (e.g., 208a-208c) extending through one or more BSG layers, multiple word line layers, and multiple insulating layers (e.g., insulating layer 206). The multiple slot structures may further extend in a direction parallel to the substrate (e.g., the X direction). Device 200A may include multiple BSG cut structures located between the slot structures (e.g., in regions 202a-202b). Device 200A may also include multiple dummy channel structures 204 extending from the substrate and further through the one or more BSG layers, the multiple word line layers, and the multiple insulating layers. However, compared with... Figure 1 Compared to the virtual channel structure 104 in the middle, Figure 2A Each dummy channel structure 204 may include multiple portions, such as a bottom portion 204a and a top portion 204b. In other embodiments, additional portions may be provided. The bottom portion 204a may be formed together with the BSG cut structure. The bottom portion 204a may extend from the substrate and through the one or more BSG layers. The top portion 204b may extend from the bottom portion 204a and further through multiple word line layers.

[0044] Figure 2B This is a top view of a 3D NAND memory device (or device) 200B according to an embodiment of this disclosure. Figure 2B As shown, device 200B may include multiple dummy channel structures (e.g., 214 and 216), multiple slot structures (e.g., 212a and 212b), multiple BSG cut structures (e.g., 210), multiple word line layers, and multiple insulating layers (e.g., 218). Figure 2A Compared to the 200A equipment, Figure 2B The bottom portion of the virtual channel structure in the middle can have a higher degree of flexibility than... Figure 2A The bottom portion of the dummy channel structure 204 has a larger dimension (e.g., width or CD). For example, the bottom portion of the dummy channel structure 214 may include a first portion 214a' and a second portion 214a'", wherein the first portion 214a' contacts the BSG cut structure 210, and the top portion 214b of the dummy channel structure 214 may extend from the second portion 214a'.

[0045] Figure 3 This is a cross-sectional view of a 3D NAND memory device (or device) 300 according to an embodiment of the present disclosure. Figure 3As shown, device 300 may include one or more BSG layers 306a-306b above substrate 302, a plurality of word line layers 308 above the one or more BSG layers 306a-306b, and a plurality of insulating layers 304 above substrate 302. The plurality of insulating layers 304 may be alternately disposed between the one or more BSG layers 306a-306b and the plurality of word line layers 308. Device 300 may include a dummy channel structure 314. The dummy channel structure 314 may include: a first dielectric structure (or bottom portion) 316 extending from substrate 302 and through the one or more BSG layers 306a-306b, and a second dielectric structure (or top portion) 318 extending from the first dielectric structure 316 and through the plurality of word line layers 308.

[0046] In some embodiments, the first dielectric structure 316 may further include spacers 310 conformally formed above the sidewalls 316a and bottom 316b of the first dielectric structure 316, and filler 320 located in and surrounded (or in contact with) the spacers 310.

[0047] In some embodiments, the filler 320 may include one of polycrystalline silicon and a dielectric material. Figure 3 In some embodiments, the filler 320 may be a polysilicon layer. Therefore, the second dielectric structure 318 may extend from the polysilicon layer 320, and the bottom portion of the second dielectric structure 318 may be further surrounded (or contacted) by the spacer 310.

[0048] In some embodiments, such as Figure 2A and Figure 2B As shown, the cross-section of the first dielectric structure 316 obtained along a direction parallel to the substrate 302 (e.g., the Y direction) may include one of a circular shape and an elliptical shape. The cross-section of the second dielectric structure 318 obtained along a direction parallel to the substrate may also include one of a circular shape and an elliptical shape.

[0049] Device 300 may include a separation structure (or BSG dicing structure) 312 extending from substrate 302 and through one or more BSG layers 306a-306b. Figure 2A and Figure 2B As shown, the partition structure 312 may also be located between the first slit structure and the second slit structure (e.g., 208a and 208b) and extend in the horizontal direction (e.g., the X direction).

[0050] In device 300, the CD D1 of the top surface of the filler 320 of the first dielectric structure 316 can be greater than the CD D2 of the bottom surface of the second dielectric structure 318 that contacts the filler 320. Furthermore, the CD D3 of the bottom surface of the first dielectric structure 316 can be greater than the CD D2 of the bottom surface of the second dielectric structure 318. As mentioned above, a larger bottom CD (e.g., D3) of the dummy channel structure can prevent or reduce incomplete etching and improve the bottom profile of the dummy channel structure, which in turn can improve the support strength of the dummy channel structure and improve the uniformity of the trenching.

[0051] It should be noted that, Figure 3 This is just one example. Depending on the circuit design, device 300 can include any number of BSG layers, any number of BSG cut structures, any number of dummy channel structures, and any number of word line layers. Furthermore, Figure 3 An exemplary dummy channel structure (e.g., 314) is provided, comprising two portions (e.g., a first dielectric structure 316 and a second dielectric structure 318). However, the dummy channel structure may include more than two portions that may be stacked over a substrate and extend through a BSG layer (e.g., 306), a word line layer (e.g., 308), and an insulating layer (e.g., 304).

[0052] In some embodiments, substrate 302 may be a semiconductor substrate, such as a Si substrate. The material of substrate 302 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. For example, in some embodiments, the material of substrate 302 may also include silicon phosphide (SiP), silicon carbide phosphide (SiPC), silicon-on-insulator (SOI) structures, SiGe structures on SOI, Ge structures on SOI, III-VI materials, or any combination of the above materials. Furthermore, the material of substrate 302 may optionally include an epitaxial layer (epi layer) that can be strained to enhance performance and / or have other suitable enhancing features.

[0053] The insulating layer 304 may be made of SiO2. The BSG layers 306a-306b and the word line layer 308 may be made of W, polysilicon, or other conductive materials. The materials of the spacer 310 and the second dielectric structure 318 may include SiO, SiN, SiC, SiCN, or other suitable dielectric materials. In some embodiments, the BSG layers 306a-306b and the word line layer 308 may be initially formed of a dielectric material (e.g., SiN) and used as sacrificial BSG layers and sacrificial word line layers. The sacrificial BSG layers and sacrificial word line layers may be replaced with conductive materials such as W to form the BSG layers 306a-306b and the word line layer 308.

[0054] Figure 4 A cross-sectional view of a 3D NAND memory device (or device) 400 according to an embodiment of the present disclosure is shown. The device 400 may have one or more BSG layers 406a-406b formed over a substrate 402, a plurality of word line layers 408 formed over the one or more BSG layers 406a-406b, and a plurality of insulating layers 404 alternately located between the one or more BSG layers 406a-406b and the plurality of word line layers 408. The device 400 may include a separator structure (or BSG dicing structure) 412 extending from the substrate 402 and through the one or more BSG layers 406a-406b. The separator structure 412 may also include a dielectric layer (or spacer) 410 formed along the sidewalls and bottom of the separator structure 412, and a polysilicon layer 422 located in and surrounded by the dielectric layer 410. The device 400 may include a dummy channel structure 414, which includes a bottom portion 416 and a top portion 418. The bottom portion 416 may extend from the substrate 402 and further through one or more BSG layers 406a-406b. The top portion 418 may extend from the bottom portion 416 and further through the word line layer 408 and the insulating layer 404 located above the spacer 410.

[0055] The bottom portion 416 of the dummy channel structure 414 may include spacers 410 formed along the sidewalls and bottom of the bottom portion 416, and a filler 420 located within and surrounded by the spacers (or dielectric layers) 410. In some embodiments, the spacers 410 and the filler 420 may be made of the same material. In some embodiments, the spacers 410 and the filler 420 may be made of different materials. For example, the materials of the spacers 410 and the filler 420 may include SiO, SiC, SiN, SiCN, SiCON, etc. In some embodiments, the filler 420 may include polycrystalline silicon. In an exemplary embodiment, the insulating layer 404, the spacers 410, and the filler 420 may be made of the same material (e.g., SiO).

[0056] Figure 5-11 This is a cross-sectional view of various intermediate steps in the manufacture of a 3D NAND memory device (or apparatus) 300 according to an exemplary embodiment of the present disclosure. Figure 5In this process, one or more BSG layers 306a-306b can be formed above the substrate 302, and a plurality of insulating layers 304 can be formed on the top and bottom surfaces of the one or more BSG layers 306a-306b, such that the one or more BSG layers 306a-206b can be spaced apart from each other by the insulating layers 304. Furthermore, a mask layer 322 can be formed on the one or more BSG layers 306a-306b and the insulating layer 304 by a photolithography process. The mask layer 322 may include a first pattern 324 and a second pattern 326 capable of exposing one or more portions of the uppermost insulating layer. To form the one or more BSG layers 306a-306b and the insulating layer 304, any suitable deposition process can be applied, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, sputtering, diffusion, or any combination thereof. Photolithography processes (e.g., photolithography or electron beam lithography) may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof.

[0057] exist Figure 6 In this process, etching processes such as plasma dry etching or wet etching can be applied to transfer the first pattern 324 and the second pattern 326 into one or more BSG layers 306a-306b and the insulating layer 304. Therefore, trench openings 328 and first openings 330 can be formed based on the first pattern 324 and the second pattern 326, respectively. Trench openings 328 and first openings 330 can extend through one or more BSG layers 306a-306b and the insulating layer 304, and further into the substrate 302.

[0058] exist Figure 7In this process, a spacer 310 can be formed along the sidewall of the first opening 330 and above the bottom of the first opening 330. The spacer 310 can further completely fill the trench opening 328 to form a partition structure (or BSG cut structure) 312. Furthermore, an etch stop layer 332 can be formed along the sidewall and bottom of the spacer 310. The etch stop layer 332 can also be disposed on the spacer 310. The material of the etch stop layer 332 can include polysilicon or a dielectric material having an etch rate lower than that of the spacer 310 or the insulating layer 304. For example, the etch stop layer 332 may have an etch rate 5-10 times lower than that of the spacer 310 or the insulating layer 304. The etch stop layer 332 prevents the etching process from penetrating the spacer 310 and extending into the substrate 302 during subsequent manufacturing processes.

[0059] exist Figure 8 In this process, surface planarization processes such as etch-back or chemical mechanical planarization (CMP) can be applied to remove any excess etch stop layer 332 above the spacer 310. The etch stop layer 332 retained in the first opening 330 can be a filler 334 surrounded by the spacer 310.

[0060] exist Figure 9 In this process, multiple word line layers 308 and multiple insulating layers 304 may be alternately formed over the spacer 310. In some embodiments, the word line layers 308 may be made of a dielectric material such as SiN and serve as sacrificial word line layers. The sacrificial word line layers may then be replaced with conductive materials in subsequent steps to form word line layers. In some embodiments, the word line layers 308 may be made of conductive materials (e.g., polycrystalline silicon or tungsten).

[0061] exist Figure 10In this process, a mask layer (not shown) can be formed by photolithography, and an etching process can then be applied to form a second opening 336 based on the mask layer. The second opening 336 can extend through the word line layer 308 and the insulating layer 304 located above the spacer 310. The etching process further removes a portion of the filler 334 to form a filler 320. Therefore, the bottom portion of the second opening 336 can be further surrounded by the spacer 310. When the second opening 336 is formed by the etching process, a bottom portion (or a first dielectric structure) 316 of a dummy channel structure (e.g., 314) can be formed accordingly. The bottom portion 316 of the dummy channel structure can include spacers 310 extending through one or more BSG layers 306a-306b and further into the substrate 302, and filler 320 surrounded by spacers 310. It should be noted that when the etching process etches through the word line layer 308 and the insulating layer 304 to form the second opening 336, the filler 334 can serve as an etch stop layer. By introducing filler (or etch stop layer) 334, the second opening 336 can be prevented from extending into the substrate 302 through filler 334 and spacer 310.

[0062] exist Figure 11 In this process, dielectric material can be deposited to fill the second opening 336. Any excess dielectric material above the uppermost insulating layer 304 can be further removed using a CMP process. The dielectric material retained in the second opening 336 can form the top portion (or second dielectric structure) 318 of the dummy channel structure 314. When the top portion 318 of the dummy channel structure 314 is formed, the device 300 can be formed accordingly. The device 300 can have... Figure 3 The devices in the series have similar characteristics to 300. For example, Figure 11 The device 300 may include a dummy channel structure 314 extending through one or more BSG layers 306-306b, word line layer 308, and insulating layer 304. The dummy channel structure 314 may include a bottom portion 316 located in one or more BSG layers 306a-306b, and a top portion 318 located above the bottom portion 316.

[0063] Figure 12-22 These are cross-sectional and top views of various intermediate steps in the manufacture of a second 3D NAND memory device (or device) 400, according to exemplary embodiments of the present disclosure. Figure 12In this process, one or more BSG layers 406a-406b can be formed above the substrate 402, and multiple insulating layers 404 can be formed on the top and bottom surfaces of the one or more BSG layers 406a-406b, such that the one or more BSG layers 406a-406b can be spaced apart from each other. Furthermore, a mask layer 424 can be formed above the one or more BSG layers 406a-406b and the insulating layers 404 using a photolithography process. The mask layer 424 may include a first pattern 426 and a second pattern 428, which can expose a portion of the uppermost insulating layer 404.

[0064] Figure 13 This is a cross-sectional view of trench openings and a first opening formed in one or more BSG layers and insulating layers based on mask layer 424. Figure 14 This is a top view of the trench openings and the first opening in one or more BSG layers and insulating layers based on mask layer 424. Figure 13 From and along Figure 14 The line A-A' is obtained from a plane that is perpendicular to the same plane. For example... Figure 13 As shown, an etching process can be applied to transfer the first pattern 426 and the second pattern 428 into one or more BSG layers 406a-406b and the insulating layer 404. Therefore, trench openings 430 and first openings 432 can be formed based on the first pattern 426 and the second pattern 428, respectively. Trench openings 430 and first openings 432 can extend through one or more BSG layers 406a-406b and the insulating layer 404, and further into the substrate 402. Figure 14 In this process, multiple groove openings 430 and multiple first openings 432 can be formed. For example, the groove openings 430 can have a rectangular outline, and the first openings 432 can have a circular or elliptical shape.

[0065] exist Figure 15 In this process, spacers 410 can be formed along the sidewalls of the trench opening 430 and the first opening 432, and at the bottom of the trench opening 430 and the first opening 432. Furthermore, an etch stop layer 434 can be formed above the spacers 410. The etch stop layer 434 can also be disposed on the spacers 410. The material of the etch stop layer 434 can include polysilicon or a dielectric material, wherein the polysilicon or dielectric material has an etch rate different from the etch rate of the spacers 410 or the insulating layer 404.

[0066] exist Figure 16In this process, surface planarization, such as an etch-back process or a CMP process, can be applied to remove any excess etch stop layer 434 above the spacer 410. The etch stop layer 434 retained in the first opening 432 can be a filler 436 surrounded by the spacer 410. Alternatively, the etch stop layer 434 retained in the trench opening 430 can be a polysilicon layer 422 located in and surrounded by the spacer 410. Thus, a spacer structure (or BSG dicing structure) 412 can be formed. The BSG dicing structure 412 can include a spacer (or dielectric layer) 410 formed along the sidewalls and bottom of the spacer structure 412, and a polysilicon layer 422 located in and surrounded by the dielectric layer 410.

[0067] exist Figure 17 In this process, multiple word line layers 408 and multiple insulating layers 404 may be alternately formed over the spacer 410. In some embodiments, the word line layers 408 may be made of a dielectric material such as SiN and serve as sacrificial word line layers. The sacrificial word line layers may then be replaced with conductive materials in subsequent steps to form word line layers.

[0068] Figure 18 This is a cross-sectional view showing the formation of the second opening in the word line layer 408 and the insulating layer 404. Figure 19 This is a top view of the second opening.

[0069] Figure 18 From and along Figure 19 The line B-B' is obtained from the plane that is perpendicular to the plane. For example... Figure 18 As shown, an etching process can be applied to form the second opening 438. The second opening 438 can extend through the word line layer 408 and the insulating layer 404, and further into the filler 436. Figure 19 In this process, multiple second openings 438 can be formed. The multiple second openings 438 can, for example, have a circular shape or an elliptical shape.

[0070] exist Figure 20The filler 436 can be removed by an etching process such as a wet etching process or a plasma dry etching process. For example, when the filler 436 is made of polysilicon, tetramethylammonium hydroxide (TMAH) can be applied to remove the filler 436. This etching process can be a selective removal process, allowing the filler 436 to be removed while the spacer 410 remains. When the filler 436 is removed, a third opening 440 can be formed. The third opening 440 can include a bottom portion 440a and a top portion 440b. The bottom portion can extend through one or more BSG layers 406a-406b and further into the substrate 402, and is surrounded by the spacer 410. The top portion 440b can extend from the bottom portion 440a and through the word line layer 408 and the insulating layer 404 located above the spacer 410.

[0071] Figure 21 This is a cross-sectional view of a virtual channel structure formed by filling the third opening 440 with dielectric material. Figure 22 This is a top view of a fictitious trench structure. Figure 21 From and along Figure 21 The line C-C' is obtained from the same plane as the perpendicular plane of the line. For example... Figure 21 As shown, a dielectric material such as SiO can be applied to fill the third opening 440. Therefore, a dummy channel structure 414 can be formed. The dielectric material located in the bottom portion 440a of the third opening 440 can serve as filler 420. Filler 420 and spacer 410 can form the bottom portion 416 of the dummy channel structure 414. In some embodiments, spacer 410 and filler 420 can be made of the same material. In some embodiments, spacer 410 and filler 420 can be made of different materials. The dielectric material located in the top portion 440b of the third opening 440 can serve as the top portion 418 of the dummy channel structure 414. When the dummy channel structure 414 is formed, a device 400 can be formed accordingly, which can have a similar Figure 4 The characteristics of device 400. In Figure 22 In this process, when the third opening 440 is filled with a dielectric material, multiple dummy channel structures 414 can be formed. The dummy channel structures 414 can have a circular or elliptical shape.

[0072] Figure 23This is a flowchart of an exemplary process 2300 for manufacturing a 3D NAND memory device. Process 2300 begins at S2301 and then proceeds to S2310. In S2310, one or more BSG layers and a plurality of first insulating layers may be formed over a substrate. A plurality of first insulating layers may be formed on the surface of the substrate and the one or more sacrificial BSG layers. In some embodiments, as referenced... Figure 5 or Figure 12 Perform S2310 as described.

[0073] In S2320, a first opening extending through one or more sacrificial BSG layers and multiple first insulating layers and further into the substrate can be formed by a first etching process. The first opening may include sidewalls and a bottom extending into the substrate. In some embodiments, it may be as referenced Figure 6 or Figure 13-14 Perform S2320 as described.

[0074] Then, process 2300 proceeds to S2330, whereby a first dielectric structure can subsequently be formed in the first opening. To form the first dielectric structure in the first opening, a dielectric material can be conformally deposited using a first deposition process to form spacers along the sidewalls of the first opening and above the bottom of the first opening. Polysilicon can be further deposited over the spacers in the first opening using a second deposition process to form a filler. In some embodiments, it can be as referenced... Figure 7-8 or Figure 15-16 Perform S2330 as described.

[0075] In S2340, a plurality of sacrificial word line layers and a plurality of second insulating layers may be formed alternately stacked over one or more sacrificial BSG layers. In some embodiments, this may be as referenced. Figure 9 or Figure 17 Perform S2340 as described.

[0076] In S2350, a second dielectric structure can be formed extending from the first dielectric structure and passing through a plurality of sacrificial word line layers and a plurality of second insulating layers. In some embodiments, it can be as referenced Figure 10-11 or Figure 18-22 Perform S2350 as described.

[0077] In some embodiments, the critical dimension (CD) of the top surface of the filler of the first dielectric structure may be greater than the CD of the bottom surface of the second dielectric structure, and the CD of the bottom surface of the first dielectric structure may be greater than the CD of the bottom surface of the second dielectric structure.

[0078] In process 2300, such as Figure 18-21As shown, to form the second dielectric structure, the second opening can be formed to extend through multiple sacrificial word line layers and multiple second insulating layers and further into the filler. The filler can be removed to form a third opening, wherein the third opening may include a bottom portion in contact with the spacer and a top portion in contact with the multiple sacrificial word line layers and multiple second insulating layers. The third opening can be filled to form the second dielectric structure in the top portion of the third opening.

[0079] In process 2300, such as Figure 13-16 As shown, a trench opening can be formed using a first etching process. The trench opening can be formed to extend through one or more sacrificial BSG layers and further extend in a horizontal direction parallel to the substrate. The trench opening may include sidewalls and a bottom extending into the substrate. A dielectric material can be conformally deposited using a first deposition process to form a dielectric layer along the sidewalls of the trench opening and above the bottom of the trench opening. Polysilicon can be deposited over the dielectric layer in the trench opening using a second deposition process to form a separation structure.

[0080] In some embodiments, in order to form a second dielectric structure, such as Figure 10 and Figure 11 As shown, a second etching process can be performed to form a second opening. The second opening can extend through multiple sacrificial word line layers and multiple second insulating layers to expose the filler. The second etching process can further remove a portion of the filler. The second opening can be filled with a dielectric material to form a second dielectric structure, such that the second dielectric structure extends from the filler and the bottom portion of the second dielectric structure contacts the spacer.

[0081] In some embodiments, the filler may be configured as an etch stop layer to prevent a second etch process from extending through the first dielectric structure.

[0082] In process 2300, such as Figure 6 and Figure 7 As shown, a trench opening can be formed by a first etching process. This trench opening can extend through one or more sacrificial BSG layers and multiple first insulating layers and into the substrate. The trench opening can be filled with a dielectric material by a first deposition process to form a separation structure.

[0083] In process 2300, such as Figure 2A and Figure 2BAs shown, a first slot structure can be formed extending through one or more sacrificial BSG layers and sacrificial word line layers into the substrate. The first slot structure can further extend in a horizontal direction. A second slot structure can be formed extending through one or more sacrificial BSG layers and sacrificial word line layers into the substrate, wherein the second slot structure can be positioned in the horizontal direction along the same line as the first slot structure. Therefore, a separator structure can extend through one or more sacrificial BSG layers and multiple first insulating layers. The separator structure can be located between the first and second slot structures and further extend in a horizontal direction.

[0084] In some embodiments, one or more sacrificial BSG layers and multiple sacrificial word line layers may be replaced with conductive materials to form one or more BSG layers and multiple word line layers.

[0085] It should be noted that additional steps may be provided before, during, and after process 2300, and for other embodiments of process 2300, some of the described steps may be replaced, eliminated, or performed in a different order. In subsequent process steps, various other interconnect structures (e.g., metallization layers with wires and / or vias) may be formed over the 3D NAND memory device (e.g., 300). Such interconnect structures electrically connect the 3D NAND memory device to other contact structures and / or active devices to form functional circuitry. Other device features such as passivation layers, input / output structures, etc., may also be formed.

[0086] Figure 24 A block diagram of a memory system device 1900 according to some examples of this disclosure is shown. The memory system device 1900 includes one or more semiconductor memory devices, such as those shown in semiconductor memory devices 1911-1914, which can be respectively connected to… Figure 3 Equipment 300 or Figure 4 The device 400 shown is configured similarly. In some examples, the memory system device 1900 is a solid-state drive (SSD) or a memory module.

[0087] The memory system device 1900 may include other suitable components. For example, the memory system device 1900 includes, for instance, components such as... Figure 24The interface (or main interface circuit) 1901 and the main controller (or main control circuit) 1902 are coupled together as shown. The memory system device 1900 may include a bus 1920 that couples the main controller 1902 to the semiconductor memory devices 1911-1914. Furthermore, the main controller 1902 is connected to the semiconductor memory devices 1911-1914 respectively, for example, as shown by the corresponding control lines 1921-1924.

[0088] Interface 1901 is appropriately mechanically and electrically configured to connect between memory system device 1900 and host device, and can be used to transfer data between memory system device 1900 and host device.

[0089] The main controller 1902 is configured to connect the individual semiconductor memory devices 1911-1914 to the interface 1901 for data transfer. For example, the main controller 1902 is configured to provide enable / disable signals to the semiconductor memory devices 1911-1914 respectively to activate one or more semiconductor memory devices 1911-1914 for data transfer.

[0090] The main controller 1902 is responsible for executing various instructions within the memory system device 1900. For example, the main controller 1902 can perform bad block management, error checking and correction, garbage collection, and so on. In some embodiments, a processor chip is used to implement the main controller 1902. In some examples, multiple master control units (MCUs) are used to implement the main controller 1902.

[0091] The various embodiments described herein offer several advantages over the related examples. In this disclosure, a dummy channel structure can be formed including a bottom portion located in a BSG layer and a top portion extending from the bottom portion. In one embodiment, the bottom portion of the dummy channel structure can be formed together with a BSG dicing structure to share one or more manufacturing processes, thereby saving process time and cost. In another embodiment, different processes can be used to manufacture the bottom portion of the dummy channel structure and the BSG dicing structure. The bottom portion can have a larger CD compared to the CD of the dummy channel structure in the related examples. A larger CD can prevent under-etching and improve the bottom profile of the dummy channel structure, which in turn can improve the support strength of the dummy channel structure and improve the uniformity of the trench. The bottom portion may also include a stop layer (e.g., a polysilicon layer) to improve the formation process window of the dummy channel structure.

[0092] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: One or more bottom select gate (BSG) layers located above the substrate; Multiple word line layers located above the one or more bottom select gate layers; A plurality of insulating layers are located above the substrate and disposed on the surfaces of the substrate, the one or more bottom select gate layers and the plurality of word line layers; A first dielectric structure extending from the substrate and through the one or more bottom selected gate layers; A second dielectric structure extending from the first dielectric structure and passing through the plurality of word line layers; as well as A virtual channel structure is provided, comprising a first dielectric structure and a second dielectric structure in a one-to-one correspondence. Wherein, the critical dimension of the bottom surface of the first dielectric structure is greater than the critical dimension of the bottom surface of the second dielectric structure, and The first dielectric structure includes a spacer and a filler, wherein the spacer surrounds the sidewalls and bottom portion of the filler such that the filler is located on the bottom portion of the spacer and contacts the bottom portion of the spacer.

2. The semiconductor device according to claim 1, wherein, The spacers are conformally formed above the sidewalls and bottom of the first dielectric structure.

3. The semiconductor device according to claim 2, wherein: The critical dimension (CD) of the top surface of the filler in the first dielectric structure is greater than the critical dimension of the bottom surface of the second dielectric structure.

4. The semiconductor device according to claim 2, wherein, The filler comprises one of polysilicon and a dielectric material, and the filler is configured as an etch stop layer to prevent the second dielectric structure from extending through the first dielectric structure.

5. The semiconductor device according to any one of claims 2-4, wherein, The second dielectric structure extends from the filler, and the bottom portion of the second dielectric structure contacts the spacer.

6. The semiconductor device according to any one of claims 2-4, further comprising: A first slot structure extends through the one or more bottom select gate layers and the plurality of word line layers and further into the substrate, the first slot structure further extending along a horizontal direction parallel to the substrate; A second slot structure extends through the one or more bottom select gate layers and the plurality of word line layers and further into the substrate, the second slot structure being positioned in the horizontal direction along the same line as the first slot structure; as well as A partition structure extends through the one or more bottom selected gate layers and further into the substrate, the partition structure being further located between the first slot structure and the second slot structure and extending in the horizontal direction.

7. The semiconductor device according to claim 6, wherein, The separation structure includes a dielectric layer, which is formed together with the spacer of the first dielectric structure using a deposition process.

8. The semiconductor device according to claim 6, wherein, The first dielectric structure is further positioned adjacent to and in contact with the partition structure.

9. The semiconductor device according to claim 6, wherein, The partition structure also includes: A dielectric layer conformally formed along the sidewalls and bottom of the partition structure; and A polycrystalline silicon layer located in and in contact with the dielectric layer.

10. The semiconductor device according to claim 9, wherein: Based on a first deposition process, the dielectric layer of the separation structure and the spacer of the first dielectric structure are formed, and The polycrystalline silicon layer of the separation structure and the filler of the first dielectric structure are formed based on the second deposition process.

11. The semiconductor device according to any one of claims 1-4 and 7-10, wherein, The semiconductor device includes a three-dimensional NAND flash memory device.

12. A method for manufacturing a semiconductor device, comprising: One or more sacrificial bottom select gate (BSG) layers and a plurality of first insulating layers are formed on the substrate and the surfaces of the one or more sacrificial bottom select gate layers; A first opening is formed by a first etching process, the first opening extending through the one or more sacrificial bottom select gate layers and the plurality of first insulating layers and extending into the substrate, the first opening including sidewalls and bottom extending into the substrate; A first dielectric structure with a virtual channel structure is formed in the first opening; Multiple sacrificial word line layers and multiple second insulating layers are formed, the multiple sacrificial word line layers and multiple second insulating layers being alternately stacked over one or more sacrificial bottom select gate layers; as well as A second dielectric structure is formed to form the dummy channel structure. The second dielectric structure extends from the first dielectric structure and passes through the plurality of sacrificial word line layers and the plurality of second insulating layers. Wherein, the critical dimension of the bottom surface of the first dielectric structure is greater than the critical dimension of the bottom surface of the second dielectric structure. The virtual channel structure includes a first dielectric structure and a second dielectric structure that correspond one-to-one. The first dielectric structure includes a spacer and a filler, wherein the spacer surrounds the sidewalls and bottom portion of the filler such that the filler is located on the bottom portion of the spacer and contacts the bottom portion of the spacer.

13. The method according to claim 12, wherein, The formation of the first dielectric structure further includes: A dielectric material is conformally deposited using a first deposition process to form the spacer along the sidewall of the first opening and above the bottom of the first opening; and Polycrystalline silicon is deposited over the spacer in the first opening using a second deposition process to form the filler.

14. The method of claim 13, wherein: The critical dimension (CD) of the top surface of the filler in the first dielectric structure is greater than the critical dimension of the bottom surface of the second dielectric structure.

15. The method according to claim 13, wherein, The formation of the second dielectric structure further includes: A second opening is formed extending through the plurality of sacrificial word line layers and the plurality of second insulating layers, the second opening further extending into the filler; The filler is removed to form a third opening, the third opening including a bottom portion in contact with the spacer and a top portion in contact with the plurality of sacrificial letter lines and the plurality of second insulating layers; and The third opening is filled to form the second dielectric structure in the top portion of the third opening.

16. The method according to any one of claims 13-15, further comprising: A trench opening is formed in one or more sacrificial bottom select gate layers by the first etching process. The trench opening extends through the one or more sacrificial bottom select gate layers and further extends in a horizontal direction parallel to the substrate. The trench opening includes sidewalls and a bottom extending into the substrate. The dielectric material is conformally deposited using the first deposition process to form a dielectric layer along the sidewalls of the trench opening and above the bottom of the trench opening; as well as The polysilicon is deposited over the dielectric layer in the trench opening using the second deposition process to form a separation structure.

17. The method according to any one of claims 13-15, wherein, The formation of the second dielectric structure further includes: A second etching process is performed to form a second opening extending through the plurality of sacrificial word line layers and the plurality of second insulating layers, thereby exposing the filler, the second etching process further removing a portion of the filler; and The second opening is filled with a dielectric material to form the second dielectric structure, such that the second dielectric structure extends from the filler and the bottom portion of the second dielectric structure contacts the spacer.

18. The method according to claim 17, wherein, The filler is configured as an etch stop layer to prevent the second etch process from extending through the first dielectric structure.

19. The method according to any one of claims 13-15 and 18, further comprising: A trench opening is formed by the first etching process, the trench opening extending through the one or more sacrificial bottom select gate layers and the plurality of first insulating layers and extending into the substrate; as well as The first deposition process uses the dielectric material to fill the trench openings to form a partition structure.

20. The method of claim 16, further comprising: A first slot structure is formed that extends through the one or more sacrificial bottom select gate layers and the sacrificial word line layers and into the substrate, the first slot structure further extending along the horizontal direction; as well as A second slot structure is formed extending through the one or more sacrificial bottom select gate layers and the sacrificial word line layers and into the substrate, the second slot structure being positioned in the horizontal direction along the same line as the first slot structure, wherein... The partition structure extends through the one or more sacrificial bottom select gate layers and the plurality of first insulating layers, the partition structure is located between the first slot structure and the second slot structure, and the partition structure further extends in the horizontal direction.

21. The method according to any one of claims 13-15, 18, and 20, further comprising: The one or more sacrificial bottom select gate layers and the plurality of sacrificial word line layers are replaced with conductive material to form one or more bottom select gate layers and the plurality of word line layers.

22. A memory system device, comprising: Control circuitry coupled to the memory device; as well as The memory device includes: One or more bottom select gate (BSG) layers located above the substrate; Multiple word line layers located above the one or more bottom select gate layers; A plurality of insulating layers are located above the substrate and disposed on the surfaces of the substrate, the one or more bottom select gate layers and the plurality of word line layers; A first dielectric structure extending from the substrate and through the one or more bottom selected gate layers; A second dielectric structure extending from the first dielectric structure and passing through the plurality of word line layers; and A virtual channel structure, comprising a first dielectric structure and a second dielectric structure in a one-to-one correspondence. Wherein, the critical dimension of the bottom surface of the first dielectric structure is greater than the critical dimension of the bottom surface of the second dielectric structure, and The first dielectric structure includes a spacer and a filler, wherein the spacer surrounds the sidewalls and bottom portion of the filler such that the filler is located on the bottom portion of the spacer and contacts the bottom portion of the spacer.

Images