Storage devices, electronic systems including the same, and methods of operating the same

Abstract

A storage device, a storage device including the same, and a method of operating the same are provided. The storage device includes a non-volatile memory including a first memory block and a second memory block different from the first memory block, and a memory controller configured to receive a first write mode command corresponding to the first memory block and a second write mode command corresponding to the second memory block from a host, control the first memory block to perform a first write operation according to the first write mode command, and control the second memory block to perform a second write operation according to the second write mode command, the first write operation and the second write operation both being sequential write operations.

Description

Technical Field

[0001] This disclosure relates to a storage device, an electronic system including the storage device, and a method of operating the storage device. Background Technology

[0002] Memory devices (e.g., flash memory devices) are non-volatile memory devices and are widely used in devices such as Universal Serial Bus (USB) drives, digital cameras, mobile phones, smartphones, tablet PCs, memory cards, and solid-state drives (SSDs).

[0003] Flash memory devices comprise multiple blocks, each block comprises multiple pages, and each of the multiple pages comprises multiple memory cells.

[0004] In flash memory devices, programming operations are performed on a page-by-page basis, and erasure operations are performed on a block-by-block basis. When data is stored across all or nearly all blocks of the flash memory device, a process is performed to move outdated data and appropriately pack the remaining valid data. This process is called garbage collection. Garbage collection is an example of automatic memory management.

[0005] Research is underway to individually control each block in a memory device from outside the device in order to improve write operation efficiency based on the data type of the memory device, or to implement multiple virtual operating systems, etc., but this research is difficult to carry out due to the automated nature of garbage collection. Summary of the Invention

[0006] This disclosure provides a storage device that allows the host to control the operating mode on a zone-by-zone basis, and in turn, on a block-by-block basis.

[0007] This disclosure also provides an electronic system for a storage device that controls its operation mode on a block basis by allowing the host to control the operation mode on a zone basis.

[0008] This disclosure also provides a method for operating a storage device by allowing the host to control the operating mode on a block-by-block basis, thereby controlling the operating mode on a zone-by-zone basis.

[0009] This disclosure also provides a storage device that performs memory management at the host level on a zone-by-zone basis.

[0010] It should be noted that the purpose of this disclosure will be obvious to those skilled in the art based on the following description.

[0011] According to one aspect of this disclosure, a storage device is provided, comprising: a non-volatile memory including a first memory block and a second memory block different from the first memory block; and a memory controller configured to receive from a host a first write mode command corresponding to the first memory block and a second write mode command corresponding to the second memory block, controlling the first memory block to perform a first write operation according to the first write mode command, and controlling the second memory block to perform a second write operation according to the second write mode command, wherein both the first write operation and the second write operation are sequential write operations.

[0012] According to one aspect of this disclosure, an electronic system is provided, comprising: a non-volatile memory including a first memory block and a second memory block; a host including a file system having a first region and a second region, the first region corresponding to the first memory block and the second region corresponding to the second memory block, the host being configured to provide a memory controller with a first write mode command corresponding to the first memory block, a second write mode command corresponding to the second memory block, a first write command corresponding to the first region, and a second write command corresponding to the second region; and a memory controller being configured to control the first memory block to perform a first write operation based on the first write command and the first write mode command, and to control the second memory block to perform a second write operation based on the second write command and the second write mode command.

[0013] According to one aspect of this disclosure, a method for operating a storage device is provided, the method comprising: receiving a first write mode command corresponding to a first memory block, the first memory block corresponding to a first partition in a file system; receiving a second write mode command corresponding to a second memory block, the second memory block corresponding to a second partition in a file system, and the second partition being different from the first partition; receiving a first write command corresponding to the first partition; performing a first write operation on the first memory block according to the first write command and the first write mode command; receiving a second write command corresponding to the second partition; and performing a second write operation on the second memory block according to the second write command and the second write mode command, wherein both the first write operation and the second write operation are sequential write operations. Attached Figure Description

[0014] The above and other aspects and features of this disclosure will become more apparent from the detailed description of some exemplary embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a block diagram illustrating an electronic system according to some example embodiments of the present disclosure;

[0016] Figure 2This is a block diagram used to describe an electronic system including a storage device according to some example embodiments of the present disclosure;

[0017] Figure 3 It is used to describe Figure 2 A block diagram of the memory controller;

[0018] Figure 4 It is used to describe Figure 2 A block diagram of non-volatile memory;

[0019] Figure 5 This is a perspective view illustrating a non-volatile memory according to some example embodiments of the present disclosure;

[0020] Figure 6 This is a circuit diagram illustrating a memory cell array according to some exemplary embodiments of the present disclosure;

[0021] Figure 7 This is a schematic diagram illustrating the interior of a non-volatile memory according to some example embodiments of the present disclosure;

[0022] Figure 8 and Figure 9 This is a diagram illustrating a method of operating a storage device according to some example embodiments of the present disclosure;

[0023] Figure 10 This is a diagram used to describe the file system and memory blocks used in an electronic system according to some example embodiments of the present disclosure;

[0024] Figure 11 This is a diagram used to describe zones in a file system used in an electronic system according to some example embodiments of the present disclosure;

[0025] Figure 12 and Figure 13 This is a diagram illustrating the operating modes of a memory block in a storage device according to some example embodiments of the present disclosure;

[0026] Figures 14 to 16 This is a diagram illustrating a method of storing data in a memory block of a storage device according to some example embodiments of the present disclosure;

[0027] Figure 17 and Figure 18 This is a diagram illustrating a method for determining an operating mode in an electronic system according to some example embodiments of the present disclosure;

[0028] Figure 19 These are diagrams used to illustrate the operation of an electronic system according to some exemplary embodiments of the present disclosure;

[0029] Figure 20This is a diagram illustrating the waste collection operation of an electronic system according to some example embodiments of the present disclosure;

[0030] Figure 21 This is a block diagram used to describe an electronic system including a storage device according to some example embodiments of the present disclosure;

[0031] Figure 22 This is a block diagram used to describe an electronic system including a storage device according to some example embodiments of the present disclosure;

[0032] Figure 23 This is a schematic diagram illustrating the internal workings of a non-volatile memory according to some example embodiments of the present disclosure; and

[0033] Figure 24 This is a circuit diagram illustrating a portion of a memory cell array according to some example embodiments of the present disclosure. Detailed Implementation

[0034] In the following description, some exemplary embodiments of this disclosure will be described with reference to the accompanying drawings. Figures 1 to 24 In the description, substantially identical components will be represented by the same reference numerals, and overlapping descriptions of corresponding components will be omitted. Furthermore, in the various figures of this disclosure, similar reference numerals are used for similar components.

[0035] Figure 1 This is a block diagram illustrating an electronic system according to some example embodiments of the present disclosure.

[0036] Figure 1 The system 1000 can generally be a mobile system, such as mobile phones, smartphones, tablet PCs, wearable devices, healthcare devices, and / or Internet of Things (IoT) devices. However, Figure 1 The system 1000 is not limited to mobile systems, but can be a personal computer, laptop computer, server, media player and / or automotive equipment such as navigation devices.

[0037] refer to Figure 1 The system 1000 may include a main processor 1100, memories 1020a and 1020b and / or storage devices 1010a and 1010b, and may be supplemented with at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470 and / or a connection interface 1480.

[0038] The main processor 1100 can control the overall operation of the system 1000, and more specifically, control the operation of other components forming the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, an application processor, etc.

[0039] The main processor 1100 may include one or more central processing unit (CPU) cores 1110, and may also include a controller 1120 for controlling memories 1020a and 1200b and / or storage devices 1010a and 1010b. According to some example embodiments, the main processor 1100 may also include an accelerator block 1130, which is dedicated circuitry for high-speed data operations, such as artificial intelligence (AI) data operations. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a discrete chip physically independent of other components of the main processor 1100.

[0040] Memory 1020a and 1020b can be used as the main memory device of system 1000 and may include volatile memory, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), but may include non-volatile memory (NVM), such as flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), and / or resistive RAM (RRAM). Memory 1020a and 1020b may be implemented in the same package as or a similar package to the main processor 1100.

[0041] Storage devices 1010a and 1010b can be used as non-volatile storage devices for storing data regardless of power supply, and can have a relatively large storage capacity compared to memories 1020a and 1020b. Storage devices 1010a and 1010b may each include memory controllers 1200a and 1200b, and NVMs 1300a and 1300b that store data under the control of memory controllers 1200a and 1200b. NVMs 1300a and 1300b may include V-NAND flash memory with a two-dimensional (2D) or three-dimensional (3D) structure, but may include other types of non-volatile memory, such as PRAM, MRAM, and / or RRAM.

[0042] Storage devices 1010a and 1010b may be included in system 1000 in a physically separate state from main processor 1100, or may be implemented in the same or similar package as main processor 1100. Furthermore, storage devices 1010a and 1010b may have the same or similar shape as a memory card and may be detachably coupled to other components of system 1000 via an interface such as connection interface 1480 described later. Storage devices 1010a and 1010b may be devices that apply standard protocols such as universal flash storage (UFS) or NVM express (NVMe), but this disclosure is not limited thereto.

[0043] Image capture device 1410 can capture still images or videos, and can be a camera, camcorder, webcam, etc.

[0044] User input device 1420 can receive various types of data input from the user of system 1000, and can be a touchpad, keypad, keyboard, mouse, microphone, etc.

[0045] Sensor 1430 can sense various types of physical quantities that can be obtained from outside the system 1000 and convert the sensed physical quantities into electrical signals. Sensor 1430 can be a temperature sensor, pressure sensor, illuminance sensor, position sensor, acceleration sensor, biosensor, gyroscope, etc.

[0046] The communication device 1440 can perform signal transmission and / or reception between the system 1000 and other devices outside the system 1000 according to various communication protocols. The communication device 1440 can be implemented by including antennas, transceivers, modems, etc.

[0047] The display 1450 and the speaker 1460 can be used as output devices to output visual and audio information to the user of the system 1000, respectively.

[0048] The power supply device 1470 can appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000.

[0049] Connection interface 1480 provides connectivity between system 1000 and external devices connected to system 1000 and capable of exchanging data with system 1000. Connection interface 1480 can be implemented in various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded MMC (eMMC), UFS, Embedded UFS (eUFS), and / or Compact Flash (CF) card interfaces.

[0050] Figure 2 This is a block diagram used to describe an electronic system including a storage device according to some example embodiments of the present disclosure.

[0051] refer to Figure 2 The electronic system 1a may include a storage device 10 and / or a host device 100. The host device 100 can control the operation of the storage device 10. The storage device 10 may correspond to... Figure 1 Storage devices 1010a and / or 1010b.

[0052] In some example embodiments, storage device 10 may correspond to a flash memory device including one or more flash memory chips. In some example embodiments, storage device 10 may be an embedded memory embedded in electronic system 1a. For example, storage device 10 may be an eMMC, eUFS, or NVMe memory device.

[0053] According to some example embodiments, storage device 10 may be an external memory that can be attached to or detached from electronic system 1a. For example, storage device 10 may be a UFS memory card, CF card, SD card, micro SD card, mini SD card, xD card, and / or Memory Stick.

[0054] The host device 100 may include a processor 110, a host memory 120, and / or a host controller 130. The processor 110, the host memory 120, and the host controller 130 may send and / or receive signals to each other via an internal bus.

[0055] The processor (CPU core) 110 can run various software loaded in the host memory 120. For example, the processor 110 can run an operating system (OS) and applications. The processor 110 can be provided as a homogeneous multi-core processor or a heterogeneous multi-core processor. The processor 110 can correspond to... Figure 1 The main processor is 1100.

[0056] Main memory 120 can be used as main memory and / or cache memory. Furthermore, host memory 120 can be used as driver memory for driver software, firmware, etc. Applications or data to be processed by processor 110 can be loaded into host memory 120. For example, file system 121, applications, device drivers, etc., can be loaded into host memory 120. Host memory 120 can correspond to... Figure 1 The memory 1020a and / or 1020b.

[0057] The file system 121 can store files or data in the storage device 10 and organize the files or data in units of partitions.

[0058] File system 121 may include a partition-to-memory block transition layer 122. File system 121 can provide logical addresses ADDR_L to storage device 10 via partition-to-memory block transition layer 122 according to commands (e.g., write command WCMD or read command). File system 121 can be used according to (e.g., compatible with) a specific operating system running on host device 100, and the operating system may support running files or data on a partition-by-partition basis. According to some example embodiments, multiple different file systems 121 may be used, each corresponding to a different specific operating system running on host device 100 (used according to, compatible with, etc., that different specific operating system).

[0059] Host device 100 can use partition-to-memory block transition layer 122 to manage the storage space of storage device 10, write user data to storage device 10, and read user data from storage device 10. File system 121 and partition-to-memory block transition layer 122 can be implemented by software, firmware, etc.

[0060] The host controller 130 can convert the data format, logical address ADDR_L, data DATA, etc., of commands corresponding to various access requests issued by the host device 100 (e.g., write command WCMD and / or write mode command WMCMD), or convert the format of exchanged commands and transmit the converted commands, addresses, and data to the storage device 10. The host controller 130 may have... Figure 1 The protocol corresponding to the 1480 connection interface protocol.

[0061] In some example embodiments, host device 100 may provide storage device 10 with a physical mapping command PMCMD, which is different from the write command WCMD, separately from the write command WCMD. In some example embodiments, the physical mapping command PMCMD may be included in a portion of the write command WCMD.

[0062] Storage device 10 may include memory controller 200, buffer memory 202, and / or NVM 300. In response to commands provided from host device 100, storage device 10 may access NVM 300 or perform requested operations.

[0063] The memory controller 200 can control the operation of the NVM 300 through channel CH. The memory controller 200 can receive write commands WCMD and logical addresses ADDR_L from the host device 100, and write data DATA to the NVM 300. The following will... Figure 10 The description provides a detailed description of the logical address ADDR_L according to some example embodiments of this disclosure. According to some example embodiments, memory controller 200 may correspond to memory controller 1200a and / or 1200b, and NVM 300 may correspond to NVM 1300a and / or 1300b, as in combination. Figure 1 The subject of discussion.

[0064] The memory controller 200 can determine the operating mode, such as write mode, of the logical address ADDR_L sent from the host in response to the write mode command WMCMD.

[0065] The following will refer to Figure 3 A detailed description of the configuration and operation of the memory controller 200 is provided.

[0066] The buffer memory 202 can temporarily store write data or read data. Write data temporarily stored in the buffer memory 202 can be written to the NVM 300, and read data temporarily stored in the buffer memory 202 can be sent to the host device 100 through the memory controller 200.

[0067] The NVM 300 can perform read / write operations under the control of the memory controller 200. The NVM 300 may include multiple memory blocks BLK 0 to BLK N, and each memory block may include multiple pages. Each page may include multiple memory cells. In some example embodiments, the NVM 300 can perform erase operations on a memory block basis and can perform write or read operations on a page basis.

[0068] Physical addresses can correspond to specific regions of the NVM 300. For example, the physical address used to select a page can be the physical page number (PPN), and the physical address used to select a memory block can be the physical block number (PBN).

[0069] In some example embodiments, the NVM 300 may include multiple flash memory cells. For example, the multiple memory cells may be NAND flash memory cells. However, this disclosure is not limited thereto, and the memory cells may be resistive memory cells, such as resistive RAM (ReRAM), PRAM, and / or MRAM.

[0070] Figure 3 It is used to describe Figure 2 Block diagram of the memory controller. Figure 4 It is used to describe Figure 2 A block diagram of NVM.

[0071] refer to Figure 3 and Figure 4 The memory controller 200 may include a processor 210, a memory 211, a host interface 212, a memory interface 213, and / or a working memory 220. According to some example embodiments, the components of the memory controller 200 (e.g., processor 210, memory 211, host interface 212, memory interface 213, and / or working memory 220) may be coupled together and be able to communicate (e.g., via bus 201).

[0072] Processor 210 may include a CPU, a controller, an application-specific integrated circuit (ASIC), etc. Processor 210 can control the overall operation of memory controller 200. Processor 210 can drive firmware loaded in working memory 220 to control memory controller 200.

[0073] Memory 211 can store information for storage device 10 (see...) Figure 2 The initial startup code data.

[0074] The memory controller 200 can be connected to the host device 100 via the host interface 212. That is, data DATA can be sent and received via the host interface 212. The host interface 212 may include ATA, SATA, eSATA, USB, NVMe, etc.

[0075] The memory controller 200 can be connected to the NVM 300 via the memory interface 213. That is, data (DATA), control signals (CTRL), addresses (ADDR), commands (CMD), etc., can be sent and received via the memory interface 213. The working memory 220 can be implemented as cache memory, DRAM, SRAM, flash memory, etc.

[0076] Working memory 220 may include a flash transition layer (FTL). The FTL may include system software for managing write, read, and erase operations of the NVM 300. For example, the FTL may include firmware. The FTL may be loaded into working memory 220. The firmware of the FTL may be executed by processor 210.

[0077] The working memory 220 may include a wear-leveling manager module 221, a mapping table manager module 222, and / or an address mapping table 223.

[0078] The working memory 220 can use the address mapping table 223 to translate the logical address ADDR_L into a physical address and provide the physical address to the NVM 300.

[0079] According to some example embodiments of this disclosure, the working memory 220 can perform management of the memory cells of the NVM 300. For example, the working memory 220 can manage blocks BLK 0 to BLK N of the memory cell array 310 of the NVM 300 (see...). Figure 2 Perform loss leveling management operations.

[0080] The loss leveling manager module 221 can manage the loss level of the NVM 300 by adjusting the program / erase (P / E) cycle, and according to some example embodiments of this disclosure, the loss leveling manager module 221 is aligned with the memory blocks BLK 0 to BLK N of the memory cell array 310 (see [link to documentation]). Figure 2The same unit (the unit that performs the erase operation) or a similar unit performs the loss leveling operation, so that the mapping table manager module 222 can be controlled at the host device level 100.

[0081] According to some example embodiments of this disclosure, the memory controller 200 does not perform garbage collection operations, so that the host device 100 directly controls the mapping table manager module 222 of the storage device 10 via the logical address ADDR_L.

[0082] The address mapping table manager module 222 can update the address mapping table 223 by reflecting the results of loss leveling operations, control of commands from host device 100, creation / deletion of namespaces, etc.

[0083] Although not shown in the accompanying drawings, when the host device 100 and the storage device 10 support multiple namespaces, the storage device 10 may include a namespace manager module, which may dynamically create namespaces in response to commands from the host device 100 and request the mapping table manager module 222 to update the address mapping table 223 according to the namespace-related commands from the host device 100.

[0084] refer to Figure 4 The NVM 300 may include a memory cell array 310, an address decoder 320, a voltage generator 330, a read / write circuit 340, control logic 350, etc.

[0085] The memory cell array 310 can be connected to the address decoder 320 via word lines WL. The memory cell array 310 can be connected to the read / write circuitry 340 via bit lines BL. The memory cell array 310 may include multiple memory cells. For example, memory cells arranged in the row direction can be connected to word lines WL. For example, memory cells arranged in the column direction can be connected to bit lines BL.

[0086] Address decoder 320 can be connected to memory cell array 310 via word line WL. Address decoder 320 can operate in response to control logic 350. Address decoder 320 can receive address ADDR from memory controller 200. Address decoder 320 can receive voltage from voltage generator 330 for operations such as programming and reading.

[0087] Address decoder 320 can decode the row address of the received address ADDR. Address decoder 320 can use the decoded row address to select the word line WL. The decoded column address DCA can be provided to the read / write circuit 340. For example, address decoder 320 may include a row decoder, a column decoder, an address buffer, etc.

[0088] Under the control of control logic 350, voltage generator 330 can generate voltages for access operations. For example, voltage generator 330 can generate programming voltages and programming verification voltages for performing programming operations. Similarly, voltage generator 330 can generate read voltages for performing read operations, and erase voltages and erase verification voltages for performing erase operations. Furthermore, voltage generator 330 can provide voltages to address decoder 320 for all operations performed by address decoder 320.

[0089] The read / write circuit 340 can be connected to the memory cell array 310 via bit line BL. The read / write circuit 340 can send data to and receive data from the memory controller 200. The read / write circuit 340 can operate in response to control logic 350. The read / write circuit 340 can receive the decoded column address DCA from the address decoder 320. The read / write circuit 340 can use the decoded column address DCA to select bit line BL.

[0090] For example, read / write circuitry 340 can program received data DATA into memory cell array 310. Read / write circuitry 340 can read data from memory cell array 310 and provide the read data to external devices (e.g., memory controller 200). For example, read / write circuitry 340 may include components such as a sense amplifier, write driver, column select circuitry, page buffer, etc.

[0091] Control logic 350 can be connected to address decoder 320, voltage generator 330, and read / write circuitry 340. Control logic 350 can control the operation of NVM 300. Control logic 350 can operate in response to control signals CTRL and commands CMD (e.g., write commands, read commands, etc.) provided from memory controller 200.

[0092] Figure 5 This is a perspective view illustrating NVM according to some example embodiments.

[0093] refer to Figure 4 and Figure 5 According to some example embodiments, the NVM 300 may include a plurality of semiconductor layers LA1 to LAn. Each of the plurality of semiconductor layers LA1 to LAn may be a memory chip (e.g., a DRAM chip), or some of the plurality of semiconductor layers LA1 to LAn may be for performing operations with external devices (e.g., Figure 1 The host device 100) is an interface chip of the main chip, and other semiconductor layers therein can be slave chips that store data.

[0094] For example, the nth layer LAn and the first layer of the NVM 300 can be a semiconductor chip including a memory cell array 310. Multiple semiconductor layers LA1 to LAn can send and receive signals to each other via through-silicon vias (TSVs). The configuration and arrangement of the NVM 300 according to some example embodiments are not limited thereto.

[0095] Figure 6 This is a circuit diagram illustrating a memory cell array according to some example embodiments.

[0096] refer to Figure 6 Multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 can be arranged on a substrate (not shown) in a first direction X and a second direction Y. The multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 can have a shape extending in a third direction Z. The multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 can be commonly connected to the substrate (not shown) or formed in a common source line CSL in the substrate (not shown). The common source line CSL is shown as being connected to the bottom of each of the multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 on the third-party direction Z. However, the common source line CSL is not limited to being physically located below the multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33, as long as the common source line CSL is electrically connected to the bottom of each of the multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 on the third-party direction Z. Furthermore, multiple cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23 and NS33 are shown in the figure as arranged in a 3×3 matrix, but the arrangement type and number of multiple cell strings arranged in the non-volatile memory cell array 310 are not limited to this.

[0097] Some unit strings NS11, NS12, and NS13 can be connected to the first ground select line GSL1. Some unit strings NS21, NS22, and NS23 can be connected to the second ground select line GSL2. Some unit strings NS31, NS32, and NS33 can be connected to the third ground select line GSL3.

[0098] In addition, some unit strings NS11, NS12, and NS13 can be connected to the first select line SSL1. Some unit strings NS21, NS22, and NS23 can be connected to the second select line SSL2. Some unit strings NS31, NS32, and NS33 can be connected to the third select line SSL3.

[0099] Each of the multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may include a string select transistor SST connected to each string select line. Furthermore, each of the multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may include a ground select transistor GST connected to each ground select line.

[0100] One end of the ground select transistor in each of the multiple cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 can be connected to the common source line CSL. Furthermore, in each of the multiple cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33, multiple memory cells can be sequentially stacked between the ground select transistor and the string select transistor in a third-direction Z. Although not shown in the figure, each of the multiple cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may include dummy cells between the ground select transistor and the string select transistor. Furthermore, the number of string select transistors included in each string is not limited to the number shown in the figure.

[0101] For example, cell string NS11 may include a ground selection transistor GST11 arranged at the bottom in the third direction Z, a plurality of memory cells M11_1 to M11_8 sequentially stacked on the ground selection transistor GST11 in the third direction Z, and a string selection transistor SST11 on the topmost memory cell M11_8 stacked in the third direction Z. Furthermore, cell string NS21 may include a ground selection transistor GS21 arranged at the bottom in the third direction Z, a plurality of memory cells M21_1 to M21_8 sequentially stacked on the ground selection transistor GS21 in the third direction Z, and a string selection transistor SS21 on the topmost memory cell M21_8 stacked in the third direction Z. Furthermore, cell string NS31 may include a ground selection transistor GS31 arranged at the bottom in the third direction Z, a plurality of memory cells M31_1 to M31_8 sequentially stacked on the ground selection transistor GS31 in the third direction Z, and a string selection transistor SS31 on the topmost memory cell M31_8 stacked in the third direction Z. The configuration of other strings can be similar to that described above.

[0102] Memory cells located at the same or similar height from the substrate (not shown) or ground selection transistor on the third direction Z can be electrically connected to each other via their respective word lines. For example, memory cells forming memory cells M11_1, M21_1, and M31_1 can be connected to the first word line WL1. Furthermore, memory cells forming memory cells M11_2, M21_2, and M31_2 can be connected to the second word line WL2. The arrangement and structure of memory cells connected to the third word lines WL3 through the eighth word lines WL8 are similar to the above, and therefore their description will be omitted.

[0103] One end of the string select transistor in each of the multiple unit strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 can be connected to bit lines BL1, BL2, and BL3. For example, string select transistors SST11, SST21, and SST31 can be connected to bit line BL1, which extends in the second direction Y. The description of the other string select transistors connected to bit lines BL2 and BL3 is similar to that above and will therefore be omitted.

[0104] A memory cell corresponding to a serial (or ground) select line and a word line can form a page. Write and read operations can be performed within each page cell. Each page's memory cell can store two or more bits. The bits written to each page's memory cell can form logical pages.

[0105] Memory cell array 310 can be provided as a three-dimensional memory array. The three-dimensional memory array can be monolithically formed on one or more physical layers of an array of memory cells having active regions disposed on a substrate (not shown) and circuitry relating to the operation of the memory cells. The circuitry relating to the operation of the memory cells can be located in or on the substrate. The statement "the three-dimensional memory array is monolithically formed" means that each level of the three-dimensional array can be directly deposited on the lower-level layers of the three-dimensional memory array. Alternatively, the circuitry relating to the operation of the memory cells can be connected to the uppermost contact portion in a third-direction Z. This will refer to... Figure 7 Detailed description.

[0106] Figure 7 This is a schematic diagram illustrating the internals of an NVM according to some example embodiments.

[0107] refer to Figure 7 According to some example embodiments, the NVM 300 can have a chip-to-chip (C2C) structure. In this figure, the cell region CELL of the NVM 300 can correspond to Figure 5 The memory cell array 310.

[0108] A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELLs) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERIs) on a second wafer different from the first wafer, and then connecting the upper and lower chips by a bonding method. As an example, the bonding method can include a method of electrically connecting bonding metals formed on the topmost metal layer of the upper chip and bonding metals formed on the topmost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method can be Cu-Cu bonding, and the bonding metal can also be formed of aluminum or tungsten.

[0109] Each of the peripheral circuitry region PERI and cell region CELL of the NVM 300 according to some example embodiments may include an external pad bonding region PA, a word line bonding region WLBA, and / or a bit line bonding region BLBA.

[0110] The Peripheral Circuit Region (PERI) may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c respectively connected to the plurality of circuit elements 1220a, 1220b, and 1220c, and second metal layers 1240a, 1240b, and 1240c respectively formed on the first metal layers 1230a, 1230b, and 1230c. In some example embodiments, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten, which has relatively high resistance, and the second metal layers 1240a, 1240b, and 1240c may be formed of copper, which has relatively low resistance.

[0111] In this specification, only the first metal layers 1230a, 1230b, and 1230c and the second metal layers 1240a, 1240b, and 1240c are shown and described. However, this disclosure is not limited thereto, and one or more metal layers may also be formed on the second metal layers 1240a, 1240b, and 1240c. At least some of the one or more metal layers formed on the second metal layers 1240a, 1240b, and 1240c may be formed of aluminum or the like, which has a lower resistance than copper, which forms the second metal layers 1240a, 1240b, and 1240c.

[0112] Interlayer insulating layer 1215 may be disposed on first substrate 1210 to cover multiple circuit elements 1220a, 1220b and 1220c, first metal layers 1230a, 1230b and 1230c and second metal layers 1240a, 1240b and 1240c, and may include insulating material such as silicon oxide, silicon nitride and the like.

[0113] The lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b in the cell region CELL by a bonding method, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b can be formed of aluminum, copper, tungsten, etc.

[0114] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 1310 and a common source line 1320 (corresponding to...). Figure 5 The common source line (CSL). On the second substrate 1310, multiple word lines 1331 to 1338 (e.g., 1330, respectively corresponding to the common source line CSL). Figure 5The word lines (WL1 to WL8) can be stacked in a third direction Z perpendicular to the upper surface of the second substrate 1310. The serial select line and the ground select line can be arranged above and below the plurality of word lines 1330, respectively, and the plurality of word lines 1330 can be arranged between the serial select line and the ground select line.

[0115] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 1310 and pass through multiple word lines 1330, serial select lines, and ground select lines. The channel structure CH may include a data storage layer, a channel layer, a buried insulation layer, etc., and the channel layer can be electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c can be a bit line contact, and the second metal layer 1360c can be a bit line (corresponding to...). Figure 5 (Bit lines BL1 to BL3). In some example embodiments, bit line 1360c may extend in a second direction Y parallel to the upper surface of the second substrate 1310.

[0116] exist Figure 7 In some example embodiments shown, the area where the channel structure CH, bit line 1360c, etc., are arranged can be defined as a bit line bonding area BLBA. In the bit line bonding area BLBA, bit line 1360c can be electrically connected to circuit element 1220c in the peripheral circuit area PERI, which provides the page buffer 1393. As an example, bit line 1360c can be connected to upper bonding metals 1371c and 1372c in the cell area CELL, and upper bonding metals 1371c and 1372c can be connected to lower bonding metals 1271c and 1272c, which are connected to the circuit element 1220c of the page buffer 1393.

[0117] In the word line bonding area (WLBA), word lines 1330 may extend in a first direction X parallel to the upper surface of the second substrate 1310 and may be connected to a plurality of cell contact plugs 1341 to 1347 (e.g., 1340). Word lines 1330 and cell contact plugs 1340 may be connected to each other in pads provided by at least some of the word lines 1330 extending at different lengths in the first direction X. A first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the upper portion of each of the cell contact plugs 1340, which are connected to each of the word lines 1330. Cell contact plugs 1340 may be connected to the peripheral circuitry area (PERI) via upper bonding metals 1371b and 1372b of the cell region (CELL) and lower bonding metals 1271b and 1272b of the peripheral circuitry area (PERI) in the word line bonding area (WLBA).

[0118] Cell contact plug 1340 can be electrically connected to circuit element 1220b in the peripheral circuitry region PERI that provides the line decoder 1394. In some example embodiments, the operating voltage of circuit element 1220b providing the line decoder 1394 may be different from the operating voltage of circuit element 1220c providing the page buffer 1393. For example, the operating voltage of circuit element 1220c providing the page buffer 1393 may be greater than the operating voltage of circuit element 1220b providing the line decoder 1394.

[0119] A common source line contact plug 1380 can be disposed in the external pad bonding region PA. The common source line contact plug 1380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 1320. A first metal layer 1350a and a second metal layer 1360a can be sequentially stacked on top of the common source line contact plug 1380. As an example, the area where the common source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed can be defined as the external pad bonding region PA.

[0120] Meanwhile, input / output pads 1205 and 1305 can be arranged in the external pad bonding area PA. (Reference) Figure 7 A lower insulating film 1201 covering the lower surface of the first substrate 1210 may be formed below the first substrate 1210, and a first input / output pad 1205 may be formed on the lower insulating film 1201. The first input / output pad 1205 can be connected to at least one of a plurality of circuit elements 1220a, 1220b, and 1220c arranged in the peripheral circuit region PERI via a first input / output contact plug 1203, and can be separated from the first substrate 1210 via the lower insulating film 1201. Furthermore, a side insulating film may be disposed between the first input / output contact plug 1203 and the first substrate 1210 to electrically isolate the first input / output contact plug 1203 and the first substrate 1210.

[0121] Continue to refer to Figure 7 An upper insulating film 1301 covering the upper surface of the second substrate 1310 may be formed on the second substrate 1310, and a second input / output pad 1305 may be disposed on the upper insulating film 1301. The second input / output pad 1305 may be connected to at least one of a plurality of circuit elements 1220a, 1220b and 1220c disposed in the peripheral circuit region PERI via a second input / output contact plug 1303.

[0122] According to some example embodiments, the second substrate 1310 and the common source line 1320 may not be arranged in the region where the second input / output contact plug 1303 is arranged. Furthermore, the second input / output pad 1305 may not overlap with the word line 1330 in the third-order Z direction. (See reference...) Figure 7 The second input / output contact plug 1303 can be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310, and can pass through the interlayer insulation layer 1215 of the cell region to connect to the second input / output pad 1305.

[0123] According to some example embodiments, the first input / output pad 1205 and the second input / output pad 1305 may be selectively formed. As an example, the NVM 300 according to some example embodiments may include only the first input / output pad 1205 disposed over the first substrate 1210 or the second input / output pad 1305 disposed over the second substrate 1310. Alternatively, the NVM 300 may include both the first input / output pad 1205 and the second input / output pad 1305.

[0124] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern in the uppermost metal layer can be provided as a dummy pattern, or the uppermost metal layer may not exist.

[0125] In the external pad bonding area PA, according to some example embodiments, the NVM 300 may include a lower metal pattern 1273a, which corresponds to the upper metal patterns 1371a and 1372a formed in the uppermost metal layer of the cell region CELL, and has the same or similar shape as the upper metal pattern 1372a of the cell region CELL in the uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a disconnect contact. Similarly, in the external pad bonding area PA, an upper metal pattern may be formed in the uppermost metal layer of the cell region CELL, which corresponds to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI, and has the same or similar shape as the lower metal pattern of the peripheral circuit region PERI.

[0126] Lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b of the cell region CELL by bonding method.

[0127] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 1392 can be formed in the uppermost metal layer of the cell region CELL. This upper metal pattern 1392 corresponds to the lower metal pattern 1252 formed in the uppermost metal layer of the peripheral circuit region PERI, and has the same or similar shape as the lower metal pattern 1252 of the peripheral circuit region PERI. Contacts may not be formed on the upper metal pattern 1392 formed in the uppermost metal layer of the cell region CELL.

[0128] Figure 8 and Figure 9 This is a diagram illustrating a method of operating storage device 10 according to some example embodiments of the present disclosure.

[0129] refer to Figure 2 , Figure 8 and Figure 9 The host device 100 can transmit a write mode command WMCMD to the memory controller 200 (S110). After receiving the write mode command WMCMD, the memory controller 200 can transmit a write command about the write mode data to the NVM 300 (S111). The write mode data can be written to memory blocks BLK0 to BLKN in the NVM 300 (see...). Figure 2 Each of (S112) in ).

[0130] Figure 10 This is a diagram used to describe the file system and memory blocks used in an electronic system according to some example embodiments of the present disclosure. Figure 11 This is a diagram used to describe a region in a file system used in an electronic system according to some example embodiments of the present disclosure. Figure 12 and Figure 13 This is a diagram illustrating the operating modes of a memory block in a storage device according to some example embodiments of the present disclosure.

[0131] Additional reference Figures 10 to 13 The logical address ADDR_L, which can be controlled by the file system 121, can be implemented as one or more namespaces NS, etc.

[0132] The logical address ADDR_L can include multiple zones Z0 to Z15. The file system 121 can program the NVM 300 through multiple zones Z0 to Z15. The number of zones included in the logical address ADDR_L shown in this figure is an example and is not limited to the number shown in this figure.

[0133] refer to Figure 11 Each of zones Z0 to Z15 (e.g., zone 57) may include multiple sections 55, each of sections 55 may include multiple segments 53, and each of segments 53 may include multiple logical blocks 51. For example, a logical block 51 may be 4 kilobytes, and a segment 53 comprising 512 blocks 51 may be 2 megabytes. However, the size of each of the sections 55 and the size of each of zones Z0 to Z15 may be defined according to the file system 121, and the data to be stored may also vary depending on the characteristics of each of zones Z0 to Z15. Specifically, a logical block 51 may correspond to a page of the NVM 300.

[0134] Zones Z0 to Z15 can each correspond to multiple memory blocks BLK 0 to BLK 15, and the correspondence can be determined by... Figure 3 Address mapping table 223 is defined. Address mapping table 223 can be found in the loss equalization manager module 221 (see...). Figure 3 Updated under the control of file system 121.

[0135] Zone 0 (Z0) corresponds to memory block 0 (BLK 0), Zone 1 (Z1) corresponds to memory block 1 (BLK 1), Zone 2 (Z2) corresponds to memory block 2 (BLK 2), and Zone 3 (Z3) corresponds to memory block 3 (BLK 3). Zone 4 (Z4) corresponds to memory block 4 (BLK 4), Zone 5 (Z5) corresponds to memory block 5 (BLK 5), Zone 6 (Z6) corresponds to memory block 6 (BLK 6), and Zone 7 (Z7) corresponds to memory block 7 (BLK 7). Zone 8 (Z8) corresponds to memory block 8 (BLK 8), Zone 9 (Z9) corresponds to memory block 9 (BLK 9), Zone 10 (Z10) corresponds to memory block 10 (BLK 10), and Zone 11 (Z11) corresponds to memory block 11 (BLK 11). Zone 12 (Z12) corresponds to memory block 12 (BLK 12), Zone 13 (Z13) corresponds to memory block 13 (BLK 13), Zone 14 (Z14) corresponds to memory block 14 (BLK 14), and Zone 15 (Z15) corresponds to memory block 15 (BLK 15).

[0136] In addition to the case where one memory block corresponds to one region as shown in the accompanying drawings, in electronic systems according to some exemplary embodiments of the present disclosure, multiple memory blocks may also correspond to one region, and the number of memory blocks in the accompanying drawings is exemplary and not limited to the number shown in the accompanying drawings.

[0137] By transmitting the write mode command WMCMD from the host device 100 (S110), the memory controller 200 can write the write mode data to each of blocks BLK 0 to BLK 15 in the NVM 300.

[0138] According to some example embodiments, memory blocks 0 through 3 (BLK 3) store write mode data corresponding to single-level cell (SLC) write mode, memory blocks 4 through 7 (BLK 7) store write mode data corresponding to multi-level cell (MLC) write mode, memory blocks 8 through 11 (BLK 11) store write mode data corresponding to triple-level cell (TLC) write mode, and memory blocks 12 through 15 (BLK 15) store write mode data corresponding to quadruple-level cell (QLC) write mode.

[0139] In an electronic system 1a according to some example embodiments of the present disclosure, when the write mode of each memory block is set according to the write mode command WMCMD, each memory block can be fixedly programmed according to the write mode data of the write mode command WMCMD unless the write mode is changed by a command from the host device 100.

[0140] The host device 100 can set the default write mode for each memory block by transmitting a write mode command (WMCMD) for each of the memory blocks BLK 0 to BLK 15. According to some example embodiments, the host transmits multiple write mode commands (WMCMD) corresponding to each of the memory blocks BLK 0 to BLK 15. According to some example embodiments, each of the memory blocks BLK 0 to BLK 15 can be fixedly programmed based on the write mode data of the corresponding write mode command (WMCMD) among the multiple write mode commands (WMCMD).

[0141] In each of the memory blocks BLK 0 to BLK 15 according to some example embodiments, the default write mode can be set by formatting or initializing the electronic system 1a instead of receiving the write mode command WMCMD.

[0142] refer to Figure 12 and Figure 13 According to some example embodiments, the 0th memory block BLK 0 corresponding to the 0th zone Z0 stores the 0th data D0 of the 0th zone Z0 according to the SLC write mode, the 4th memory block BLK 4 corresponding to the 4th zone Z4 stores the 4th data D4 of the 4th zone Z4 according to the MLC write mode, the 8th memory block BLK 8 corresponding to the 8th zone Z8 stores the 8th data D8 of the 8th zone Z8 according to the TLC write mode, and the 12th memory block BLK 12 corresponding to the 12th zone Z12 stores the 12th data D12 of the 12th zone Z12 according to the QLC write mode.

[0143] For ease of description, MLC write mode, TLC write mode and QLC write mode are collectively referred to as multilevel cell write mode.

[0144] When a write operation is performed according to the multilevel cell write mode, the number of bits of data that can be stored per memory cell increases, thereby increasing the storage capacity of each memory block. On the other hand, when a memory block is written according to the SLC write mode, only one bit of data can be stored per memory cell. Therefore, compared to the case of writing operations according to the multilevel cell write mode, the storage capacity of the memory block may be smaller, but the write or read speed is faster and the data reliability is increased.

[0145] The SLC in memory block BLK 0 has 1 bit of data and can have one of the following states: erase state "E" and / or programming state "P" (e.g., one of them). The MLC in memory block BLK4 has 2 bits of data and can have one of the following states: erase state "E", first programming state "P1", second programming state "P2" and / or third programming state "P3" (e.g., one of them). The TLC in memory block BLK 8 has 3 bits of data and has one of the following states: erase state "E" and / or first programming state to seventh programming state (e.g., one of them). The QLC in memory block BLK 12 has 4 bits of data and has one of the following states: erase state "E" and / or first programming state to fifteenth programming state (e.g., one of them).

[0146] Therefore, the storage capacity of the fourth data D4 is twice that of the 0th data D0, the storage capacity of the eighth data D8 is three times that of the 0th data D0, and the storage capacity of the twelfth data D12 is four times that of the 0th data D0.

[0147] Figure 10 The first memory block BLK 1 to the third memory block BLK 3 each correspond to the 0th memory block BLK 0, and Figure 10The first zone Z1 to the third zone Z3 each correspond to the 0th zone Z0. Figure 10 The fifth memory block BLK 5 to the seventh memory block BLK 7 each correspond to the fourth memory block BLK 4, and Figure 10 Zones 5 through 7 each correspond to zone 4 (Z4). Figure 10 The ninth memory block BLK 9 to the eleventh memory block BLK 11 each correspond to the eighth memory block BLK 8, and Figure 10 Zones 9 through 11, each corresponding to zone 8, are Z9. Figure 10 The thirteenth memory block BLK 13 to the fifteenth memory block BLK 15 each correspond to the twelfth memory block BLK 12, and Figure 10 Zones 13 through 15 each correspond to zone 12, so their descriptions can be replaced by the descriptions of memory block 0 (BLK 0), memory block 4 (BLK 4), memory block 8 (BLK 8), memory block 12 (BLK 12), zone 0 (Z0), zone 4 (Z4), zone 8 (Z8), and zone 12 (Z12).

[0148] Refer again Figure 8 and Figure 9 After the operation of writing the write mode data (S112), the host device 100 can transmit a first write command about the first data to the memory controller 200 (S120). Upon receiving the first write command, the memory controller 200 can transmit the first write command about the first data to the NVM 300 (S121). The NVM 300 can then write the first data to the memory block according to the write mode data (S130).

[0149] Figures 14 to 16 This is a diagram illustrating a method of storing data in a memory block of a storage device according to some example embodiments of the present disclosure.

[0150] refer to Figure 14 The 0th memory block BLK 0 may include the 0th meta block 311 and / or the 0th data block 312.

[0151] After operation S130, the 0th data block 312 can store the 0th data D0, which includes the contents of the file or data to be stored in the file system 121, and the 0th meta block 311 can store the 0th meta data 311a, which includes the attributes of the 0th data D0, the location of the block storing the 0th data D0, and the 0th region descriptor 311b.

[0152] In the descriptor 311b of region 0, the region characteristics of region Z0 of region 0 can be stored (see [reference]). Figure 10), the default write mode data 311c, the temporary write mode data 311d, and / or whether to write sequentially for data block 312.

[0153] Let's refer to each other. Figure 10 In the descriptor 311b of the 0th region, SLC write mode data can be stored as default write mode data 311c, and temporary write mode data 311d can have an erase state.

[0154] In the 0th data block 312 of the NVM 300 according to some example embodiments of the present disclosure, the 0th data D0 can be written according to the SLC write mode data as the default write mode data 311c.

[0155] Furthermore, the 0th data D0 can be written using a sequential write method, and whether the 0th data D0 is written sequentially can be determined by the 0th region descriptor 311b. Therefore, according to some example embodiments, the 0_0 data D0_0 and the 0_1 data D0_1 to the 0_N data D0_N included in the 0th data D0 can be written sequentially to the 0th data block 312.

[0156] Refer again Figure 8 and Figure 9 After the operation of writing the first data (S130), the host device 100 can transmit a second write command for the second data, along with temporary write mode data, to the memory controller 200 (S140). Upon receiving the second write command, the memory controller 200 can transmit the second write command and the write command for the temporary write mode data to the NVM 300 (S141). The NVM 300 can write the temporary write mode data to the memory block (S143). The NVM 300 can write the second data on the memory block according to the temporary write mode data (S150).

[0157] refer to Figure 14 and Figure 15 After operation S150, the descriptor 311b of region 0 can have multilevel cell write mode data as temporary write mode data 311d, and as an example, it can have QLC write mode data.

[0158] In the 0th data block 312 of the NVM 300 according to some example embodiments of the present disclosure, the 0' data D0' can be written according to the QLC write mode data as temporary write mode data 311d, and the write operation can be performed in a sequential write manner.

[0159] Therefore, according to some example embodiments, the data D0'_0 and D0'_1 to D0'_N, including the data D0'_0 in the data D0'_0'_0'_0'_0'_1'_1'_1'_1'_1'_2'_N'_N'_N'_1'_2 ... Figure 14 In contrast, since the write operation is performed according to the QLC write mode, the storage capacity of data 0'D0 can correspond to four times the storage capacity of data 0'D0.

[0160] Refer again Figure 8 and Figure 9 After the operation of writing the second data (S150), the host device 100 can send a reset command to the memory controller 200 (S160). Upon receiving the reset command, the memory controller 200 can send an erase command to the NVM 300 (S161). The NVM 300 can erase the temporary write mode data from the memory block (S170). The NVM 300 can erase the second data from the memory block (S171).

[0161] refer to Figure 16 After operation S171, in the descriptor 311b of region 0, SLC write mode data can be stored as default write mode data 311c, and temporary write mode data 311d can have an erase state.

[0162] According to some example embodiments, the default write mode data 311c in the 0th element block 311 can be changed by commands from the host device 100 or by formatting or initializing the electronic system 1a.

[0163] Refer again Figure 8 and Figure 9 After operation S171, the host device 100 can transmit a third write command about the third data to the memory controller 200 (S180). Upon receiving the third write command, the memory controller 200 can transmit the third write command about the third data to the NVM 300 (S181). The NVM 300 can write the third data to the memory block according to the write mode data (S190).

[0164] Operations S180, S181, and S190 can correspond to operations S120, S121, and S130, respectively. Specifically, the third data write operation (S190) can be performed according to the write mode data of the write mode command WMCMD, just like the first data write operation.

[0165] Each of the first memory blocks BLK 1 to the third memory blocks BLK 3 can be operated in the same or similar manner as the 0th memory block BLK 0, and each of the first regions Z1 to the third regions Z3 can be operated in the same or similar manner as the 0th region Z0. Therefore, the description of the operation of each of the first memory blocks BLK 1 to the third memory blocks BLK 3 and the operation of each of the first regions Z1 to the third regions Z3 can be replaced by the description of the operation of the 0th memory block BLK 0 and the operation of the 0th region Z0, respectively.

[0166] Similarly, each of the fourth memory block BLK 4 to the seventh memory block BLK 7 and each of the fourth region Z4 to the seventh region Z7 can respectively correspond to each of the 0th memory block BLK 0 to the third memory block BLK 3 and each of the 0th region Z0 to the third region Z3.

[0167] When compared with each of memory blocks 0 through 3 (BLK 3) and zone 0 through 3 (Z0), each of memory blocks 4 through 7 (BLK 7) and zone 4 through 7 (Z7) can operate in the same or similar manner as each of memory blocks 0 through 3 (BLK 3) and zone 0 through 3 (Z3), except that in each of memory blocks 4 through 7 (BLK 7), the default write mode data is MLC write mode data, and the temporary write mode data is one of SLC write mode data, TLC write mode data, and QLC write mode data, in addition to MLC write mode data. Therefore, the descriptions of the operations of each of the fourth memory blocks BLK 4 to the seventh memory blocks BLK 7 and the operations of each of the fourth region Z4 to the seventh region Z7 can be replaced by the descriptions of the operations of each of the 0th memory block BLK 0 to the third memory block BLK 3 and the operations of each of the 0th region Z0 to the third region Z3, respectively.

[0168] Similarly, each of the eighth memory block BLK 8 to the eleventh memory block BLK 11 and each of the eighth zone Z8 to the eleventh zone Z11 can respectively correspond to each of the 0th memory block BLK 0 to the third memory block BLK 3 and each of the 0th zone Z0 to the third zone Z3.

[0169] When compared with each of memory blocks 0 through 3 (BLK 3) and zone 0 through 3 (Z3), each of memory blocks 8 through 11 (BLK 11) and zone 8 through 11 (Z11) can operate in the same or similar manner as each of memory blocks 0 through 3 (BLK 3) and zone 0 through 3 (Z3), except that in each of memory blocks 8 through 11 (BLK 11), the default write mode data is TLC write mode data, and the temporary write mode data is one of SLC write mode data, MLC write mode data, and QLC write mode data, in addition to TLC write mode data. Therefore, the descriptions of the operations of each of the eighth memory blocks BLK 8 to the eleventh memory blocks BLK 11 and the operations of each of the eighth zone Z8 to the eleventh zone Z11 can be replaced by the descriptions of the operations of each of the 0th memory blocks BLK0 to the third memory blocks BLK 3 and the operations of each of the 0th zone Z0 to the third zone Z3, respectively.

[0170] Similarly, each of the twelfth memory block BLK 12 to the fifteenth memory block BLK 15 and each of the twelfth zone Z12 to the fifteenth zone Z15 can respectively correspond to each of the 0th memory block BLK 0 to the third memory block BLK 3 and each of the 0th zone Z0 to the third zone Z3.

[0171] When compared with each of memory blocks 0 through 3 (BLK 3) and zone 0 through 3 (Z3), each of memory blocks 12 through 15 (BLK 15) and zone 12 through 15 (Z15) can operate in the same or similar manner as each of memory blocks 0 through 3 (BLK 3) and zone 0 through 3 (Z3), except that in memory blocks 12 through 15 (BLK 15), the default write mode data is QLC write mode data, and the temporary write mode data is one of SLC write mode data, MLC write mode data, and TLC write mode data, in addition to QLC write mode data. Therefore, the descriptions of the operations of each of the twelfth memory block BLK 12 to the fifteenth memory block BLK 15 and the operations of each of the twelfth zone Z12 to the fifteenth zone Z15 can be replaced by the descriptions of the operations of each of the 0th memory block BLK 0 to the third memory block BLK 3 and the operations of each of the 0th zone Z0 to the third zone Z3, respectively.

[0172] Figure 17and Figure 18 This is a diagram illustrating a method for determining an operating mode in an electronic system according to some example embodiments of the present disclosure.

[0173] refer to Figure 17 and Figure 18 The host device 100 can transmit area report commands to the memory controller 200.

[0174] Upon receiving a zone report command, the memory controller 200 may provide the host device 100 with zone descriptors 311b0 to 311b15 corresponding to memory blocks BLK 0 to BLK 15, and a zone descriptor header 311bh, respectively.

[0175] The zone descriptor header 311bh may include data about the number of times reports are provided to the host device 100, as well as the wear level or utilization of each write mode, and each of the zone descriptors 311b0 to 311b15 may include default write mode data and temporary write mode data for each of the memory blocks BLK 0 to BLK 15.

[0176] Figure 19 This is a diagram illustrating the operation of an electronic system according to some example embodiments of the present disclosure.

[0177] When the usage frequency of data D0 in zone Z0 is high (hot), the file system 121 of the host device 100 can be configured to perform write operations on memory block BLK 0 according to SLC write mode or MLC write mode. When the usage frequency of data D0 in zone Z0 is medium (warm), the file system 121 of the host device 100 can be configured to perform write operations on memory block BLK 0 according to MLC write mode or TLC write mode. When the usage frequency of data D0 in zone Z0 is low (cold), the file system 121 of the host device 100 can be configured to perform write operations on memory block BLK 0 according to TLC write mode or QLC write mode. The above settings can be provided through default write mode data or temporary write mode data.

[0178] Figure 19 The description applies in kind or similarly to each of the first zone Z1 to the fifteenth zone Z15 and each of the first memory block BLK 1 to the fifteenth memory block BLK 15.

[0179] Figure 20 This is a diagram illustrating the waste collection operation of an electronic system according to some example embodiments of the present disclosure.

[0180] refer to Figure 20In the file system 121 of an electronic system according to some example embodiments, the twelfth zone Z12 becomes the garbage collection destination area for zones 0 to 3, such that data 0 to 3 can be garbage collected to data 12' D12'.

[0181] Let's refer to each other. Figure 12 When assuming that regions Z0 to Z15 have the same or similar size, memory blocks BLK0 to BLK3 corresponding to regions Z0 to Z3 can perform SLC write operations, and memory block BLK12 corresponding to region Z12 can perform QLC write operations. Since the size of each of the data D0 to D3 stored in each of regions Z0 to Z3 is 1 / 4 of the storage capacity of region Z12, garbage collection can be performed on regions Z0 to Z3 using region Z12.

[0182] Zone Z12, which performs the write according to QLC write mode, is an example of a garbage collection destination area, and according to some example embodiments, garbage collection can be performed on zones Z0 to Z3, which perform the write according to SLC write mode, using zones that perform the write according to MLC write mode or TLC write mode.

[0183] Figure 21 This is a block diagram used to describe an electronic system including a storage device according to some example embodiments of the present disclosure.

[0184] In the following text, reference will be made to Figure 21 An electronic system 1b according to some example embodiments of the present disclosure will be described. The main focus will be on describing... Figure 2 The differences between electronic system 1a and electronic system 1b are shown in the figure.

[0185] and Figure 2 In contrast, the partition-memory block transition layer 122 can be separated from the file system 121. The file system 121 can be used depending on the specific operating system running on the host device 100, and the operating system may not support executing files or data on a partition-by-partition basis.

[0186] Therefore, in the electronic system 1b according to some example embodiments, the host memory 120 can drive the partition-memory block transition layer 122 separately from the file system 121, and provide the storage device 10 with commands of the file system 121 (e.g., write command WCMD or read command) and the logical address ADDR_L according to the command through the partition-memory block transition layer 122.

[0187] Figure 22This is a block diagram for describing an electronic system 1c including a storage device 10' according to some example embodiments of the present disclosure. Figure 23 This is a schematic diagram illustrating the internals of an NVM according to some example embodiments. Figure 24 This is a circuit diagram illustrating a portion of a memory cell array according to some example embodiments of the present disclosure.

[0188] refer to Figure 22 The storage device 10' may include a first NVM 300a and a second NVM 300b. According to some example embodiments, the first NVM 300a and the second NVM 300b may be heterogeneous memories that are different from each other. For example, the first NVM 300a may be PRAM or MRAM, and the second NVM 300b may be flash memory.

[0189] The operation of the first NVM 300a can be controlled via the first channel CH1, and the operation of the second NVM 300b can be controlled via the second channel CH2. The memory controller 200 can receive the write command WCMD and the logical address ADDR_L from the host device 100, and write data DATA to the first NVM 300a and the second NVM 300b.

[0190] The non-volatile memory blocks BLK'0 to BLK'M in the first NVM 300a and the memory blocks BLK0 to BLKN in the second NVM 300b can respectively correspond to Figure 10 The 0th zone Z0 to the 15th zone Z15, and therefore each can have a write mode set by the file system 121 of the host device 100.

[0191] The structure of the second NVM 300b of storage device 10' can correspond to Figure 2 The structure of NVM 300.

[0192] Reference Figure 23 and Figure 24 The structure of the first NVM 300a is described. The first NVM 300a may include a plurality of non-volatile memory blocks BLK'0 to M-th non-volatile memory blocks BLK'M. The plurality of non-volatile memory blocks BLK'0 to BLK'M may be arranged to be spaced apart from each other in a first direction X and / or a second direction Y. Each of the plurality of non-volatile memory blocks BLK'0 to BLK'M includes a plurality of memory cells.

[0193] The description of the structure of the 0th non-volatile memory block BLK'0 can correspond to the description of the structure of each remaining non-volatile memory block. The 0th non-volatile memory block BLK'0 may include, for example, PRAM cells.

[0194] The 0th non-volatile memory block BLK'0 can be a two-dimensional memory. When the 0th non-volatile memory block BLK'0 is formed by multiple layers, the 0th non-volatile memory block BLK'0 can be a three-dimensional memory.

[0195] The 0th non-volatile memory block BLK'0 may include multiple word lines WL0 to WLn, multiple bit lines BL0 to BLm, and multiple memory cells MC. The number of word lines WL, the number of bit lines BL, and the number of memory cells MC can be modified in various ways according to some example embodiments. In addition, a set of memory cells that can be accessed simultaneously or concurrently by the same word line or similar word lines can be defined as a page.

[0196] In the 0th nonvolatile memory block BLK'0 according to some example embodiments of the present disclosure, each of the plurality of memory cells MC may include a variable resistive element R and a selection element S. Here, the variable resistive element R may be referred to as a variable resistor (or alternatively, a variable resistive material), and the selection element S may be referred to as a switching element.

[0197] According to some exemplary embodiments of this disclosure, in the memory block BLK'0, the selection element S may be a two-way threshold switch (OTS) selector, which includes such as GeSe, GeS, AsSe, AsTe, AsS, SiTe, SiSe, SiS, GeAs, SiAs, SnSe, SnTe, GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiasTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, SnAsTe, GeSiAsTe, GeSiAsSe, GeSiSeTe, GeSeTe Sb、GeSiSeSb、GeSiTeSb、GeSeTeBi、GeSiseBi、GeSiTeBi、GeAsSeSb、GeAsTeSb、GeAsteBi、GeAsSeBi、GeAsSeIn、GeAsseGa、GeAsseAl、GeAsSeTl、GeAsSeSn、GeAsSeZn、GeAsteIn、GeAstega、GeAsteAl、GeAsteTl、GeAsteSn、GeAsteZn、Gesiassete、GeAssetes、Gesiassetes、Gesiassetes、Gesiassetes、Gesias sSeP、GeSiAsTeP、GeAsSeTeP、GeSiAsSeIn、GeSiAsSeGa、GeSiAsSeAl、GeSiAsSeTl、GeSiAsSeZn、GeSiAsSeSn、GeSiAsTeIn、GeSiAsTeGa、GeSiAsTeAl、 GeSiAsTeTl、GeSiAsTeZn、GeSiAsTeSn、GeASeTeIn、GeAsSeTeGa、GeASeTeAl、GeASeTeTl、GeASeTeZn、GeASeTeSn、GeASeSin、GeASeSGa、GeAsS eSAL, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIN, GeAsTeSga, GeAsTeSAL, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsseGaAl, GeAsseGaTl, GeAsseGaZn, GeAsseGaSn, GeAsseAlTl, GeAsseAlZn, GeAsSEAlSn, GeAsSeTlZn, GeAsSeTlSn,GeAsSeZnSn, GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn, G eSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, GeSiA sSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeTePI n, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl, Ge SiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGaSn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTeGaAl , GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeSInTl, Compounds of GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn and / or GeAsSeSAlSn. ,

[0198] For example, the variable resistor element R can be connected between one of the multiple bit lines BL0 to BLm and the selection element S, and the selection element S can be connected between the variable resistor element R and one of the multiple word lines WL0 to WLn.

[0199] However, this disclosure is not limited thereto. The selection element S may be connected between one of the multiple bit lines BL0 to BLm and the variable resistor element R, and the variable resistor element R may be connected between the selection element S and one of the multiple word lines WL0 to WLn.

[0200] The selector element S can be connected between any one of the multiple word lines WL0 to WLn and the variable resistor element R, and the current source of the variable resistor element R can be controlled according to the voltage applied to the connected word line and bit line.

[0201] Conventional devices and methods for controlling memory devices use the memory controller of the corresponding memory device to perform memory management operations, such as garbage collection. The memory controller performs programming operations on a page-by-page basis and erasure operations on a block-by-block basis. However, conventional devices and methods cannot perform memory management operations under the control of an external device (e.g., a host device). Therefore, conventional devices and methods for controlling memory devices are inefficient and cannot implement different operating systems running on external devices.

[0202] However, according to some example embodiments, improved apparatuses and methods are provided for controlling memory devices. Specifically, some example embodiments provide control of individual blocks of the memory device to an external device (e.g., a host) by using regions corresponding to blocks. Therefore, the improved apparatuses and methods enable the external device to perform memory management operations (e.g., garbage collection) on the memory device. Thus, the improved apparatuses and methods overcome the shortcomings of conventional apparatuses and methods to improve the efficiency of memory devices and enable the implementation of different operating systems running on the external device.

[0203] According to some example embodiments, operations described herein performed by system 1000, main processor 1100, controller 1120, accelerator block 1130, storage controllers 1200a and 1200b, storage devices 1010a and 1010b, electronic system 1a, storage device 10, host device 100, processor 110, host controller 130, memory controller 200, processor 210, working memory 220, loss leveling manager module 221, mapping table manager module 222, namespace manager module, address decoder 320, voltage generator 330, read / write circuitry 340, control logic 350, electronic system 1b, electronic system 1c, and / or storage device 10' can be performed by processing circuitry. As used herein, the term "processing circuitry" can refer to, for example, hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0204] The various operations of the methods described above can be performed by any suitable device capable of performing the operations, such as the processing circuits discussed above. For example, as discussed above, the operations of the methods described above can be performed by various hardware and / or software implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0205] Software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any processor-readable medium for use by or in conjunction with an instruction-running system, apparatus, or device, such as a single-core or multi-core processor or a system containing a processor.

[0206] The blocks or operations of methods, algorithms, and functions described in conjunction with some of the example embodiments disclosed herein can be directly embodied in hardware, software modules executed by a processor, or a combination of both. If implemented in software, the functions can be stored as one or more instructions or code on or transmitted through a tangible, non-transitory computer-readable medium. Software modules can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0207] It should be understood that when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to that other element, or there may be an intermediate element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0208] Some example embodiments can be described with reference to the actions and symbolic representations of the operations implemented by the units and / or devices discussed in more detail below (e.g., in the form of flowcharts, diagrams, data flow diagrams, block diagrams, etc.). Although discussed in a particular manner, the functions or operations specified in a particular block may be performed differently from the processes specified in the flowcharts, diagrams, etc. For example, functions or operations shown as being performed serially in two consecutive blocks may actually be performed in parallel, simultaneously, concurrently, or in some cases in the reverse order.

[0209] However, the effects of some exemplary embodiments are not limited to those set forth herein. The above and other effects of some exemplary embodiments will become more apparent to those skilled in the art to which this disclosure pertains upon reference to the claims.

Claims

1. A storage device, comprising: The non-volatile memory includes a first memory block and a second memory block different from the first memory block; and The memory controller is configured to, Receive a first write mode command corresponding to the first memory block and a second write mode command corresponding to the second memory block from the host. The first write operation is controlled by the first write mode command to perform a first write operation on the first memory block. The first write operation includes sequentially writing first data into the first memory block, and... The second write operation is controlled by the second write mode command to perform a second write operation on the second memory block, wherein the second write operation includes sequentially writing second data into the second memory block. The first memory block stores first write mode data based on the first write mode command, the first write mode data indicating the first write mode among a plurality of write modes, and The second memory block stores second write mode data based on the second write mode command, the second write mode data indicating the second write mode among the plurality of write modes.

2. The storage device according to claim 1, wherein, The memory controller is not configured to perform garbage collection.

3. The storage device according to claim 2, wherein, The memory controller is configured to: After receiving the first write mode command, a first write command is received, the first write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one of the plurality of write modes; as well as In response to receiving the first write command, the first storage block is controlled to store the first write mode data and the temporary write mode data.

4. The storage device according to claim 1, wherein, The memory controller is configured to: The first memory block is controlled to perform the first write operation according to the single-level cell write mode; and The second memory block is controlled to perform the second write operation according to the multi-level cell write mode.

5. The storage device according to claim 4, wherein, The multi-level cell write mode includes multi-level cell write mode, three-level cell write mode, or four-level cell write mode.

6. The storage device according to claim 1, wherein, The memory controller is configured to: After receiving the first write mode command, a first write command is received, the first write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one of the plurality of write modes; as well as The first memory block is controlled to perform a third write operation based on the first write command and the temporary write mode data.

7. The storage device according to claim 6, wherein, The memory controller is configured to: After receiving the first write command, a write mode reset command corresponding to the first memory block is received; as well as After receiving the write mode reset command, the first memory block is controlled to perform another write operation according to the first write mode command.

8. The storage device according to claim 1, wherein, The memory controller is configured to perform a loss leveling operation in the same memory block cells as the first memory block and the second memory block.

9. The storage device according to claim 1, wherein, The memory controller is configured to: Receive a report command from the host; as well as In response to receiving the report command, the non-volatile memory is controlled to read the first write mode data and the second write mode data.

10. An electronic system comprising: The non-volatile memory includes a first memory block and a second memory block; A host, comprising a file system having a first region and a second region, the first region corresponding to the first memory block and the second region corresponding to the second memory block, the host being configured to, A first write mode command corresponding to the first memory block is provided to the memory controller, and a second write mode command corresponding to the second memory block is provided to the memory controller. Provide the memory controller with a first write command corresponding to the first region, and The memory controller is provided with a second write command corresponding to the second region; and the memory controller is configured to, The first write operation is controlled by the first write command and the first write mode command to perform a first write operation on the first memory block. The first write operation includes sequentially writing first data into the first memory block. The second write operation is controlled by the second write command and the second write mode command to perform a second write operation on the second memory block. The second write operation includes sequentially writing second data into the second memory block. After receiving the first write mode command, a third write command is received, the third write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one of a plurality of write modes, and In response to receiving the third write command, the first memory block is controlled to perform a third write operation based on the third write command and the temporary write mode data.

11. The electronic system according to claim 10, wherein, The memory controller is not configured to perform garbage collection.

12. The electronic system according to claim 11, wherein, The host is configured to perform the garbage collection from the first zone to the second zone.

13. The electronic system according to claim 12, wherein, The memory controller is configured to: The first memory block is controlled to perform the first write operation according to the single-level cell write mode; and The second memory block is controlled to perform the second write operation according to the multi-level cell write mode.

14. The electronic system according to claim 10, wherein, The memory controller is configured to perform a loss leveling operation in the same memory block cells as the first memory block and the second memory block.

15. A method of operating a storage device, the method comprising: Receive a first write mode command corresponding to a first memory block, the first memory block corresponding to a first partition in the file system; Receive a second write mode command corresponding to a second memory block, the second memory block corresponding to a second region in the file system, and the second region being different from the first region; Receive the first write command corresponding to the first region; A first write operation is performed on the first memory block according to the first write command and the first write mode command, wherein the first write operation includes sequentially writing first data into the first memory block; Receive the second write command corresponding to the second zone; A second write operation is performed on the second memory block according to the second write command and the second write mode command, the second write operation including sequentially writing second data into the second memory block; After receiving the first write mode command, a third write command is received, the third write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one of a plurality of write modes; and The third write operation is performed based on the third write command and the temporary write mode data.

16. The method of claim 15, further comprising: After receiving the third write command, a write mode reset command corresponding to the first memory block is received; as well as In response to receiving the write mode reset command, another write operation is performed on the first memory block according to the first write mode command.

17. The method of claim 15, further comprising: The first write mode data is stored in the first memory block based on the first write mode command, and the first write mode data indicates the first write mode among a plurality of write modes; as well as The second write mode data is stored in the second memory block based on the second write mode command, and the second write mode data indicates the second write mode among the plurality of write modes.

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