Semiconductor memory devices

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes: a substrate including a device isolation pattern defining an active pattern extending in a first direction and including a first source / drain region and a second source / drain region; a word line extending in a second direction intersecting the first direction; a bit line located on the word line and electrically connected to the first source / drain region, and extending upward in a third direction intersecting the first and second directions; a bit line spacer located on a sidewall of the bit line; a memory node contact electrically connected to the second source / drain region and spaced apart from the bit line across the bit line spacer; and a dielectric pattern located between the bit line spacer and the memory node contact. The bit line spacer includes a first spacer covering the sidewall of the bit line and a second spacer located between the dielectric pattern and the first spacer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0152715, filed on November 16, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a semiconductor memory device. Background Technology

[0003] Semiconductor devices play a vital role in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices have become increasingly highly integrated with the development of the electronics industry. To achieve this high integration, the linewidth of semiconductor device patterns is decreasing. However, new and / or expensive exposure techniques are being used for the fine patterning of highly integrated semiconductor devices. Therefore, various studies on new integration techniques have recently been conducted. Summary of the Invention

[0004] Some exemplary embodiments of the present invention provide a semiconductor memory device with improved electrical characteristics.

[0005] Some exemplary embodiments of the present invention provide a semiconductor memory device with improved reliability.

[0006] The purpose of this invention is not limited to the contents mentioned above, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some exemplary embodiments of the present invention, a semiconductor memory device may include: a substrate including a device isolation pattern defining an active pattern extending in a first direction, the active pattern including a first source / drain region and a second source / drain region; a word line extending in a second direction intersecting the first direction; a bit line located on the word line and electrically connected to the first source / drain region, the bit line extending upward in a third direction intersecting both the first and second directions; a bit line spacer located on a sidewall of the bit line; a memory node contact electrically connected to the second source / drain region and spaced apart from the bit line, the bit line spacer being disposed between the bit line and the memory node contact; and a dielectric pattern located between the bit line spacer and the memory node contact. The bit line spacer may include: a first spacer covering the sidewall of the bit line; and a second spacer located between the dielectric pattern and the first spacer.

[0008] According to some exemplary embodiments of the present invention, a semiconductor memory device may include: a substrate including a device isolation pattern defining an active pattern extending in a first direction, the active pattern including a first source / drain region and a second source / drain region; a word line extending in a second direction intersecting the first direction; a bit line located on the word line and electrically connected to the first source / drain region, the bit line extending upward in a third direction intersecting both the first and second directions; a bit line spacer located on a sidewall of the bit line; a memory node contact electrically connected to the second source / drain region and spaced apart from the bit line, the bit line spacer being disposed between the bit line and the memory node contact; a dielectric barrier vertically stacked with the word line and located between the memory node contact and another memory node contact; and a dielectric pattern located between the memory node contact and the bit line spacer and between the memory node contact and the dielectric barrier. When the semiconductor memory device is viewed in a plan view, the dielectric pattern may have a square ring structure or a circular ring structure.

[0009] According to some exemplary embodiments of the present invention, a semiconductor memory device may include: a substrate including an active pattern having a long axis in a first direction, the active pattern including a first source / drain region and a pair of second source / drain regions spaced apart from each other in the first direction, the first source / drain region being disposed between the pair of second source / drain regions, and the substrate including a device isolation pattern defining the active pattern; a word line extending in a second direction intersecting the first direction; and a bit line located on the word line and electrically connected to the first source / drain region, the bit line being in the first direction and the second direction. The third part where the two intersect extends upwards; a first line spacer is located on the sidewall of the bit line; a first memory node contact is electrically connected to one of the pair of second source / drain regions and spaced apart from the bit line, the first line spacer being disposed between the first memory node contact and the bit line; a bit line contact is electrically connected to the first source / drain region; a bit line overlay pattern is located on the bit line; a bonding pad is electrically connected to the first memory node contact; a bottom electrode is located on the bonding pad; and a dielectric pattern is located between the first line spacer and the first memory node contact. The first line spacer may include: a first spacer covering the sidewall of the bit line; and a second spacer located between the dielectric pattern and the first spacer. Attached Figure Description

[0010] Figure 1A A plan view of a semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0011] Figure 1B It shows along Figure 1A The sectional view taken by lines I-I' and II-II'.

[0012] Figures 2A to 10AA plan view of a method for manufacturing a semiconductor memory device according to some exemplary embodiments of the present invention is shown.

[0013] Figures 2B to 10B They show the following along Figures 2A to 10A The sectional view taken by lines I-I' and II-II'. Detailed Implementation

[0014] Some exemplary embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings to help clearly illustrate the inventive concept.

[0015] Figure 1A A plan view of a semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown. Figure 1B It shows along Figure 1A The sectional view taken by lines I-I' and II-II'.

[0016] Reference Figure 1A and Figure 1B The substrate 100 may have a device isolation pattern 102 defining an active pattern ACT therein. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The device isolation pattern 102 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride, or may be formed from, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. When the substrate 100 is viewed in a plan view (hereinafter referred to as "viewed in plan view"), each active pattern ACT may have a strip shape and may be configured such that its major axis lies on a first direction D1 intersecting both a second direction D2 and a third direction D3 intersecting the second direction D2. For example, the strip shape may extend longitudinally in the first direction D1. The first direction D1 to the third direction D3 may be coplanar lines located on the same plane parallel to the top surface or bottom surface of the substrate 100.

[0017] The substrate 100 may have word lines WL extending across the active pattern ACT. The word lines WL may extend in a second direction D2 and may be arranged along a third direction D3 (i.e., spaced apart from each other in the third direction D3). The word lines WL may be disposed in grooves formed on the device isolation pattern 102 and the active pattern ACT. Each word line WL may have a curved bottom surface. The inventive concept is not limited thereto. For example, each word line WL may have an uneven bottom surface. The bottom surface of the word line WL on the device isolation pattern 102 may be lower than the bottom surface of the word line WL on the active pattern ACT. The word lines WL may comprise or be formed of a conductive material. For example, the conductive material may include one of the following: doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). Alternatively, it may be formed from one of the following: doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). The gate dielectric pattern 105 may be positioned between the word line WL and the active pattern ACT, and between the word line WL and the device isolation pattern 102. The gate dielectric pattern 105 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric, or may be formed from at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric.

[0018] Word line overlay patterns 110 may be disposed on each word line WL. Word line overlay patterns 110 may have a linear shape extending along the longitudinal direction of the word line WL and may cover the entire top surface of the word line WL. For example, word line overlay patterns 110 may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride, or may be formed from at least one of silicon oxide, silicon nitride, and silicon oxynitride. Word line overlay patterns 110 may have a top surface substantially coplanar with the top surface of the substrate 100.

[0019] Each active pattern ACT may have a first impurity region 112a and a second impurity region 112b thereon, the second impurity regions 112b being spaced apart from each other across the first impurity regions 112a. The first impurity regions 112a may be disposed within an active pattern ACT between a pair of word lines WL extending across the active pattern ACT. The second impurity regions 112b (e.g., two second impurity regions 112b) may be disposed within the active pattern ACT and may be spaced apart from each other across the pair of word lines WL. For example, the first impurity region 112a may be disposed on one side of a word line WL within the active pattern ACT, and the second impurity region 112b may be disposed on the other side of the word line WL within the active pattern ACT. The first impurity region 112a may include impurities whose conductivity is the same as that of the impurities in the second impurity regions 112b.

[0020] An interlayer dielectric layer 120 may be disposed on the substrate 100. The interlayer dielectric layer 120 may be formed as a single layer or multiple layers comprising one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. When viewed in a plan view, the interlayer dielectric layer 120 may have an island shape spaced apart from each other. The interlayer dielectric layer 120 may be formed to simultaneously cover the ends of two adjacent active patterns ACT. The substrate 100, the device isolation pattern 102, and the word line overlay pattern 110 may be partially recessed at their upper portions to form a first groove 122. When viewed in a plan view, the first groove 122 may have a grid (or lattice) shape.

[0021] A substrate 100 may have bit lines BL extending in a third direction D3 and spaced apart from each other in a second direction D2. The bit lines BL may be disposed on an interlayer dielectric layer 120 and may extend across word line overlay pattern 110 and word line WL. Each bit line BL may include a first bit line pattern 150, a bit line blocking pattern 151, and a second bit line pattern 152, or may be formed from the first bit line pattern 150, the bit line blocking pattern 151, and the second bit line pattern 152. The first bit line pattern 150 may include doped polysilicon or undoped polysilicon, or may be formed from doped polysilicon or undoped polysilicon. The bit line blocking pattern 151 may include a metal silicide layer or may be formed from a metal silicide layer. The second bit line pattern 152 may include a metallic material or a conductive metal nitride, or may be formed from a metallic material or a conductive metal nitride. For example, the metallic material may include at least one selected from tungsten, titanium, tantalum, aluminum, copper, nickel, and cobalt, or may be formed from at least one selected from tungsten, titanium, tantalum, aluminum, copper, nickel, and cobalt, and the conductive metal nitride may include at least one selected from titanium nitride, tantalum nitride, and tungsten nitride, or may be formed from at least one selected from titanium nitride, tantalum nitride, and tungsten nitride. A bit line overlay pattern 155 may be disposed on each bit line BL. The bit line overlay pattern 155 may extend along the bit line BL in a third direction D3 to cover the top surface of the bit line BL. The bit line overlay pattern 155 may include or may be formed from a dielectric material. For example, the bit line overlay pattern 155 may include one or more of nitrides (e.g., silicon nitride) and oxides nitrides (e.g., silicon oxynitride), or may be formed from one or more of nitrides (e.g., silicon nitride) and oxides nitrides (e.g., silicon oxynitride).

[0022] Bit line contacts DC may be disposed in a first recess 122 intersecting with bit lines BL. Bit line contacts DC may comprise or be formed of doped or undoped polysilicon. Each bit line BL may be electrically connected to a first impurity region 112a via bit line contacts DC. According to some example embodiments, the first bit pattern 150 and bit line contacts DC may comprise or be formed of the same material and may contact each other to form a single unit. Bit line contacts DC may penetrate at least a portion of the substrate 100 to contact the first impurity region 112a. It will be understood that when an element is referred to as "connected" or "bonded" to another element or "on" another element, the element may be directly connected or bonded to said other element or directly on said other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly bonded" to another element, or referred to as "contacting" another element or "in contact with" another element, no intermediate elements are present. Other terms used to describe relationships between elements should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent to" and "directly adjacent to," etc.). The bit line contact DC may have a bottom surface lower than the top surface of the substrate 100. According to some example embodiments, the bit line BL and the bit line contact DC may have their widths in the second direction D2, and the width of the bit line BL may be substantially the same as the width of the bit line contact DC. In this specification, the term "width" may indicate a distance measured along the second direction D2.

[0023] The first recess 122 may have empty space not occupied by the bit line contact DC, and the lower buried pattern 141 may be disposed in the empty space of the first recess 122. The lower buried pattern 141 may be formed as a single layer or multiple layers comprising at least one selected from silicon oxide, silicon nitride, and silicon oxynitride layers. A dielectric pad 140 may be disposed between the lower buried pattern 141 and the inner sidewall of the first recess 122 and between the lower buried pattern 141 and the bit line contact DC. The dielectric pad 140 may comprise or be formed of a dielectric material having etch selectivity relative to the lower buried pattern 141. For example, the lower buried pattern 141 may comprise or be formed of silicon nitride, and the dielectric pad 140 may comprise or be formed of silicon oxide.

[0024] Storage node contacts BC can be disposed on opposite sides of each bit line BL. Storage node contacts BC can be spaced apart from each other across their corresponding bit lines BL. Storage node contacts BC can comprise or be formed of doped or undoped polysilicon. Storage node contacts BC can have a concave bottom surface. Dielectric barriers 300 can be disposed between storage node contacts BC and between bit lines BL. For example, dielectric barriers 300 can be disposed between two storage node contacts BC spaced apart from each other along a third direction D3 and between two bit lines BL spaced apart from each other along a second direction D2. Dielectric barriers 300 can comprise or be formed of a dielectric material (such as silicon nitride, silicon oxide, or silicon oxynitride). A bit line BL can have storage node contacts BC and dielectric barriers 300 disposed alternately and repeatedly along the bit line BL on one side. The dielectric barrier 300 may have a top whose height (or level) is higher than the height (or level) of the top of each storage node contact BC.

[0025] The first spacer 210, the air gap AG, and the second spacer 230 can be placed between the bit line BL and the memory node contact BC, such as Figure 1B The first spacer 210, the air gap AG, and the second spacer 230 are shown in the cross-sectional view taken along line I-I'. They can be collectively referred to as bit line spacers SP. For example, bit line spacers SP can be disposed on each of the opposite sidewalls of the bit line BL. The first spacer 210 can be adjacent to the sidewall of the bit line BL, and the second spacer 230 can be adjacent to the memory node contact BC. The air gap AG can be disposed between the first spacer 210 and the second spacer 230. The first spacer 210, the air gap AG, and the second spacer 230 can extend along the side surface of the bit line BL and can also be disposed between the bit line BL and the dielectric barrier 300, as shown in the image. Figure 1BThe first spacer 210 and the second spacer 230 are shown in the cross-sectional view taken along line II-II'. The first spacer 210 and the second spacer 230 may comprise the same material or may be formed of the same material. For example, the first spacer 210 and the second spacer 230 may comprise silicon nitride or may be formed of silicon nitride. The top surface of the memory node contact BC may be lower than the uppermost surface of the second spacer 230, and the upper sidewall of the second spacer 230 may be exposed. For example, the upper sidewall of the second spacer 230 may extend vertically beyond the top surface of the memory node contact BC. The dielectric pattern 250 may have a top surface whose height (or level) is lower than the height (or level) of the uppermost surface of the second spacer 230. The second spacer 230 may have an uppermost surface whose height (or level) is higher than the height (or level) of the top surface of the bit line BL. The air gap AG may have an uppermost surface whose height (or level) is higher than the height (or level) of the top surface of the bit line BL. The second spacer 230 may have a bottom surface lower than the bottom surface of the first spacer 210. The uppermost surface of the second spacer 230 may be lower than the uppermost surface of the first spacer 210. This configuration of the first spacer 210 and the second spacer 230 can increase the process margin for forming the bonding pad LP, which will be discussed below, and improve the connection between the bonding pad LP and the storage node contact BC. According to some example embodiments, the first spacer 210 may have an uppermost surface at substantially the same height (or level) as the uppermost surface of the second spacer 230.

[0026] The first spacer 210 may extend to cover the sidewalls of the bit line contact DC and the inner sidewalls and bottom surface of the first recess 122. The first spacer 210 may be positioned between the bit line contact DC and the dielectric pad 140, between the dielectric pad 140 and the inner sidewall of the first recess 122, between the dielectric pad 140 and the bottom surface of the first recess 122, and between the word line overlay pattern 110 and the dielectric pad 140. For example, the first spacer 210 may be positioned between the substrate 100 and the dielectric pad 140, and between the device isolation pattern 102 and the dielectric pad 140.

[0027] Dielectric pattern 250 can be positioned between bit line spacers SP and memory node contacts BC. For example, dielectric pattern 250 can be positioned between second spacers 230 and memory node contacts BC. Dielectric pattern 250 can cover the sidewalls of second spacers 230 and memory node contacts BC. Dielectric pattern 250 can be positioned between memory node contacts BC and dielectric fence 300. Dielectric pattern 250 can cover the sidewalls of dielectric fence 300. For example, when viewed in a plan view, dielectric pattern 250 can have a square ring structure or a circular ring structure.

[0028] The dielectric pattern 250 may have a top surface that is substantially coplanar with the top surface of the memory node contact BC. When viewed in plan view, the dielectric pattern 250 may surround the memory node contact BC. For example, the dielectric pattern 250 may contact and surround the entire sidewall of the memory node contact BC. The dielectric pattern 250 may have a bottom surface that is substantially coplanar with the top surface of the substrate 100. For example, the bottom surface of the dielectric pattern 250 may be substantially coplanar with the top surface of the active pattern ACT. The memory node contact BC may have a stepped portion. The stepped portion may be formed on the top surface of the substrate 100. The memory node contact BC may have a larger width at the portion adjacent to the bottom surface of the substrate 100 compared to the portion adjacent to the top surface of the substrate 100. The dielectric pattern 250 may have a width smaller than the width of the second spacer 230. The dielectric pattern 250 may include a material different from the material of the first spacer 210 and the second spacer 230, or may be formed of a material different from the material of the first spacer 210 and the second spacer 230. The dielectric pattern 250 may include or may be formed of oxides (such as silicon oxide or hafnium oxide). When referring to orientation, layout, location, shape, size, amount, or other measures, terms as used herein (such as “identical,” “equal,” “planar,” or “coplanar”) do not necessarily refer to exactly the same orientation, layout, location, shape, size, amount, or other measures, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “substantially” may be used herein to emphasize that meaning. For example, terms describing “substantially identical,” “substantially equal,” or “substantially planar” may be exactly the same, completely equal, or completely planar, or may be identical, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0029] At the interface between a memory node contact comprising polysilicon and a second spacer comprising silicon nitride, dangling bonds can form, increasing depletion in the memory node contact. For example, high-energy alpha particles irradiating a semiconductor memory device can form dangling bonds at the interface between polysilicon and silicon nitride. The formation of these dangling bonds causes free electrons in the memory node contact to expand from their diffused depletion layer, and thus reduces the effective width of the memory node contact (i.e., the contact area between the memory node contact and the bonding pad), thereby increasing the contact resistance between the bonding pad and the memory node contact. This short-channel effect leads to reduced reliability and electrical characteristics in the semiconductor memory device.

[0030] According to the present invention, because a dielectric pattern 250, which may include silicon oxide or hafnium oxide, or may be formed from silicon oxide or hafnium oxide, is placed between the memory node contact BC and the second spacer 230, an interface between polysilicon and silicon oxide or hafnium oxide can be formed, and at the interface between the memory node contact BC and the second spacer 230, for example, only a small amount of dangling bonds due to alpha particles can be formed, or the formation can be prevented. Therefore, depletion at the memory node contact BC can be prevented, and a reduction in the effective width of the memory node contact BC can be avoided. The semiconductor memory device according to the present invention can improve reliability and electrical characteristics.

[0031] A bonding pad LP can be disposed on the storage node contact BC. A portion of the bit line BL can be vertically stacked with the bonding pad LP. The storage node contact BC and the bonding pad LP can be used to achieve a connection between the active pattern ACT and the bottom electrode BE of the capacitor formed on the bit line BL. The bonding pad LP can be configured to be stacked correspondingly with the storage node contact BC. The bonding pad LP can include or be formed of a metallic material (e.g., tungsten).

[0032] The conductive barrier layer 310 may be disposed between the memory node contact BC and the bonding pad LP, between the bit line spacer SP and the bonding pad LP, and between the bit line BL and the bonding pad LP. The conductive barrier layer 310 may conformally cover the bit line BL, the memory node contact BC, and the bit line spacer SP. The conductive barrier layer 310 may include or may be formed of a metal nitride (such as titanium nitride or tantalum nitride).

[0033] A second groove 312 may be formed on the bit line covering pattern 155 and between the bonding pads LP. The second groove 312 may share the sidewalls of the bonding pads LP as its inner sidewalls. The second groove 312 may have a bottom surface spaced apart from the bit line BL. The second groove 312 may expose the sidewalls of the bonding pads LP. The second groove 312 may separate the bonding pads LP from each other in the second direction D2 and the third direction D3.

[0034] The upper buried pattern 320 may be placed in the second recess 312. The upper buried pattern 320 may fill the space between the bonding pads LP. The upper buried pattern 320 may have a top surface that is substantially coplanar with the top surface of the bonding pads LP. The upper buried pattern 320 may include silicon oxide, silicon nitride, or a combination thereof, or may be formed of silicon oxide, silicon nitride, or a combination thereof.

[0035] Semiconductor memory devices according to some exemplary embodiments of the present invention may include data storage elements. Each data storage element may be a capacitor. For example, a data storage element may include a bottom electrode BE, a top electrode TE covering the bottom electrode BE, and a dielectric layer 330 between the bottom electrode BE and the top electrode TE. The bottom electrode BE may be disposed on a bonding pad LP. The top electrode TE may be a common electrode that commonly covers the bottom electrode BE. According to some exemplary embodiments, each bottom electrode BE may have a hollow cylindrical shape or a columnar shape. The dielectric layer 330 may conformally cover the top surface and sidewalls of each bottom electrode BE.

[0036] The bottom electrode BE and the top electrode TE may comprise, or may be formed from, one of doped silicon, metal, and metal compounds. The dielectric layer 330 may be a monolayer or a combination of monolayers comprising at least one metal oxide (such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) and / or a perovskite dielectric material (such as SrTiO3(STO), (Ba,Sr)TiO3(BST), BaTiO3, PZT, and PLZT) or at least one metal oxide (such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) and / or a perovskite dielectric material (such as SrTiO3(STO), (Ba,Sr)TiO3(BST), BaTiO3, PZT, and PLZT).

[0037] Figures 2A to 10A A plan view is shown illustrating a method for manufacturing a semiconductor memory device according to some exemplary embodiments conceived in accordance with the present invention. Figures 2B to 10B They show the following along Figures 2A to 10A The sectional view taken by lines I-I' and II-II'.

[0038] Reference Figure 2A and Figure 2BDevice isolation patterns 102 can be formed in substrate 100 to define active patterns ACT. For example, trenches can be formed at cell array regions of substrate 100, and device isolation patterns 102 can fill the trenches. Device isolation patterns 102 can be formed using shallow trench isolation (STI) methods. Device isolation patterns 102 can include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride, or can be formed from at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. When viewed in a plan view, each active pattern ACT can have a strip shape, and its major axis can lie on a first direction D1 that intersects both a second direction D2 and a third direction D3 that intersects the second direction D2. For example, the strip shape can extend longitudinally in the first direction D1. The first direction D1 to the third direction D3 can be coplanar lines lying on the same plane parallel to the top surface or bottom surface of substrate 100.

[0039] Word lines WL can be formed in corresponding grooves formed in the substrate 100. A pair of word lines WL can extend across each active pattern ACT. The pair of word lines WL can divide each active pattern ACT into a first source / drain region SDR1 and a pair of second source / drain regions SDR2. The first source / drain region SDR1 can be defined between the pair of word lines WL, and the pair of second source / drain regions SDR2 can be defined on opposite edges (i.e., end portions) of each corresponding active pattern ACT.

[0040] The substrate 100 can be patterned to form grooves extending linearly in the second direction D2. A gate dielectric layer can be formed on the substrate 100 with the grooves formed. The gate dielectric layer can be formed using a thermal oxidation process, an atomic layer deposition process, or a chemical vapor deposition process. The gate dielectric layer may include a dielectric material (e.g., one or more of silicon oxide, silicon nitride, and metal oxides) or may be formed of a dielectric material (e.g., one or more of silicon oxide, silicon nitride, and metal oxides). A gate electrode layer can be formed on the substrate 100 on which the gate dielectric layer is formed. The gate electrode layer can be formed using a chemical vapor deposition process. The gate electrode layer may include one of the following: doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.), or may be formed from one of the following: doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). An etching process may be performed to etch the gate electrode layer to form a word line WL in a corresponding recess. The etching process may continue until the gate electrode layer has a certain thickness in the recess. The portion of the gate dielectric layer exposed and not covered by the word line WL may be removed to form a gate dielectric pattern 105. The gate dielectric pattern 105 may be formed between the word line WL and the active pattern ACT and / or between the word line WL and the device isolation pattern 102. The etching process can expose the top surface of the device isolation pattern 102 and the top surface of the active pattern ACT. A word line overlay layer can be formed on the substrate 100, and then a planarization process can be performed to form a word line overlay pattern 110 in each recess. The word line overlay layer may include a dielectric material (e.g., silicon nitride) or may be formed of a dielectric material (e.g., silicon nitride).

[0041] Reference Figure 3A and Figure 3B Impurities can be implanted into each active pattern ACT to form a first impurity region 112a and a second impurity region 112b. The first impurity region 112a and the second impurity region 112b can be formed by an ion implantation process. For example, the first impurity region 112a and the second impurity region 112b can be regions doped with n-type impurities. Compared to the second impurity region 112b, the first impurity region 112a can extend relatively deeper into the substrate 100. The first impurity region 112a and the second impurity region 112b can be formed in the first source / drain region SDR1 and the second source / drain region SDR2, respectively.

[0042] An interlayer dielectric layer and a first word line layer can be formed on the entire surface of substrate 100. The first word line layer may comprise or be formed of polysilicon. The first word line layer can be used as an etch mask to etch the interlayer dielectric layer, device isolation pattern 102, substrate 100, and word line overlay pattern 110 to simultaneously form a first recess 122 and a preliminary interlayer dielectric layer 121. The preliminary interlayer dielectric layer 121 can be formed as a single layer or multiple layers comprising at least one selected from silicon oxide, silicon nitride, and silicon oxynitride layers, or formed from at least one selected from silicon oxide, silicon nitride, and silicon oxynitride layers. When viewed in a plan view, the preliminary interlayer dielectric layer 121 can be shaped to resemble a plurality of islands spaced apart from each other. The preliminary interlayer dielectric layer 121 can be formed to simultaneously cover the ends of two adjacent active patterns ACT. When viewed in a plan view, the first recess 122 can have a grid (or lattice) shape. The first recess 122 can expose a first impurity region 112a.

[0043] A bit line contact layer can be formed on the entire surface of substrate 100, filling the first groove 122. For example, the bit line contact layer may comprise or be formed of polysilicon. The bit line contact layer may undergo a planarization process to remove the bit line contact layer on the first bit line layer and expose the top surface of the first bit line layer. A bit line barrier layer, a second bit line layer, and a bit line capping layer can be sequentially formed on the first bit line layer and the bit line contact layer. The bit line barrier layer may comprise or be formed of a metal silicide layer. The second bit line layer may comprise a metal (e.g., tungsten, titanium, tantalum, aluminum, copper, nickel, or cobalt) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), or may be formed of a metal (e.g., tungsten, titanium, tantalum, aluminum, copper, nickel, or cobalt) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride). The bit line capping layer may include one or more of nitrides (e.g., silicon nitride) and oxides (e.g., silicon oxynitride), or may be formed from one or more of nitrides (e.g., silicon nitride) and oxides (e.g., silicon oxynitride). An etching process may be performed such that the bit line capping layer, the second bit line layer, the bit line barrier layer, the first bit line layer, and the bit line contact layer are sequentially etched to form bit line capping pattern 155, second bit line pattern 152, bit line barrier pattern 151, first bit line pattern 150, and bit line contact DC, respectively. The first bit line pattern 150, bit line barrier pattern 151, and second bit line pattern 152 may be collectively referred to as bit line BL. The etching process may partially expose the top surface of the initial interlayer dielectric layer 121, and may also partially expose the inner sidewalls and bottom surface of the first recess 122.

[0044] Reference Figure 4A and Figure 4BA first spacer layer can be formed on the entire surface of the substrate 100. The first spacer layer can conformally cover the bottom surface and inner sidewalls of the first recess 122. The first spacer layer may include or may be formed of silicon nitride. A dielectric pad layer and a buried dielectric layer can be sequentially formed on the entire surface of the substrate 100 to fill the first recess 122, and then an anisotropic etching process can be performed such that the dielectric pad layer and the buried dielectric layer are anisotropically etched to form a dielectric pad 140 and a lower buried pattern 141 in the first recess 122. The dielectric pad 140 may include or may be formed of silicon oxide, and the lower buried pattern 141 may include or may be formed of silicon nitride. When the anisotropic etching process is performed, the first spacer layer can be etched to form the first spacer 210. A sacrificial spacer layer can be conformally formed over the entire surface of substrate 100, and then anisotropically etched to form a sacrificial spacer 220 covering the sidewalls of the first spacer 210. The sacrificial spacer 220 may comprise a material (such as silicon oxide) that is etch-selective relative to the first spacer 210, or may be formed from a material (such as silicon oxide) that is etch-selective relative to the first spacer 210. Anisotropic etching can be performed on the initial interlayer dielectric layer 121 to form the interlayer dielectric layer 120 and expose the top surface of substrate 100. A second spacer layer can be conformally formed over the entire surface of substrate 100, and then anisotropically etched to form a second spacer 230 covering the sidewalls of the sacrificial spacer 220. The second spacer 230 may comprise silicon nitride.

[0045] Reference Figure 5A and Figure 5B A sacrificial pattern can be formed on the entire surface of the substrate 100, defining the location of the memory node contact BC, which will be discussed below. For example, the sacrificial pattern can comprise, or be formed from, silicon oxide, polysilicon, or silicon germanium. The sacrificial patterns can be separated from each other between bit lines BL and can be vertically stacked with the second impurity region 112b. An opening can be provided therebetween defining the location of the dielectric gate 300, which will be discussed below. When the sacrificial pattern is formed, partial etching can be performed on the upper portions of the first spacer 210, sacrificial spacer 220, and second spacer 230 exposed to the opening. In embodiments, damage to the first spacer 210, sacrificial spacer 220, and second spacer 230 can be avoided during partial etching by appropriately controlling the etching conditions using methods such as load effects.

[0046] A dielectric gate 300 can be formed in the opening. The dielectric gate 300 may include, for example, silicon nitride, silicon oxide, or silicon oxynitride, or may be formed from, for example, silicon nitride, silicon oxide, or silicon oxynitride. The dielectric gate 300 may be vertically stacked with the word line WL. The sacrificial pattern may be removed, and a third groove 202 may be formed to expose the second impurity region 112b of the substrate 100.

[0047] Reference Figure 6A and Figure 6B A polysilicon layer filling the third recess 202 can be formed on the entire surface of the substrate 100, and then etched to form a first preliminary contact 241. The first preliminary contact 241 can fill a portion of the third recess 202. For example, a portion of the polysilicon layer can remain at the bottom of the third recess 202 as the first preliminary contact 241. The first preliminary contact 241 can have a top surface that is substantially coplanar with the top surface of the substrate 100. For example, the first preliminary contact 241 can expose the sidewalls of the second spacer 230.

[0048] A first preliminary dielectric layer 251 may be formed on the entire surface of the substrate 100. The first preliminary dielectric layer 251 may conformally cover the sidewalls of the second spacer 230, the top surface of the second spacer 230, the top surface of the sacrificial spacer 220, the top surface of the first spacer 210, the top surface of the bit line overlay pattern 155, and the top surface of the first preliminary contact 241. The first preliminary dielectric layer 251 may comprise an oxide (e.g., silicon oxide or hafnium oxide) or may be formed of an oxide (e.g., silicon oxide or hafnium oxide).

[0049] Reference Figure 7A and Figure 7B An etching process can be performed to etch the first preliminary dielectric layer 251 to form a second preliminary dielectric layer 252 and expose the top surface of the first preliminary contact 241. For example, the first preliminary dielectric layer 251 can be partially removed to reduce its thickness, and the first preliminary dielectric layer 251 retained after the etching process can correspond to the second preliminary dielectric layer 252. The second preliminary dielectric layer 252 can conformally cover the sidewalls of the second spacer 230, the top surface of the second spacer 230, the top surface of the sacrificial spacer 220, the top surface of the first spacer 210, and the top surface of the bit line overlay pattern 155. The second preliminary dielectric layer 252 can have a thickness smaller than that of the first preliminary dielectric layer 251. In this specification, for example, the term "thickness" can indicate a distance measured in a direction perpendicular to the top surface of the substrate 100 that corresponds to the top surface of the second impurity region 112b. When the etching process is performed, the top surface of the first preliminary contact 241 can be partially etched to make it concave. A cleaning process can be performed to remove etching byproducts from the top surface of the first initial contact 241.

[0050] Reference Figure 8A and Figure 8B A second polysilicon layer can be formed on the entire surface of the substrate 100, and an etching process can be performed to etch the polysilicon layer to form a second preliminary contact 242. The second preliminary contact 242 may include a first preliminary contact 241 and a second polysilicon layer stacked and etched on the first preliminary contact 241, or it may be formed from the first preliminary contact 241 and the second polysilicon layer stacked and etched on the first preliminary contact 241. The second preliminary contact 242 may have a top surface that is lower in height (or level) than the top surface of the bit line cover pattern 155 and the top surface of the first spacer 210. The etching process may partially etch the upper portions of the bit line cover pattern 155, the sacrificial spacer 220, and the second spacer 230. The upper portion of the first spacer 210 may also be partially etched to give it a small width at the upper portion of the first spacer 210.

[0051] When performing an etching process, the second preliminary dielectric layer 252 can be etched to form a third preliminary dielectric layer 253. The third preliminary dielectric layer 253 can expose the top surfaces of the bit line cover pattern 155, the first spacer 210, the sacrificial spacer 220, and the second spacer 230. The third preliminary dielectric layer 253 can be positioned between the second spacer 230 and the second preliminary contact 242. The third preliminary dielectric layer 253 can cover the sidewalls of the second spacer 230. The third preliminary dielectric layer 253 can have a top surface at a height (or level) substantially the same as the top surface of the second spacer 230. The height (or level) of the top surface of the third preliminary dielectric layer 253 can be substantially the same as the height (or level) of the top surface of the second preliminary contact 242. The third preliminary dielectric layer 253 can have a bottom surface substantially coplanar with the top surface of the substrate 100 (e.g., the top surface of the second impurity region 112b). An upper capping layer 260 can be formed over the entire surface of the substrate 100. For example, the upper capping layer 260 may include or be formed of silicon nitride. The upper capping layer 260 may conformally cover the top surface of the second preliminary contact 242, the third preliminary dielectric layer 253, the second spacer 230, the sacrificial spacer 220, and the bit line cover pattern 155, and may also conformally cover the sidewalls of the first spacer 210. The upper capping layer 260 may be formed to prevent damage during subsequent etching processes.

[0052] Reference Figure 9A and Figure 9BAn etching process can be performed to etch the second preliminary contact 242 to form the memory node contact BC. The etching process can partially etch the upper cover layer 260, the sacrificial spacer 220, and the upper portion of the second spacer 230. In the etching process, the third preliminary dielectric layer 253 is etched to form a dielectric pattern 250. The dielectric pattern 250 can expose the sidewalls of the second spacer 230. The dielectric pattern 250 can be positioned between the second spacer 230 and the memory node contact BC. For example, the dielectric pattern 250 can cover both the sidewalls of the second spacer 230 and the sidewalls of the memory node contact BC. The dielectric pattern 250 can have a top surface at a height (or level) substantially the same as the top of the memory node contact BC. The dielectric pattern 250 can have a bottom surface substantially coplanar with the top surface of the substrate 100. The height (or level) of the top surface of the storage node contact BC can be lower than the height (or level) of the top surfaces of the bit line overlay pattern 155, the first spacer 210, the sacrificial spacer 220, and the second spacer 230. The first spacer 210 can be exposed at its upper sidewall. The aforementioned process can increase the process margin for forming the bonding pad, which will be discussed below.

[0053] A cleaning process can be performed to clean the top surface of the storage node contact BC. A conductive barrier layer 310 can be conformally formed across the entire surface of the substrate 100. For example, the conductive barrier layer 310 may comprise titanium nitride or tantalum nitride.

[0054] Reference Figure 10A and Figure 10B A bonding pad layer can be formed on the entire surface of the substrate 100, filling the space between the bit lines covering the patterns 155. For example, the bonding pad layer may include tungsten or may be formed of tungsten. An upper mask pattern 311 may be formed on the bonding pad layer. For example, the upper mask pattern 311 may include an amorphous carbon layer (ACL) or may be formed of an amorphous carbon layer (ACL). The upper mask pattern 311 may define the location of the bonding pads, which will be discussed below. The upper mask pattern 311 may be formed to be vertically stacked with the storage node contact BC. When viewed in a plan view, the upper mask pattern 311 may be shaped to resemble a plurality of islands spaced apart from each other.

[0055] An etching process can be performed using the upper mask pattern 311 as an etching mask to partially remove the bonding pad layer, conductive barrier layer 310, and bit line cover pattern 155. Thus, the bonding pad LP can be formed, and simultaneously, the second groove 312 can be formed. In this step, the first spacer 210 and the second spacer 230 on one side of the bit line cover pattern 155 can be removed to expose the tip of the sacrificial spacer 220. When performing the etching process to form the bonding pad LP and the second groove 312, the etchant supply can be controlled to suppress the etching of the sidewalls of the bonding pad LP, thereby preventing a reduction in the width of the bonding pad LP. Therefore, the process margin of the bonding pad LP can be increased. In this embodiment, the formation and etching processes of the bonding pad layer can be performed continuously.

[0056] Selective removal can be performed on the sacrificial spacer 220 exposed to the second groove 312. An etchant for etching the sacrificial spacer 220 can be introduced through the second groove 312 to remove it. The etchant can be introduced into the sacrificial spacer 220. The introduction of the etchant can continue satisfactorily without interruption by the dielectric barrier 300, etc., thus the sacrificial spacer 220 can be completely removed. Alternatively, the sacrificial spacer 220 can be completely replaced with an air gap AG. Therefore, the air gap AG can be uniformly distributed on the sidewalls of the bit line BL, resulting in a reduction in the capacitance dispersion of the bit line BL. In this embodiment, the air gap AG can reduce the parasitic capacitance between adjacent bit lines BL.

[0057] Reference Figure 1A and Figure 1B The upper mask pattern 311 can be removed to expose the top surface of the bonding pad LP. The upper mask pattern 311 can be removed before forming the air gap AG. An upper buried pattern 320 can be formed between the bonding pads LP. For example, the upper buried pattern 320 can fill the second recess 312. The upper buried pattern 320 can close the entrance to the air gap AG. For example, the upper buried pattern 320 can cover the top of the air gap AG. The upper buried pattern 320 can include or be formed of a dielectric material (e.g., silicon oxide or silicon nitride). The term "gas" as discussed herein can refer to atmospheric air or other gases that may be present during the manufacturing process.

[0058] A bottom electrode BE can be formed on the bonding pad LP. The bottom electrode BE may include, or may be formed from, doped silicon, metal, or metal compound. A dielectric layer 330 can be formed on the bottom electrode BE. The dielectric layer 330 may conformally cover the top surface of the bottom electrode BE. The dielectric layer 330 may be a monolayer or a combination of monolayers comprising at least one metal oxide (such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) and / or perovskite dielectric materials (such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT). A top electrode TE can be formed on the dielectric layer 330. The top electrode TE may include, or may be formed from, doped silicon, metal, or metal compound. The bottom electrode BE, dielectric layer 330, and top electrode TE can constitute a data storage element (e.g., a capacitor).

[0059] In semiconductor memory devices according to some exemplary embodiments of the present invention, a dielectric pattern can be placed between the memory node contacts and the bit line spacers, thereby preventing the formation of floating blocks between the memory node contacts and the bit line spacers. Therefore, depletion can be prevented at the memory node contacts, and ultimately the semiconductor memory device according to the present invention can improve reliability and electrical characteristics.

[0060] Although the inventive concept has been described with reference to some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes a device isolation pattern defined by an active pattern extending in a first direction, the active pattern including a first source / drain region and a second source / drain region. The character line extends in a second direction that intersects with the first direction; Bit lines are located on word lines and are electrically connected to the first source / drain region. The bit lines extend upward at a third point where they intersect the first and second directions. Position line spacers are located on the sidewalls of the position lines; The memory node contact is electrically connected to the second source / drain region and spaced from the bit line; the bit line spacer is disposed between the bit line and the memory node contact. as well as Dielectric pattern, located between bit line spacers and memory node contacts. The bit line spacers include: The first spacer covers the sidewall of the position line; and The second spacer is located between the dielectric pattern and the first spacer. Wherein, the entire first spacer is spaced apart from the entire second spacer, and The dielectric pattern contacts the second spacer.

2. The semiconductor memory device according to claim 1, wherein, The top surface of the dielectric pattern is coplanar with the top surface of the memory node contact, and The bottom surface of the dielectric pattern is coplanar with the top surface of the substrate.

3. The semiconductor memory device according to claim 1, in, The dielectric pattern includes a material that is different from the material of the first spacer and the material of the second spacer.

4. The semiconductor memory device according to any one of claims 1 to 3, in, The dielectric pattern includes silicon oxide or hafnium oxide.

5. The semiconductor memory device according to any one of claims 1 to 3, in, When viewing a semiconductor memory device in a planar diagram, the dielectric pattern has a square ring structure or a circular ring structure.

6. The semiconductor memory device according to any one of claims 1 to 3, in, The second spacer has a first width in the second direction, and The dielectric pattern has a second width in the second direction, which is smaller than the first width of the second spacer.

7. The semiconductor memory device of claim 1, further comprising: The bonding pad is electrically connected to the storage node contact; as well as The buried pattern is located on the sidewall of the joint pad. Among them, an air gap is provided between the first spacer and the second spacer in the position line spacer, and The upper buried pattern covers the top of the air gap.

8. The semiconductor memory device of claim 1, further comprising: Bit line overlay pattern, located on the bit line; as well as Bit line contacts are electrically connected to the first source / drain region.

9. The semiconductor memory device of claim 1, further comprising: The bonding pad has an electrical connection to the storage node contact and is vertically stacked with a portion of the bit line; The bottom electrode is located on the bonding pad; as well as The top electrode is located on the bottom electrode.

10. The semiconductor memory device according to any one of claims 1 to 3 and 7 to 9, in, The dielectric pattern covers the sidewalls of the storage node contacts and the sidewalls of the second spacer.

11. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes a device isolation pattern defined by an active pattern extending in a first direction, the active pattern including a first source / drain region and a second source / drain region. The character line extends in a second direction that intersects with the first direction; Bit lines are located on word lines and are electrically connected to the first source / drain region. The bit lines extend upward at a third point where they intersect the first and second directions. Position line spacers are located on the sidewalls of the position lines; The memory node contact is electrically connected to the second source / drain region and spaced from the bit line; the bit line spacer is disposed between the bit line and the memory node contact. A dielectric barrier is stacked vertically with the word line and located between a memory node contact and another memory node contact; as well as Dielectric patterns are located between memory node contacts and bit line spacers, and between memory node contacts and dielectric fences. When a semiconductor memory device is viewed in a planar diagram, the dielectric pattern has a square ring structure or a circular ring structure. The bit line spacers include a first spacer and a second spacer located between the bit line and the memory node contact. Wherein, the entire first spacer is spaced apart from the entire second spacer, and The dielectric pattern contacts the second spacer.

12. The semiconductor memory device according to claim 11, in, The first spacer is adjacent to the sidewall of the bit line, and the second spacer is adjacent to the sidewall of the memory node contact. The spacer also includes an air gap located between the first spacer and the second spacer.

13. The semiconductor memory device according to claim 12, wherein, The top surface of the dielectric pattern is lower than the top surface of the second spacer. The top surface of the second spacer is higher than the top surface of the bit line, and The top surface of the first spacer is higher than the top surface of the second spacer.

14. The semiconductor memory device according to any one of claims 11 to 13, wherein, The bottom surface of the dielectric pattern is coplanar with the top surface of the substrate, and The dielectric pattern covers the sidewalls of the memory node contacts, the sidewalls of the bit line spacers, and the sidewalls of the dielectric fence.

15. The semiconductor memory device of claim 11, further comprising: Bit line overlay pattern, located on the bit line; as well as A conductive barrier layer conformally covers the bit line overlay pattern, storage node contacts, and bit line spacers.

16. The semiconductor memory device according to claim 11, in, Bit lines include: The first line pattern is located on the base; The second line pattern is located above the first line pattern; and The bit line blocking pattern is located between the first bit line pattern and the second bit line pattern.

17. The semiconductor memory device of claim 11, further comprising: The bonding pad has an electrical connection to the storage node contact and is vertically stacked with a portion of the bit line; The bottom electrode is located on the bonding pad; The top electrode is located on top of the bottom electrode; as well as The dielectric layer is located between the bottom electrode and the top electrode.

18. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes an active pattern having a long axis in a first direction, the active pattern including a first source / drain region and a pair of second source / drain regions spaced apart from each other in the first direction, the first source / drain region being disposed between the pair of second source / drain regions, and the substrate including a device isolation pattern defining the active pattern. The character line extends in a second direction that intersects with the first direction; Bit lines are located on word lines and are electrically connected to the first source / drain region. The bit lines extend upward at a third point where they intersect the first and second directions. The first line spacer is located on the side wall of the position line; A first memory node contact is electrically connected to one of the pair of second source / drain regions and spaced apart from the bit line, and a first bit spacer is disposed between the first memory node contact and the bit line; Bit line contact, electrically connected to the first source / drain region; Bit line overlay pattern, located on the bit line; The bonding pad is electrically connected to the first storage node contact. The bottom electrode is located on the bonding pad; as well as The dielectric pattern is located between the first line spacer and the first memory node contact. The first line spacer includes: The first spacer covers the sidewall of the position line; and The second spacer is located between the dielectric pattern and the first spacer. Wherein, the entire first spacer is spaced apart from the entire second spacer, and The dielectric pattern contacts the second spacer.

19. The semiconductor memory device of claim 18, further comprising: Multiple storage node contacts, including a first storage node contact; Multiple bit line spacers, including the first bit line spacer; as well as Multiple dielectric barriers are located on the word lines and within the space between two memory node contacts of the plurality of memory node contacts. The dielectric pattern is also disposed between the first storage node contact and a corresponding dielectric fence among the plurality of dielectric fences.

20. The semiconductor memory device of claim 18, further comprising: The air gap is located between the first spacer and the second spacer. as well as The buried pattern is located on the top of the air gap and on the sidewalls of the joint pad.

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