Memory device, memory system, and operating method thereof

Abstract

A method of operating a memory device, the method including: performing a first programming operation to form a plurality of first threshold voltage distributions; and based on offset information, performing a second programming operation to form a plurality of second threshold voltage distributions respectively corresponding to a plurality of program states from the plurality of first threshold voltage distributions by using a coarse verify voltage and a fine verify voltage, wherein the offset information includes a plurality of offsets that vary according to a characteristic of the second threshold voltage distributions.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0154092, filed with the Korean Intellectual Property Office on November 17, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to storage devices, and more specifically, to storage devices, storage systems and methods of operating thereof that perform programming through multiple steps. Background Technology

[0004] With the advancement of data technology, there is a need for highly reliable storage of massive amounts of data. To address this, various programming methods are being researched. In an example of a multi-step programming operation, after forming an approximate threshold voltage distribution in the first step, multiple target threshold voltage distributions, each corresponding to a different programming state, can be formed in the second step. However, in the second step, the offset between the coarse verification voltage and the fine verification voltage used to form the multiple target threshold voltage distributions is set equally, which may degrade the reliability of the programming operation. Summary of the Invention

[0005] According to an embodiment of the present invention, a method for operating a storage device is provided, the method comprising: performing a first programming operation to form a plurality of first threshold voltage distributions; and performing a second programming operation based on offset information by using a coarse verification voltage and a fine verification voltage to form a plurality of second threshold voltage distributions corresponding to a plurality of programming states, wherein the offset information includes a plurality of offsets varying according to characteristics of the second threshold voltage distributions.

[0006] According to an embodiment of the present invention, a storage device is provided, comprising: a storage cell array including a plurality of storage cells; and control logic that controls a first programming operation on the plurality of storage cells to form a plurality of first threshold voltage distributions, and controls a second programming operation on the plurality of storage cells to form a plurality of second threshold voltage distributions respectively corresponding to a plurality of programming states, wherein the control logic controls the second programming operation by using a plurality of offsets between coarse verification voltages and fine verification voltages that vary according to the characteristics of the second threshold voltage distributions.

[0007] According to an embodiment of the present invention, a storage device is provided, comprising: a storage cell region including a first metal pad; a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is connected to the storage cell region via the first and second metal pads in a direction perpendicular to a substrate in the storage cell region; a storage cell array including a plurality of storage cells, the plurality of storage cells being arranged in a plurality of strings in a direction perpendicular to a substrate in the storage cell region; and control logic in the peripheral circuit region, wherein the control logic controls a first programming operation on the plurality of storage cells to form a plurality of first threshold voltage distributions, and controls a second programming operation on the plurality of storage cells to form a plurality of second threshold voltage distributions corresponding to a plurality of programming states, wherein, for the second threshold voltage distributions, the control logic controls the second programming operation by using a plurality of offsets between a coarse verification voltage and a fine verification voltage.

[0008] According to an embodiment of the present invention, a storage system is provided, comprising: a plurality of storage devices; and a storage controller that controls the operation of the plurality of storage devices, wherein each of the plurality of storage devices performs a first step programming operation in response to a programming command from the storage controller to form a plurality of first threshold voltage distributions, and performs a second step programming operation by using coarse verification voltages and fine verification voltages with different offsets according to the characteristics of the second threshold voltage distributions to form a plurality of second threshold voltage distributions corresponding to a plurality of programming states. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present invention;

[0011] Figure 2A It is shown Figure 1 A diagram of the storage cell array; Figure 2B yes Figure 1 A perspective view of the storage cell array; Figure 2C It is shown Figure 2A A diagram of the equivalent circuit of the first memory block;

[0012] Figure 3 This is a flowchart illustrating a method for operating a storage device according to an embodiment of the present invention;

[0013] Figure 4A , Figure 4B and Figure 4C This is a diagram illustrating various programming methods based on memory cell types according to embodiments of the present invention;

[0014] Figure 5A and Figure 5B This is a diagram illustrating a programming method for a first-step programming operation and a second-step programming operation of a storage device according to an embodiment of the present invention;

[0015] Figure 6A and Figure 6B This is a diagram illustrating the first and second step programming operations of a storage device according to an embodiment of the present invention.

[0016] Figure 7A and Figure 7B This is a diagram illustrating a programming method based on a programming sequence among various programming methods according to embodiments of the present invention; Figure 7C and Figure 7D This is a diagram illustrating a high-speed programming (HSP) method among various programming methods according to embodiments of the present invention;

[0017] Figure 8 This is a flowchart illustrating a method for generating and storing offset information according to an embodiment of the present invention;

[0018] Figure 9A and Figure 9B This is a tabular diagram illustrating offset information according to an embodiment of the present invention;

[0019] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10F This is a diagram illustrating the second step of the programming operation using offset according to a conceptual embodiment of the present invention;

[0020] Figure 11A , Figure 11B and Figure 11C This is a diagram illustrating the second step of the programming operation using offset according to a conceptual embodiment of the present invention;

[0021] Figure 12A This is a block diagram illustrating an example of an implementation of a storage device that performs a second-step programming operation according to a conceptual embodiment of the present invention; Figure 12B It is shown Figure 12A A block diagram of an electronic fuse circuit;

[0022] Figure 13 This is a block diagram illustrating another implementation example of a storage device performing a second-step programming operation according to a conceptual embodiment of the present invention;

[0023] Figure 14 This is a flowchart illustrating a method for operating a storage device according to an embodiment of the present invention;

[0024] Figure 15This is a flowchart illustrating a method for operating a storage system according to an embodiment of the present invention;

[0025] Figure 16 This is a flowchart illustrating the operation of updating offset information based on programming / erasing (P / E) cycle information in operation S310;

[0026] Figure 17A and Figure 17B This is a diagram illustrating the operation of updating offset information based on the P / E cycle of the storage device;

[0027] Figure 18 This is a block diagram illustrating a storage system according to an embodiment of the present invention;

[0028] Figure 19 This is a block diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present invention; and

[0029] Figure 20 This is a diagram illustrating a chip-to-chip (C2C) structure applied to a memory device according to an embodiment of the present invention. Detailed Implementation

[0030] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Embodiments of the inventive concept will be described with reference to NAND flash memory. However, the inventive concept is not limited to NAND flash memory. The inventive concept can be applied to various non-volatile memory devices, such as electrically erasable programmable read-only memory (ROM) (EEPROM), NOR flash memory devices, phase-change random access memory (RAM) (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0031] Figure 1 This is a block diagram illustrating a storage device 100 according to an embodiment of the present invention.

[0032] refer to Figure 1 The storage device 100 may include a memory cell array 110, a page buffer circuit 120, control logic 130, a voltage generator 140, an address decoder 150, and data input / output circuitry 160. Furthermore, the control logic 130 may include a coarse-to-fine verification control module 132 operating according to embodiments of the present invention, as described later. The storage device 100 may also include various other functional blocks related to storage operations. The coarse-to-fine verification control module 132 may be implemented using hardware logic or software logic. Additionally, the coarse-to-fine verification control module 132 may be included in a storage controller.

[0033] The memory cell array 110 may include multiple strings (or cell strings) arranged in rows and columns on a substrate. Each of the multiple strings may include multiple memory cells stacked in a direction perpendicular to the substrate. In other words, the multiple memory cells may be stacked in a direction perpendicular to the substrate and may be configured as a three-dimensional structure. Each of the multiple memory cells may have a cell type such as a single-level cell, a two-level cell, a three-level cell, or a four-level cell. The inventive concept can be flexibly applied according to each of the various cell types of each of the multiple memory cells.

[0034] According to embodiments of the present invention, as examples of the memory cell array 110, U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Publication No. 2011 / 0233648 describe a three-dimensional memory cell array with multiple levels, and word lines WL and / or bit lines BL shared among the multiple levels, which are incorporated herein by reference in their entirety. Furthermore, the disclosures of U.S. Patent Publications Nos. 2012-0051138 and 2011-0204420 are incorporated herein by reference in their entirety.

[0035] Multiple memory cells of the memory cell array 110 can be connected to the word line WL, the serial select line SSL, the ground select line GSL, and the bit line BL. The memory cell array 110 can be connected to the address decoder 150 via the word line WL, the serial select line SSL, and the ground select line GSL, and can be connected to the page buffer circuit 120 via the bit line BL.

[0036] Page buffer circuit 120 can temporarily store data to be programmed into memory cell array 110 and read data from memory cell array 110. Page buffer circuit 120 may include multiple page buffers (or multiple latch units). For example, each of the multiple page buffers may include multiple latches corresponding to multiple bit lines BL and may store data in units of pages. In some embodiments of the present invention, page buffer circuit 120 may include a sensing latch unit, and the sensing latch unit may include multiple sensing latches corresponding to multiple bit lines BL. Furthermore, each of the multiple sensing latches may be connected to a sensing node via a corresponding bit line to read data.

[0037] Control logic 130 can control the overall operation of storage device 100, and can output various internal control signals, for example, based on commands CMD, address ADDR and control signal CTRL received from the storage controller, for programming data to the storage cell array 110, reading data from the storage cell array 110 or erasing data stored in the storage cell array 110.

[0038] Various internal control signals output from control logic 130 can be provided to page buffer circuit 120, voltage generator 140, and address decoder 150. For example, control logic 130 can provide a voltage control signal CS_vol to voltage generator 140. Voltage generator 140 may include one or more pumps and can generate voltages VWL with various levels based on the voltage control signal CS_vol and the pump operation. Additionally, control logic 130 can provide row address X_ADD to address decoder 150 and column address Y_ADD and page buffer control signal PB_CS for controlling page buffer circuit 120 to page buffer circuit 120. The operation of coarse-fine verification control module 132 will be described below. Control logic 130 can generate internal control signals that conform to the operation of coarse-fine verification control module 132 and can output the generated internal control signals to corresponding functional blocks of storage device 100.

[0039] Control logic 130 can respond to programming command CMD to control a first-step programming operation and a second-step programming operation of storage device 100. The first-step programming operation causes multiple memory cells of memory cell array 110 to form multiple first threshold voltage distributions. Multiple first threshold voltage distributions approximately formed before performing the second-step programming operation can be referred to as multiple approximate threshold voltage distributions. After the first-step programming operation, the second-step programming operation causes multiple memory cells to form multiple second threshold voltage distributions, each corresponding to a multiple programming state. Multiple second threshold voltage distributions correctly formed to distinguish programming states can be referred to as multiple target threshold voltage distributions. For example, the number of approximate threshold voltage distributions generated by the first-step programming operation can be different from or equal to the number of target threshold voltage distributions generated by the second-step programming operation. For example, when the number of approximate threshold voltage distributions is 8 and the number of target threshold voltage distributions is 16, the first-step programming operation and the second-step programming operation can be referred to as an "8-16" step programming operation. In another example, when the number of approximate threshold voltage distributions is 16 and the number of target threshold voltage distributions is 16, the first-step programming operation and the second-step programming operation can be referred to as a "16-16" step programming operation.

[0040] According to an embodiment of the present invention, the second-step programming operation may include a programming loop, a coarse verification operation, and a fine verification operation. In the second-step programming operation, through the coarse and fine verification operations, the storage device 100 can repeat the programming loop until multiple memory cells form multiple target threshold voltage distributions. For example, in the second-step programming operation, among the memory cells included in the predetermined threshold voltage distribution, memory cells with a threshold voltage not less than the coarse verification voltage pass the coarse verification operation, while memory cells with a threshold voltage less than the coarse verification voltage can have their programming loop repeated. In other words, memory cells with a threshold voltage greater than the coarse verification voltage pass the coarse verification operation, while memory cells with a threshold voltage less than the coarse verification voltage fail, and therefore the programming loop is repeated for the failed memory cells. When all memory cells included in the predetermined threshold voltage distribution pass the coarse verification operation, a fine verification operation is performed on these memory cells, and memory cells with a threshold voltage not less than the fine verification voltage pass the fine verification operation, while memory cells with a threshold voltage less than the fine verification voltage can have their programming loop repeated. Therefore, in the second-step programming operation, the predetermined threshold voltage distribution can be moved to the target threshold voltage distribution. For example, the levels of the coarse verification voltage used for coarse verification operations and the fine verification voltage used for fine verification operations can vary depending on the programming state to be verified.

[0041] According to an embodiment of the present invention, the coarse-fine verification control module 132 can control the coarse verification operation and the fine verification operation included in the second step programming operation. As described below, the operation of the coarse-fine verification control module 132 can be referred to as the operation of the control logic 130. The coarse-fine verification control module 132 can control the coarse verification operation and the fine verification operation based on offset information including multiple offsets, according to the characteristics of the target threshold voltage distribution, by using coarse verification voltage and fine verification voltage.

[0042] The offset can be the difference between the coarse verification voltage and the fine verification voltage, and can refer to the level difference between the coarse verification voltage and the fine verification voltage, or the length difference between a first development interval using the coarse verification voltage and a second development interval using the fine verification voltage. In the first development interval or the second development interval, the voltage of the read node corresponding to the bit line of the corresponding memory cell connected in the page buffer circuit 120 develops from a predetermined precharge voltage to verify the programming state of the memory cell.

[0043] The characteristic of the target threshold voltage distribution can be described as the estimated movement distance in the direction of increasing threshold voltage, from the plurality of approximate threshold voltage distributions formed by the first step programming operation, through the second step programming operation. For example, the target threshold voltage distribution may include a first target threshold voltage distribution and a second target threshold voltage distribution, and in the second target threshold voltage distribution, the estimated movement distance in the second step programming operation may be greater than the estimated movement distance in the first target threshold voltage distribution. In this case, the offset between the coarse verification voltage and the fine verification voltage used to form the second target threshold voltage distribution may be greater than the offset between the coarse verification voltage and the fine verification voltage used to form the first target threshold voltage distribution. In some embodiments of the inventive concept, the characteristic of the target threshold voltage distribution can be described as the distribution velocity of the plurality of target threshold voltage distributions in the second step programming operation. For example, in the second step programming operation, the distribution velocity of the second target threshold voltage distribution may be greater than the distribution velocity of the first target threshold voltage distribution. In this case, the offset between the coarse verification voltage and the fine verification voltage used to form the second target threshold voltage distribution may be greater than the offset between the coarse verification voltage and the fine verification voltage used to form the first target threshold voltage distribution.

[0044] According to an embodiment of the present invention, the coarse-fine verification control module 132 can control coarse verification operations and fine verification operations by referring to offset information and using coarse verification voltages and fine verification voltages having offsets predetermined by a target threshold voltage distribution. According to an embodiment of the present invention, the offset information can be stored in a predetermined area of ​​the memory cell array 110 or in an electronic fuse circuit included in the memory device 100. Specific embodiments of the offset information will be described later.

[0045] Furthermore, according to embodiments of the present invention, the offset information may include offsets corresponding to multiple programming methods. Control logic 130 can control the first-step programming operation and the second-step programming operation based on a programming method selected from the multiple programming methods. The programming method can vary depending on the number of bits in the programming data and the programming order of the storage units, based on the cell type of the storage units. According to embodiments of the present invention, the coarse-fine verification control module 132 can control the coarse verification operation and the fine verification operation by obtaining the offset from the offset information corresponding to the programming method applied to the current first-step programming operation and the second-step programming operation. According to embodiments of the present invention, the offset information can be pre-generated during the mass production or testing of the storage device 100.

[0046] According to an embodiment of the present invention, the storage device 100 can perform coarse verification and fine verification operations by taking into account the characteristics of the target threshold voltage distribution in the second step programming operation, thereby increasing the interval between the target threshold voltage distributions as much as possible. Therefore, the storage device 100 can ensure improved data reliability.

[0047] Figure 2A To show Figure 1 A diagram of the storage cell array 110. Figure 2B for Figure 1 A perspective view of the storage cell array 110, and Figure 2C To show Figure 2A The diagram shows the equivalent circuit of the first storage block BLK1.

[0048] Reference Figure 1 and Figure 2A The storage cell array 110 may include multiple storage blocks BLK1 to BLKz. Each of the multiple storage blocks BLK1 to BLKz may have a three-dimensional structure (or a vertical structure). For example, each of the multiple storage blocks BLK1 to BLKz may include a structure extending in a first direction to a third direction. Each of the multiple storage blocks BLK1 to BLKz may include multiple cell strings extending in a second direction. The multiple cell strings may be spaced apart from each other in the first direction and the third direction. The cell strings of a storage block are connected to multiple bit lines BL, multiple string select lines SSL, multiple word lines WL, one ground select line or multiple ground select lines GSL, and a common source line. The cell strings of the multiple storage blocks BLK1 to BLKz may share multiple bit lines BL. For example, the multiple bit lines BL may extend in the second direction and may be shared by the multiple storage blocks BLK1 to BLKz.

[0049] Multiple storage blocks BLK1 to BLKz can be generated by Figure 1 The address decoder 150 shown is selected. For example, the address decoder 150 can select the memory block corresponding to the received address ADDR from a plurality of memory blocks BLKI to BLKz. Programming, reading, and erasing can be performed by the selected memory block. Furthermore, the first and second programming operations according to embodiments of the present invention can be performed by the selected memory block; however, this is only an example. For example, the present invention is not limited thereto, and therefore, the first and second programming operations can be performed on a per-memory sub-block or a predetermined group of memory blocks.

[0050] Further reference Figure 2BA substrate 111 is provided. The substrate 111 may be a first conductivity type well. In the substrate 111, a plurality of common source regions CSRs extending in a first direction and spaced apart from each other in a second direction may be provided. The plurality of common source regions CSRs may be interconnected to configure a common source line. The plurality of common source regions CSRs have a second conductivity type different from the first conductivity type of the substrate 111.

[0051] Between two adjacent common source regions in a plurality of common source regions (CSRs), a plurality of insulating materials 112 and 112a may be sequentially disposed on substrate 111 in a third direction (e.g., perpendicular to substrate 111). The plurality of insulating materials 112 and 112a may be spaced apart from each other in the third direction. The plurality of insulating materials 112 and 112a may extend in a first direction.

[0052] Between two adjacent common source regions, a plurality of pillars PL can be provided, sequentially arranged in a first direction and passing through a plurality of insulating materials 112 and 112a in a second direction. The plurality of pillars PL can contact the substrate 111 through the plurality of insulating materials 112 and 112a. Between two adjacent common source regions, the plurality of pillars PL can be spaced apart from each other in the first direction. The plurality of pillars PL can be arranged side-by-side in the first direction.

[0053] Multiple pillars PL can comprise a variety of materials. For example, multiple pillars PL can comprise a channel layer 114 and an internal material 115. The channel layer 114 can comprise a semiconductor material of a first conductivity type (e.g., silicon). The channel layer 114 can comprise a semiconductor material (e.g., silicon) having the same conductivity type as the substrate 111. The channel layer 114 can comprise an intrinsic semiconductor that does not have a conductivity type.

[0054] The internal material 115 may include an insulating material. For example, the internal material 115 may include an insulating material such as silicon oxide. The internal material 115 may also include an air gap. Between two adjacent common source regions, an information storage layer 116 may be disposed on the exposed surfaces of multiple insulating materials 112 and 112a and multiple pillars PL. The information storage layer 116 can store information by capturing or discharging charge.

[0055] Between two adjacent common source regions (CSRs) and between multiple insulating materials 112 and 112a, a first conductive material CM1, a second conductive material CM2, a third conductive material CM3, a fourth conductive material CM4, a fifth conductive material CM5, a sixth conductive material CM6, a seventh conductive material CM7, and an eighth conductive material CM8 are disposed on the exposed surface of the information storage layer 116. The first conductive materials CM1 to the eighth conductive materials CM8 may extend in a first direction. On the multiple common source regions (CSRs), the first conductive materials CM1 to the eighth conductive materials CM8 may be separated by word line cutouts (WL_Cut). The word line cutouts (WL_Cut) may expose the multiple common source regions (CSRs). The word line cutouts (WL_Cut) may extend in the first direction. The first conductive materials CM1 to the eighth conductive materials CM8 may include metallic conductive materials. The first conductive materials CM1 to the eighth conductive materials CM8 may also include non-metallic conductive materials such as polysilicon.

[0056] The information storage layer 116 disposed on the upper surface of the insulating material in the uppermost part of the plurality of insulating materials 112 and 112a can be removed. The information storage layer 116 disposed on the side surface of the plurality of insulating materials 112 and 112a facing the plurality of pillars PL can be removed.

[0057] Multiple drains 320 may be disposed on multiple pillars PL. The multiple drains 320 may comprise a semiconductor material of a second conductivity type (e.g., silicon). For example, the multiple drains 320 may comprise an N-conductivity type semiconductor material (e.g., silicon).

[0058] Multiple bit lines BL can be provided on multiple drains 320, extending in a second direction and spaced apart from each other in the first direction. The multiple bit lines BL are connected to the multiple drains 320. The multiple drains 320 can be connected to the multiple bit lines BL via contact plugs. The first bit line BL1 and the second bit line BL2 (see...) Figure 2C ,or Figure 2B The BL in the diagram may include a metallic conductive material. The first conductive line BL1 and the second conductive line BL2 may include a non-metallic conductive material such as polycrystalline silicon. The first conductive material CM1 to the eighth conductive material CM8 may have a first height to an eighth height in sequence starting from the substrate 111.

[0059] Multiple pillars PL can form multiple strings together with the information storage layer 116 and the first conductive materials CM1 to the eighth conductive materials CM8. Each of the multiple pillars PL can be configured into a string together with the information storage layer 116 and the adjacent conductive materials of the first conductive materials CM1 to the eighth conductive materials CM8. On the substrate 111, multiple pillars PL can be arranged in rows and columns. The eighth conductive material CM8 can be configured as a row. Pillars connected to the same eighth conductive material can be configured as a row. Multiple bit lines BL can be configured as columns. Pillars connected to the same bit line can be configured as a column. Multiple pillars PL together with the information storage layer 116 and the first conductive materials CM1 to the eighth conductive materials CM8 are configured into multiple strings arranged in rows and columns. Each of the multiple strings may include multiple unit transistors (or memory cells) stacked in a direction perpendicular to the substrate 111.

[0060] Reference Figure 2C Cell strings CS11, CS12, CS21, and CS22 can be connected between the first bit line BL1, the second bit line BL2, and the common source line CSL. Cell strings CS11 and CS21 can be connected between the first bit line BL1 and the common source line CSL. Cell strings CS12 and CS22 can be connected between the second bit line BL2 and the common source line CSL. Multiple common source regions CSR (reference) Figure 2B They can be connected together and a common source line (CSL) can be configured.

[0061] Memory cells of the same height are connected to a single word line, and when voltage is applied to a word line of a specific height, that voltage can be applied to all strings CS11, CS12, CS21, and CS22. Strings in different rows can be connected to the first string select line SSL1 and the second string select line SSL2, respectively. By selecting or deselecting the first string select line SSL1 and the second string select line SSL2, strings CS11, CS12, CS21, and CS22 can be selected or deselected row by row. For example, strings CS11 and CS12 or CS21 and CS22 connected to the unselected string select lines SSL1 or SSL2 can be electrically disconnected from the first bit line BL1 and the second bit line BL2. Strings CS21 and CS22 or CS11 and CS12 connected to the selected string select lines SSL2 or SSL1 can be electrically connected to the first bit lines BL1 and BL2.

[0062] Strings CS11, CS12, CS21, and CS22 can be connected to the first bit line BL1 and the second bit line BL2, column by column. Strings CS11 and CS21 can be connected to the first bit line BL1, and strings CS12 and CS22 can be connected to the second bit line BL2. By selecting or deselecting the first bit lines BL1 and BL2, strings CS11, CS12, CS21, and CS22 can be selected or deselected, column by column.

[0063] The first memory block BLK1 may also include multiple memory cells MC1, MC2, MC3, MC4, MC5 and MC6 respectively connected to multiple word lines WL1, W2, W3, W4, W5 and WL6, a ground select transistor GST connected to the ground select line GSL, and a string select transistor SST connected to one of the first string select line SSL1 or the second string select line SSL2.

[0064] Figure 3 This is a flowchart illustrating a method for operating a storage device according to an embodiment of the present invention.

[0065] Reference Figure 3 In operation S100, the storage device can perform a first-step programming operation on multiple storage cells. The storage device can form multiple approximate threshold voltage distributions through the first-step programming operation. In operation S120, the storage device can perform a second-step programming operation on the multiple storage cells using coarse verification voltages and fine verification voltages that conform to the characteristics of a target threshold voltage distribution. For example, the target threshold voltage distribution includes a first target threshold voltage distribution and a second target threshold voltage distribution, and when the characteristics of the first target threshold voltage distribution differ from the characteristics of the second target threshold voltage distribution, the storage device can control the offset between the coarse verification voltage and the fine verification voltage used to form the first target threshold voltage distribution to be different from the offset between the coarse verification voltage and the fine verification voltage used to form the second target threshold voltage distribution.

[0066] Figures 4A to 4C This is a diagram illustrating various programming methods based on storage unit types according to embodiments of the present invention.

[0067] Reference Figure 4A According to an embodiment of the present invention, when the storage cell type is a dual-level cell, the storage cell can form a target threshold voltage (Vth) distribution E corresponding to the erase state, and target threshold voltage distributions P1 to P3 corresponding to the first to third programming states respectively as a result of performing the first step programming operation and the second step programming operation.

[0068] Reference Figure 4B According to an embodiment of the present invention, when the memory cell type is a three-level cell, the memory cell can form a target threshold voltage (Vth) distribution E corresponding to the erase state, and target threshold voltage distributions P1 to P7 corresponding to the first to seventh programming states respectively as a result of performing the first step programming operation and the second step programming operation.

[0069] Reference Figure 4CAccording to an embodiment of the present invention, when the memory cell type is a four-level cell, the memory cell can form a target threshold voltage (Vth) distribution E corresponding to the erase state, and target threshold voltage distributions P1 to P15 corresponding to the first to fifteenth programming states respectively as a result of performing the first step programming operation and the second step programming operation.

[0070] Figures 4A to 4C The embodiments shown are merely examples, and therefore the inventive concept is not limited thereto and can also be applied to other applications. Figures 4A to 4C Various storage unit types not shown.

[0071] Figure 5A and Figure 5B This diagram illustrates a programming method for a memory device according to an embodiment of the present invention, including a first-step programming operation and a second-step programming operation. For convenience, the threshold voltage distribution corresponding to the erase state is omitted below, and for ease of understanding, this is assumed to be based on a three-level cell type. Embodiments of the present invention are not limited thereto.

[0072] Reference Figure 5A The storage device can form a first approximate threshold voltage distribution P1_1 to a fourth approximate threshold voltage distribution P4_1 by performing a first-step programming operation on the storage cells. After the first-step programming operation, the storage device can form a first target threshold voltage distribution P1 to a seventh target threshold voltage distribution P7 by performing a second-step programming operation on the storage cells. For example, the first target threshold voltage distribution P1 and the second target threshold voltage distribution P2 can be moved from the first approximate threshold voltage distribution P1_1. The third target threshold voltage distribution P3 and the fourth target threshold voltage distribution P4 can be moved from the second approximate threshold voltage distribution P2_1. The fifth target threshold voltage distribution P5 and the sixth target threshold voltage distribution P6 can be moved from the third approximate threshold voltage distribution P3_1. The seventh target threshold voltage distribution P7 can be moved from the fourth approximate threshold voltage distribution P4_1.

[0073] According to embodiments of the present invention, the characteristics of the second target threshold voltage distribution P2, the fourth target threshold voltage distribution P4, and the sixth target threshold voltage distribution P6, respectively corresponding to even-number programming states, may differ from the characteristics of the first target threshold voltage distribution P1, the third target threshold voltage distribution P3, the fifth target threshold voltage distribution P5, and the seventh target threshold voltage distribution P7, respectively corresponding to odd-number programming states. For example, the distance the second target threshold voltage distribution P2 moves from the first approximate threshold voltage distribution P1_1 may be greater than the distance the first target threshold voltage distribution P1 moves from the first approximate threshold voltage distribution P1_1. Furthermore, the distribution speed of the second target threshold voltage distribution P2 may be greater than the distribution speed of the first target threshold voltage distribution P1. The moving distance may be the distance between the minimum or maximum threshold voltage of the approximate threshold voltage distribution and the minimum or maximum threshold voltage of the target threshold voltage distribution. The minimum threshold voltage of the first approximate threshold voltage distribution P1_1 may refer to the leftmost side of the first approximate threshold voltage distribution P1_1, and the maximum threshold voltage of the first approximate threshold voltage distribution P1_1 may refer to the rightmost side of the first approximate threshold voltage distribution P1_1.

[0074] According to embodiments of the present invention, the storage device can control the coarse verification voltage and the fine verification voltage such that a first offset used to form the second target threshold voltage distribution P2, the fourth target threshold voltage distribution P4, and the sixth target threshold voltage distribution P6 is greater than a second offset used to form the first target characteristic threshold voltage distribution P1, the third target threshold voltage distribution P3, the fifth target threshold voltage distribution P5, and the seventh target threshold voltage distribution P7. In other words, considering the fast distribution characteristics or long estimation travel distance of the second target threshold voltage distribution P2, the fourth target threshold voltage distribution P4, and the sixth target threshold voltage distribution P6, the storage device can form the second target threshold voltage distribution P2, the fourth target threshold voltage distribution P4, and the sixth target threshold voltage distribution P6 by using the coarse verification voltage and the fine verification voltage with the first offset. Considering the slow distribution characteristics or short estimated movement distance of the first target characteristic threshold voltage distribution P1, the third target threshold voltage distribution P3, the fifth target threshold voltage distribution P5, and the seventh target threshold voltage distribution P7, the storage device can form the first target characteristic threshold voltage distribution P1, the third target threshold voltage distribution P3, the fifth target threshold voltage distribution P5, and the seventh target threshold voltage distribution P7 by using a coarse verification voltage and a fine verification voltage with a second offset.

[0075] Reference Figure 5BThe storage device can form a first approximate threshold voltage distribution P1_1 to a seventh approximate threshold voltage distribution P7_1 by performing a first-step programming operation on the storage cells. After the first-step programming operation, the storage device can form a first target threshold voltage distribution P1 to a seventh target threshold voltage distribution P7 by performing a second-step programming operation on the storage cells. For example, the first target threshold voltage distribution P1 to the seventh target threshold voltage distribution P7 can be moved from the first approximate threshold voltage distribution P1_1 to the seventh approximate threshold voltage distribution P7_1.

[0076] According to embodiments of the present invention, some of the characteristics of the first target threshold voltage distribution P1 to the seventh target threshold voltage distribution P7 may be identical to each other, while the characteristics of some other target threshold voltage distributions P1 to P7 may be different from each other. For example, the first target threshold voltage distribution P1 and the second target threshold voltage distribution P2 may have the same characteristics, while the third target threshold voltage distribution P3 may have characteristics different from those of the first target threshold voltage distribution P1 and the second target threshold voltage distribution P2. The second step programming operation can be performed considering the characteristics of the first target threshold voltage distributions P1 to P7, whether identical or different.

[0077] Figure 6A and Figure 6B This diagram illustrates the first and second programming operations of a memory device according to an embodiment of the present invention. In the following description, for convenience, only some of the multiple target threshold voltage distributions are shown and described. Furthermore, the following description is an example used to illustrate the inventive concept, and the inventive concept is not limited thereto. Figure 6A Corresponding to reference Figure 5A The described embodiments, and Figure 6B Corresponding to reference Figure 5B The described embodiments. In the following text, previous references may be omitted. Figure 5A and 5B The given description.

[0078] Reference Figure 6ABy performing a second-step programming operation using a coarse verification voltage V_c11 with a first level and a fine verification voltage V_f11 with a second level, the storage device can form a first target threshold voltage distribution P1 from a first approximate threshold voltage distribution P1_1. The offset os11 between the coarse verification voltage V_c11 and the fine verification voltage V_f11 used to form the first target threshold voltage distribution P1 can be referred to as the first offset. By performing a second-step programming operation using a coarse verification voltage V_c12 with a third level and a fine verification voltage V_f12 with a fourth level, the storage device can form a second target threshold voltage distribution P2 from the first approximate threshold voltage distribution P1_1. The offset os12 between the coarse verification voltage V_c12 and the fine verification voltage V_f12 used to form the second target threshold voltage distribution P2 can be referred to as the second offset. According to an embodiment of the present invention, the second offset os12 can be greater than the first offset os11, which may be a result of taking into account the characteristic that the second target threshold voltage distribution P2 has a faster distribution or a longer estimated movement distance than the first target threshold voltage distribution P1 in the second-step programming operation. This is an example embodiment, and the invention is not limited thereto. For example, depending on the characteristics of the target threshold voltage distribution, the first offset os11 can be greater than the second offset os12.

[0079] By performing a second-step programming operation using a coarse verification voltage V_c21 with a fifth level and a fine verification voltage Vf21 with a sixth level, the storage device can form a third target threshold voltage distribution P3 from a second approximate threshold voltage distribution P21. The offset os21 between the coarse verification voltage V_c21 and the fine verification voltage V_f21 used to form the third target threshold voltage distribution P3 can be referred to as the third offset. By performing a second-step programming operation using a coarse verification voltage V_c22 with a seventh level and a fine verification voltage V_f22 with an eighth level, the storage device can form a fourth target threshold voltage distribution P4 from a second approximate threshold voltage distribution P2_1. The offset os22 between the coarse verification voltage V_c22 and the fine verification voltage V_f22 used to form the fourth target threshold voltage distribution P4 can be referred to as the fourth offset. According to an embodiment of the present invention, the fourth offset os22 can be greater than the third offset os21, which may be a result of taking into account the characteristic that the fourth target threshold voltage distribution P4 has a faster distribution or a longer estimated movement distance than the third target threshold voltage distribution P3 in the second-step programming operation. This is an example embodiment, and the invention is not limited thereto. For example, depending on the characteristics of the target threshold voltage distribution, the third offset os21 can be greater than the fourth offset os22.

[0080] According to embodiments of the present invention, the first offset os11 and the third offset os21 may be identical or similar to each other, and the second offset os12 and the fourth offset os22 may be identical or similar to each other. Additionally, in Figure 6A The diagram shows that the first to fourth offsets os11, os12, os21, and os22 correspond to the level difference between the coarse verification voltage and the fine verification voltage. However, the inventive concept is not limited thereto, and the first to fourth offsets os11, os12, os21, and os22 may correspond to the length difference between the development interval using the coarse verification voltage and the development interval using the fine verification voltage.

[0081] Reference Figure 6B By performing a second-step programming operation using a coarse verification voltage V_c1 with a first level and a fine verification voltage V_f1 with a second level, the storage device can form a first target threshold voltage distribution P1 from a first approximate threshold voltage distribution P1_1. The offset os1 between the coarse verification voltage V_c1 and the fine verification voltage V_f1 used to form the first target threshold voltage distribution P1 can be referred to as the first offset. By performing a second-step programming operation using a coarse verification voltage V_c2 with a third level and a fine verification voltage V_f2 with a fourth level, the storage device can form a second target threshold voltage distribution P2 from a second approximate threshold voltage distribution P2_1. The offset os2 between the coarse verification voltage V_c2 and the fine verification voltage V_f2 used to form the second target threshold voltage distribution P2 can be referred to as the second offset. According to an embodiment of the present invention, the second offset os2 can be greater than the first offset os1, which may be a result of taking into account the characteristic that the second target threshold voltage distribution P2 has a faster distribution or a longer estimated movement distance than the first target threshold voltage distribution P1 in the second-step programming operation. This is an exemplary embodiment, and the invention is not limited thereto. For example, based on the characteristics of the target threshold voltage distribution, the first offset os1 can be greater than the second offset os2.

[0082] Figure 7A and Figure 7B This is a diagram illustrating a programming method according to programming order among various programming methods according to embodiments of the present invention; Figure 7C and Figure 7D This is a diagram illustrating a high-speed programming (HSP) method among various programming methods according to embodiments of the present invention.

[0083] Reference Figure 7AThe storage block BLK1 may include a plurality of storage cells MC connected to the first select line SSL1 to the third select line SSL3 and the first word line WL1 to the third word line WL3. According to an embodiment of the present invention, when performing a first step programming operation and a second step programming operation on the plurality of storage cells MC connected to the first word line WL1 to the third word line WL3, the storage device can execute a programming sequence based on address scrambling 1->2->3...->9. The storage device can sequentially perform programming operations on storage cells connected to the same word line in a predetermined order. According to an embodiment of the present invention, the storage device can perform programming operations on storage cells connected to the same word line in the order of storage cells connected to the first select line SSL1, storage cells connected to the second select line SSL2, and storage cells connected to the third select line SSL3.

[0084] Reference Figure 7B The storage block BLK1 may include multiple storage cells MC connected to the first select line SSL1 to the third select line SSL3 and the first word line WL1 to the third word line WL3. According to an embodiment of the present invention, when a first step programming operation and a second step programming operation are performed on the multiple storage cells MC connected to the first word line WL1 to the third word line WL3 based on a shadow programming method, the storage device can execute a programming sequence based on address scrambling 1->2->3...->6.

[0085] In the following text, Figure 7C and Figure 7D For convenience, in the current programming operation, it is assumed that the selected word line is the first word line and the unselected word line is the second word line. The reference numerals in the attached figure are used to distinguish word lines from each other and do not represent the physical location of the word lines.

[0086] For convenience, assume the previous page (PDp) is stored in the first word line. For example, before programming the first word line, the 0th word line can be programmed. In the programming operation on the 0th word line, the 0th word line can be the selected word line, the first word line can be the unselected word line, and at least one of the multiple pages corresponding to the 0th word line (e.g., PDp) can be non-selectively programmed into the first word line. In other words, at the point when programming operations begin on the first word line, the previous page (PDp) programmed in the previous non-selective programming operation can be stored in the first word line.

[0087] Reference Figure 7C and Figure 7DThe storage device can receive the first page PD11, the second page PD12, and the third page PD13 corresponding to the first word line. According to an embodiment of the present invention, the first page PD11, the second page PD12, and the third page PD13 can be stored in the page buffer of the storage device.

[0088] The storage device can program one of the first page PD11, the second page PD12, and the third page PD13 (e.g., the third page PD13) corresponding to the first word line to the second word line, which is an unselected word line. In other words, the storage device can perform a non-selective programming operation PGM_unsel on the second word line.

[0089] For example, such as Figure 7D As shown, the storage device can perform a non-selective programming operation PGM_unsel on the second word line, such that each memory cell connected to the second word line is in one of an erase state E and a non-selective programming state P01. According to an embodiment of the present invention, in the non-selective programming operation PGM_unsel, a non-selective verification voltage VF01 can be used to verify the non-selective programming state P01. When the non-selective programming operation PGM_unsel is performed on the second word line, the third page PD13 corresponding to the first word line is stored in the second word line, and the previous page PDp is stored in the first word line.

[0090] According to an embodiment of the present invention, when the number of pages corresponding to the selected word lines is n (n is a positive integer) and a non-selection programming operation PGM_unsel is performed on the unselected word lines, the number of memory cells connected to the unselected word lines can be less than 2. n Threshold voltage distribution.

[0091] Then, the storage device can read the previous page PDp by performing a previous page read operation RD_pre on the first word line. For example, as Figure 7D As shown, each memory cell on the first word line storing the previous page PDp can be in one of the erase state E and the non-selective programming state P01. The memory device can read the previous page PDp by performing a previous page read operation RD_pre using the read voltage VRD01.

[0092] According to an embodiment of the present invention, the previous page PDp read by the previous page read operation RD_pre can be stored in a specific latch of the page buffer. The specific latch can indicate a data latch in which the programmed page (e.g., the third page PD13) is stored in an unselected word line. In other words, after performing the previous page read operation RD_pre, the page buffer of the storage device can store the first page PD11 and the second page PD12 corresponding to the first word line, and the previous page PDp corresponding to another word line.

[0093] Then, the storage device can perform a selection programming operation PGM_sel on the first word line based on the first page PD11, the second page PD12, and the previous page PDp. For example, as described above, after performing the previous page read operation RD_pre, the page buffer of the storage device can store the first page PD11, the second page PD12, and the previous page PDp. The storage device can then perform a selection programming operation PGM_sel on the first word line based on the first page PD11, the second page PD12, and the previous page PDp stored in the page buffer.

[0094] By executing the selection programming operation PGM_sel, memory cells in the first word line that are in erase state E can be in one of the erase state E and the first programming state P1 to the third programming state P3, and memory cells in the non-selection programming state P01 can be in one of the fourth programming state P4 to the seventh programming state P7. In the selection programming operation PGM_sel, to verify the first programming state P1 to the seventh programming state P7, the first verification voltage VF1 to the seventh verification voltage VF7 can be used. Such a programming operation can be referred to as the 2-8HSP method, and the inventive concept can be applied during the programming operation described above as an example embodiment. The inventive concept is not limited thereto, and the 4-8HSP method can also be applied.

[0095] When the selection programming operation PGM_sel is performed on the first word line, the first word line can store the previous page PDp and the first page PD11 and the second page PD12 corresponding to the first word line, and the second word line can store the third page PD13 corresponding to the first word line.

[0096] because Figures 7A to 7D The embodiments described are examples, so the inventive concept is not limited thereto and can also be applied to the sun-who programming method.

[0097] Figure 8 This is a flowchart illustrating a method for generating and storing offset information according to an embodiment of the present invention. For example, the storage device can be connected to an external test device, and the offset information can be generated under the control of the external test device. In another example, the storage device can generate offset information via an internal built-in self-test (BIST) circuit. Hereinafter, embodiments of offset information generated by the storage device will be described primarily. However, the inventive concept is not limited thereto, and offset information according to the present invention can be generated in various ways to include multiple offsets that take into account the threshold voltage distribution characteristics of the storage cells of the storage device.

[0098] Reference Figure 8In operation S210, the storage device can execute a first-step programming operation and a second-step programming operation in the k-th programming method (k is an integer not less than 1). In operation S220, the storage device can measure the movement distance according to the second-step programming operation, which corresponds to multiple target threshold voltage distributions respectively for multiple programming states. For example, by measuring the movement distance from multiple approximate threshold voltage distributions formed in the first-step programming operation to multiple target threshold voltage distributions in the second-step programming operation, the storage device can determine the distribution speed of the multiple target threshold voltage distributions. In operation S230, based on the measurement results of operation S220, the storage device can determine the offset between the coarse verification voltage and the fine verification voltage of the target threshold voltage distribution. For example, the storage device can determine a first offset between the coarse verification voltage and the fine verification voltage used to form the first target threshold voltage distribution corresponding to the first programming state, and a second offset between the coarse verification voltage and the fine verification voltage used to form the second target threshold voltage distribution corresponding to the second programming state. The first offset may be different from the second offset. In operation S240, when the number of supported programming methods is n (n is an integer not less than 1), the storage device can determine whether "k" is equal to "n" and check whether offsets corresponding to all supported programming methods have been generated. When it is determined in operation S240 that "k" is not equal to "n", operation S250 is then executed, allowing the storage device to count to "k" and subsequently execute operation S210. When it is determined in operation S240 that "k" is equal to "n", the storage device can store offset information, including offsets corresponding to various programming methods, in a predetermined area within the storage device.

[0099] Figure 9A and Figure 9B This is a tabular diagram illustrating offset information according to an embodiment of the present invention.

[0100] Reference Figure 9A The first table, Table_1, which serves as an example of the implementation of offset information, may include first offset data items OS_DATA1 to OS_DATAn, respectively corresponding to the first programming method M1 to the nth programming method Mn. In some embodiments of the present invention, the storage device may support a limited number of programming methods. In this case, the offset information of the storage device may only include offset data corresponding to the supported programming methods. For example, the first programming method M1 may correspond to the four-level cell QLC and the '8-16' shadow programming method in the cell type. On the other hand, each of the first offset data items OS_DATA1 to OS_DATAn may include an offset applied to multiple threshold voltage distributions, such as... Figure 9B As described in detail in [the text].

[0101] Reference Figure 9B As Figure 9A The second table, Table_2, of the implementation example of the first offset data OS_DATA1 of the first table Table_1, may include first offset OS1 to fifteenth offset OS15 for forming a first target threshold voltage distribution P1 to a fifteenth target threshold voltage distribution P15 corresponding to the first programming state to the fifteenth programming state, respectively. For example, using a coarse verification voltage and a fine verification voltage with a first offset OS1, the storage device can form the first target threshold voltage distribution P1 by performing a second-step programming operation. Furthermore, by using a coarse verification voltage and a fine verification voltage with a second offset OS2, the storage device can perform a second-step programming operation to form a second target threshold voltage distribution P2. Furthermore, using a coarse verification voltage and a fine verification voltage with a fifteenth offset OS15, the storage device can perform a second-step programming operation to form the fifteenth target threshold voltage distribution P15.

[0102] Figures 10A to 10F This diagram illustrates the second step of the programming operation using offset according to an embodiment of the present invention. Figures 10A to 10F The following description is based on an embodiment in which an offset is achieved by using the length difference between the development interval of a coarse verification voltage and the development interval of a fine verification voltage. The following description is based on a second-step programming operation for forming a first target threshold voltage distribution and a second target threshold voltage distribution, provided that the second target threshold voltage distribution corresponds to a programming state higher than the first target threshold voltage distribution, the distribution rate of the second target threshold voltage distribution is greater than the distribution rate of the first target threshold voltage distribution, and the second offset corresponding to the second target threshold voltage distribution is greater than the first offset corresponding to the first target threshold voltage distribution.

[0103] Reference Figure 10A The levels of the coarse verification voltage V_c1 and the fine verification voltage V_f1 used to form the first target threshold voltage distribution can be the same as each other as the first level, or similar to each other. The levels of the coarse verification voltage V_c2 and the fine verification voltage Vf2 used to form the second target threshold voltage distribution can be the same as each other as the second level, or similar to each other. The second level can be higher than the first level. Figure 10A These are merely illustrative embodiments. The inventive concept is not limited thereto, and the coarse verification voltages V_c1 and V_c2 and the fine verification voltages V_f1 and V_f2 can be implemented with various levels that conform to the programming operation of the second step.

[0104] Reference Figure 10B The storage device 200 may include a storage cell array 210 and a page buffer circuit 220. Figure 10B The memory cell array 210 and page buffer circuit 220 shown can be Figure 1 An example of the memory cell array 110 and page buffer circuit 120 shown.

[0105] The memory cell array 210 may include multiple string select transistors SST1 to SSTq, multiple memory cells MC1q to MCpq, and multiple ground select transistors GST1 to GSTq. The multiple memory cells MC1q to MCpq may be connected between the multiple string select transistors SST1 to SSTq and the multiple ground select transistors GST1 to GSTq, and the control gates of the multiple memory cells MC1q to MCpq may be respectively connected to multiple word lines WL1 to WLp.

[0106] The drains of multiple string select transistors SST1 to SSTq can be connected to multiple bit lines BL1 to BLq respectively, and the gates of multiple string select transistors SST1 to SSTq can be connected to multiple string select lines SSL. Furthermore, the sources of multiple ground select transistors GST1 to GSTq can be connected to a common source line CSL, and the gates of multiple ground select transistors GST1 to GSTq can be connected to a ground select line GSL. A string can be defined as a string consisting of a string select transistor SST1, a ground select transistor GST1, and multiple memory cells MC1q to MCpq connected between the string select transistor SST1 and the ground select transistor GST1.

[0107] Page buffer circuit 220 may include multiple page buffers 221_1 to 221_q corresponding to multiple bit lines BL1 to BLq, respectively. The multiple page buffers 221_1 to 221_q may include multiple bit line connection units 223_1 to 223_q, multiple precharge units 225_1 to 225_q, and multiple data latch units 227_1 to 227_q. The multiple precharge units 225_1 to 225_q may be connected to the read node SN and may precharge the read node SN at a predetermined voltage in response to a precharge control signal during a precharge interval. The multiple data latch units 227_1 to 227_q may read data from selected memory cells by sensing the voltage level of the read node SN, or may output data received from an external source to the multiple bit line connection units 223_1 to 223_q via the read node SN.

[0108] Reference Figure 10CWhen performing a coarse verification operation to form a first target threshold voltage distribution, the storage device 200 can precharge the read node SN with a predetermined voltage VPRE during a precharge interval T1_1a between a first time t1a and a second time t2a. Then, during a first development interval T1v2a between the second time t2a and a third time t3a, a coarse verification voltage V_c1 is applied to multiple word lines WL1 to WLp, such that the voltage of the read node SN can be maintained when the threshold voltage of the selected memory cell is greater than the coarse verification voltage V_c1, and the voltage of the read node SN can be reduced when the threshold voltage of the selected memory cell is less than the coarse verification voltage V_c1. After the first development interval T1_2a, the selected memory cell passes the coarse verification operation when the voltage of the read node SN is not less than the reference voltage VREF, and fails the coarse verification operation when the voltage of the read node SN is less than the reference voltage VREF. In other words, when the voltage of the read node SN is greater than the reference voltage VREF, the selected memory cell passes the coarse verification operation; however, when the voltage of the read node SN is less than the reference voltage VREF, the coarse verification of the selected memory cell fails, allowing the programming loop to be repeated for the selected memory cell. For example, the selected memory cell may pass the coarse verification operation in the first case, but fail in the second case, resulting in repeated programming loops.

[0109] Reference Figure 10D When performing a fine-verification operation to form a first target threshold voltage distribution, the storage device 200 can precharge the read node SN with a predetermined voltage VPRE during a pre-charge interval T1_1b between the fourth time t1b and the fifth time t2b. Then, during a second development interval T2_1b between the fifth time t2b and the sixth time t3b, a fine-verification voltage V_f1 is applied to multiple word lines WL1 to WLp, such that the voltage of the read node SN can be maintained when the threshold voltage of the selected memory cell is greater than the fine-verification voltage V_f1, and the voltage of the read node SN can be reduced when the threshold voltage of the selected memory cell is less than the fine-verification voltage V_f1. After the second development interval T1_2b, the selected memory cell passes the fine-verification operation when the voltage of the read node SN is not less than the reference voltage VREF, and fails the fine-verification operation when the voltage of the read node SN is less than the reference voltage VREF, allowing the programming loop to be repeated for the selected memory cell. For example, the selected memory cell may pass the fine verification operation in the first case, but fail in the fine verification operation in the second case. According to an embodiment of the present invention, a first length difference tdiff1 may exist between the first development interval T1_2a and the second development interval T1_2b used to form the first target threshold voltage distribution.

[0110] Reference Figure 10E When performing a coarse verification operation to form a second target threshold voltage distribution, during the pre-charge interval T2_1a between the seventh time t1c and the eighth time t2c, the memory device 200 can pre-charge the read node SN with a predetermined voltage VPRE. Then, during the first development interval T2_2a between the eighth time t2c and the ninth time t3c, a coarse verification voltage V_c2 is applied to multiple word lines WL1 to WLp, such that the voltage of the read node SN can be maintained when the threshold voltage of the selected memory cell is greater than the coarse verification voltage V_c2, and the voltage of the read node SN can be reduced when the threshold voltage of the selected memory cell is less than the coarse verification voltage V_c2. After the first development interval T2_2a, when the voltage of the read node SN is not less than the reference voltage VREF, the selected memory cell passes the coarse verification operation, and when the voltage of the read node SN is less than the reference voltage VREF, the coarse verification operation fails, allowing the programming loop to be repeated for the selected memory cell. For example, with Figure 10C The difference is that the selected storage unit can pass the coarse verification operation in the first case, but fails the coarse verification operation in the second case.

[0111] Reference Figure 10F When performing a fine-verification operation to form a second target threshold voltage distribution, the storage device 200 can precharge the read node SN with a predetermined voltage VPRE during a pre-charge interval T2_1b between the tenth time t1d and the eleventh time t2d. Then, during a second development interval T2_2b between the eleventh time t2d and the twelfth time t3b, a fine-verification voltage V_f2 is applied to multiple word lines WL1 to WLp, such that the voltage of the read node SN can be maintained when the threshold voltage of the selected memory cell is greater than the fine-verification voltage V_f2, and can be reduced when the threshold voltage of the selected memory cell is less than the fine-verification voltage V_f2. After the second development interval T2_2b, the selected memory cell passes the fine-verification operation when the voltage of the read node SN is not less than the reference voltage VREF, and fails the fine-verification operation when the voltage of the read node SN is less than the reference voltage VREF, allowing the programming loop to be repeated for the selected memory cell. For example, the selected memory cell passes the fine-verification operation in the first case, and fails the fine-verification operation in the second case. According to an embodiment of the present invention, a second length difference tdiff2 may exist between the first development interval T2_2a and the second development interval T2_2b used to form the second target threshold voltage distribution.

[0112] According to an embodiment of the present invention, the second length difference tdiff2 can be greater than the first length difference tdiffl. In other words, considering that the second target threshold voltage distribution is faster than the first target threshold voltage distribution, the storage device can make the first development interval T2_2a using the coarse verification voltage V_c2 shorter than the first development interval T1_2a using the coarse verification voltage V_c1. Therefore, when the second target threshold voltage distribution is formed taking into account its characteristics, the storage device can increase the number of memory cells that pass the coarse verification operation.

[0113] The memory device according to embodiments of the present invention can control the number of memory cells to be coarsely verified by taking into account the characteristics of the target threshold voltage distribution, and thus improve the data reliability and performance of the memory device by forming an optimal target threshold voltage distribution.

[0114] Figures 11A to 11C This is a diagram illustrating the second step of the programming operation using offset, according to an embodiment of the concept of the present invention. Figures 11A to 11C The following description is based on an embodiment that achieves offset through the level difference between a coarse verification voltage and a fine verification voltage. The following description is based on a second-step programming operation for forming a first target threshold voltage distribution and a second target threshold voltage distribution, provided that the second target threshold voltage distribution corresponds to a programming state higher than the first target threshold voltage distribution, the distribution rate of the second target threshold voltage distribution is greater than the distribution rate of the first target threshold voltage distribution, and the second offset corresponding to the second target threshold voltage distribution is greater than the first offset corresponding to the first target threshold voltage distribution.

[0115] Reference Figure 11A The coarse verification voltage V_c1 used to form the first target threshold voltage distribution is at a first level, and the fine verification voltage V_f1 can be at a second level. The second level can be greater than the first level. The level difference between the coarse verification voltage V_c1 and the fine verification voltage V_f1 can correspond to the first level difference Ldiff1. The coarse verification voltage V_c2 used to form the second target threshold voltage distribution can be at a third level, and the fine verification voltage V_f2 can be at a fourth level. The fourth level can be greater than the third level. The level difference between the coarse verification voltage V_c2 and the fine verification voltage V_f2 can correspond to the second level difference Ldiff2. The second level difference Ldiff2 can be greater than the first level difference Ldiff1. Figure 11A These are exemplary embodiments. The inventive concept is not limited thereto, and the coarse verification voltages V_c1 and V_c2 and the fine verification voltages V_f1 and V_f2 can be implemented with various levels that conform to the programming operation of the second step.

[0116] refer to Figure 10B and Figure 11B When performing a coarse verification operation to form a first target threshold voltage distribution, the storage device 200 can precharge the read node SN with a predetermined voltage VPRE during a pre-charge interval T1a between a first time t1e and a second time t2e. Then, during a first development interval T2a between the second time t2e and a third time t3e, a coarse verification voltage V_c1 can be applied to multiple word lines WL1 to WLp.

[0117] refer to Figure 10B and Figure 11C When performing a fine-grained verification operation to form a first target threshold voltage distribution, the storage device 200 can precharge the read node SN with a predetermined voltage VPRE during a pre-charge interval T1b between a fourth time t1f and a fifth time t2f. Then, during a second development interval T2b between a fifth time t2f and a sixth time t3f, a fine-grained verification voltage V_f1 can be applied to multiple word lines WL1 to WLp. According to an embodiment of the present invention, a predetermined length difference tdiff can exist between the first development interval T2a and the second development interval T2b for forming the first target threshold voltage distribution, and the length difference between the first development interval and the second development interval for forming the second target threshold voltage distribution can correspond to this predetermined length difference tdiff. In other words, the predetermined length difference tdiff between the first development interval T2a and the second development interval T2b for forming the first target threshold voltage distribution, and the length difference tdiff between the first development interval and the second development interval for forming the second target threshold voltage distribution, can be the same.

[0118] On the other hand, in some embodiments of the inventive concept, the storage device can control the level difference between the coarse verification voltage and the fine verification voltage, and the length difference between the first development interval using the coarse verification voltage and the second development interval using the fine verification voltage, to vary according to the target threshold voltage distribution. In other words, referring to... Figures 10A to 10F The described embodiments can be compared with the references Figures 11A to 11C The described embodiments combine the features so that the combination can be implemented using a storage device.

[0119] Figure 12A This is a block diagram illustrating an implementation example of a storage device 200a performing a second-step programming operation according to a conceptual embodiment of the present invention, and Figure 12B It is shown Figure 12A A block diagram of the electronic fuse circuit 260a is provided. For convenience, previous references may be omitted in the following text. Figure 1 Description of overlapping elements. Figure 12A The storage device 200a can execute reference Figures 10A to 10F The described operation.

[0120] Reference Figure 12A ,and Figure 1 Compared to the storage device 100, the storage device 200a may further include an electronic fuse circuit 260a. The electronic fuse circuit 260a may include first fuse unit regions 262a_1 to nth fuse unit regions 262a_n. In each of the first fuse unit regions 262a_1 to nth fuse unit regions 262a_n, offset information conforming to a corresponding programming method may be stored. For example, in the first fuse unit region 262a_1, offset information conforming to a first programming method may be stored. The number of fuse unit regions included in the electronic fuse circuit 260a may vary depending on the number of programming methods supported by the storage device 200a.

[0121] According to an embodiment of the present invention, the coarse-fine verification control module 232a can generate a fuse address F_ADD based on a programming method applied to the second-step programming operation, and can provide the fuse address F_ADD to the electronic fuse circuit 260a. One of the first fuse cell regions 262a_1 to the nth fuse cell region 262a_n can be activated in response to the fuse address F_ADD, and can generate a development control signal DT_CS for controlling the development interval of the second-step programming operation. The electronic fuse circuit 260a can provide the development control signal DT_CS to the page buffer circuit 220a, and can control the connection of the read nodes such that the length difference between the coarse verification interval and the fine verification interval varies according to the characteristics of the target threshold voltage distribution. In addition, the control logic 230a can provide a voltage control signal CS_vol_a to the voltage generator 240a, such that the voltage generator 240a generates a coarse verification voltage V_c and a fine verification voltage V_f that conform to the coarse verification operation and the fine verification operation using the electronic fuse circuit 260a. In the following, Figure 12B In this paper, assuming that the programming method corresponding to the first fuse unit region 262a_1 is a four-level unit, the first fuse unit region 262a_1 included in the electronic fuse circuit 260a is described in detail.

[0122] Reference Figure 12BThe electronic fuse circuit 260a may include a control circuit 264a and a first fuse unit region 262a_1. The first fuse unit region 262a_1 may include first fuse units 262a_11 to fifteenth fuse units 262a_115. In the first fuse units 262a_11 to fifteenth fuse units 262a_115, offsets for forming a first target threshold voltage distribution to a fifteenth target threshold voltage distribution may be stored respectively. For example, a first offset for forming a first target threshold voltage distribution may be stored in the first fuse unit 262a_11, and a second offset for forming a second target threshold voltage distribution may be stored in the second fuse unit 262a_12. The control circuit 264a may generate an enable signal EN in response to the fuse address F_ADD for selectively activating one of the first fuse units 262a_11 to fifteenth fuse units 262a_15. When the first fuse unit 262a_11 to the fifteenth fuse unit 262a_15 are activated, the first fuse unit 262a_11 to the fifteenth fuse unit 262a_15 can output the first development control signal DT_CS1 to the fifteenth development control signal DT_CS15 respectively.

[0123] use Figure 12A and Figure 12B The electronic fuse circuit 260a shown for controlling the development interval is merely an example. The inventive concept is not limited thereto, and various embodiments for controlling the development interval can be applied to the storage device 200a.

[0124] Figure 13 This is a block diagram illustrating another implementation example of a storage device 200b performing a second-step programming operation according to an embodiment of the present invention. In the following text, previous references may be omitted for convenience. Figure 1 Description of repeating elements. Figure 13 The storage device 200b can execute reference Figures 11A to 11C The described operation.

[0125] Reference Figure 13 The storage cell array 210b may include a redundant cell region 212b. In the redundant cell region 212b, offset information according to embodiments of the present invention may be stored. Control logic 230b may receive the offset information OS_I from the redundant cell region 212b via page buffer circuit 220b. Control logic 230b may generate a voltage control signal CS_vol_b based on the offset information OS_I. Voltage generator 240b may, in response to the voltage control signal CS_vol_b, generate a coarse verification voltage V_c and a fine verification voltage V_f having a level difference based on the characteristics of a target threshold voltage distribution. Figure 13 The coarse-fine verification control module 232b and the address decoder 250b are also shown.

[0126] Figure 14 This is a flowchart illustrating a method for operating a storage device according to an embodiment of the present invention.

[0127] Reference Figure 14 In operation S200, the storage device can perform a first-step programming operation. In operation S220, taking into account the operating conditions of the storage device, the storage device can perform a second-step programming operation by using a coarse verification voltage and a fine verification voltage that conform to the characteristics of the target threshold voltage distribution. The operating conditions of the storage device may include the temperature conditions, interference conditions, noise conditions, and program / erase (P / E) cycle conditions under which the storage device is currently performing the storage operation. The characteristics of the storage cells can change according to the operating conditions of the storage device, thereby changing the characteristics of the aforementioned target threshold voltage distribution. According to an embodiment of the present invention, the storage device updates offset information based on its operating conditions to adapt to changes in the characteristics of the current target threshold voltage distribution, and can perform the second-step programming operation based on the updated offset information.

[0128] Figure 15 This is a flowchart illustrating a method for operating a storage system according to an embodiment of the present invention.

[0129] Reference Figure 15 The storage system may include a storage controller 310 and a storage device 320. The storage controller 310 may periodically or non-periodically monitor the operating conditions of the storage device 320, generate operating condition information based on the monitoring results, and update the operating condition information. In operation S300, the storage controller 310 may send the operating condition information to the storage device 320. In operation S310, the storage device 320 may update offset information based on the operating condition information. In operation S320, the storage controller 310 may send a programming command to the storage device 320. In operation S330, the storage device 320 may, in response to the programming command, use the updated offset information to perform a programming operation including a first-step programming operation and a second-step programming operation.

[0130] Figure 16 It is shown in Figure 15 The flowchart shows the operation of the storage device in operation S310 updating the offset information based on the P / E cycle information. Figure 17A and Figure 17B This is a diagram illustrating the operation of updating offset information based on the P / E cycle of the storage device.

[0131] Reference Figure 16In operation S311, the storage device can receive P / E cycle information representing its P / E cycle from the storage controller. In some embodiments of the present invention, the storage device can directly manage the P / E cycle information. In this case, the P / E cycle information stored in the storage device can be read. In operation S312, the storage device can determine whether the P / E cycle exceeds a threshold. If it is determined in operation S312 that the P / E cycle does not exceed the threshold, operation S311 can then be executed. If it is determined in operation S312 that the P / E cycle exceeds the threshold, operation S313 can then be executed, allowing the storage device to update the offset information.

[0132] refer to Figure 17A When the memory device reaches the first P / E cycle (P / E Cycle 1), the memory cells of the memory device can have a first threshold voltage distribution D1, and when the memory device reaches the second P / E cycle (P / E Cycle 2), the memory cells of the memory device can have a second threshold voltage distribution D2. For example... Figure 17A As shown, the cell speed of the memory cell in the memory device increases with the increase of the P / E cycle; however, this is merely an example. In some embodiments of the present invention, the cell speed of the memory cell in the memory device may decrease with the increase of the P / E cycle.

[0133] refer to Figure 17B Assuming the conditions of the first P / E cycle (P / E Cycle1), a first offset os11 between the coarse verification voltage V_c11 and the fine verification voltage V_f11 used to form the first target threshold voltage distribution P1 from the first approximate threshold voltage distribution P1_1, and a method for forming the first target threshold voltage distribution P1 from the first approximate threshold voltage distribution P1_1, can be used. Figure 6A The first approximate threshold voltage distribution P1_1 forms a second offset os12 between the coarse verification voltage V_c12 and the fine verification voltage V_n2 of the second target threshold voltage distribution P2. Under the condition of the second P / E cycle P / E cycle 2, the storage device updates the first offset os11 and the second offset os12 to be greater than the previous offset, and the first target threshold voltage distribution P1 and the second target threshold voltage distribution P2 can be formed by using the updated first offset os11′ and second offset os12′. Figure 17B These are merely illustrative embodiments. The inventive concept is not limited thereto, and the offset can be updated in various ways. As described above, the storage device can form an optimal target threshold voltage distribution during programming operations by updating the offset information according to changes in the characteristics of the storage cells.

[0134] Figure 18 This is a block diagram illustrating a storage system 400 according to an embodiment of the present invention. In the following text, previous references may be omitted. Figure 1 Description of repeating elements.

[0135] Reference Figure 18 The storage system 400 may include a storage controller 410 and a storage device 420. The storage controller 410 may, in response to read / write requests from a host, control the storage device 420 to read data items stored in or write data to the storage device 420. For example, the storage controller 410 may control programming, write, read, and erase operations on the storage device 420 by providing commands CMD, address ADD, and control signals CTRL to the storage device 420. Furthermore, data to be written (DATA) and data to be read (DATA) may be sent and received between the storage controller 410 and the storage device 420. The storage device 420 may include a storage cell array 421 and control logic 423.

[0136] According to an embodiment of the present invention, the memory controller 410 may include a coarse-fine verification control module 412, and the coarse-fine verification control module 412 may control the second-step programming operation of the memory device 420 by taking into account the characteristics of the target threshold voltage distribution. (See reference...) Figures 1 to 17B The embodiments of the inventive concept described herein can be applied to the coarse-fine verification control module 412.

[0137] Figure 19 This is a block diagram illustrating a solid-state drive (SSD) system 430 according to an embodiment of the present invention.

[0138] refer to Figure 19 The SSD system 430 may include a host 431 and an SSD 432. The SSD 432 can send signals to and receive signals from the host 431 via a signal connector, and can receive power via a power connector. The SSD 432 may include an SSD controller 433, an auxiliary power supply 434, and first storage devices 435_1 to s-th storage devices 435_s. (Reference) Figures 1 to 18 The described embodiments can be applied to first storage devices 435_1 to s-th storage devices 435_s. First storage devices 435_1 to s-th storage devices 435_s can respectively store first offset information items OS_Info.1 to s-th offset information items OS_Info.s. First storage devices 435_1 to s-th storage devices 435_s can perform a second-step programming operation using the first offset information items OS_Info.1 to s-th offset information items OS_Info.s. Host 431 and SSD 432 can communicate with each other via signal line SGL, and host 431 can supply power to the SSD via power line PWR. First storage devices 435_1 to s-th storage devices 435_s can be coupled to SSD controller 433 via multiple channels Ch1 to CHs. Figure 20This is a diagram illustrating a chip-to-chip (C2C) structure applied to a memory device 1000 according to an exemplary embodiment of the present invention. The memory device 1000 is... Figure 1 The implementation of the storage device 100.

[0139] Reference Figure 20 The memory device 1000 may have a chip-to-chip (C2C) structure. In a C2C structure, after an upper chip including cell regions (CELL) is fabricated on a first wafer and a lower chip including peripheral circuit regions (PERI) is fabricated on a second wafer different from the first wafer, the upper and lower chips are connected to each other by a bonding method. For example, in the bonding method, a bonding metal formed in the uppermost metal layer of the upper chip is electrically connected to a bonding metal formed in the uppermost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may include aluminum (Al) or tungsten (W).

[0140] Each of the peripheral circuit region PERI and cell region CELL of the storage device 1000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0141] The Peripheral Circuit Area (PERI) may include a first substrate 510, an interlayer insulating layer 515, a plurality of circuit elements 520a, 520b, and 520c formed on the first substrate 510, first metal layers 530a, 530b, and 530c respectively connected to the plurality of circuit elements 520a, 520b, and 520c, and second metal layers 540a, 540b, and 540c formed on the first metal layers 530a, 530b, and 530c. In embodiments of the present invention, the first metal layers 530a, 530b, and 530c may include W with high resistance, and the second metal layers 540a, 540b, and 540c may include Cu with low resistance.

[0142] exist Figure 20 Only the first metal layers 530a, 530b, and 530c and the second metal layers 540a, 540b, and 540c are shown and described. However, the inventive concept is not limited thereto, and at least one metal layer may further be formed on the second metal layers 540a, 540b, and 540c. At least a portion of at least one metal layer formed on the second metal layers 540a, 540b, and 540c may include Al, which has a lower resistivity than Cu contained in the second metal layers 540a, 540b, and 540c.

[0143] The interlayer insulating layer 515 may be disposed on the first substrate 510 to cover a plurality of circuit elements 520a, 520b and 520c, first metal layers 530a, 530b and 530c and second metal layers 540a, 540b and 540c, and may include an insulating material, such as silicon oxide or silicon nitride.

[0144] Lower bonding metals 571b and 572b may be formed on the second metal layer 540b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 571b and 572b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 671b and 672b of the cell region CELL by bonding method, and the lower bonding metals 571b and 572b and the upper bonding metals 671b and 672b may include Al, Cu or W.

[0145] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 610 and a common source line 620. Multiple word lines 631, 632, 633, 634, 635, 636, 637, and 638 (630) may be stacked on the second substrate 610 in a direction perpendicular to the upper surface of the second substrate 610 (Z-axis direction). A serial select line may be arranged on the multiple word lines 631 to 638, a ground select line may be arranged below the multiple word lines 631 to 638, and the multiple word lines 631 to 638 may be arranged between the serial select line and the ground select line.

[0146] In the bit line bonding region BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 610 and can pass through multiple word lines 631 to 638, a serial select line, and a ground select line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 650c and the second metal layer 660c. For example, the first metal layer 650c may be a bit line contact, and the second metal layer 660c may be a bit line. In an embodiment of the present invention, the second metal layer 660c may extend in a first direction (Y direction) parallel to the upper surface of the second substrate 610.

[0147] exist Figure 20In the illustrated embodiment, the region where the channel structure CH and the second metal layer 660c are arranged can be referred to as the bit line bonding region BLBA. The second metal layer 660c in the bit line bonding region BLBA can be electrically connected to the circuit elements 520c included in the page buffer 693 in the peripheral circuit region PERI. For example, the second metal layer 660c can be connected to the upper bonding metals 671c and 672c in the peripheral circuit region PERI, and the upper bonding metals 671c and 672c can be connected to the lower bonding metals 571c and 572c connected to the circuit elements 520c of the page buffer 693.

[0148] In the word line bonding area (WLBA), multiple word lines 631 to 637 may extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate 610 and may be connected to multiple cell contact plugs 641, 642, 643, 644, 645, 646, and 647 (640). The multiple word lines 631 to 637 may be connected to the multiple cell contact plugs 641 to 647 via pads, wherein at least some of the multiple word lines 631 to 637 extend at different lengths. A first metal layer 650b and a second metal layer 660b may be sequentially connected to the multiple cell contact plugs 641 to 647 connected to the multiple word lines 631 to 637. In the word line bonding area (WLBA), the multiple cell contact plugs 641 to 647 may be connected to the peripheral circuit region PERI via upper bonding metals 671b and 672b of the cell region CELL and lower bonding metals 571b and 572b of the peripheral circuit region PERI.

[0149] Multiple unit contact plugs 641 to 647 can be electrically connected to circuit elements 520b included in the line decoder 694 in the peripheral circuitry region (PERI). In embodiments of the present invention, the operating voltage of the circuit elements 520b included in the line decoder 694 may differ from the operating voltage of the circuit elements 520c included in the page buffer 693. For example, the operating voltage of the circuit elements 520c included in the page buffer 693 may be greater than the operating voltage of the circuit elements 520b included in the line decoder 694.

[0150] In the external pad bonding region PA, a common source line contact plug 680 may be disposed. The common source line contact plug 680 may comprise a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to a common source line 620. A first metal layer 650a and a second metal layer 660a may be sequentially stacked on the common source line contact plug 680. For example, the region in which the common source line contact plug 680, the first metal layer 650a, and the second metal layer 660a are disposed may be referred to as the external pad bonding region PA.

[0151] Furthermore, the first input / output pad 505 and the second input / output pad 605 can be arranged in the external pad bonding area PA. A lower insulating layer 501 covering the lower surface of the first substrate 510 can be formed below the first substrate 510, and the first input / output pad 505 can be formed on the lower insulating layer 501. The first input / output pad 505 can be connected to at least one of a plurality of circuit elements 520a, 520b, and 520c arranged in the peripheral circuit area PERI via a first input / output contact plug 503, and can be separated from the first substrate 510 via the lower insulating layer 501. In addition, a side insulating layer can be provided between the first input / output contact plug 503 and the first substrate 510 to electrically isolate the first input / output contact plug 503 from the first substrate 510.

[0152] An upper insulating layer 601 covering the upper surface of the second substrate 610 can be formed on the second substrate 610, and second input / output pads 605 can be arranged on the upper insulating layer 601. The second input / output pads 605 can be connected to at least one of a plurality of circuit elements 520a, 520b and 520c arranged in the peripheral circuit region PERI via second input / output contact plugs 603.

[0153] According to an embodiment of the present invention, the second substrate 610 and the common source line 620 may not be disposed in the region where the second input / output contact plug 603 is arranged. Furthermore, the second input / output pad 605 may not overlap with the multiple word lines 631 to 638 in the third direction (Z-axis direction). The multiple word lines 631 to 638 may be separated from the second substrate 610 in a direction perpendicular to the upper surface of the second substrate 610, and may be connected to the second input / output pad 605 through the interlayer insulating layer 615 of the cell region.

[0154] According to embodiments of the present invention, the first input / output pad 505 and the second input / output pad 605 can be selectively formed. For example, the storage device 1000 may include only the first input / output pad 505 disposed on the first substrate 501, or the second input / output pad 605 disposed on the second substrate 601. Alternatively, the storage device 1000 may include both the first input / output pad 505 and the second input / output pad 605.

[0155] In the outer pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, a metal pattern of the top metal layer is provided as a dummy pattern, or the top metal layer may be empty.

[0156] In the external pad bonding area PA of the storage device 1000, in order to correspond to the upper metal pattern 672a formed in the uppermost metal layer of the cell region CELL, a lower metal pattern 573a with the same form as the upper metal pattern 672a of the cell region CELL can be formed in the uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 573a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to the additional contacts in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, in order to correspond to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI, an upper metal pattern with the same form as the lower metal pattern of the peripheral circuit region PERI can be formed in the upper metal layer of the cell region CELL.

[0157] Lower bonding metals 571b and 572b can be formed on the second metal layer 540b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 571b and 572b of the peripheral circuit area PERI can be electrically connected to the upper bonding metals 671b and 672b of the cell area CELL.

[0158] Furthermore, in the bit line bonding region BLBA, in order to correspond to the lower metal pattern 552 formed in the uppermost metal layer of the peripheral circuit region PERI, an upper metal pattern 692 with the same form as the lower metal pattern 552 of the peripheral circuit region PERI can be formed in the uppermost metal layer of the cell region CELL. No contact portion may be formed on the upper metal pattern 692 formed in the uppermost metal layer of the cell region CELL.

[0159] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a storage device, the method comprising: Perform a first programming operation to form multiple first threshold voltage distributions; as well as Based on offset information, a second programming operation is performed using coarse and fine verification voltages to form multiple second threshold voltage distributions corresponding to multiple programming states from the multiple first threshold voltage distributions, wherein the offset information includes multiple offsets that vary according to the characteristics of the second threshold voltage distributions. The plurality of programming states include a first programming state and a second programming state. The plurality of second threshold voltage distributions include a first target threshold voltage distribution corresponding to the first programming state and a second target threshold voltage distribution corresponding to the second programming state. The plurality of offsets includes a first offset between the coarse verification voltage and the fine verification voltage for forming the first target threshold voltage distribution, and a second offset between the coarse verification voltage and the fine verification voltage for forming the second target threshold voltage distribution. In the second programming operation, the estimated threshold voltage increase of the second target threshold voltage distribution is greater than the estimated threshold voltage increase of the first target threshold voltage distribution, and Wherein, the second offset is greater than the first offset.

2. The method according to claim 1, wherein, The characteristics of the second threshold voltage distribution are related to the increase of the estimated threshold voltage from the plurality of first threshold voltage distributions, respectively, corresponding to the plurality of second threshold voltage distributions in the second programming operation.

3. The method according to claim 1, wherein, The plurality of offsets are related to at least one of a level difference and a length difference, wherein the level difference is the level difference between the coarse verification voltage and the fine verification voltage, and the length difference is the length difference between a first development interval using the coarse verification voltage and a second development interval using the fine verification voltage.

4. The method according to claim 1, wherein, The first offset includes a first level difference between the coarse verification voltage and the fine verification voltage used to form the first target threshold voltage distribution. Wherein, the second offset includes a second level difference between the coarse verification voltage and the fine verification voltage used to form the second target threshold voltage distribution, and Wherein, the second level difference is greater than the first level difference.

5. The method according to claim 1, wherein, The first offset includes a first length difference between the development interval of the coarse verification voltage and the fine verification voltage used to form the first target threshold voltage distribution. Wherein, the second offset includes a second length difference between the development interval of the coarse verification voltage and the fine verification voltage used to form the second target threshold voltage distribution, and Wherein, the second length difference is greater than the first length difference.

6. The method according to claim 1, wherein, The number of first threshold voltage distributions is less than the number of second threshold voltage distributions.

7. The method according to claim 1, wherein, The storage device includes multiple storage cells, which are to be subjected to the first programming operation and the second programming operation. Each of the plurality of storage cells corresponds to at least one of a dual-level cell, a tri-level cell, and a quad-level cell.

8. The method according to claim 1, wherein, The first programming operation and the second programming operation are based on one of the shadow programming method, the sun-who programming method, and the high-speed programming method.

9. The method according to claim 1, further comprising: Receive the operating condition information of the storage device from the storage controller; as well as The offset information is updated based on the operating condition information of the storage device.

10. A storage device comprising: A storage cell array, comprising multiple storage cells; as well as The control logic controls a first programming operation on the plurality of memory cells to form a plurality of first threshold voltage distributions, and controls a second programming operation on the plurality of memory cells to form a plurality of second threshold voltage distributions corresponding to a plurality of programming states. The control logic controls the second programming operation by using multiple offsets between a coarse verification voltage and a fine verification voltage, wherein these offsets vary according to the characteristics of the second threshold voltage distribution. The plurality of programming states include a first programming state and a second programming state. The plurality of second threshold voltage distributions include a first target threshold voltage distribution corresponding to the first programming state and a second target threshold voltage distribution corresponding to the second programming state. The plurality of offsets includes a first offset between the coarse verification voltage and the fine verification voltage for forming the first target threshold voltage distribution, and a second offset between the coarse verification voltage and the fine verification voltage for forming the second target threshold voltage distribution. In the second programming operation, the estimated threshold voltage increase of the second target threshold voltage distribution is greater than the estimated threshold voltage increase of the first target threshold voltage distribution, and Wherein, the second offset is greater than the first offset.

11. The storage device according to claim 10, wherein, The characteristics of the second threshold voltage distribution are related to the estimated distribution rate of the plurality of second threshold voltage distributions in the second programming operation.

12. The storage device according to claim 11, wherein, The second target threshold voltage distribution has a higher distribution velocity than the first target threshold voltage distribution.

13. The storage device according to claim 10, wherein, The multiple offsets are related to the level difference between the coarse verification voltage and the fine verification voltage. The storage device further includes a voltage generator for generating the coarse verification voltage and the fine verification voltage, and The control logic controls the voltage generator based on the characteristics of the second threshold voltage distribution to control the level difference.

14. The storage device of claim 10, further comprising: Page buffer circuitry includes multiple read nodes connected to the memory cell array via multiple bit lines; as well as The electronic fuse circuit controls the first and second development intervals of the plurality of readout nodes. At least one of the plurality of offsets is related to the length difference between a first development interval using the coarse verification voltage and a second development interval using the fine verification voltage.

15. The storage device according to claim 14, wherein, The electronic fuse circuit includes a plurality of fuse unit regions that are selectively activated in the second programming operation, and information about the length difference used to form the plurality of second threshold voltage distributions is stored in the plurality of fuse unit regions.

16. The storage device according to claim 10, wherein, The storage cell array also includes redundant cell regions for storing the plurality of offsets.

17. A storage system, comprising: Multiple storage devices; as well as The storage controller controls the operation of the plurality of storage devices. Each of the plurality of storage devices forms a plurality of first threshold voltage distributions by performing a first-step programming operation in response to a programming command from the storage controller, and forms a plurality of second threshold voltage distributions corresponding to a plurality of programming states by performing a second-step programming operation using coarse verification voltages and fine verification voltages, wherein the coarse verification voltages and the fine verification voltages have different offsets according to the characteristics of the second threshold voltage distributions. The plurality of programming states include a first programming state and a second programming state. The plurality of second threshold voltage distributions include a first target threshold voltage distribution corresponding to the first programming state and a second target threshold voltage distribution corresponding to the second programming state. The plurality of offsets includes a first offset between the coarse verification voltage and the fine verification voltage for forming the first target threshold voltage distribution, and a second offset between the coarse verification voltage and the fine verification voltage for forming the second target threshold voltage distribution. In the second programming step, the estimated threshold voltage increase of the second target threshold voltage distribution is greater than the estimated threshold voltage increase of the first target threshold voltage distribution. Wherein, the second offset is greater than the first offset.

18. The storage system according to claim 17, wherein, Each of the plurality of storage devices stores offset information related to the offset of the plurality of storage cells included in the storage device, and performs the second step programming operation based on the offset information.

Images