Capacitor and method of manufacturing the same

Abstract

A capacitor preparation method comprises: providing a substrate, stacking a first sacrificial layer, an intermediate support layer and a second sacrificial layer on the substrate; forming a lower electrode, the lower electrode penetrating through the second sacrificial layer, the intermediate support layer and the first sacrificial layer, and the lower electrode being electrically connected with a conductive pad in the substrate; forming a top support layer on the second sacrificial layer and the top surface of the lower electrode; patterning the top support layer and removing the second sacrificial layer; patterning the intermediate support layer and removing the first sacrificial layer; forming a dielectric layer, the dielectric layer covering the substrate, the exposed surface of the lower electrode, the exposed surface of the intermediate support layer and the exposed surface of the top support layer; and forming an upper electrode, the upper electrode covering the surface of the dielectric layer. The preparation method can form the top support layer covering only the top surface of the lower electrode, the side surface of the lower electrode is not covered by the top support layer, the area of the exposed area of the lower electrode is increased, the storage capacitance of the capacitor is increased, the capacitor can be maintained to be not inclined, and the user demand is met.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a capacitor and a method for its fabrication. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. In DRAM manufacturing processes below 20nm, DRAM mostly adopts a stacked capacitor structure, where the capacitors are vertical cylindrical capacitors with a high aspect ratio.

[0003] Because cylindrical capacitors have a high aspect ratio, at least two support layers are usually required to increase their stability. However, this design reduces the capacitor's storage capacity to some extent, making it unable to meet the demand. Summary of the Invention

[0004] This disclosure provides a capacitor and a method for manufacturing the same, which can improve the storage capacity of the capacitor.

[0005] This disclosure provides a method for fabricating a capacitor, the method comprising: providing a substrate, wherein a first sacrificial layer, an intermediate support layer, and a second sacrificial layer are stacked on the substrate; forming a lower electrode, the lower electrode penetrating the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, the lower electrode being electrically connected to a conductive pad within the substrate; forming a top support layer on the top surface of the second sacrificial layer and the lower electrode; patterning the top support layer and removing the second sacrificial layer; patterning the intermediate support layer and removing the first sacrificial layer; forming a dielectric layer covering the substrate, the lower electrode, the exposed surfaces of the intermediate support layer, and the exposed surfaces of the top support layer; and forming an upper electrode covering the surface of the dielectric layer.

[0006] In one embodiment, the method for forming the first sacrificial layer includes the following steps: forming a first material layer on the substrate, wherein a first type of dopant in the first material layer has a first doping concentration; forming a second material layer on the first material layer, wherein a first type of dopant in the second material layer has a second doping concentration, the second doping concentration being greater than the first doping concentration.

[0007] In one embodiment, the first type of dopant includes boron.

[0008] In one embodiment, the first doping concentration is 2-7%, and the second doping concentration is 5-10%.

[0009] In one embodiment, both the first material layer and the second material layer are phosphorus-doped silicate glasses, wherein the phosphorus doping concentration in the silicate glass is 3-5%.

[0010] In one embodiment, the method of forming the lower electrode further includes: forming a capacitor hole that penetrates the second sacrificial layer, the intermediate support layer and the first sacrificial layer and exposes a conductive pad in the substrate; and forming the lower electrode in the capacitor hole.

[0011] In one embodiment, the top surface of the lower electrode is flush with the surface of the second sacrificial layer.

[0012] In one embodiment, the second sacrificial layer includes a first sublayer disposed on the surface of the intermediate support layer and a second sublayer disposed on the surface of the first sublayer. During the step of patterning the top support layer, the second sublayer is patterned simultaneously, and a portion of the first sublayer is exposed.

[0013] In one embodiment, the thickness of the second sub-layer is less than or equal to the thickness of the top support layer, and the second sub-layer and the top support layer are made of the same material.

[0014] In one embodiment, the density of the second sublayer is less than the density of the top support layer.

[0015] In one embodiment, the film-forming temperature of the second sub-layer is lower than that of the top support layer and the intermediate support layer.

[0016] In one embodiment, the step of patterning the top support layer and removing the second sacrificial layer further includes the steps of: patterning the top support layer to form a first opening; and removing the second sacrificial layer along the first opening to expose the intermediate support layer.

[0017] In one embodiment, in the step of removing the second sacrificial layer along the first opening to expose the intermediate support layer, the first sub-layer is removed, the second sub-layer and the top support layer are partially removed, and in the step of removing the second sacrificial layer, the remaining second sub-layer is completely removed.

[0018] In one embodiment, after the steps of patterning the intermediate support layer and removing the first sacrificial layer, the thickness of the remaining top support layer is 1 nm to 10 nm.

[0019] In one embodiment, the step of patterning the intermediate support layer and removing the first sacrificial layer further includes: patterning the intermediate support layer to form a second opening; and removing the first sacrificial layer along the second opening to expose the conductive pad of the substrate.

[0020] In one embodiment, the step of patterning the intermediate support layer to form the second opening further includes: removing a portion of the first sacrificial layer when forming the second opening.

[0021] In one embodiment, the thickness of the removed portion of the first sacrificial layer is 1 nm to 10 nm.

[0022] In one embodiment, the method further includes the following steps: forming a bottom support layer, the top surface of which is flush with the top surface of the conductive pad; and forming a first sacrificial layer, an intermediate support layer, and a second sacrificial layer on the bottom support layer and the conductive pad.

[0023] Another aspect of this disclosure provides a capacitor, the capacitor comprising: a substrate, wherein a conductive pad is disposed within the substrate; an intermediate support layer disposed at a predetermined distance above the substrate; a top support layer disposed at a predetermined distance above the intermediate support layer; a lower electrode disposed on the substrate and electrically connected to the conductive pad within the substrate, the lower electrode penetrating the intermediate support layer, and the top support layer disposed on the top surface of the lower electrode; a dielectric layer covering the surfaces of the lower electrode, the intermediate support layer, and the top support layer; and an upper electrode covering the surface of the dielectric layer.

[0024] In one embodiment, the thickness of the top support layer is 1 nm to 10 nm.

[0025] In one embodiment, the capacitor further includes a bottom support layer located within the substrate, wherein the top surface of the bottom support layer is flush with the top surface of the conductive pad.

[0026] The capacitor manufacturing method provided in this disclosure can form a top support layer that only covers the top surface of the lower electrode, while the side surface of the lower electrode is not covered by the top support layer. This increases the area of ​​the exposed region of the lower electrode, thereby increasing the storage capacity of the capacitor, and can keep the capacitor from tilting, thus meeting user requirements. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the steps in the method for preparing a capacitor according to the first embodiment of this disclosure;

[0029] Figures 2A to 2GThis is a cross-sectional schematic diagram of the semiconductor structure corresponding to the main process for forming a capacitor provided in the first embodiment of the present invention;

[0030] Figures 3A to 3D This is a cross-sectional schematic diagram of the semiconductor structure corresponding to the main process for forming a capacitor provided in the second embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical means, and effects of this disclosure clearer, the following description, in conjunction with the accompanying drawings, will further elaborate on this disclosure. It should be understood that the embodiments described herein are merely some embodiments of this disclosure, not all embodiments, and are not intended to limit this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0032] Figure 1 This is a schematic diagram of the steps in the method for manufacturing a capacitor according to the first embodiment of this disclosure. Please refer to [link / reference]. Figure 1 The fabrication method includes: step S10, providing a substrate, and stacking a first sacrificial layer, an intermediate support layer, and a second sacrificial layer on the substrate; step S11, forming a lower electrode, the lower electrode penetrating the second sacrificial layer, the intermediate support layer, and the first sacrificial layer, and the lower electrode being electrically connected to a conductive pad in the substrate; step S12, forming a top support layer on the top surface of the second sacrificial layer and the lower electrode; step S13, patterning the top support layer and removing the second sacrificial layer; step S14, patterning the intermediate support layer and removing the first sacrificial layer; step S15, forming a dielectric layer, the dielectric layer covering the substrate, the lower electrode, the exposed surfaces of the intermediate support layer, and the exposed surfaces of the top support layer; and step S16, forming an upper electrode, the upper electrode covering the surface of the dielectric layer.

[0033] Figures 2A to 2G This is a cross-sectional schematic diagram of the semiconductor structure corresponding to the main process for forming a capacitor provided in the first embodiment of the present invention.

[0034] Please refer to step S10 and Figure 2A A substrate 200 is provided, on which a first sacrificial layer 210, an intermediate support layer 220 and a second sacrificial layer 230 are stacked.

[0035] The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 200 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 200 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 200 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the substrate 200. In this embodiment, the substrate 200 is a silicon substrate, which also includes other device structures, such as bit line structures and transistor structures, but these are not shown as they are not relevant to this invention.

[0036] A conductive pad 201 is disposed within the substrate 200, and the conductive pad 201 can serve as an electrical connection pad for capacitors and other device structures.

[0037] As an example, in this embodiment, the first sacrificial layer 210 is a two-layer structure composed of a first material layer 211 and a second material layer 212. This embodiment also provides a method for forming the first sacrificial layer 210. The method includes the following steps:

[0038] A first material layer 211 is formed on the substrate 200. The first material layer 211 has a first type of dopant with a first doping concentration. In this step, the first material layer 211 can be formed using processes such as spin coating or chemical vapor deposition. In this embodiment, the first material layer 211 is doped silicate glass, the first type of dopant is boron, and the boron has a first doping concentration. As an example, the first doping concentration is 2-7%. As an example, in addition to boron, the first material layer 211 is also doped with phosphorus, with a phosphorus doping concentration of 3-5%.

[0039] A second material layer 212 is formed on the first material layer 211. The second material layer 212 has a first type of dopant, and the first type of dopant has a second doping concentration. In this step, the second material layer 212 can be formed by processes such as spin coating or chemical vapor deposition. In this embodiment, the second material layer 212 is a doped silicate glass, the first type of dopant is boron, and the boron has a second doping concentration. As an example, the second doping concentration is 5-10%. As an example, the second material layer 212 is doped with phosphorus in addition to boron, and the phosphorus doping concentration is 3-5%. In this embodiment, the phosphorus doping concentrations in the first material layer 211 and the second material layer 212 are the same; in other embodiments, the phosphorus doping concentrations in the first material layer 211 and the second material layer 212 may be different.

[0040] Wherein, the second doping concentration is greater than the first doping concentration, that is, the doping concentration of the first material layer 211 (the lower layer of the first sacrificial layer 210) is less than the doping concentration of the second material layer 212 (the upper layer of the first sacrificial layer 210), so that the etching rate of the first material layer 211 is greater than the etching rate of the second material layer 212. Then, when the etching process to remove the first sacrificial layer 210 is subsequently performed, the first material layer 211 located on the lower layer is easily removed due to its high etching rate, which greatly reduces the residual amount of the first material layer 211, that is, greatly reduces the residual amount of the first sacrificial layer 210.

[0041] The above is only one example of the first sacrificial layer 210. In other embodiments of this disclosure, the first sacrificial layer 210 may also be a phosphosilicate glass with uniform boron doping concentration, or silicon oxide.

[0042] The intermediate support layer 220 can be made of silicon nitride (SiN) or silicon carbon nitride (SiCN). As an example, this embodiment also provides a method for forming the intermediate support layer 220, the method comprising: using NH3 and SIH4 as the main reactant gases, and mixing them with a silicon-containing substance or trimethylsilane to form a silicon nitride layer or a silicon carbon nitride layer. The film-forming temperature of the intermediate support layer 220 is between 500°C and 550°C. The intermediate support layer 220 formed at this temperature has a higher density, improving the support strength of the intermediate support layer 220 for the subsequently formed capacitor and further preventing capacitor tilting. In this embodiment, the density of the formed intermediate support layer 220 can be adjusted by adjusting the flow rate of the silicon-containing substance or trimethylsilane.

[0043] The second sacrificial layer 230 may be an oxide (OX), such as silicon oxide. As an example, this embodiment also provides a method for forming the second sacrificial layer 230, the method comprising: depositing tetraethyl orthosilicate (TEOS) on an intermediate support layer 220 to form the second sacrificial layer 230. The process for depositing tetraethyl orthosilicate includes high-density plasma chemical vapor deposition, atomic layer deposition, furnace tube deposition, etc., and the deposition temperature may be 300℃-630℃.

[0044] In this embodiment, a bottom support layer 202 is further disposed within the substrate 200, the bottom support layer 202 exposing the conductive pad 201, and the first sacrificial layer 210 covering the bottom support layer 202 and the conductive pad 201. In some embodiments, the top surface of the bottom support layer 202 is flush with the top surface of the conductive pad 201, thereby preventing the bottom support layer 202 from obscuring the conductive pad 201, increasing the contact area between the lower electrode formed in subsequent processes and the conductive pad 201, and improving electrical contact performance. In this embodiment, the bottom support layer 202 and the intermediate support layer 220 are made of the same material, for example, both are nitride layers, such as silicon nitride carbon layers. The formation process of the bottom support layer 202 is the same as the formation process of the intermediate support layer.

[0045] It is understandable that the first sacrificial layer 210 and the second sacrificial layer 230 can be formed of materials that are etch-selective relative to the intermediate support layer 220 and can be easily removed by a wet etching process. This avoids the first sacrificial layer 210 and the second sacrificial layer 230 from being left behind during the subsequent removal process, and also avoids the intermediate support layer 220 from being significantly thinned, which would affect the support strength of the intermediate support layer 220.

[0046] Please refer to step S11 and Figure 2B A lower electrode 240 is formed, which penetrates the second sacrificial layer 230, the intermediate support layer 220 and the first sacrificial layer 210, and is electrically connected to the conductive pad 201 in the substrate 200.

[0047] As an example, this embodiment provides a method for forming the lower electrode 240, the method comprising the following steps:

[0048] A capacitor hole (not shown in the accompanying drawings) is formed, which penetrates the second sacrificial layer 230, the intermediate support layer 220, and the first sacrificial layer 210, and exposes the conductive pad 201 within the substrate 200. In this step, photolithography and etching processes can be used to form the capacitor hole.

[0049] The lower electrode 240 is formed in the capacitor hole. As an example, this step specifically includes the following steps: filling the capacitor hole with a conductive material, which not only fills the capacitor hole but also covers the surface of the second sacrificial layer 230. The conductive material can be titanium nitride or other materials suitable for serving as the lower electrode 240 of the capacitor. The conductive material is then etched back to expose the second sacrificial layer 230, and the conductive material located within the capacitor hole forms the lower electrode 240. In this embodiment, in this step, a titanium nitride etch-back process is used to etch back the conductive material, removing the conductive material from the surface of the second sacrificial layer 230 and exposing the second sacrificial layer 230.

[0050] In this embodiment, the top surface of the lower electrode 240 is flush with the surface of the second sacrificial layer 230, so the top support layer 250 formed in subsequent processes (see [link to documentation]) Figure 2C It only covers the top surface of the lower electrode 240, but not the sidewalls of the lower electrode 240, which further improves the storage capacity of the capacitor.

[0051] Please refer to step S12 and Figure 2C A top support layer 250 is formed on the top surface of the second sacrificial layer 230 and the lower electrode 240. The top support layer 250 covers the top surface of the second sacrificial layer 230 and the lower electrode 240.

[0052] The top support layer 250 can be a silicon nitride (SiN) layer or a silicon carbon nitride (SiCN) layer, as an example. This embodiment provides a method for forming the top support layer 250. The method includes: using NH3 and SIH4 as the main reactant gases, and mixing them with a silicon-containing material or trimethylsilane to form a silicon nitride layer or a silicon carbon nitride layer. The film-forming temperature of the top support layer 250 is between 500°C and 550°C. The top support layer 250 formed at this temperature has a higher density, which improves the support strength of the top support layer 250 for the subsequently formed capacitor and further prevents the capacitor from tilting. In this embodiment, the density of the formed top support layer 250 can be adjusted by adjusting the flow rate of the silicon-containing material or trimethylsilane.

[0053] In this embodiment, the forming process of the top support layer 250 is the same as that of the intermediate support layer 220. In other embodiments, the forming processes of the top support layer 250 and the intermediate support layer 220 may be different, or there may be differences in their process parameters.

[0054] Please refer to step S13 and Figure 2D The top support layer 250 is patterned, and the second sacrificial layer 230 is removed.

[0055] Specifically, in this step, the top support layer 250 is patterned to form a first opening 251; the second sacrificial layer 230 is removed along the first opening 251, exposing the intermediate support layer 220. The patterning of the top support layer 250 can be achieved through photolithography and dry etching, i.e., a patterned mask layer is formed on the top support layer 250, and a portion of the top support layer 250 is etched away using the mask layer as a shield to form a top support layer 250 with the first opening 251. After forming the first opening 251, the mask layer can be removed or retained; the mask layer provides a mask for subsequent removal of the second sacrificial layer 230. The method for removing the second sacrificial layer 230 can be a wet etching process, i.e., using the mask layer and the top support layer 250 as masks, a wet etching process is used to remove the second sacrificial layer 230. In this embodiment, after the second opening is formed, the mask layer is removed. Then, when removing the second sacrificial layer 230, the top support layer 250 is used as a mask to remove the second sacrificial layer 230. It is understood that during the removal of the second sacrificial layer 230, the top support layer 250 is also thinned. Therefore, the thickness of the top support layer 250 formed in step S12 is greater than the thickness of the final top support layer 250 of the capacitor, providing sufficient thinning allowance for subsequent steps and reducing the processing difficulty caused by insufficient thickness of the top support layer 250.

[0056] Please refer to step S14 and Figure 2E The intermediate support layer 220 is patterned, and the first sacrificial layer 210 is removed.

[0057] Specifically, in this step, the intermediate support layer 220 is patterned to form a second opening 221. The second opening 221 corresponds in position to the first opening 251. The first sacrificial layer 210 is removed along the second opening 221 to expose the substrate 200. The process for patterning the intermediate support layer 220 can be photolithography and dry etching, and the method for removing the first sacrificial layer 210 can be wet etching.

[0058] Understandably, during the step of patterning the intermediate support layer 220, the top support layer 250 is also thinned. After removing the first sacrificial layer 210, the remaining thickness of the top support layer 250 is 1 nm to 10 nm. If the thickness of the top support layer 250 is less than 1 nm, it cannot provide sufficient support for the capacitor. If the thickness of the top support layer 250 is greater than 10 nm, although the support strength is greater, it will increase the volume occupied by the capacitor and cannot meet the requirements of device miniaturization.

[0059] In this embodiment, the first sacrificial layer 210 is composed of a first material layer 211 and a second material layer 212, and the doping concentration of the first type of dopant in the first material layer 211 is less than the doping concentration of the first type of dopant in the second material layer 212, making the bottom layer of the first sacrificial layer 210 easier to remove and greatly reducing the residual amount of the first sacrificial layer 210.

[0060] In this embodiment, the bottom support layer 202 is exposed after the first sacrificial layer 210 is removed.

[0061] Please refer to step S15 and Figure 2F A dielectric layer 260 is formed, which covers the exposed surfaces of the substrate 200, the lower electrode 240, the intermediate support layer 220, and the top support layer 250. In this embodiment, due to the presence of the bottom support layer 202, the dielectric layer 260 covers the exposed surfaces of the bottom support layer 202, the lower electrode 240, the intermediate support layer 220, and the top support layer 250.

[0062] The dielectric layer 260 can be a high-k dielectric layer to improve the performance of the capacitor. For example, Al2O3, HfO2, Ta2O5, ZrO2, etc. The dielectric layer 260 can be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal-organic chemical vapor deposition (MOCVD) processes.

[0063] Please refer to step S16 and Figure 2G An upper electrode 270 is formed, which covers the surface of the dielectric layer 260.

[0064] In this embodiment, a conductive material is formed in the gaps between the bottom support layer 202, the intermediate support layer 220, and the top support layer 250, and on the surface of the top support layer 250. This conductive material serves as the upper electrode 270. It is understood that in some embodiments, the process further includes thinning and planarizing the top surface of the conductive material to make the top surface of the formed lower electrode 240 flat.

[0065] The upper electrode 270, the dielectric layer 260 and the lower electrode 240 constitute a columnar capacitor, and the multiple capacitor arrays are arranged to form a capacitor array structure.

[0066] The capacitor manufacturing method provided in this embodiment can form a top support layer 250 that only covers the top surface of the lower electrode 240, while the side surface of the lower electrode 240 is not covered by the top support layer 250. This increases the area of ​​the exposed region of the lower electrode 240, thereby increasing the storage capacity of the capacitor, and can maintain the capacitor from tilting, thus meeting user requirements.

[0067] In the first embodiment of this disclosure, the second sacrificial layer 230 is a single-layer structure, such as an oxide layer, while in other embodiments of this disclosure, the second sacrificial layer 230 may be a multilayer structure. Therefore, the second embodiment of this disclosure provides a method for fabricating a capacitor.

[0068] Please see Figure 3A A first sacrificial layer 210, an intermediate support layer 220, and a second sacrificial layer 230 are stacked on a substrate 200. A lower electrode 240 penetrates the second sacrificial layer 230, the intermediate support layer 220, and the first sacrificial layer 210. The lower electrode 240 is electrically connected to a conductive pad 201 in the substrate 200. A top support layer 250 covers the second sacrificial layer 230 and the lower electrode 240.

[0069] The second sacrificial layer 230 includes a first sub-layer 231 disposed on the surface of the intermediate support layer 220 and a second sub-layer 232 disposed on the surface of the first sub-layer 231, and the top support layer 250 covers the second sub-layer 232 and the lower electrode 240.

[0070] In this embodiment, the method for forming the first sacrificial layer 210, the intermediate support layer 220, the top support layer 250, and the lower electrode 240 is the same as in the first embodiment, and will not be described again. As an example, this embodiment provides a method for forming the second sacrificial layer 230. The method includes:

[0071] After the intermediate support layer 220 is formed and before the lower electrode 240 is formed, tetraethyl orthosilicate (TEOS) is deposited on the intermediate support layer 220 to form the first sublayer 231. The process of depositing tetraethyl orthosilicate includes high-density plasma chemical vapor deposition, atomic layer deposition, furnace tube deposition and other processes, and the deposition temperature can be 300℃-630℃.

[0072] A second sublayer 232 is formed on the first sublayer 231. The material of the second sublayer 232 may be a silicon nitride layer (SiN) or a silicon carbon nitride layer (SiCN). As an example, this embodiment also provides a method for forming the second sublayer 232, the method comprising: using NH3 and SIH4 as the main reactant gases, and mixing them with a silicon-containing material or trimethylsilane to form a silicon nitride layer or a silicon carbon nitride layer. The film-forming temperature of the second sub-layer 232 is between 300℃ and 550℃. This film-forming temperature is lower than the film-forming reaction temperatures of the intermediate support layer 220 and the top support layer 250, resulting in a lower density of the second sub-layer 232 compared to the intermediate and top support layers 220. This reduces the thinning of the intermediate and top support layers 220 during subsequent removal of the second sub-layer 232, preventing excessive thinning that could affect their support for the capacitor. In this embodiment, the density of the formed second sub-layer 232 can also be adjusted by changing the flow rate of the silicon-containing material or trimethylsilane.

[0073] In the subsequent process of removing the first sub-layer 231, the second sub-layer 232, together with the intermediate support layer 220 and the top support layer 250, can support the lower electrode 240 to prevent the lower electrode 240 from tipping over during the process.

[0074] In this embodiment, the second sub-layer 232 and the top support layer 250 are made of the same material. For example, if the top support layer 250 is a silicon nitride layer (SiN) or a silicon carbon nitride layer (SiCN), then the second sub-layer 232 is also a silicon nitride layer (SiN) or a silicon carbon nitride layer (SiCN).

[0075] Since the second sub-layer 232 plays a supporting role, its thickness should not be too thick. If the second sub-layer 232 is too thick, the intermediate support layer 220 and the top support layer 250 may be excessively thinned when the second sub-layer 232 is removed. Therefore, the thickness of the second sub-layer 232 is less than or equal to the thickness of the top support layer 250 to avoid the intermediate support layer 220 and the top support layer 250 being excessively thinned.

[0076] In this embodiment, since the second sub-layer 232 is made of the same material as the top support layer 250, in order to avoid the top support layer 250 being excessively thinned when the second sacrificial layer 230 is removed, the thickness of the second sub-layer 232 is set to be less than the thickness of the first sub-layer 231.

[0077] Please see Figure 3BThe top support layer 250 is patterned, and the first sub-layer 231 is removed. Simultaneously, the second sub-layer 232 is patterned.

[0078] Specifically, in this step, the top support layer 250 and the second sub-layer 232 are patterned to form a first opening 251; the first sub-layer 231 is removed along the first opening 251 to expose the intermediate support layer 220. The process for patterning the top support layer 250 can be photolithography and dry etching.

[0079] During the removal of the first sub-layer 231, the second sub-layer 232 and the top support layer 250 are partially removed. In this embodiment, since the density of the second sub-layer 232 is less than that of the top support layer 250, the thickness of the second sub-layer 232 removed in this step is greater than the thickness of the top support layer 250 removed. This further avoids the top support layer 250 being excessively thinned and also avoids the second sub-layer 232 being left behind due to incomplete removal in subsequent processes.

[0080] Please see Figure 3D The intermediate support layer 220 is patterned, and the first sacrificial layer 210 is removed. At the same time, the remaining second sub-layer 232 is completely removed.

[0081] Specifically, in this step, the intermediate support layer 220 is patterned to form a second opening 221. The second opening 221 corresponds in position to the first opening 251. The first sacrificial layer 210 and the remaining second sub-layer 232 are removed along the first opening 251 and the second opening 221, exposing the bottom support layer 202. The patterning process for the intermediate support layer 220 can be photolithography and dry etching, and the method for removing the first sacrificial layer 210 can be wet etching.

[0082] In this embodiment, the second sub-layer 232 is made of the same material as the intermediate support layer 220, or their etching rates are similar. Therefore, when patterning the intermediate support layer 220, the second sub-layer 232 is also simultaneously thinned. To further ensure that the second sub-layer 232 is completely removed after the step of removing the first sacrificial layer 210, the first sacrificial layer 210 is partially removed during the formation of the second opening 221, i.e., when patterning the intermediate support layer 220. Please refer to [link to relevant documentation]. Figure 3C The first sacrificial layer 210 is over-etched, which prolongs the etching time of the second sublayer 232 and increases the thinning amount of the second sublayer 232, thereby ensuring that the second sublayer 232 can be completely removed after the first sacrificial layer 210 is removed, avoiding the residue of the second sublayer 232.

[0083] If the thickness of the first sacrificial layer 210 removed is too large, it indicates a long etching time. Although this can further thin the second sub-layer 232, it may lead to excessive thinning of the top support layer 250. Therefore, in this embodiment, the thickness of the removed portion of the first sacrificial layer 210 is set to 1 nm to 10 nm.

[0084] After the first sacrificial layer 210 is removed, the steps of forming the dielectric layer 260 and the upper electrode 270 are performed. These steps are the same as the corresponding steps in the first embodiment and will not be described again.

[0085] The preparation method provided in the second embodiment of this disclosure can form a second sub-layer 232 supporting the sidewall of the lower electrode 240 in the top region of the lower electrode 240. During the process flow, the second sub-layer 232 can support the lower electrode 240 and prevent the lower electrode 240 from tilting. Before the dielectric layer 260 is formed, the second sub-layer 232 is gradually thinned to the point of removal as the process proceeds, which also avoids the sidewall of the lower electrode 240 being blocked, so that the storage capacity of the capacitor will not be affected by the presence of the second sub-layer 232.

[0086] This disclosure also provides a capacitor prepared using the above-described method. Please refer to [link to relevant documentation]. Figure 2G The capacitor includes a substrate 200, an intermediate support layer 220, a top support layer 250, a lower electrode 240, a dielectric layer 260, and an upper electrode 270.

[0087] The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 200 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 200 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 200 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the substrate 200. In this embodiment, the substrate 200 is a silicon substrate, which also includes other device structures, such as bit line structures and transistor structures, but these are not shown as they are not relevant to this invention. A conductive pad 201 is disposed within the substrate, which can serve as an electrical connection pad for capacitors and other device structures.

[0088] The intermediate support layer 220 is disposed at a predetermined distance above the substrate 200. That is, the intermediate support layer 220 is not disposed on the surface of the substrate 200, but is disposed at a distance from the substrate 200. The predetermined distance can be determined according to the actual structure of the capacitor.

[0089] The top support layer 250 is disposed at a predetermined distance above the intermediate support layer 220. That is, the top support layer 250 is not disposed on the surface of the intermediate support layer 220, but is spaced apart from it. The predetermined distance can be determined according to the actual structure of the capacitor. In this embodiment, the top support layer 250 and the intermediate support layer 220 are made of the same material and have the same or similar density. For example, both are made of SiCN.

[0090] In this embodiment, the thickness of the top support layer 250 is 1 nm to 10 nm. If the thickness of the top support layer 250 is less than 1 nm, it cannot provide sufficient support for the capacitor. If the thickness of the top support layer 250 is greater than 10 nm, although the support strength is greater, it will increase the volume occupied by the capacitor and cannot meet the requirements of device miniaturization.

[0091] The lower electrode 240 is disposed on the substrate 200 and electrically connected to the conductive pad 201 within the substrate 200. The lower electrode 240 penetrates the intermediate support layer 220, and the top support layer 250 is disposed on the top surface of the lower electrode 240. That is, the top support layer 250 does not cover the sidewall of the lower electrode 240, so as to maximize the area of ​​the sidewall of the lower electrode 240 covered by the dielectric layer 260 and increase the storage capacity of the capacitor.

[0092] The dielectric layer 260 covers the surfaces of the lower electrode 240, the intermediate support layer 220, and the top support layer 250. The dielectric layer 260 can be a high-k dielectric layer to improve capacitor performance. Examples include Al₂O₃, HfO₂, Ta₂O₅, and ZrO₂.

[0093] The upper electrode 270 covers the surface of the dielectric layer 260. In this embodiment, the upper electrode 270 also fills the gap between the substrate 200, the intermediate support layer 220 and the top support layer 250, and covers the surface of the top support layer 250.

[0094] The upper electrode 270, the dielectric layer 260 and the lower electrode 240 constitute a columnar capacitor, and the multiple capacitor arrays are arranged to form a capacitor array structure.

[0095] In this embodiment, the capacitor further includes a bottom support layer 202. The bottom support layer 202 covers the substrate 200 and exposes the conductive pad 201. The top surface of the bottom support layer 202 is flush with the top surface of the conductive pad 201, thereby preventing the bottom support layer 202 from obstructing the conductive pad 201, increasing the contact area between the lower electrode 240 and the conductive pad 201, and improving electrical contact performance. In this embodiment, the bottom support layer 202 and the intermediate support layer 220 are made of the same material, for example, both are nitride layers, such as silicon nitride carbon layers.

[0096] In the capacitor provided in this embodiment, the top support layer 250 is only disposed on the top surface of the lower electrode 240, and the sidewall of the lower electrode 240 is not covered by the top support layer 250. The sidewall of the lower electrode 240 is exposed to the maximum extent, thereby increasing the storage capacity of the capacitor without changing the key dimensions of the lower electrode 240.

[0097] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a capacitor, characterized in that, include: A substrate is provided, on which a first sacrificial layer, an intermediate support layer and a second sacrificial layer are stacked; A lower electrode is formed, which penetrates the second sacrificial layer, the intermediate support layer and the first sacrificial layer, and is electrically connected to a conductive pad in the substrate; A top support layer is formed on the second sacrificial layer and the top surface of the lower electrode; The top support layer is patterned such that it is located on the top surface of the lower electrode but not on the sidewall of the lower electrode, and the second sacrificial layer is removed. Pattern the intermediate support layer and remove the first sacrificial layer; A dielectric layer is formed, which covers the substrate, the lower electrode, the exposed surface of the intermediate support layer, and the exposed surface of the top support layer; An upper electrode is formed, which covers the surface of the dielectric layer.

2. The method for preparing a capacitor according to claim 1, characterized in that, The method for forming the first sacrificial layer includes the following steps: A first material layer is formed on the substrate, wherein a first type of dopant in the first material layer has a first doping concentration; A second material layer is formed on the first material layer, wherein a first type of dopant in the second material layer has a second doping concentration, which is greater than the first doping concentration.

3. The method for preparing a capacitor according to claim 2, characterized in that, The first type of dopant includes boron.

4. The method for preparing a capacitor according to claim 2, characterized in that, The first doping concentration is 2-7%, and the second doping concentration is 5-10%.

5. The method for preparing a capacitor according to claim 2, characterized in that, Both the first material layer and the second material layer are phosphorus-doped silicate glasses, and the phosphorus doping concentration in the silicate glass is 3-5%.

6. The method for preparing a capacitor according to claim 1, characterized in that, The method of forming the lower electrode further includes: A capacitor hole is formed, which penetrates the second sacrificial layer, the intermediate support layer and the first sacrificial layer, and exposes the conductive pad in the substrate; A lower electrode is formed in the capacitor hole.

7. The method for preparing a capacitor according to claim 1, characterized in that, The top surface of the lower electrode is flush with the surface of the second sacrificial layer.

8. The method for preparing a capacitor according to claim 1, characterized in that, The second sacrificial layer includes a first sublayer disposed on the surface of the intermediate support layer and a second sublayer disposed on the surface of the first sublayer. During the step of patterning the top support layer, the second sublayer is patterned simultaneously, and a portion of the first sublayer is exposed.

9. The method for manufacturing a capacitor according to claim 8, characterized in that, The thickness of the second sub-layer is less than or equal to the thickness of the top support layer, and the second sub-layer and the top support layer are made of the same material.

10. The method for manufacturing a capacitor according to claim 9, characterized in that, The density of the second sublayer is less than that of the top support layer.

11. The method for preparing a capacitor according to claim 10, characterized in that, The film-forming temperature of the second sub-layer is lower than that of the top support layer and the middle support layer.

12. The method for preparing a capacitor according to claim 8, characterized in that, The steps of patterning the top support layer and removing the second sacrificial layer further include the following steps: The top support layer is patterned to form a first opening; The second sacrificial layer is removed along the first opening, exposing the intermediate support layer.

13. The method for preparing a capacitor according to claim 12, characterized in that, In the step of removing the second sacrificial layer along the first opening to expose the intermediate support layer, the first sub-layer is removed, the second sub-layer and the top support layer are partially removed, and in the step of removing the first sacrificial layer, the remaining second sub-layer is completely removed.

14. The method for preparing a capacitor according to claim 12, characterized in that, After the steps of patterning the intermediate support layer and removing the first sacrificial layer, the thickness of the remaining top support layer is 1 nm to 10 nm.

15. The method for manufacturing a capacitor according to claim 1, characterized in that, The steps of patterning the intermediate support layer and removing the first sacrificial layer further include: The intermediate support layer is patterned to form a second opening; The first sacrificial layer is removed along the second opening, exposing the conductive pad of the substrate.

16. The method for manufacturing a capacitor according to claim 15, characterized in that, The step of patterning the intermediate support layer to form the second opening further includes: When forming the second opening, a portion of the first sacrificial layer is removed.

17. The method for manufacturing a capacitor according to claim 16, characterized in that, The thickness of the first sacrificial layer in the removed portion is 1 nm to 10 nm.

18. The method for preparing a capacitor according to claim 1, characterized in that, It also includes the following steps: A bottom support layer is formed, the top surface of which is flush with the top surface of the conductive pad; The first sacrificial layer, the intermediate support layer, and the second sacrificial layer are formed on the bottom support layer and the conductive pad.

19. A capacitor, characterized in that, include: A substrate, wherein a conductive pad is disposed within the substrate; An intermediate support layer is disposed at a predetermined distance above the substrate; A top support layer is positioned at a predetermined distance above the intermediate support layer; A lower electrode is disposed on the substrate and electrically connected to a conductive pad within the substrate. The lower electrode penetrates the intermediate support layer, and a top support layer is disposed on the top surface of the lower electrode. The top support layer is not located on the sidewall of the lower electrode. A dielectric layer covers the surfaces of the lower electrode, the intermediate support layer, and the top support layer; The upper electrode covers the surface of the dielectric layer.

20. The capacitor according to claim 19, characterized in that, The thickness of the top support layer is 1nm to 10nm.

21. The capacitor according to claim 19, characterized in that, The capacitor also includes: A bottom support layer is located within the substrate, and the top surface of the bottom support layer is flush with the top surface of the conductive pad.

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