Memory package and storage device including memory package

Abstract

A memory package comprising: a package substrate including a redistribution layer and bond pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein a first group of the plurality of memory chips is connected to a first chip pad of the plurality of chip pads through first routing, and wherein a second group of the plurality of memory chips is connected to a second chip pad of the plurality of chip pads through second routing and at least a portion of the plurality of signal paths.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0152800, filed on November 16, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of this disclosure relate to a memory package and a storage device including the memory package. Background Technology

[0004] A memory package may include multiple memory chips mounted on a package substrate, and a storage device may include one or more memory packages. The storage device may include a device controller for controlling the memory package, and the device controller may control multiple memory chips via buffer chips included in the memory package. As the data storage space required by various electronic devices increases, the demand for memory packages and storage devices with efficiently arranged buffer chips and memory chips has been steadily increasing. Summary of the Invention

[0005] At least one example embodiment of this disclosure provides a memory package and storage device in which memory chips are effectively interconnected using a redistribution layer of a package substrate and / or a system substrate.

[0006] According to at least one example embodiment of the present disclosure, a memory package includes: a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to a plurality of memory channels, wherein a first group of memory chips is connected to a first chip pad in the plurality of chip pads via a first wiring, and wherein a second group of memory chips is connected to a second chip pad in the plurality of chip pads via a second wiring and at least a portion of the signal paths.

[0007] According to at least one example embodiment of the present disclosure, a storage device includes: a system substrate; device controller circuitry mounted on the system substrate; and a plurality of memory packages mounted on the system substrate and configured to operate in response to a control command received from the device controller circuitry, wherein each of the plurality of memory packages includes: a package substrate connected to the system substrate; a buffer chip mounted on the package substrate and configured to receive a control command from the device controller circuitry and output the control command to at least one of a plurality of memory channels; and a plurality of memory chips connected to the buffer chip via the plurality of memory channels, wherein a first group of memory chips is electrically connected to the buffer chip via a first wiring, and wherein a second group of memory chips is electrically connected to the buffer chip via a second wiring and a redistribution layer disposed in the package substrate.

[0008] According to at least one example embodiment of the present disclosure, a storage device includes: a system substrate including a redistribution layer; device controller circuitry mounted on the system substrate; and a plurality of memory packages mounted on the system substrate and configured to operate in response to control commands received from the device controller circuitry, wherein each of the plurality of memory packages includes a package substrate connected to the system substrate and including a plurality of bonding pads, and a plurality of memory chips mounted on the package substrate, wherein at least one of the memory packages includes a buffer chip connected to the memory chips via a plurality of channels and transmitting control commands received from the device controller circuitry to the memory chips, wherein the buffer chip includes a plurality of chip pads, and wherein at least one of the chip pads is connected via wiring and a redistribution layer to a memory chip in a memory package of the plurality of memory packages that does not include the buffer chip. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 and Figure 2 This is a view illustrating a storage device according to at least one example embodiment of the present disclosure;

[0011] Figure 3 This is a block diagram illustrating a storage device according to at least one example embodiment of the present disclosure;

[0012] Figure 4 This is a circuit diagram illustrating a memory cell array of a memory device according to at least one example embodiment of the present disclosure;

[0013] Figure 5 This is a view showing a buffer chip included in a memory package according to at least one example embodiment of the present disclosure;

[0014] Figures 6 to 9 This is a view showing a memory package according to at least one example embodiment of the present disclosure;

[0015] Figure 10 This is a view showing the appearance of a storage device according to at least one example embodiment of the present disclosure;

[0016] Figure 11 and Figure 12 This is a view illustrating a storage device according to at least one example embodiment of the present disclosure;

[0017] Figure 13 This is a view showing the appearance of a storage device according to at least one example embodiment of the present disclosure;

[0018] Figures 14 to 16 This is a view illustrating a storage device according to at least one example embodiment of the present disclosure; and

[0019] Figure 17 It is a storage device suitable for memory packaging and storage devices according to at least one example embodiment of the present disclosure. Detailed Implementation

[0020] As is common in the field of the inventive concept, embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of the embodiments can be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments can be physically combined into more complex blocks, units, and / or modules.

[0021] Figure 1 and Figure 2 This is a view showing a storage device according to at least one example embodiment.

[0022] Reference Figure 1 Storage device 1 may include a memory region 10 and a device controller 20. Device controller 20 may be configured as a memory controller for controlling the operation of memory region 10. Storage device 1 may support multiple channels CH1 to CHm, and memory region 10 and device controller 20 may be interconnected via multiple channels CH1 to CHm. For example, storage device 1 may include a solid-state drive (SSD) device.

[0023] Memory region 10 may include multiple memory packages 101 to 10 m Multiple memory packages 101 to 10 m Multiple channels CH1 to CHm can be connected to the device controller 20, and multiple memory packages 101 to 10... m Each of the memory packages 101 may include a plurality of memory devices NVM11 to NVMmn. Each of the plurality of memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, the memory devices NVM11 to NVM1n included in the first memory package 101 may be connected to the first channel CH1 via paths W11 to W1n, while the memory devices NVM21 to NVM2n included in the second memory package 102 may be connected to the second channel CH2 via paths W21 to W2n.

[0024] In at least one example embodiment, each of the plurality of memory devices NVM11 to NVMmn can be implemented as an arbitrary memory cell that operates according to individual commands from the device controller 20. For example, each of the plurality of memory devices NVM11 to NVMmn can be implemented as a chip or a die. However, the example embodiment is not limited thereto. When each of the plurality of memory devices NVM11 to NVMmn is implemented as a chip or a die, the plurality of memory packages 101 to 10 m Multiple storage devices NVM11 to NVMmn can be stacked alternately in each of them.

[0025] Device controller 20 can send signals to and receive signals from memory region 10 through multiple channels CH1 to CHm. For example, device controller 20 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to memory region 10 through channels CH1 to CHm, or it can receive data DATAa to DATAm from memory region 10.

[0026] In at least one example embodiment, multiple memory packages 101 to 10 mAt least one of the storage devices 10 may include a buffer chip, which can transmit signals between the storage devices NVM11 to NVMmn and the device controller 20. For example, during a programming operation, the device controller 20 may send data and address signals to be stored in the memory region 10 to the buffer chip. The buffer chip may then send data to one of the storage devices NVM11 to NVMmn based on the address signals.

[0027] When multiple memory packages are 101 to 10 m When at least one of the devices includes a buffer chip, the buffer chip can output data and address signals to at least one of the multiple channels CH1 to CHm in response to data and address signals sent to the buffer chip by the device controller 20. In other words, the buffer chip can branch between the device controller 20 and the multiple storage devices NVM11 to NVMmn and provide signal transmission paths.

[0028] Device controller 20 can select one of the non-volatile memory devices connected to the corresponding channel through each channel, and can send signals to and receive signals from the selected non-volatile memory device. For example, device controller 20 can select non-volatile memory device NVM11 from non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. Device controller 20 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 through the first channel CH1, or can receive data DATAa from the selected non-volatile memory device NVM11.

[0029] Device controller 20 can send signals to and receive signals from memory region 10 in parallel through different channels. For example, device controller 20 can send command CMDb to second memory package 102 through second channel CH2, while simultaneously sending command CMDa to first memory package 101 through first channel CH1. For this purpose, each of first memory package 101 and second memory package 102 may include a buffer chip. Alternatively, device controller 20 can simultaneously send commands CMDa and CMDb through a single buffer chip shared by first memory package 101 and second memory package 102 via first channel CH1 and second channel CH2. For example, when device controller 20 receives data DATAa from first memory package 101 through first channel CH1, device controller 20 can receive data DATAb from second memory package 102 through second channel CH2.

[0030] Device controller 20 can control the overall operation of memory region 10. Device controller 20 can control each of the multiple memory devices NVM11 to NVM1n connected to multiple channels CH1 to CHm by sending signals to multiple channels CH1 to CHm. For example, device controller 20 can control the selection of one of the multiple memory devices NVM11 to NVM1n by sending command CMDa and address ADDRa via the first channel CH1.

[0031] Each of the multiple storage devices NVM11 to NVMmn can operate under the control of device controller 20. For example, storage device NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided through the first channel CH1. For example, storage device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided through the second channel CH2, and can send the read data DATAb to device controller 20.

[0032] Figure 1 An example is shown in which memory region 10 can communicate with device controller 20 through m channels, and memory region 10 may include n non-volatile storage devices corresponding to each channel. The number of channels and the number of storage devices connected to a single channel can vary.

[0033] Figure 2 This could be a view illustrating a storage device 100 according to at least one example embodiment. (Refer to...) Figure 2 The storage device 100 may include a device controller 110 and a memory package 120.

[0034] The device controller 110 may be or include processing circuitry, such as hardware including logic circuitry; hardware / software combination for executing software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, one or more of a central processing unit (CPU), processor core, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc.

[0035] The processing circuitry of the device controller 110 can be configured to perform and / or control any operations described herein as being performed by the device controller or its components, via hardware and / or software (e.g., firmware). The device controller 110 may also be referred to herein as device controller circuitry 110.

[0036] The memory package 120 may include a buffer chip 130 and multiple memory chips, and the multiple memory chips may be divided into multiple groups 140 and 150. Figure 2 In the example embodiment shown, each group of group 140 and group 150 includes the same number of memory chips, but unlike the example, at least a portion of group 140 and group 150 may include different numbers of memory chips.

[0037] Each of the multiple groups 140 and 150 includes memory chips that can be connected to the buffer chip 130 via different paths. For example, the multiple memory chips included in the first group 140 can be connected to each other via a first wiring W1 and can also be connected to the buffer chip 130. Figure 2 In this diagram, the first wiring W1 is shown as a single wiring; however, the first wiring W1 may include multiple wirings. The multiple memory chips included in the second group 150 can be connected to each other via the second wiring W2 and can also be connected to the buffer chip 130. Similar to the first wiring W1, the second wiring W2 may include multiple wirings. In other words, although in Figure 2 The diagram is schematically shown, but to connect each of the first group 140 and the second group 150 to the buffer chip 130, multiple first wirings W1 and multiple second wirings W2 can be provided. Furthermore, in the example embodiment, the memory chips can be connected to each other via connections other than wirings W1 and W2, or the memory chips can be connected to the buffer chip 130. For example, the memory chips in the first group 140 can be connected to each other via through-silicon vias (TSVs) and can be connected to the buffer chip 130 via the first wirings W1.

[0038] Buffer chip 130 can be configured to coordinate signal exchange between device controller 110 and memory package 120. Buffer chip 130 can be connected to wiring W1 and wiring W2 via multiple chip pads PAD1 and PAD2. Although in Figure 2 The diagram is schematically shown, but each of the first chip pad PAD1 and the second chip pad PAD2 may include multiple chip pads. The multiple chip pads PAD1 and PAD2 may be connected to selection circuitry 131, and selection circuitry 131 may select at least one of the multiple chip pads PAD1 and PAD2 according to commands from device controller 110.

[0039] The buffer chip 130 may be or include processing circuitry, such as hardware including logic circuitry; a hardware / software combination for executing software; or a combination of both. For example, the processing circuitry may more specifically include, but is not limited to, one or more of a central processing unit (CPU), processor core, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc.

[0040] The processing circuitry of the buffer chip 130 can be configured to perform and / or control any operations described herein as being performed by the buffer chip or its components (e.g., selection circuitry 131) via hardware and / or software (e.g., firmware).

[0041] As an example, device controller 110 can send an address signal to buffer chip 130 to select at least one of the memory chips included in the first group 140 and the second group 150. Buffer chip 130 can select at least one of the first chip pad PAD1 and the second chip pad PAD2 based on the address signal, and can send data to the memory chip or receive data output from the memory chip. When storage device 100 supports multi-channel operation to reduce latency, it can simultaneously send the address signal generated by device controller 110 and the corresponding control command to the first group 140 and the second group 150.

[0042] For example, when device controller 110 generates a control command to perform a control operation such as a programming operation or a reading operation, the control command may include address information specifying the address of the memory chip used to perform the control operation. The selection circuit 131 of buffer chip 130 may select at least one of multiple chip pads PAD1 and PAD2 based on the address information included in the control command, and may not select the other chip pads.

[0043] In an example embodiment, at least one of a transmitter for outputting data and / or signals to the memory chip and a receiver for receiving data from the memory chip can be connected to each of a plurality of chip pads PAD1 and PAD2. Selection circuitry 131 can select at least one of the plurality of chip pads PAD1 and PAD2 based on address information received from device controller 110, and can activate the transmitter and / or receiver connected to the selected at least one chip pad. Furthermore, selection circuitry can deactivate the transmitter and receiver connected to the unselected chip pads among the plurality of chip pads PAD1 and PAD2.

[0044] As an example, selection circuit 131 may include a multiplexer and a demultiplexer. Therefore, selection circuit 131 can selectively send data and signals received from device controller 110 to multiple memory chips divided into N groups (N is a natural number of 2 or greater). In at least one example embodiment, data and signals can be selectively sent to multiple memory chips divided into three or more groups using a single buffer chip 130, thus enabling a high-capacity storage device 100 without increasing the number of buffer chips 130 and device controller 110.

[0045] In at least one example embodiment, storage device 100 may include multiple memory packages, and only a portion of the multiple memory packages may include a buffer chip 130. In some example embodiments, a memory chip in a memory package that does not include a buffer chip 130 may be connected to device controller 110 via a buffer chip 130 in another memory package. Therefore, without changing the design of device controller 110, a storage device 100 with high capacity can be implemented by increasing the number of memory packages connected to device controller 110.

[0046] Figure 3 This is a block diagram illustrating a storage device according to at least one example embodiment.

[0047] Reference Figure 3 The storage device 200 may include control logic circuitry 220, a memory cell array 230, a page buffer portion 240, a voltage generator 250, and a row decoder 260. The storage device 200 may further include a memory interface circuitry 210 for signals and data required for input and output operations, and may further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. According to at least some example embodiments, the storage device 200 may include circuitry configured to perform and / or control any operations described in the specification as being performed by the storage device 200 or its components (e.g., memory interface circuitry 210, control logic circuitry 220, memory cell array 230, page buffer portion 240, voltage generator 250, and row decoder 260) via hardware and / or software (e.g., firmware).

[0048] The control logic circuit 220 can control various operations within the storage device 200. The control logic circuit 220 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface circuit 210. For example, the control logic circuit 220 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0049] The storage cell array 230 may include multiple storage blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple storage blocks BLK1 to BLKz may include multiple storage cells. The storage cell array 230 can be connected to the page buffer section 240 via bit lines BL, and can be connected to the line decoder 260 via word lines WL, string select lines SSL, and ground select lines GSL.

[0050] In at least one example embodiment, the memory cell array 230 may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines and stacked vertically on a substrate. U.S. Patent Publications Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference. In at least one example embodiment, the memory cell array 230 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0051] Page buffer section 240 may include multiple page buffers PB1 to PBn (n is an integer equal to or greater than 3), and the multiple page buffers PB1 to PBn may be connected to memory cells via multiple bit lines BL. Page buffer section 240 may select at least one bit line from bit lines BL in response to column address Y-ADDR. Depending on the operating mode, page buffer section 240 may operate as a write driver or a read amplifier. For example, in a programming operation, page buffer section 240 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. In a read operation, page buffer section 240 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0052] Voltage generator 250 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 250 can generate programming voltage, reading voltage, programming verification voltage, erasing voltage, etc., as word line voltage VWL.

[0053] The row decoder 260 can select one of multiple word lines WL in response to the row address X-ADDR, and can also select one of multiple string select lines SSL. For example, in a programming operation, the row decoder 260 can apply a programming voltage and a programming verification voltage to the selected word line, and in a reading operation, the row decoder 260 can apply a reading voltage to the selected word line.

[0054] Figure 4 This is a circuit diagram illustrating a memory cell array of a memory device according to at least one example embodiment.

[0055] Figure 4 This is a view illustrating a 3D V-NAND structure suitable for a memory package according to at least one example embodiment. When the memory device included in the memory package is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks included in the memory device can be... Figure 8 The equivalent circuit shown is used to represent this.

[0056] Figure 4 The memory block BLK shown can represent a three-dimensional memory block formed on a substrate in a three-dimensional structure. For example, multiple NAND strings included in the memory block BLK can be formed in a direction perpendicular to the substrate.

[0057] Reference Figure 4 The memory block BLK may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. Figure 4 An example is shown in which each of the plurality of memory NAND strings NS11 to NS33 may include eight memory cells MC1, MC2, ..., MC8, but the example embodiment is not limited thereto.

[0058] The string select transistor SST can be connected to the corresponding string select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8. Gate lines GTL1, GTL2, ..., GTL8 can be word lines, and some of them can be dummy word lines. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The string select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0059] Word lines with the same height (e.g., GTL1) can be connected together, while ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 can be isolated from each other. Figure 4An example is shown in which the memory block BLK can be connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2 and BL3, but the example embodiment is not limited thereto.

[0060] Figure 5 This is a view showing a buffer chip included in a memory package according to at least one example embodiment.

[0061] Reference Figure 5 According to at least one example embodiment, the buffer chip 300 may include a plurality of chip pads 301 to 320. A portion of the plurality of chip pads 301 to 320 (301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320) may be connected to an external device controller located outside the memory package, and another portion may be connected to a plurality of memory chips included in the memory package together with the buffer chip 300.

[0062] The buffer chip 300 can send or receive data strobe signals (DQS), data signals (DQ), chip enable signals (nCE), command latch enable signals (CLE), address latch enable signals (ALE), write enable signals (nWE), read enable signals (nRE), ready / busy signals (nR / B), and select signals (SEL) from the device controller via a portion of the chip pads 301 to 309 connected to the device controller. Multiple chip pads 302 can be provided for sending and receiving data signals DQ. Commands, addresses, and data used to control the memory chip can be sent via the data signals DQ.

[0063] Furthermore, the buffer chip 300 can send or receive data strobe signals (DQS), data signals (DQ), chip enable signals (nCE), command latch enable signals (CLE), address latch enable signals (ALE), write enable signals (nWE), read enable signals (nRE), and ready / busy signals (nR / B) from the memory chip by connecting to a portion of the chip pads 310 to 320 of the memory chip included in the memory package. In at least one example embodiment, the buffer chip 300 can be connected to memory chips divided into four groups and can output the data signal DQ received from the device controller as at least one of data signals DQ1 to DQ4 corresponding to the first to fourth groups, or can output at least one of the data signals DQ1 to DQ4 received from the memory chip as the data signal DQ to the device controller. In other words, in Figure 5In the example embodiment shown, the buffer chip 300 can be connected to the memory chips divided into four groups via four channels. However, in the example embodiment, the number of channels connecting the buffer chip 300 to the memory chips can be varied.

[0064] Reference Figure 5 The buffer chip 300 may include logic circuitry 330 configured to transmit signals and / or data received from an external device controller to a memory chip disposed within a memory package. Logic circuitry 330 may provide signal and data transmission paths between multiple chip pads 301 to 320. For example, the number of device controllers connected to the buffer chip 300 may differ from the number of memory chips, and the number of memory chips may be greater than the number of device controllers. Therefore, the buffer chip 300 may, in response to a control command from a device controller, activate a portion of the chip pads 310 to 320 connected to the memory chip to transmit signals and / or data.

[0065] Reference Figure 5 The logic circuit 330 may include a selection circuit 340 and a transmission circuit 350. The transmission circuit 350 may include a plurality of unit transmission circuits 351 to 354 corresponding to channels connecting the memory chip to the buffer chip 300. For example, the plurality of unit transmission circuits 351 to 354 may be connected to chip pads 311 to 314 for transmitting first to fourth data signals DQ1 to DQ4 through the first to fourth channels. Each of the plurality of unit transmission circuits 351 to 354 may include a transmitter Tx and a receiver Rx. The transmitter Tx may be or include, for example, a transmitter circuit configured to transmit signals according to known methods. The receiver Rx may be or include, for example, a receiver circuit configured to receive signals according to known methods.

[0066] Selection circuit 340 can select and activate at least one of multiple unit transmission circuits 351 to 354 in response to a selection signal SEL received from the device controller, and can deactivate the other unit transmission circuits. When the memory package including buffer chip 300 supports multi-channel operation, two or more of the multiple unit transmission circuits 351 to 354 can be activated simultaneously.

[0067] As an example, when the device controller wants to store data in a memory chip connected to the buffer chip 300 via the first channel, the selection circuit 340 can activate the first unit transmission circuit 351 according to the selection signal SEL, and can deactivate the other unit transmission circuits 352 to 354. In the first unit transmission circuit 351, the transmitter Tx can be activated, and the data signal DQ received from the device controller can be sent as the first data signal DQ1 to the first group of memory chips via the chip pad 311.

[0068] In at least one example embodiment, when the data to be read by the device controller from the memory package is stored in the memory chip connected to the buffer chip 300 via the fourth channel, the selection circuit 340 can activate the fourth unit transmission circuit 354 according to the selection signal SEL, and can deactivate the other unit transmission circuits 351 to 353. In the fourth unit transmission circuit 354, the receiver Rx can be activated and can receive the fourth data signal DQ4 from the fourth group of memory chips, and the fourth data signal DQ4 can be output to the device controller as signal DQ through the chip pad 302.

[0069] As described above, the buffer chip 300 according to at least one example embodiment can be used as a 1:N multiplexer / demultiplexer between a device controller and memory chips. Furthermore, the buffer chip 300 can provide signal branching between a single device controller and memory chips divided into three or more groups. Therefore, by using a single buffer chip 300, the number of memory chips connected to a single device controller and the number of channels for controlling the memory chips can be increased, and the storage space of memory packages and storage devices including memory packages can be efficiently increased and managed.

[0070] In at least one example embodiment, at least a portion of the memory chips connected to the buffer chip 300 may be included in different memory packages. As an example, memory chips connected to the buffer chip 300 via first and second channels may be included together with the buffer chip 300 in a first memory package, and memory chips connected to the buffer chip 300 via third and fourth channels may be included in a second memory package separate from the first memory package. As an example, the memory chips in the second memory package may be connected to the buffer chip 300 via a redistribution layer disposed in a system substrate on which the first and second memory packages are mounted. The redistribution layer in the system substrate may be implemented to provide wiring for various signal paths. By connecting a single buffer chip 300 capable of 1:N signal branching between the device controller and the memory chips, the design flexibility of the memory package can be improved.

[0071] Furthermore, the buffer chip 300 according to at least one example embodiment may include a plurality of unit transmission circuits 351 to 354 corresponding to a plurality of channels for transmitting and receiving signals. Each of the plurality of unit transmission circuits 351 to 354 can be connected to the memory chip via a single channel, and the load on each of the plurality of unit transmission circuits 351 to 354 can be reduced compared to examples using methods that connect signal transmission circuits to the memory chip via two or more channels. Therefore, high-speed signal operation using high-frequency signals can be achieved by the buffer chip 300.

[0072] Figures 6 to 9 This is a view showing a memory package according to at least one example embodiment.

[0073] Reference Figure 6 A memory package 400 according to at least one example embodiment may include a plurality of memory chips MC, a buffer chip 430, and a package substrate 440. The plurality of memory chips MC may be divided into a first group 410 and a second group 420, and the memory chips MC in the first group 410 and the second group 420 may be arranged at different positions in a direction parallel to the upper surface of the package substrate 440. In each group of the first group 410 and the second group 420, the memory chips MC may form a stepped difference and may be stacked in a stepped shape.

[0074] Each of the memory chips MC may include a semiconductor substrate 411 and a first structure 412 and a second structure 413 stacked on the semiconductor substrate 411. For example, the first structure 412 may include a peripheral circuit region, in which peripheral circuitry required for the operation of each of the memory chips MC is arranged, such as a row decoder, a page buffer, and a voltage generator. The second structure 413 may include a cell region in which a common source line 414, a gate stack structure 415 having a gate electrode layer stacked on the common source line 414, a channel structure 416 passing through the gate stack structure 415, and a bit line 417 electrically connected to the channel structure 416 are arranged.

[0075] Each of the memory chips MC may include a through-wire 418 connected to peripheral circuitry in the first structure 412 and extending from the second structure 413. The through-wire 418 may be connected to input / output pads 419 disposed on each of the memory chips MC. The input / output pads 419 of each of the memory chips MC included in the first group 410 may be connected to the first wiring W1, while the input / output pads 419 of each of the memory chips MC included in the second group 420 may be connected to the second wiring W2. Therefore, the memory chips MC included in the first group 410 and the second group 420 may be electrically connected to each other.

[0076] Refer to the cross-sectional view shown. Figure 6 A single through-wire 418 can be provided in each memory chip MC, but each memory chip MC can include multiple through-wires. Multiple through-wires can be connected to multiple first wires through multiple input / output pads.

[0077] Multiple memory chips (MC) and buffer chips (430) can be mounted on a package substrate (440). The package substrate (440) may include multiple bonding pads (441 and 443) and redistribution layers (442 and 444) providing multiple signal paths. Redistribution layers (442 and 444) can provide signal paths between an external device controller and the buffer chip (430) and / or between the buffer chip (430) and the memory chip (MC). At least a portion of the redistribution layers (442 and 444) can be connected via bonding pads (441 and 443) to chip bumps (435) that connect the buffer chip (430) to the package substrate (440) and / or to package bumps (445) disposed beneath the package substrate (440).

[0078] A portion of redistribution layers 442 and 444 can provide a signal path connecting the upper bonding pad 441 to the lower bonding pad 443, and through this signal path, the external device controller and the buffer chip 430 can exchange signals via package bumps 445 disposed beneath the package substrate 440. A portion of redistribution layer 444 can provide a signal path connecting the second wiring W2 to the upper bonding pad 441, and through this signal path, the memory chip MC and the buffer chip 430 of the second group 420 can exchange signals. In other words, a portion of redistribution layer 444 can provide a signal path between the second wiring W2 and the lower chip pad 432 of the buffer chip 430.

[0079] Reference Figure 6 The memory chips MC of the first group 410 can be connected to the buffer chip 430 via the first wiring W1. As an example, the buffer chip 430 may include multiple chip pads 431 and 432, and the first chip pad 431 may be connected to the first wiring W1. The first chip pad 431 may be an upper chip pad formed on the upper surface of the buffer chip 430 to connect to the first wiring W1. In at least one example embodiment, the buffer chip 430 and the memory chips MC of the first group 410 can be connected to each other via multiple first wirings W1, and each of the memory chips MC may include multiple input / output pads 419.

[0080] Unlike the first group 410, the memory chip MC of the second group 420 can be connected to the second chip pad 432 of the buffer chip 430 via the second wiring W2 and the signal path provided by a portion of the redistribution layers 442 and 444. Unlike the first chip pad 431, the second chip pad 432 can be a lower chip pad formed on the lower surface of the buffer chip 430, and can be connected to the upper bonding pad 441 of the package substrate 440 via chip bumps 435.

[0081] In other words, in Figure 6 In the illustrated example embodiment, the memory chips MC of the first group 410 can be directly connected to the buffer chip 430 via the first wiring W1, while the memory chips MC of the second group 420 can be connected to the buffer chip 430 via the second wiring W2 and at least a portion of the signal path provided by the redistribution layers 442 and 444 arranged in the package substrate 440. Therefore, the number and arrangement of the memory chips MC connected to a single buffer chip 430 in the memory package 400, as well as the number of groups 410 and 420 dividing the memory chips MC, can be flexibly designed.

[0082] In at least one example embodiment, the groups 410 and 420 that divide the memory chip MC can correspond to the channels required by the device controller to control the memory package 400. Figure 6 In the example embodiment shown, the device controller can divide the memory chip MC into a first channel and a second channel when controlling the memory chip MC. In at least one example embodiment, by applying a buffer chip 430 capable of 1:N signal branching to the memory package 400, the number of channels for dividing the memory chip MC can be sufficiently ensured by a single buffer chip 430.

[0083] Reference Figure 7 According to at least one example embodiment, a memory package 500 may include a plurality of memory chips MC, a buffer chip 550, and a package substrate 560. The plurality of memory chips MC may be divided into a first group 510 to a fourth group 540, and within each group 510 to 540, the memory chips MC may form a stepped difference and may be stacked in a stepped shape. Figure 7 In the example embodiment shown, the memory chips MC of the first group 510 and the third group 530 can be stacked alternately, and the memory chips MC of the second group 520 and the fourth group 540 can be stacked alternately. Therefore, the memory chips of each group in the first group 510 and the second group 520 can be arranged at the same height in a direction perpendicular to the upper surface of the package substrate 560.

[0084] Each of the memory chips (MC) can have a reference. Figure 6The aforementioned example describes a similar structure. Each of the memory chips MC may include a semiconductor substrate 511 and a first structure 512 and a second structure 513 stacked on the semiconductor substrate 511. For example, the first structure 512 may include a peripheral circuit region, such as a peripheral circuitry required for the operation of each of the memory chips MC, which is arranged in the peripheral circuitry region, such as a row decoder, a page buffer, and a voltage generator. The second structure 513 may include a cell region in which a common source line 514, a gate stack structure 515 having a gate electrode layer stacked on the common source line 514, a channel structure 516 passing through the gate stack structure 515, and a bit line 517 electrically connected to the channel structure 516 are arranged. Each of the memory chips MC may include a through wiring 518 connected to the peripheral circuitry in the first structure 512 and extending from the second structure 513.

[0085] For example, each of the memory chips MC may include an input / output pad 519 connected to one of the wirings W1 to W4. The memory chips MC of the first group 510 can be directly connected to the first chip pad 551 of the buffer chip 550 via the first wiring W1, while the memory chips MC of the third group 530 can be directly connected to the first chip pad 551 of the buffer chip 550 via the third wiring W3. The first wiring W1 and the third wiring W3 can be connected to different chip pads in the first chip pad 551. The configuration that the memory chips MC can be directly connected to the buffer chip 550 via the first wiring W1 or the third wiring W3 indicates that the memory chips MC can transmit signals without using different structures other than the first wiring W1 and the third wiring W3.

[0086] The memory chip MC of the second group 520 can be connected to the second wiring W2, while the memory chip MC of the fourth group 540 can be connected to the fourth wiring W4. The second wiring W2 and the fourth wiring W4 can be connected to a portion of the redistribution layers 562 and 564 arranged in the package substrate 560 via upper bonding pads 561 formed on the upper surface of the package substrate 560. In other words, the memory chip MCs of the second group 520 and the fourth group 540 can be connected to the buffer chip 550 via signal paths provided by a portion of the redistribution layers 562 and 564 arranged in the package substrate 560, in addition to the second wiring W2 and the fourth wiring W4. Each of the first wiring W1 to the fourth wiring W4 may include multiple wirings.

[0087] As in the example embodiments above, refer to Figure 6The redistribution layers 562 and 564 can be connected to at least one of the upper bonding pad 561 and the lower bonding pad 563. Furthermore, a portion of the redistribution layer 564, connected to the second wiring W2 and the fourth wiring W4, can be connected to the second chip pad 552 of the buffer chip 550 via chip bumps 555. Therefore, the memory chips MC of the second group 520 and the fourth group 540 can exchange signals with the buffer chip 550 via the second wiring W2 and the fourth wiring W4, as well as a portion of the redistribution layers 562 and 564.

[0088] exist Figure 7 In the illustrated example embodiment, the memory chip MC can be divided into four groups 510 to 540, and the buffer chip 550 can provide four channels, allowing the memory chip MC to be divided into four groups 510 to 540. In other words, the buffer chip 550 can branch signals in a 1:4 ratio to coordinate signals between a single device controller and the memory chip MCs included in the memory package 500. For example, a signal received from the device controller can be sent to at least one selected channel of the four channels, or a signal received from at least one of the four channels can be sent to the device controller. The number of channels included in the memory package 500 can vary depending on the number of memory chip MCs or the method of grouping the memory chip MCs.

[0089] Reference Figure 8 According to at least one example embodiment, the memory package 600 may include a plurality of memory chips MC, a buffer chip 630, and a package substrate 640. The plurality of memory chips MC may be divided into a first group 610 and a second group 620, and the memory chips MC may be stacked alternately in each of the first group 610 and the second group 620.

[0090] The structure of each element in a memory chip (MC) can be compared with a reference. Figure 6 and Figure 7The foregoing examples are similar. Each of the memory chips MC may include a semiconductor substrate 611 and a first structure 612 and a second structure 613 stacked on the semiconductor substrate 611. For example, the first structure 612 may include a peripheral circuit region, such as a peripheral circuitry required for the operation of each of the memory chips MC, which is arranged in the peripheral circuitry region, such as a row decoder, a page buffer, and a voltage generator. The second structure 613 may include a cell region in which a common source line 614, a gate stack structure 615 having a gate electrode layer stacked on the common source line 614, a channel structure 616 passing through the gate stack structure 615, and a bit line 617 electrically connected to the channel structure 616 are arranged. Each of the memory chips MC may include a through wiring 618 connected to the peripheral circuitry in the first structure 612 and extending from the second structure 613.

[0091] However, in Figure 8 In the example embodiment shown, the memory chips MC can be stacked alternately without step differences in each of the first group 610 and the second group 620. Therefore, the memory chips MC can be connected to each other via through wiring 618 instead of the first wiring W1 or the second wiring W2. Figure 8 In the example embodiment shown, with Figure 6 and Figure 7 The through-wires 418 and 518 shown in the example are different; the through-wire 618 can be a through-silicon via (TSV) for connecting stacked memory chips MC.

[0092] The method of connecting the memory chip MC of each of the first group 610 and the second group 620 to the buffer chip 630 can be the same as that described in reference. Figure 6 The examples described are similar. The memory chips MC of the first group 610 can be directly connected to the buffer chip 630 via the first wiring W1. For example, the first wiring W1 can be connected to the first chip pad 631 formed on the upper surface of the buffer chip 630. The memory chips MC of the second group 620 can be connected to the buffer chip 630 via the second wiring W2 and a signal path provided by a portion of the redistribution layers 642 and 644 formed in the package substrate 660. As an example, the memory chips MC of the second group 620 can be connected to the second chip pad 632 formed on the lower surface of the buffer chip 630 via a signal path provided by a portion of the redistribution layers 642 and 644.

[0093] Reference Figure 9The memory package 700 according to at least one example embodiment may include a plurality of memory chips MC, a buffer chip 750, and a package substrate 760. The plurality of memory chips MC may be divided into a first group 710 to a fourth group 740, and the memory chips MC in each of the first group 710 to the fourth group 740 may be stacked alternately. For example, the memory chips MC in the first group 710 and the third group 730 may be stacked alternately, while the memory chips MC in the second group 720 and the fourth group 740 may be stacked alternately.

[0094] Each of the memory chips MC may include a semiconductor substrate 711 and a first structure 712 and a second structure 713 stacked on the semiconductor substrate 711. For example, the first structure 712 may include a peripheral circuit region, such as a peripheral circuitry required for the operation of each of the memory chips MC, which is arranged in the peripheral circuitry region, such as a row decoder, a page buffer, and a voltage generator. The second structure 713 may include a cell region in which a common source line 714, a gate stack structure 715 having a gate electrode layer stacked on the common source line 714, a channel structure 716 passing through the gate stack structure 715, and a bit line 717 electrically connected to the channel structure 716 are arranged. Each of the memory chips MC may include a through wiring 718 connected to the peripheral circuitry in the first structure 712 and extending from the second structure 713.

[0095] Memory chips MC arranged at the upper part of the package substrate 760, such as the first group 710 and the second group 720, can be connected to the buffer chip 750 via wirings W1 and W2. For example, the memory chips MC of the first group 710 can be directly connected to the buffer chip 750 via the first wiring W1, while the memory chips MC of the second group 720 can be connected to the buffer chip 750 via the second wiring W2 and a signal path provided by at least a portion of the redistribution layers 762 and 764 arranged in the package substrate 760.

[0096] Memory chips MC arranged at their lower positions in a direction perpendicular to the upper surface of the package substrate 760, such as the memory chips MC of the third group 730 and the fourth group 740, can be connected to the buffer chip 750 without using wirings W1 and W2. For example, the memory chips MC of each of the third group 730 and the fourth group 740 can be connected to the buffer chip 750 via a signal path provided by at least a portion of the redistribution layers 762 and 764 without using wiring. In some example embodiments, taking into account the arrangement of the redistribution layers 762 and 764 that provide the signal path, the upper bonding pad 761 connected to the second wiring W2 and the upper bonding pad 761 connected to the memory chip MC of the fourth group 740 can be isolated from each other in a direction parallel to the upper surface of the package substrate 760.

[0097] The structure of the memory chip MC can be compared with a reference. Figures 6 to 9 The foregoing example embodiments are similar. However, the structures of the memory chips MC included in the first group 710 and the second group 720 may differ from those of the memory chips MC included in the third group 730 and the fourth group 740. For example, the memory chips MC of the first group 710 and the second group 720, which are arranged on the upper part of the relative portion, can be connected to the input / output pads 719 arranged above the memory chips MC via through wiring 718. The memory chips MC of the third group 730 and the fourth group 740 can be connected to the input / output pads 719 formed below the memory chips MC via through wiring 718.

[0098] Figure 10 This is a view showing the appearance of a storage device according to at least one example embodiment.

[0099] According to the example embodiment Figure 10 The storage device 800 shown can be implemented using a solid-state drive (SSD). The storage device 800 can have a form factor compliant with the M.2 standard and can communicate with external central processing units, systems-on-a-chip, application processors, etc., according to the Peripheral Component Interconnect Fast (PCIe) protocol. In the example embodiment, the form factor of the storage device 800 and the protocol used for communication with other external devices can be varied. For example, the storage device 800 can have a form factor such as a 2.5-inch disk drive and can communicate with other external devices according to the Serial Advanced Technology Attachment (SATA) protocol.

[0100] Storage device 800 may include a system substrate 801, connector pins 802 formed on the system substrate 801, component elements 803, a device controller 810 mounted on the system substrate 801, a memory package 820, a DRAM 830, and a PMIC 840. Connector pins 802 may contact pins of a computer device on which storage device 800 is mounted and / or contact pins of a server device. Component elements 803 may include passive components, such as resistors and capacitors required for the operation of storage device 800.

[0101] Device controller 810 can control storage device 800 according to control commands from computer equipment and / or server equipment. Device controller 810 can store data received through connector pin 802 in memory package 820 and / or DRAM 830, or can read data stored in memory package 820 and / or DRAM 830, and can output data to computer equipment and / or server equipment. PMIC 840 can distribute power supplied through connector pin 802 to device controller 810, memory package 820, and DRAM 830.

[0102] Each of the memory packages 820 can be implemented as the memory package described in the foregoing example embodiments. For example, at least one of the memory packages 820 may include a buffer chip and a plurality of memory chips. In example embodiments, only one of the memory packages 820 may include a buffer chip, while other memory packages may include only memory chips. In some example embodiments, the memory chips included in different memory packages 820 may share a buffer chip included in one of the memory packages 820.

[0103] To enable memory chips included in different memory packages 820 to share a buffer chip included in one of the memory packages 820, wiring for connecting the memory chips included in the different memory packages 820 may be necessary. In at least one example embodiment, a portion of the wiring formed in the system substrate 801 can be used as a redistribution layer for connecting the memory chips included in the different memory packages 820. In the following description, reference will be made to... Figure 11 and Figure 12 Describe the configuration in more detail.

[0104] Figure 11 and Figure 12 This is a view showing a storage device according to at least one example embodiment.

[0105] Reference Figure 11The storage device 900 according to at least one example embodiment may include memory packages 910 and 920, a device controller 930, and a system substrate 940. The device controller 930 may be mounted on the system substrate 940 via chip bumps 935, and the memory packages 910 and 920 may be mounted on the system substrate 940 via package bumps 918 and 928. The device controller 930 and the memory packages 910 and 920 may be electrically connected to each other via wiring 942 formed in the system substrate 940 and may exchange signals with each other. As an example, signals generated by the device controller 930 to control the memory packages 910 and 920, and data stored in the memory chips (arranged in the memory packages 910 and 920), may be transmitted to the memory chips via wiring 942 and buffer chips 915 and 925.

[0106] Memory packages 910 and 920 may have the same configuration. Taking the first memory package 910 as an example, a plurality of memory chips, a buffer chip 915, and a first package substrate 916 may be included in the first memory package 910. The buffer chip 915 and the plurality of memory chips may be covered by a protective layer 919 disposed on the first package substrate 916. Taking the second memory package 920 as an example, a plurality of memory chips, a buffer chip 925, and a second package substrate 926 may be included in the second memory package 920. The buffer chip 925 and the plurality of memory chips included in the second memory package 920 may be covered by a protective layer 929 disposed on the second package substrate 926.

[0107] Multiple memory chips in a first memory package 910 can be divided into multiple groups 911 to 914 and connected to a buffer chip 915. The buffer chip 915 can allocate channels to the multiple groups 911 to 914 and coordinate signal transmission and reception between the device controller 930 and the multiple memory chips. For example, the memory chips in the first group 911 to the fourth group 914 can be connected to the first to fourth channels of the buffer chip 915, respectively. In each of the multiple groups 911 to 914, the memory chips can be stacked alternately and connected to each other via through-wires (such as through-silicon vias) through the memory chips. In an example embodiment, the memory chips included in each of the multiple groups 911 to 914 can be connected to each other via wiring other than through-wires.

[0108] exist Figure 11In the illustrated example embodiment, the memory chips in the first group 911 and the second group 912, located at the upper part of the buffer chip 915, can be connected to the buffer chip 915 via a first wiring W1 and a second wiring W2. The memory chips in the first group 911 can be directly connected to the buffer chip 915 via the first wiring W1. The memory chips in the second group 912 can be connected to the buffer chip 915 via the second wiring W2 and a redistribution layer 917 disposed in the first package substrate 916. The memory chips in the third group 913 and the fourth group 914, located at the lower part of the buffer chip 915, can be connected to the buffer chip 915 via the redistribution layer 917 disposed in the first package substrate 916. To ensure connection paths with the memory chips in the first group 911 to the fourth group 914, chip pads can be formed on both the upper and lower surfaces of the buffer chip 915.

[0109] As an example, the redistribution layer 917 can be electrically isolated from the package bump 918. The redistribution layer 917 can connect the memory chip included in the third group 913 and the fourth group 914 in the first memory package 910 to the buffer chip 915. Therefore, the redistribution layer 917 may not be electrically connected to the package bump 918, which is used to connect the memory package 910 to the system substrate 940 and other components mounted on the system substrate 940, such as the device controller 930.

[0110] Encapsulation bumps 918 can be formed on the lower surface of the first package substrate 916, and the encapsulation bumps 918 can be connected to the chip bumps 935 of the device controller 930 via the upper bonding pads 941 and wiring 942 of the system substrate 940. Therefore, the first memory package 910 can be connected to the device controller 930.

[0111] exist Figure 11In the illustrated example embodiment, the structure of the second memory package 920 can be the same as that of the first memory package 910. Therefore, elements 921 to 929 included in the second memory package 920 can correspond to elements 911 to 919 included in the first memory package 910. For example, multiple memory chips in the second memory package 920 can be divided into multiple groups 921 to 924 and can be connected to a buffer chip 925. The buffer chip 925 can allocate channels to the multiple groups 921 to 924 and can coordinate signal transmission and reception between the device controller 930 and the multiple memory chips. For example, the memory chips in the fifth group 921 to the eighth group 924 can be connected to the fifth to eighth channels of the buffer chip 925, respectively. In each of the multiple groups 921 to 924, the memory chips can be stacked alternately and connected to each other via through-wires (such as through-silicon vias). In the illustrated embodiment, the memory chips included in each of the multiple groups 921 to 924 can be connected to each other via wiring other than through-wires.

[0112] exist Figure 11 In the illustrated example embodiment, the memory chips in the fifth group 921 and the sixth group 922, located at the upper relative positions, can be connected to the buffer chip 925 via the third wiring W3 and the fourth wiring W4. The memory chips in the fifth group 921 can be directly connected to the buffer chip 925 via the third wiring W3. The memory chips in the sixth group 922 can be connected to the buffer chip 925 via the fourth wiring W4 and the redistribution layer 927 arranged in the second packaging substrate 926. The memory chips in the seventh group 923 and the eighth group 924, located at the lower relative positions, can be connected to the buffer chip 925 via the redistribution layer 927 arranged in the second packaging substrate 926. To ensure connection paths with the memory chips in the fifth group 921 to the eighth group 924, chip pads can be formed on both the upper and lower surfaces of the buffer chip 925.

[0113] As an example, the redistribution layer 927 can be electrically isolated from the package bump 928. The redistribution layer 927 can connect the memory chips included in the seventh group 923 and the eighth group 924 of the second memory package 920 to the buffer chip 925. Therefore, the redistribution layer 927 may not be electrically connected to the package bump 928, which is used to connect the second memory package 920 to the system substrate 940 and other components mounted on the system substrate 940, such as the device controller 930.

[0114] Encapsulation bumps 928 can be formed on the lower surface of the second package substrate 926, and the encapsulation bumps 928 can be connected to the chip bumps 935 of the device controller 930 via the upper bonding pads 941 and wiring 942 of the system substrate 940. Therefore, the second memory package 920 can be connected to the device controller 930.

[0115] According to Figure 12 In the storage device 900A of the example embodiment shown, the first memory package 910A and the second memory package 920A may have different structures. (Refer to...) Figure 12 Only the first memory package 910A may include a buffer chip 915A, while the second memory package 920A may include only a plurality of memory chips divided into multiple groups 921 to 924. The plurality of memory chips included in the second memory package 920A can be connected to the buffer chip 915A of the first memory package 910A via the second package substrate 926 and the system substrate 940. For example, the memory chips of the second memory package 920A can be connected to the buffer chip 915A via a redistribution layer provided by a portion of the wiring 942 of the system substrate 940. Therefore, signals and / or data generated by the device controller 930 to control the second memory package 920A can be sent to the memory chips of the second memory package 920A via the buffer chip 915A of the first memory package 910A.

[0116] exist Figure 12 In the example embodiment shown, the buffer chip 915A can control the ratio Figure 11 The buffer chip 915 described in the foregoing example embodiment shown has a greater number of channels. As an example, the buffer chip 915A can control the memory chips in the first group 911 to the fourth group 914 included in the first memory package 910A via the first to fourth channels, and can control the memory chips in the fifth group 921 to the eighth group 924 included in the second memory package 920A via the fifth to eighth channels. The buffer chip 915A can select at least one of the first to eighth channels by referring to an address signal in the signals received from the device controller 930, and can send signals and data to the selected channel, or can receive data from the memory chip through the selected channel and transmit the data to the device controller 930.

[0117] Figure 13 This is a view showing the appearance of a storage device according to at least one example embodiment.

[0118] Similar to a reference Figure 10 The described example embodiments, according to Figure 13The storage device 1000 shown in the example embodiment can be implemented using a solid-state drive (SSD). The storage device 1000 can communicate with external central processing units, systems-on-a-chip, application processors, etc. The form factor of the storage device 1000 and the protocol used for communicating with external devices can be changed.

[0119] Storage device 1000 may include a system substrate 1001, connector pins 1002 and component 1003 formed on the system substrate 1001, a device controller 1010 mounted on the system substrate 1001, a memory package 1020, a DRAM 1030, and a PMIC 1040. Figure 13 In the example embodiment shown, the memory package 1020 can be mounted on both surfaces of the system substrate 1001.

[0120] The capacity of the storage device 1000 can be increased by mounting memory packages 1020 on both surfaces of the system substrate 1001. In an example embodiment, each memory package 1020 may include a buffer chip, or alternatively, only at least one memory package 1020 may include a buffer chip. In some example embodiments, memory chips in memory packages 1020 that do not include a buffer chip may share that buffer chip. For example, memory chips in memory packages 1020 mounted on a first surface of the system substrate 1001 and memory chips in memory packages 1020 mounted on a second surface may share a single buffer chip through a redistribution layer arranged in the system substrate 1001. (Refer to...) Figures 14 to 16 Describe the configuration in more detail.

[0121] Figures 14 to 16 This is a view showing a storage device according to at least one example embodiment.

[0122] Reference Figure 14 A storage device 1100 according to at least one example embodiment may include memory packages 1110 and 1120, a device controller 1130, and a system substrate 1140. The device controller 1130 may be mounted on the system substrate 1140 via chip bumps 1135, and the memory packages 1110 and 1120 may be mounted on two surfaces of the system substrate 1140 respectively via package bumps 1118 and 1128. As an example, a first memory package 1110 may be mounted together with the device controller 1130 on a first surface of the system substrate 1140, and a second memory package 1120 may be mounted on a second surface of the system substrate 1140. Figure 14 As shown, the first surface and the second surface can be opposite each other.

[0123] Device controller 1130 and memory packages 1110 and 1120 can be electrically connected to each other via wiring 1142 formed in system substrate 1140 and can exchange signals. As an example, signals generated by device controller 1130 to control memory packages 1110 and 1120 and data exchanged with memory packages 1110 and 1120 can be transmitted via wiring 1142.

[0124] Memory packages 1110 and 1120 can have the same configuration. Taking the first memory package 1110 as an example, a plurality of memory chips, a buffer chip 1115, and a first package substrate 1116, divided into four groups 1111 to 1114, can be included in the first memory package 1110. The buffer chip 1115 and the plurality of memory chips can be covered by a protective layer 1119 disposed on the first package substrate 1116. The method of connecting the plurality of memory chips to the buffer chip 1115 can be the same as described in the reference. Figure 11 The examples described are similar.

[0125] Device controller 1130 can generate signals including control commands for storing or retrieving data from a memory chip, and can send these signals to at least one of buffer chips 1115 and 1125. Buffer chips 1115 and 1125 can send control commands for storing or retrieving data to at least one of the memory chips based on address information included in the received signals.

[0126] exist Figure 14 In the example embodiment shown, the first buffer chip 1115 and the second buffer chip 1125 can control the memory chip through the same number of channels. (Refer to...) Figure 14 In each of memory packages 1110 and 1120, the memory chips can be divided into four groups. For example, the memory chips in the first groups 1111 and 1121 can be connected to the first buffer chip 1115 and the second buffer chip 1125 via wirings W1 and W2, respectively. Furthermore, the memory chips in the second to fourth groups 1112, 1113, 1114, 1122, 1123, and 1124 can be connected to the first buffer chip 1115 and the second buffer chip 1125 via redistribution layers 1117 and 1127 disposed in package substrates 1116 and 1126. Therefore, each of the first buffer chip 1115 and the second buffer chip 1125 can coordinate the transmission and reception of signals between the memory chip and the device controller 1130 via four channels.

[0127] Reference Figure 15The storage device 1200 according to at least one example embodiment may include memory packages 1210 and 1220, a device controller 1230, and a system board 1240. Figure 15 In the example embodiment shown, the structures of the first memory package 1210 and the second memory package 1220 may differ. For example, the first memory package 1210 may include a buffer chip 1215, while the second memory package 1220 may not include a buffer chip. The first memory package 1210 may have the same structure as... Figure 14 The memory package in the example embodiment shown has a similar structure, therefore, the elements 1211, 1212, 1213, 1214, 1215, 1216, 1217, 1218 and 1219 included in the first memory package 1210 can be similar to the elements 1111-1119 described above.

[0128] The memory chips in the second memory package 1220, excluding the buffer chip, can be divided into four groups 1221, 1222, 1223, and 1224, and can be connected to the buffer chip 1215 of the first memory package 1210 via wiring 1242 arranged in the system substrate 1240. The memory chips in the second memory package 1220 can be covered by a protective layer 1229. The device controller 1230 can send signals including control commands for controlling the memory chips in the second memory package 1220 to the buffer chip 1215, and the buffer chip 1215 can send the signals to the memory chips in the second memory package 1220 with reference to the address information included in the signals. The memory chips in the second memory package 1220 can be connected to chip pads formed on the lower surface of the buffer chip 1215 via wiring 1242 arranged in the system substrate 1240, redistribution layers 1217 and 1227 arranged in the package substrates 1216 and 1226, and chip bumps 1218.

[0129] Therefore, in Figure 15 In the example embodiment shown, with Figure 14 The example embodiment shown differs from the one illustrated; the number of channels connecting a single buffer chip 1215 to the memory chip can be increased. Figure 15 In the example embodiment shown, the memory chips in each of memory packages 1210 and 1220 can be divided into four groups, so that buffer chip 1215 can be connected to the memory chips through eight channels. Buffer chip 1215 may include selection circuitry that can select at least one of the eight channels.

[0130] Reference Figure 15A portion of the memory chip in the first memory package 1210 can be connected to the buffer chip 1215 via a first wiring W1. A portion of the memory chip in the second memory package 1220 (e.g., memory chips in the first group 1221 and the second group 1222) can be connected to the lower bonding pad 1243 of the system substrate 1240 via a second wiring W2 and a third wiring W3. In at least one example embodiment, the second wiring W2 can be configured to connect one of the memory chips to the second package substrate 1226, and the third wiring W3 can be configured to connect the second package substrate 1226 to the system substrate 1240. The length of the third wiring W3 can be shorter than the lengths of the first wiring W1 and the second wiring W2. In an example embodiment, without the third wiring W3, the memory chip in the second memory package 1220 can be connected to the wiring 1242 of the system substrate 1240 via a redistribution layer 1227 and package bumps 1228 disposed in the second package substrate 1226.

[0131] Reference Figure 16 The storage device 1300 according to at least one example embodiment may include memory packages 1310 and 1320, a device controller 1330, and a system board 1340. The memory packages 1310 and 1320 may be attached to the system board 1340 via package bumps 1318 and 1328. Figure 16 In the example embodiment shown, the structures of the first memory package 1310 and the second memory package 1320 may differ. As an example, the first memory package 1310 may include a buffer chip 1315, while the second memory package 1320 may not include a buffer chip.

[0132] For example, in each of memory packages 1310 and 1320, the memory chips can be divided into four groups: 1311, 1312, 1313, 1314 and 1321, 1322, 1323, 1324. In the first memory package 1310, the memory chips in the first group 1311 and the second group 1312 can be connected to the buffer chip 1315 via a first wiring W1, while the memory chips in the third group 1313 and the fourth group 1314 can be connected to the buffer chip 1315 via a redistribution layer 1317 of the first package substrate 1316. In each group from the first group 1311 to the fourth group 1314, the memory chips can be interconnected with each other via through wiring such as through-silicon vias (TSVs).

[0133] Each memory chip in the second memory package 1320 can be connected to the system substrate 1340 via a second wiring W2. Furthermore, the memory chips included in each of the first groups 1321 to the fourth groups 1324 of the second memory package 1320 can also be interconnected with each other via the second wiring W2 instead of through wiring. The memory chips can be arranged in a stepped shape with a step difference in at least one direction, such that the memory chips can be interconnected with each other via the second wiring W2. Therefore, as... Figure 16 As shown, the structures of the first memory package 1310 and the second memory package 1320 can be different.

[0134] With reference Figure 15 Similar to the aforementioned example embodiments, in Figure 16 In the illustrated example embodiment, the memory chip of the second memory package 1320 can be connected to wiring 1342 arranged in the system substrate 1340 via second wiring W2 and third wiring W3, and can be connected to the buffer chip 1315 via wiring 1342. The second wiring W2 can be configured to connect the memory chip to the redistribution layer 1327 of the second package substrate 1326, while the third wiring W3 can be configured to connect the second package substrate 1326 to the system substrate 1340. The length of the second wiring W2 can be longer than the length of the third wiring W3.

[0135] Reference Figure 16 The memory chip in the second memory package 1320 can be connected to wiring 1342 arranged in the system substrate 1340 via package bumps 1328. In other words, as Figure 16 As shown, the memory chip in the second memory package 1320 can be connected to the wiring 1342 arranged in the system substrate 1340 via the package bump 1328 instead of the third wiring W3, and can be connected to the buffer chip 1315. However, the example embodiment is not limited to this, as... Figure 15 As shown, the memory chip in the second memory package 1320 can be connected to wiring arranged in the system substrate 1340 via the third wiring W3.

[0136] Figure 17 It is a storage device suitable for memory packaging and storage devices according to at least one example embodiment.

[0137] Reference Figure 17The memory device 1400 may have a chip-to-chip (C2C) structure. In a C2C structure, an upper chip including cell regions (CELL) can be fabricated on a first wafer, and a lower chip including peripheral circuit regions (PERI) can be fabricated on a second wafer different from the first wafer. The upper and lower chips can be connected to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting bonding metal formed on the uppermost metal layer of the upper chip to bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a copper-to-copper bonding method, and the bonding metal may be formed of aluminum or tungsten.

[0138] Each of the peripheral circuit region PERI and cell region CELL of the storage device 1400 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0139] The Peripheral Circuit Region (PERI) may include a first substrate 1510, an interlayer insulating layer 1515, a plurality of circuit elements 1520a, 1520b, and 1520c formed on the first substrate 1510, first metal layers 1530a, 1530b, and 1530c connected to the plurality of circuit elements 1520a, 1520b, and 1520c, and second metal layers 1540a, 1540b, and 1540c formed on the first metal layers 1530a, 1530b, and 1530c. In at least one example embodiment, the first metal layers 1530a, 1530b, and 1530c may be formed of tungsten, which has relatively high resistance, while the second metal layers 1540a, 1540b, and 1540c may be formed of copper, which has relatively low resistance.

[0140] In the exemplary embodiment, only the first metal layers 1530a, 1530b, and 1530c and the second metal layers 1540a, 1540b, and 1540c are shown and described, but the exemplary embodiment is not limited thereto. At least one or more metal layers may be formed on the second metal layers 1540a, 1540b, and 1540c. At least a portion of the one or more metal layers formed on the second metal layers 1540a, 1540b, and 1540c may be formed of aluminum, which has a lower resistivity than the copper used to form the second metal layers 1540a, 1540b, and 1540c.

[0141] Interlayer insulating layer 1515 may be disposed on first substrate 1510 to cover multiple circuit elements 1520a, 1520b and 1520c, first metal layers 1530a, 1530b and 1530c, and second metal layers 1540a, 1540b and 1540c, and may include insulating material such as silicon oxide or silicon nitride.

[0142] The lower bonding metals 1571b and 1572b can be formed on the second metal layer 1540b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1571b and 1572b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1671b and 1672b of the cell region CELL by a bonding method, and the lower bonding metals 1571b and 1572b and the upper bonding metals 1671b and 1672b can be formed of aluminum, copper or tungsten.

[0143] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 1610 and a common source line 1620. Multiple word lines 1631, 1632, 1633, 1634, 1635, 1636, 1637, and 1638 (1630) may be stacked on the second substrate 1610 in a direction perpendicular to the upper surface of the second substrate 1610 (Z-axis direction). Serial select lines and ground select lines may be arranged above and below the word lines 1630, and multiple word lines 1630 may be arranged between the serial select lines and the ground select lines.

[0144] In the bit line bonding area BLBA, the channel structure CH can extend along a direction perpendicular to the upper surface of the second substrate 1610 and can pass through the word line 1630, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 1650c and the second metal layer 1660c. For example, the first metal layer 1650c may be a bit line contact, and the second metal layer 1660c may be a bit line. In at least one example embodiment, the bit line 1660c may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate 1610.

[0145] exist Figure 17 In the illustrated example embodiment, the region where the channel structure CH and bit line 1660c are arranged can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 1660c can be electrically connected to circuit element 1520c in the peripheral circuit region PERI that provides the page buffer 1693. As an example, bit line 1660c can be connected to upper bonding metals 1671c and 1672c in the peripheral circuit region PERI, and upper bonding metals 1671c and 1672c can be connected to lower bonding metals 1571c and 1572c, which are connected to circuit element 1520c of the page buffer 1693.

[0146] In the word line bonding area (WLBA), word line 1630 can extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate 1610 and can be connected to a plurality of cell contact plugs 1601, 1602, 1603, 1604, 1605, 1606, 1607 (1600). Word line 1630 and cell contact plugs 1600 can be connected to pads provided by extending at least a portion of word line 1630 by different lengths in the second direction. A first metal layer 1650b and a second metal layer 1660b can be sequentially connected to the upper portion of cell contact plug 1600 connected to word line 1630. In the word line bonding area (WLBA), cell contact plug 1600 can be connected to the peripheral circuit area (PERI) via upper bonding metals 1671b and 1672b of the cell area (CELL) and lower bonding metals 1571b and 1572b of the peripheral circuit area (PERI).

[0147] The cell contact plug 1600 may be electrically connected to circuit element 1520b providing line decoder 1694 in the peripheral circuitry region PERI. In at least one example embodiment, the operating voltage of circuit element 1520b providing line decoder 1694 may be different from the operating voltage of circuit element 1520c providing page buffer 1693. For example, the operating voltage of circuit element 1520c providing page buffer 1693 may be greater than the operating voltage of circuit element 1520b providing line decoder 1694.

[0148] A common source line contact plug 1680 can be disposed in the external pad bonding region PA. The common source line contact plug 1680 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 1620. A first metal layer 1650a and a second metal layer 1660a can be sequentially stacked on the common source line contact plug 1680. For example, the region where the common source line contact plug 1680, the first metal layer 1650a, and the second metal layer 1660a are disposed can be defined as the external pad bonding region PA.

[0149] Input / output pads 1505 and 1640 can be placed within the external pad bonding area PA. (See reference...) Figure 17A lower insulating layer 1501 covering the lower surface of the first substrate 1510 may be formed below the first substrate 1510, and a first input / output pad 1505 may be formed on the lower insulating layer 1501. The first input / output pad 1505 can be connected to at least one of a plurality of circuit elements 1520a, 1520b, and 1520c arranged in the peripheral circuit region PERI via a first input / output contact plug 1503, and can be isolated from the first substrate 1510 by the lower insulating layer 1501. In addition, a side insulating layer may be disposed between the first input / output contact plug 1503 and the first substrate 1510 and can electrically isolate the first input / output contact plug 1503 from the first substrate 1510.

[0150] Reference Figure 17 An upper insulating layer 1601 covering the upper surface of the second substrate 1610 may be formed on the second substrate 1610, and a second input / output pad 1640 may be disposed on the upper insulating layer 1601. The second input / output pad 1640 may be connected to at least one of a plurality of circuit elements 1520a, 1520b and 1520c disposed in the peripheral circuit region PERI via a second input / output contact plug 1680.

[0151] In the example embodiment, the second substrate 1610 and the common source line 1620 may not be arranged in the region where the second input / output contact plug 1680 is disposed. Furthermore, the second input / output pad 1640 may not overlap with the word line 1630 in the third direction (Z-axis direction). See also... Figure 17 The second input / output contact plug 1680 can be isolated from the second substrate 1610 in a direction parallel to the upper surface of the second substrate 1610, and can penetrate the interlayer insulating layer 1645 of the cell region to connect to the second input / output pad 1640.

[0152] In an example embodiment, the first input / output pad 1505 and the second input / output pad 1640 may be selectively formed. For example, the storage device 1400 may include only the first input / output pad 1505 disposed on the first substrate 1510, or it may include only the second input / output pad 1640 disposed on the second substrate 1610. Alternatively, the storage device 1400 may include both the first input / output pad 1505 and the second input / output pad 1640.

[0153] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and peripheral circuit area PERI respectively, the metal pattern of the uppermost metal layer can be set as a dummy pattern, or the uppermost metal layer can be empty.

[0154] The storage device 1400 may include a lower metal pattern 1573a on the uppermost metal layer of the peripheral circuit region PERI, having the same shape as the upper metal pattern 1672a of the cell region CELL, to correspond to the upper metal pattern 1672a formed on the uppermost metal layer of the cell region CELL. The lower metal pattern 1573a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to the contacts in the peripheral circuit region PERI. Similarly, in the external pad bonding region PA, an upper metal pattern with the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed on the upper metal layer of the cell region CELL, to correspond to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI.

[0155] Lower bonding metals 1571b and 1572b can be formed on the second metal layer 1540b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1571b and 1572b of the peripheral circuit region PERI can be electrically connected to each other with the upper bonding metals 1671b and 1672b of the cell region CELL by bonding methods.

[0156] Furthermore, in the bit line bonding area (BLBA), an upper metal pattern with the same shape as the lower metal pattern 1552 of the peripheral circuit area (PERI) can be formed on the uppermost metal layer of the cell region (CELL) to correspond to the lower metal pattern 1552 formed on the uppermost metal layer of the peripheral circuit area (PERI) in the bit line bonding area (BLBA). No contact portion may be formed on the upper metal pattern 1692 formed on the uppermost metal layer of the cell region (CELL).

[0157] according to Figure 17 The storage device 1400 of the example embodiment shown can be applied to the memory packages and storage devices described in the foregoing embodiments. For example, refer to... Figure 17 The described memory device 1400 can be used as a memory chip MC. Figure 8 The memory package 600 is shown in the example embodiment. As an example, the memory chips MC included in the first group 610 or the second group 620 can be stacked alternately and can be electrically connected to each other via input / output pads.

[0158] According to the foregoing example embodiments, the redistribution layer of the packaging substrate can be used to increase the number of memory chips connected to a single buffer chip, thus effectively increasing the storage space of the memory package. Furthermore, different memory packages can share a single buffer chip using the redistribution layer of the system substrate included in the storage device, and the storage space of the storage device can be increased without increasing the number of buffer chips and / or device controllers.

[0159] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A memory package, comprising: A packaging substrate includes a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including multiple signal paths; A buffer chip is mounted on the packaging substrate and includes multiple chip pads corresponding to multiple memory channels; as well as Multiple memory chips are stacked on the packaging substrate and divided into multiple groups corresponding to the multiple memory channels. The buffer chip includes: a plurality of unit transmission circuits corresponding to and connected to the plurality of chip pads of the plurality of memory channels; and a selection circuit for selecting and activating at least one of the plurality of unit transmission circuits in response to a selection signal received from an external device controller, wherein each of the plurality of unit transmission circuits is connected to a memory chip corresponding to the single memory channel via a single memory channel of the plurality of memory channels. Among them, the first group of memory chips, corresponding to the first memory channel among the plurality of memory channels, is connected to the first chip pad corresponding to the first memory channel among the plurality of chip pads via a first wiring, and The second group of memory chips, which corresponds to the second memory channel among the plurality of memory chips, is connected to the second chip pad corresponding to the second memory channel among the plurality of chip pads through a second wiring and at least a portion of the signal paths among the plurality of signal paths.

2. The memory package according to claim 1, wherein, The buffer chip is configured to send control commands received from the external device controller to two or more groups corresponding to two or more memory channels among the plurality of memory channels.

3. The memory package according to claim 1, wherein, The third group of memory chips in the plurality of memory chips is connected to the third chip pad in the plurality of chip pads via a third wiring.

4. The memory package according to claim 3, wherein, The fourth group of memory chips in the plurality of memory chips is connected to the fourth chip pad in the plurality of chip pads via a fourth wiring and another part of the signal paths that is different from the at least part of the signal paths.

5. The memory package according to claim 1, wherein, The number of memory chips in the first group is the same as the number of memory chips in the second group.

6. The memory package according to claim 1, wherein, The first group of memory chips and the second group of memory chips are arranged at different positions in a direction parallel to the upper surface of the packaging substrate.

7. The memory package according to claim 6, wherein, The first group of memory chips and the second group of memory chips are arranged at the same height in a direction perpendicular to the upper surface of the packaging substrate.

8. The memory package according to claim 1, wherein, The first group of memory chips are connected to each other by through wiring, and the through wiring is connected to the first wiring.

9. The memory package according to claim 1, in, The plurality of chip pads includes upper chip pads disposed on the upper surface of the buffer chip and lower chip pads disposed on the lower surface of the buffer chip, and The upper chip pad includes the first chip pad.

10. The memory package according to claim 9, wherein, The lower chip pad includes the second chip pad, and the second chip pad is directly connected to the at least part of the signal path.

11. The memory package according to claim 9, in, The third group of memory chips in the plurality of memory chips is arranged between the second group of memory chips and the packaging substrate, and The third group of memory chips is connected to the third chip pad included in the lower chip pad through another part of the multiple signal paths.

12. A storage device, comprising: System substrate; The device controller circuit is mounted on the system base plate; as well as Multiple memory packages are mounted on the system substrate and configured to operate in response to control commands received from the device controller circuitry. Each of the plurality of memory packages includes: a package substrate connected to the system substrate; a buffer chip mounted on the package substrate and configured to receive the control command from the device controller circuitry and output the control command to at least one of the plurality of memory channels; and a plurality of memory chips connected to the buffer chip through the plurality of memory channels. The buffer chip includes: a plurality of unit transmission circuits corresponding to the plurality of memory channels; and a selection circuit for selecting and activating at least one of the plurality of unit transmission circuits in response to a selection signal received from the device controller circuit, wherein each of the plurality of unit transmission circuits is connected to a memory chip corresponding to the single memory channel via a single memory channel among the plurality of memory channels. Among them, the first group of memory chips, corresponding to the first memory channel among the multiple memory channels, is electrically connected to the buffer chip through a first wiring, and The second group of memory chips, which corresponds to the second memory channel among the plurality of memory channels, is electrically connected to the buffer chip via a second wiring and a redistribution layer arranged in the packaging substrate.

13. The storage device according to claim 12, The buffer chip includes a plurality of chip pads, and the plurality of chip pads include an upper chip pad disposed on the upper surface of the buffer chip and a lower chip pad disposed on the lower surface of the buffer chip. in, The upper chip pad is electrically connected to the first group of memory chips through the first wiring, and The lower chip pad is electrically connected to the second group of memory chips through the second wiring and the redistribution layer.

14. The storage device according to claim 12, in, The first group of memory chips are connected to each other via the first wiring, and The second group of memory chips are connected to each other via the second wiring.

15. The storage device according to claim 12, wherein, The first group of memory chips is connected to each other through a first through-silicon via (TSV), while the second group of memory chips is connected to each other through a second TSV.

16. The storage device according to claim 12, in, Each of the plurality of memory packages is mounted on the system substrate by a plurality of package bumps formed on the lower surface of the package substrate, and The encapsulation bumps and the redistribution layer are electrically isolated from each other.

17. A storage device, comprising: The system substrate includes a redistribution layer; The device controller circuit is mounted on the system base plate; as well as Multiple memory packages are mounted on the system substrate and configured to operate in response to control commands received from the device controller circuitry. Each of the memory packages includes a package substrate connected to the system substrate and including multiple bonding pads, and multiple memory chips mounted on the package substrate. At least one of the memory packages includes a buffer chip, which is connected to the memory chip via multiple channels and sends control commands received from the device controller circuitry to the memory chip via at least one of the multiple channels. The buffer chip includes: a plurality of chip pads; a plurality of unit transmission circuits corresponding to and connected to the plurality of channels and the plurality of chip pads; and a selection circuit for selecting and activating at least one of the plurality of unit transmission circuits in response to a selection signal received from the device controller circuit, wherein each of the plurality of unit transmission circuits is connected to a memory chip corresponding to the single channel via a single channel of the plurality of channels, and Wherein, at least one of the plurality of chip pads is connected to a memory chip in a memory package that does not include the buffer chip in the memory package via wiring and the redistribution layer.

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