Electromigration test structure and forming method, electromigration test method, memory

Abstract

The present application relates to the technical field of semiconductor manufacturing, and in particular to an electromigration test structure, a forming method thereof, an electromigration test method and a memory. The electromigration test structure comprises a storage region and a peripheral region outside the storage region; the electromigration test structure further comprises: a test layer, which is continuously distributed in the storage region and the peripheral region; an interconnection structure, which is located in the storage region and comprises an interconnection layer and a semiconductor layer, one end of the interconnection layer being connected to the test layer and the other end being connected to the semiconductor layer; and a monitoring structure, which is located in the peripheral region, connected to the test layer and distributed on opposite two outer sides of the interconnection layer, and used for monitoring resistance change of the test layer. The present application avoids the influence of resistance inside the interconnection structure on resistance monitoring of the test layer, and improves the accuracy and reliability of electromigration test results.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electromigration test structure and its formation method, an electromigration test method, and a memory. Background Technology

[0002] In recent years, with the continuous miniaturization and increasing integration of semiconductor devices, the current drawn during operation has been constantly increasing. Electromigration (EM) has become one of the bottlenecks in the reliability of semiconductor devices. Electromigration refers to the phenomenon where current flows through the metal lines of an integrated circuit in a semiconductor device, causing metal ions to be transported under the influence of this current. Consequently, some parts of the metal lines may develop voids due to electromigration, leading to open circuits, while other parts may develop hillocks, causing short circuits.

[0003] Current electromigration testing of test structures primarily involves applying a constant current to the test structure. Driven by an electron wind, conductive particles (such as Cu or Al atoms) migrate within the structure, creating voids. The size of these voids is determined by monitoring changes in the structure's resistance. When the resistance drops by 10%, the structure is considered to have failed, and the time to failure (TTF) is recorded. Subsequently, the Black equation is used to estimate the lifetime of the semiconductor device under operating conditions, thus enabling performance evaluation. However, current limitations of the test structure itself prevent accurate monitoring of resistance changes, reducing the accuracy and reliability of electromigration test results.

[0004] Therefore, improving the accuracy and reliability of electromigration test results is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides an electromigration test structure and its formation method, as well as an electromigration test method, to solve the problem of low accuracy and reliability of electromigration test results in the prior art.

[0006] To address the above problems, the present invention provides an electromigration test structure, including a storage region and a peripheral region located outside the storage region; the electromigration test structure further includes: The test layer is continuously distributed in the storage area and the peripheral area; An interconnect structure, located in the memory region, includes an interconnect layer and a semiconductor layer, wherein one end of the interconnect layer is connected to the test layer and the other end is connected to the semiconductor layer; A monitoring structure, located in the peripheral area, is connected to the test layer and distributed on the opposite outer sides of the interconnect layer, and is used to monitor the resistance change of the test layer.

[0007] Optionally, the monitoring structure includes: The contact plug and the interconnect layer both extend in a direction parallel to the semiconductor layer and pointing towards the test layer; The adapter layer has one end of the contact plug connected to the test layer and the other end connected to the adapter layer. Both the adapter layer and the semiconductor layer extend in a direction perpendicular to the semiconductor layer and pointing towards the test layer.

[0008] Optionally, the contact resistance between the contact plug and the adapter layer is less than the contact resistance between the interconnect layer and the semiconductor layer.

[0009] Optionally, the contact plug includes a first sub-contact plug and a second sub-contact plug; the electromigration test structure further includes: A first dielectric layer is located on the surface of the semiconductor layer opposite to the interconnect layer. The transition layer is located on the surface of the first dielectric layer opposite to the interconnect layer. The first sub-contact plug penetrates the first dielectric layer in a direction parallel to the semiconductor layer and points towards the test layer, and is in contact with the transition layer. The second dielectric layer is located between the semiconductor layer and the test layer. The interconnect layer penetrates the second dielectric layer in a direction parallel to the semiconductor layer and pointing towards the test layer. The second sub-contact plug penetrates the second dielectric layer and the semiconductor layer in a direction parallel to the semiconductor layer and pointing towards the test layer, and is in contact with the first sub-contact plug.

[0010] Optionally, the first medium layer is continuously distributed in the storage area and the peripheral area; The storage region includes a storage array, and the first media layer covers the storage array.

[0011] Optionally, the contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer, where the initial resistance refers to the resistance of the test layer before electromigration testing.

[0012] To address the above problems, the present invention also provides a method for forming an electromigration test structure, comprising the following steps: An interconnect structure is formed in a storage region and a monitoring structure is formed in a peripheral region outside the storage region. The interconnect structure includes a semiconductor layer and an interconnect layer located on the surface of the semiconductor layer. The monitoring structure is distributed on two opposite outer sides of the interconnect layer. A test layer is formed that is connected to both the interconnect layer and the monitoring structure and is continuously distributed in the storage area and the peripheral area. The monitoring structure is used to monitor the resistance change of the test layer.

[0013] Optionally, the specific steps of forming an interconnection structure in the storage area and a monitoring structure in the peripheral area outside the storage area include: The monitoring structure, including a contact plug and an interconnect layer, is formed in the storage region, and the interconnect structure, including the semiconductor layer and the interconnect layer, is formed in the peripheral region outside the storage region. The contact plug penetrates the semiconductor layer, and one end of the contact plug is connected to the interconnect layer, while the other end is used to connect to the test layer. Both the contact plug and the interconnect layer extend in a direction parallel to the semiconductor layer and pointing towards the test layer. Both the interconnect layer and the semiconductor layer extend in a direction perpendicular to the semiconductor layer and pointing towards the test layer.

[0014] Optionally, the specific steps of forming the monitoring structure including contact plugs and transition layers in the storage region and forming an interconnect structure including the semiconductor layer and the interconnect layer in the peripheral region outside the storage region include: Form the first dielectric layer; A first sub-contact plug is formed that penetrates the first dielectric layer; A transition layer is formed on the surface of the first dielectric layer to connect with the first sub-contact plug; The semiconductor layer is formed on the surface of the first dielectric layer opposite to the transition layer; A second dielectric layer is formed on the surface of the semiconductor layer opposite to the first dielectric layer; A second sub-contact plug is formed through the second dielectric layer and the semiconductor layer, and an interconnect layer is formed through the second dielectric layer to form the contact plug including the first sub-contact plug and the second sub-contact plug.

[0015] Optionally, the first medium layer is continuously distributed in the storage area and the peripheral area; The storage region includes a storage array, and the first media layer covers the storage array.

[0016] Optionally, the contact resistance between the contact plug and the adapter layer is less than the contact resistance between the interconnect layer and the semiconductor layer.

[0017] Optionally, the contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer, where the initial resistance refers to the resistance of the test layer before electromigration testing.

[0018] To address the above problems, the present invention also provides an electromigration testing method, comprising the following steps: A test current signal is applied to a test layer, which is continuously distributed in the memory region and the peripheral region. The test layer is connected to an interconnect structure located in the memory region. The interconnect structure includes an interconnect layer and a semiconductor layer. One end of the interconnect layer is connected to the test layer and the other end is connected to the semiconductor layer. The peripheral region is located outside the memory region. The resistance change of the test layer is monitored by a monitoring structure located in the peripheral region, distributed on the opposite sides of the interconnect layer, and connected to the test layer.

[0019] Optionally, the specific steps for applying a test current signal to a test layer include: Connect the semiconductor layer to the first external pad; The test current signal is transmitted from the first external pad, through the semiconductor layer and the interconnect layer, to the test layer.

[0020] Optionally, the monitoring structure includes a contact plug and an adapter layer. One end of the contact plug is connected to the test layer, and the other end is connected to the adapter layer. Both the contact plug and the interconnect layer extend in a direction parallel to the semiconductor layer and pointing towards the test layer. Both the adapter layer and the semiconductor layer extend in a direction perpendicular to the semiconductor layer and pointing towards the test layer. The specific steps for monitoring the resistance change of the test layer through the monitoring structure distributed on opposite outer sides of the interconnect layer and connected to the test layer include: Connect the adapter layer to the second external solder pad; The resistance change of the test layer is monitored using the second external pad.

[0021] Optionally, the contact resistance between the contact plug and the adapter layer is less than the contact resistance between the interconnect layer and the semiconductor layer.

[0022] Optionally, the contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer, where the initial resistance refers to the resistance of the test layer before electromigration testing.

[0023] To address the aforementioned problems, the present invention also provides a memory comprising a memory array wafer, the memory array wafer including the electromigration test structure as described in any of the preceding claims.

[0024] This invention provides an electromigration test structure, its formation method, an electromigration test method, and a memory. By additionally setting a monitoring structure outside the interconnect structure connected to the test layer, and making the test layer continuously distributed in the storage region and the peripheral region outside the storage region, the interconnect structure is located in the storage region, and the monitoring structure is located in the peripheral region, the monitoring structure monitors the resistance change of the test layer during the electromigration test, avoiding the influence of the internal resistance of the interconnect structure on the resistance monitoring of the test layer, and improving the accuracy and reliability of the electromigration test results. Attached Figure Description

[0025] Appendix Figure 1 This is a schematic diagram of the electromigration test structure in a specific embodiment of the present invention; Appendix Figure 2 This is a schematic diagram of the memory structure in a specific embodiment of the present invention; Appendix Figure 3 This is a flowchart illustrating the method for forming the electromigration test structure in a specific embodiment of the present invention; Appendix Figure 4 This is a flowchart of the electromigration testing method in a specific embodiment of the present invention. Detailed Implementation

[0026] The electromigration test structure and its formation method, as well as the specific implementation method of the electromigration test method provided by the present invention, will be described in detail below with reference to the accompanying drawings.

[0027] In 3D memory structures such as 3D NAND flash memory, the well region is connected to the BTM (Bottom Top Metal) via an NPU (N-well Pick Up) structure. However, the NPU is typically made of metal, while the well region is typically made of silicon, resulting in a significant contact resistance between the NPU and the well region. Currently, during electromigration testing of the BTM, the test signal is transmitted through the well region and the NPU to the BTM. The resistance change is then monitored via a pin leading from the well region; that is, the overall resistance of the BTM, NPU, and well region is being monitored. However, due to the large contact resistance between the NPU and the well region, and the fact that the resistance of the BTM is much smaller than that between the NPU and the well region, if there is a problem with the interface contact between the BTM and the NPU, and a large void is created inside the BTM due to electromigration, this cannot be detected by monitoring the resistance change, leading to low reliability and accuracy of the electromigration test results.

[0028] To improve the accuracy and reliability of electromigration test results, this specific embodiment provides an electromigration test structure, attached... Figure 1This is a schematic diagram of the electromigration test structure in a specific embodiment of the present invention. For example... Figure 1 As shown, the electromigration test structure includes a storage region CA and a peripheral region PA located outside the storage region CA; the electromigration test structure further includes: Test layer 10, which continuously distributes the storage area CA and the peripheral area PA; An interconnect structure located in the memory region CA includes an interconnect layer 11 and a semiconductor layer 12, wherein one end of the interconnect layer 11 is connected to the test layer 10 and the other end is connected to the semiconductor layer 12; A monitoring structure, located in the peripheral region PA, is connected to the test layer 10 and distributed on the two opposite outer sides of the interconnect layer 11, and is used to monitor the resistance change of the test layer 10.

[0029] Specifically, the test layer 10 can be a metal line under test. The test layer 10, the interconnect layer 11, and the semiconductor layer 12 together form the structure under test. The interconnect layer 11 extends along a first direction D1 (i.e., parallel to the direction of the semiconductor layer 12 pointing to the test layer 10), and the test layer 10 and the semiconductor layer 12 extend along a second direction D2 (i.e., perpendicular to the direction of the semiconductor layer 12 pointing to the test layer 10). The first direction D1 and the second direction D2 intersect. In this specific embodiment, the intersection can be perpendicular or oblique. This specific embodiment uses the perpendicular intersection of the first direction D1 and the second direction D2 as an example for explanation.

[0030] During the electromigration test, the test signal from the outside is transmitted to the test layer 10 through the semiconductor layer 12 and the interconnect layer 11. The resistance change of the test layer 10 is directly monitored by the monitoring structure connected to the test layer 10 and distributed on the opposite outer sides of the interconnect layer 11. That is, in this specific embodiment, the monitoring structure only monitors the resistance change of the test layer 10. The resistance inside the interconnect structure does not affect the monitoring structure's monitoring of the resistance of the test layer 10. If the interface contact between the interconnect layer 11 and the test layer 10 is abnormal, and a void is generated inside the test layer 10 due to the electromigration effect, it can be monitored in a timely and accurate manner by the monitoring structure, thereby improving the accuracy and reliability of the electromigration test results. Figure 1 The arrows in the diagram indicate the direction of electron flow during the electromigration test.

[0031] Optionally, the monitoring structure includes: Contact plug 13, the contact plug 13 and the interconnect layer 11 both extend in a direction parallel to the semiconductor layer 12 and pointing towards the test layer 10; The adapter layer 14 has one end of the contact plug 13 in contact with the test layer 10 and the other end connected to the adapter layer 14. Both the adapter layer 14 and the semiconductor layer 12 extend in a direction perpendicular to the semiconductor layer 12 and pointing towards the test layer 10.

[0032] Specifically, such as Figure 1 As shown, the monitoring structure includes the contact plugs 13 and the transition layers 14. Two contact plugs 13 are distributed on opposite sides of the interconnect structure, and two transition layers 14 are connected to the two contact plugs 13 in a one-to-one correspondence. This allows the test layer 10 to form a detection loop with the two contact plugs located on opposite sides of the interconnect structure and the two transition layers, thereby enabling the monitoring of resistance changes in the test layer 10.

[0033] This specific embodiment is illustrated by taking the example where the contact plug 13 and the interconnect layer 11 are located on the same side of the test layer 10, in order to reduce the overall volume of the electromigration test structure. In other specific embodiments, the contact plug 13 and the interconnect layer 11 may be disposed on different sides of the test layer 10 to avoid mutual interference between the signals in the contact plug 13 and the signals in the interconnect layer 11.

[0034] Optionally, the contact resistance between the contact plug 13 and the transition layer 14 is less than the contact resistance between the interconnect layer 11 and the semiconductor layer 12.

[0035] Specifically, by setting the contact resistance between the contact plug 13 and the transition layer 14 to be less than the contact resistance between the interconnect layer 11 and the semiconductor layer 12, the influence of the contact resistance between the contact plug 13 and the transition layer 14 on the resistance monitoring results of the test layer 10 can be reduced.

[0036] Optionally, the contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer 10, where the initial resistance refers to the resistance of the test layer 10 before electromigration testing.

[0037] Specifically, by ensuring that the contact resistance within the monitoring structure is less than or equal to the resistance of the test layer 10, the influence of the contact resistance within the monitoring structure on the resistance monitoring results of the test layer 10 can also be reduced. The contact resistance between the contact plug 13 and the transition layer 14 should be close to the initial resistance of the test layer 10 (i.e., the resistance before electromigration testing), for example, the difference between the contact resistance between the contact plug 13 and the transition layer 14 and the initial resistance of the test layer 10 should be less than 10 ohms. In one example, the initial resistance of the test layer 10 is 50 ohms, the contact resistance between the interconnect layer 11 and the semiconductor layer 12 is 1000 ohms, and the contact resistance between the contact plug 13 and the transition layer 14 is 50 ohms.

[0038] Optionally, the contact plug 13 includes a first sub-contact plug 131 and a second sub-contact plug 132; the electromigration test structure further includes: The first dielectric layer 20 is located on the surface of the semiconductor layer 12 opposite to the interconnect layer 11, the transition layer 14 is located on the surface of the first dielectric layer 20 opposite to the interconnect layer 11, and the first sub-contact plug 131 penetrates the first dielectric layer 20 in a direction parallel to the semiconductor layer 12 and pointing to the test layer 10 and is in contact with the transition layer 14. The second dielectric layer 21 is located between the semiconductor layer 12 and the test layer 10. The interconnect layer 11 penetrates the second dielectric layer 21 in a direction parallel to the semiconductor layer 12 and pointing towards the test layer 10. The second sub-contact plug 132 penetrates the second dielectric layer 21 and the semiconductor layer 12 in a direction parallel to the semiconductor layer 12 and pointing towards the test layer 10, and is in contact with the first sub-contact plug 131.

[0039] Optionally, the first dielectric layer 20 is continuously distributed in the storage region CA and the peripheral region PA; The storage region CA includes a storage array, and the first media layer 20 covers the storage array.

[0040] Furthermore, this specific embodiment also provides a memory, attached... Figure 2 This is a schematic diagram of the memory structure in a specific embodiment of the present invention. The memory described in this specific embodiment can be, but is not limited to, a three-dimensional memory such as 3D NAND. The memory includes a memory array wafer, and the memory array wafer includes the electromigration test structure as described in any of the preceding claims.

[0041] For example, the memory is a three-dimensional memory, which includes mutually bonded peripheral circuit wafers (e.g., CMOS wafers) and memory array wafers. Figure 2As shown, the memory array wafer includes a test layer 10, a second dielectric layer 21, a semiconductor layer 12, and a first dielectric layer 20, which are stacked sequentially along a direction parallel to the semiconductor layer 12 and pointing towards the test layer 10. The memory array wafer includes a memory region CA and a peripheral region PA located outside the memory region CA. The first dielectric layer 20 contains a memory array located in the memory region CA and a first sub-contact plug 131 located in the peripheral region PA. A transition layer 14 is disposed on the surface of the first dielectric layer 20 facing away from the semiconductor layer 12, meaning the transition layer 14 can be disposed on the same layer as the first metal layer (M1 layer) of the memory array wafer. The peripheral circuit wafer includes a CMOS circuit layer. The first metal layer is used to connect the memory structure (e.g., a channel structure) in the memory array to the CMOS circuit layer in the peripheral circuit wafer. The second sub-contact plug 132 penetrates the second dielectric layer 21 and the semiconductor layer 12 in a direction parallel to the semiconductor layer 12 and pointing towards the test layer 10, and is in contact with the first sub-contact plug 131. The semiconductor layer 12 can be made of polycrystalline silicon and serves as the N-well of the memory array wafer. The interconnect layer 11 can be made of a metal (e.g., tungsten) and serves as the N-well lead-out layer of the memory array wafer. The test layer 10 can be made of a metal (e.g., aluminum) and serves as the bottom and top metal layers of the memory array wafer.

[0042] Furthermore, this specific embodiment also provides a method for forming an electromigration test structure. Figure 3 This is a flowchart illustrating the method for forming the electromigration test structure in a specific embodiment of the present invention. A schematic diagram of the electromigration test structure formed in this specific embodiment can be found in [reference needed]. Figure 1 .like Figure 1 and Figure 3 As shown, the method for forming the electromigration test structure includes the following steps: Step S31: An interconnect structure is formed in the storage region CA and a monitoring structure is formed in the peripheral region PA outside the storage region CA. The interconnect structure includes a semiconductor layer 12 and an interconnect layer 11 located on the surface of the semiconductor layer 12. The monitoring structure is distributed on the two opposite outer sides of the interconnect layer 11. Step S32: A test layer 10 is formed that is connected to both the interconnect layer 11 and the monitoring structure and is continuously distributed in the storage area CA and the peripheral area PA. The monitoring structure is used to monitor the resistance change of the test layer 10.

[0043] Optionally, the specific steps for forming an interconnect structure in the storage region CA and a monitoring structure in the peripheral region PA outside the storage region CA include: The monitoring structure, including a contact plug 13 and a transition layer 14, is formed in the storage region CA, and the interconnect structure, including the semiconductor layer 12 and the interconnect layer 11, is formed in the peripheral region PA outside the storage region CA. The contact plug 13 penetrates the semiconductor layer 12, and one end of the contact plug 13 is in contact with the transition layer 14, while the other end is used to connect with the test layer 10. Both the contact plug 13 and the interconnect layer 11 extend in a direction parallel to the semiconductor layer 12 and pointing towards the test layer 10. Both the transition layer 14 and the semiconductor layer 12 extend in a direction perpendicular to the semiconductor layer 12 and pointing towards the test layer 10.

[0044] Optionally, the specific steps of forming the monitoring structure including the contact plug 13 and the transition layer 14 in the storage region CA, and the interconnect structure including the semiconductor layer 12 and the interconnect layer 11 in the peripheral region PA outside the storage region CA, include: Forming the first dielectric layer 20; A first sub-contact plug 131 is formed that penetrates the first dielectric layer 20; A transition layer 14 is formed on the surface of the first dielectric layer 20 to connect with the first sub-contact plug 131; The semiconductor layer 12 is formed on the surface of the first dielectric layer 20 that is opposite to the transition layer 14; A second dielectric layer 21 is formed on the surface of the semiconductor layer 12 opposite to the first dielectric layer 20; A second sub-contact plug 132 is formed penetrating the second dielectric layer 21 and the semiconductor layer 12, and an interconnect layer 11 is formed penetrating the second dielectric layer 21, so as to form the contact plug 13 including the first sub-contact plug 131 and the second sub-contact plug 132.

[0045] Optionally, the first dielectric layer 20 is continuously distributed in the storage region CA and the peripheral region PA; The storage region CA includes a storage array, and the first media layer 20 covers the storage array.

[0046] The following description uses a 3D NAND flash memory as an example. The first sub-contact plug 131 can be formed simultaneously with the gate contact plug for connection to the gate layer in the memory array, and the transition layer 14 can be formed simultaneously with the first metal layer of the memory array wafer, thus eliminating the need for additional steps. The first sub-contact plug 131 and the second sub-contact plug 132 can be made of tungsten, and the transition layer 14 can be made of copper. The first sub-contact plug 131, the second sub-contact plug 132, and the transition layer 14 are all located in the peripheral region PA, and therefore do not affect the memory array in the memory region.

[0047] Optionally, the contact resistance between the contact plug 13 and the transition layer 14 is less than the contact resistance between the interconnect layer 11 and the semiconductor layer 12.

[0048] Optionally, the contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer 10, where the initial resistance refers to the resistance of the test layer 10 before electromigration testing.

[0049] Furthermore, this specific embodiment also provides an electromigration testing method, attached... Figure 4 This is a flowchart of the electromigration testing method in a specific embodiment of the present invention. The electromigration testing method provided in this specific embodiment can be used for, for example, Figure 1 Electromigration tests were performed on the electromigration test structure shown. Figure 1 and Figure 4 As shown, the electromigration test method includes the following steps: Step S41: Apply a test current signal to a test layer 10. The test layer 10 is continuously distributed in the memory region CA and the peripheral region PA. The test layer 10 is connected to the interconnect structure located in the memory region CA. The interconnect structure includes an interconnect layer 11 and a semiconductor layer 12. One end of the interconnect layer 11 is connected to the test layer 10 and the other end is connected to the semiconductor layer 12. The peripheral region PA is located outside the memory region CA. Step S42: The resistance change of the test layer 10 is monitored by a monitoring structure located in the peripheral region PA, distributed on the two opposite outer sides of the interconnect layer 11 and connected to the test layer 10.

[0050] Optionally, the specific steps for applying a test current signal to a test layer 10 include: Connect the semiconductor layer 12 to the first external pad; The test current signal is transmitted from the first external pad, through the semiconductor layer 12 and the interconnect layer 11, to the test layer 10.

[0051] Optionally, the monitoring structure includes a contact plug 13 and a transition layer 14. One end of the contact plug 13 is connected to the test layer 10, and the other end is connected to the transition layer 14. Both the contact plug 13 and the interconnect layer 11 extend in a direction parallel to the semiconductor layer 12 and pointing towards the test layer 10. Both the transition layer 14 and the semiconductor layer 12 extend in a direction perpendicular to the semiconductor layer 12 and pointing towards the test layer 10. The specific steps for monitoring the resistance change of the test layer 10 through the monitoring structure distributed on the two opposite outer sides of the interconnect layer 11 and connected to the test layer 10 include: Connect the adapter layer 14 to the second external solder pad; The resistance change of the test layer 10 is monitored using the second external pad.

[0052] Specifically, during the electromigration test performed to detect whether the interface contact between the interconnect layer 11 and the test layer 10 is normal, the electromigration test signal is applied to the test layer 10 through the semiconductor layer 12 and the interconnect layer 11 via the first external pad. The monitoring structure leads the contacts of the test layer 10 to the second external pad through the contact plug 13 and the adapter layer 14, thereby monitoring and monitoring only the resistance change of the test layer 10.

[0053] Optionally, the contact resistance between the contact plug 13 and the transition layer 14 is less than the contact resistance between the interconnect layer 11 and the semiconductor layer 12.

[0054] Optionally, the contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer 10, where the initial resistance refers to the resistance of the test layer 10 before electromigration testing.

[0055] This specific embodiment provides an electromigration test structure and its formation method, an electromigration test method, and a memory. By additionally setting a monitoring structure outside the interconnect structure connected to the test layer, and making the test layer continuously distributed in the storage area and the peripheral area outside the storage area, the interconnect structure is located in the storage area, and the monitoring structure is located in the peripheral area, the resistance change of the test layer during the electromigration test is monitored by the monitoring structure, avoiding the influence of the internal resistance of the interconnect structure on the resistance monitoring of the test layer, and improving the accuracy and reliability of the electromigration test results.

[0056] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An electromigration test structure, characterized in that, It includes a storage area and a peripheral area located outside the storage area; The electromigration test structure also includes: The test layer is continuously distributed in the storage area and the peripheral area; An interconnect structure, located in the memory region, includes an interconnect layer and a semiconductor layer, wherein one end of the interconnect layer is connected to the test layer and the other end is connected to the semiconductor layer; A monitoring structure, located in the peripheral area, connects to the test layer and is distributed on both opposite sides of the interconnect layer. The test layer and the two monitoring structures located on opposite sides of the interconnect structure form a detection loop, such that the monitoring structure only monitors the resistance change of the test layer. The contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer, which refers to the resistance of the test layer before electromigration testing. The monitoring structure includes a contact plug and a transition layer. The contact plug and the interconnect layer both extend in a direction parallel to the semiconductor layer and pointing towards the test layer. One end of the contact plug is in contact with the test layer, and the other end is connected to the transition layer. The transition layer and the semiconductor layer both extend in a direction perpendicular to the semiconductor layer and pointing towards the test layer. The contact resistance between the contact plug and the transition layer is less than the contact resistance between the interconnect layer and the semiconductor layer.

2. The electromigration test structure according to claim 1, characterized in that, The contact plug includes a first sub-contact plug and a second sub-contact plug; The electromigration test structure also includes: A first dielectric layer is located on the surface of the semiconductor layer opposite to the interconnect layer. The transition layer is located on the surface of the first dielectric layer opposite to the interconnect layer. The first sub-contact plug penetrates the first dielectric layer in a direction parallel to the semiconductor layer and points towards the test layer, and is in contact with the transition layer. The second dielectric layer is located between the semiconductor layer and the test layer. The interconnect layer penetrates the second dielectric layer in a direction parallel to the semiconductor layer and pointing towards the test layer. The second sub-contact plug penetrates the second dielectric layer and the semiconductor layer in a direction parallel to the semiconductor layer and pointing towards the test layer, and is in contact with the first sub-contact plug.

3. The electromigration test structure according to claim 2, characterized in that, The first dielectric layer is continuously distributed in the storage area and the peripheral area; The storage region includes a storage array, and the first media layer covers the storage array.

4. A method for forming an electromigration test structure, characterized in that, Includes the following steps: An interconnect structure is formed in a storage region, and a monitoring structure is formed in a peripheral region outside the storage region. The interconnect structure includes a semiconductor layer and an interconnect layer located on the surface of the semiconductor layer. The monitoring structure is distributed on two opposite outer sides of the interconnect layer. The monitoring structure includes a contact plug and a transition layer. The contact plug penetrates the semiconductor layer, and one end of the contact plug is in contact with the transition layer, while the other end is used to connect to a test layer. Both the contact plug and the interconnect layer extend in a direction parallel to the semiconductor layer and pointing towards the test layer. Both the transition layer and the semiconductor layer extend in a direction perpendicular to the semiconductor layer and pointing towards the test layer. The contact resistance between the contact plug and the transition layer is less than the contact resistance between the interconnect layer and the semiconductor layer. A test layer is formed that is connected to both the interconnect layer and the monitoring structure and is continuously distributed in the storage area and the peripheral area. The test layer and the two monitoring structures located on opposite sides of the interconnect structure form a detection loop, such that the monitoring structure only monitors the resistance change of the test layer. The contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer, where the initial resistance refers to the resistance of the test layer before electromigration testing.

5. The method for forming the electromigration test structure according to claim 4, characterized in that, The specific steps of forming an interconnect structure including the semiconductor layer and the interconnect layer in the storage region and forming the monitoring structure including contact plugs and transition layers in the peripheral region outside the storage region include: Form the first dielectric layer; A first sub-contact plug is formed that penetrates the first dielectric layer; A transition layer is formed on the surface of the first dielectric layer to connect with the first sub-contact plug; The semiconductor layer is formed on the surface of the first dielectric layer opposite to the transition layer; A second dielectric layer is formed on the surface of the semiconductor layer opposite to the first dielectric layer; A second sub-contact plug is formed through the second dielectric layer and the semiconductor layer, and an interconnect layer is formed through the second dielectric layer to form the contact plug including the first sub-contact plug and the second sub-contact plug.

6. The method for forming the electromigration test structure according to claim 5, characterized in that, The first dielectric layer is continuously distributed in the storage area and the peripheral area; The storage region includes a storage array, and the first media layer covers the storage array.

7. A method for electromigration testing, characterized in that, Includes the following steps: A test current signal is applied to a test layer, which is continuously distributed in the memory region and the peripheral region. The test layer is connected to an interconnect structure located in the memory region. The interconnect structure includes an interconnect layer and a semiconductor layer. One end of the interconnect layer is connected to the test layer and the other end is connected to the semiconductor layer. The peripheral region is located outside the memory region. The resistance change of the test layer is monitored by monitoring structures located in the peripheral region, distributed on opposite sides of the interconnect layer, and connected to the test layer. The test layer and the two monitoring structures located on opposite sides of the interconnect structure form a detection loop, so that the monitoring structures only monitor the resistance change of the test layer. The contact resistance inside the monitoring structure is less than or equal to the initial resistance of the test layer, which refers to the resistance of the test layer before electromigration testing. The monitoring structure includes a contact plug and a transition layer. The contact plug and the interconnect layer both extend in a direction parallel to the semiconductor layer and pointing towards the test layer. One end of the contact plug is in contact with the test layer, and the other end is connected to the transition layer. The transition layer and the semiconductor layer both extend in a direction perpendicular to the semiconductor layer and pointing towards the test layer. The contact resistance between the contact plug and the transition layer is less than the contact resistance between the interconnect layer and the semiconductor layer.

8. The electromigration testing method according to claim 7, characterized in that, The specific steps for applying a test current signal to a test layer include: Connect the semiconductor layer to the first external pad; The test current signal is transmitted from the first external pad, through the semiconductor layer and the interconnect layer, to the test layer.

9. The electromigration testing method according to claim 7, characterized in that, The specific steps for monitoring the resistance change of the test layer using a monitoring structure distributed on the opposite outer sides of the interconnect layer and connected to the test layer include: Connect the adapter layer to the second external solder pad; The resistance change of the test layer is monitored using the second external pad.

10. A memory, characterized in that, The invention includes a memory array wafer, the memory array wafer comprising the electromigration test structure as described in any one of claims 1-3.

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