Drive delay compensation method, digital PWM module, chip and three-phase PFC drive circuit

Abstract

The application discloses a driving delay compensation method, a digital PWM module, a chip and a three-phase PFC driving circuit. The method comprises the following steps: the digital PWM module acquires a delay time caused by the delay of a PWM signal due to the action of the driving circuit; based on the switching period of the PWM signal and the counting frequency, a theoretical counting value corresponding to an ideal PWM signal is calculated, and a compensation counting value corresponding to the delay time is calculated; the theoretical counting value is compensated by using the compensation counting value to obtain an actual counting value, so that the PWM signal output based on the actual counting value can compensate the delay time in advance; and a PWM signal is output based on the actual counting value. In this way, through compensation, the PWM of the software PWM module will be phase-advanced, the phase delay of the driving circuit part is compensated, the phase margin and the gain margin in the control loop are improved compared with the case without PWM wave compensation, the anti-interference ability of the system is improved, and Thdi is lower.

Description

Technical Field

[0001] This invention relates to the field of power factor correction technology, and in particular to a drive delay compensation method, a digital PWM module, a chip, and a three-phase PFC drive circuit. Background Technology

[0002] Three-phase PFC (Power Factor Correction) is increasingly widely used in the market due to its superior performance. Digital control systems based on digital chips further reduce the Thdi (Total Harmonic Current Distortion, the ratio of the effective value of total harmonic current to the effective value of the fundamental current) of PFC circuits. After the digital chip in the digital control system generates a PWM signal, a drive circuit is needed to convert the generated signal into a drive voltage signal for the power transistor. However, various interferences are unavoidable in practice. To prevent the power transistor from being turned on incorrectly, the drive circuit contains a low-pass filter. This filter introduces a delay element into the drive circuit. This delay element in the drive circuit is a portion with an amplitude of 0dB and a phase delay that varies with frequency, increasing with higher frequencies. This phase delay leads to a larger high-frequency phase shift in the control loop, resulting in a smaller phase margin and a smaller gain margin. When the system's phase margin and gain margin are poor, the circuit's steady-state performance deteriorates, its ability to suppress disturbances weakens, and more interference is reflected in the input current, leading to a worse Thdi. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a drive delay compensation method, a digital PWM module, a chip and a three-phase PFC drive circuit that can improve Thdi performance, in view of the above-mentioned defects of Thdi deterioration in the prior art, and to solve the problem of Thdi performance deterioration caused by drive circuit delay.

[0004] The technical solution adopted by this invention to solve its technical problem is: constructing a drive delay compensation method, based on a digital PWM module capable of outputting PWM signals, applicable to a three-phase PFC drive circuit, wherein the drive circuit is used to convert the PWM signal into a drive voltage signal for the power transistor, and the drive circuit includes a filter circuit for filtering the PWM signal, characterized in that the method includes:

[0005] The digital PWM module acquires the delay time of the PWM signal caused by the action of the driving circuit;

[0006] Based on the switching period and counting frequency of the PWM signal, calculate the theoretical count value corresponding to the ideal PWM signal, and calculate the compensation count value corresponding to the delay time.

[0007] The actual count value is obtained by compensating the theoretical count value with the compensation count value, so that the PWM signal output based on the actual count value can compensate for the delay time in advance;

[0008] The PWM signal is output based on the actual count value.

[0009] Preferably, the digital PWM module is configured to increment / decrement the counter, the delay time includes the turn-on delay time and the turn-off delay time, the compensation count value includes the turn-on compensation count value and the turn-off compensation count value, and the theoretical count value includes the theoretical turn-on count value and the theoretical turn-off count value.

[0010] Preferably, the method further includes:

[0011] Detect the voltage output by the filter circuit;

[0012] The turn-on delay time is defined as the time required for the voltage output by the filter circuit to rise from a low level to the turn-on voltage.

[0013] The time required for the voltage output by the filter circuit to drop from a high level to the turn-off voltage is used as the turn-off delay time.

[0014] Preferably, calculating the compensation count value corresponding to the delay time includes:

[0015] The activation compensation count value is calculated based on the formula TBCLK*T(Delay-on);

[0016] The shutdown compensation count value is calculated based on the formula TBCLK*T(Delay-off);

[0017] Where TBCLK represents the operating frequency of the digital PWM module, T(Delay-on) represents the turn-on delay time, and T(Delay-off) represents the turn-off delay time.

[0018] Preferably, the step of compensating the theoretical count value with the compensated count value to obtain the actual count value includes:

[0019] Subtract the activation compensation count value from the theoretical activation count value and write the resulting count value into the first register;

[0020] The theoretical shutdown count value is added to the shutdown compensation count value, and the resulting count value is written into the second register.

[0021] Preferably, the step of outputting a PWM signal based on the actual count value includes:

[0022] The digital PWM module controls the output PWM level to go high when its counter count increases and equals the count value of the first register;

[0023] The digital PWM module controls the output PWM level to go low when its counter count decreases and equals the count value of the second register.

[0024] Secondly, a digital PWM module is constructed to implement the method described above.

[0025] In three aspects, a digital chip is constructed, including the digital PWM module as described above.

[0026] Fourthly, a three-phase PFC drive circuit is constructed to convert PWM signals into drive voltage signals for power transistors, including a digital chip and a filter circuit for filtering the PWM signals.

[0027] Preferably, the driving circuit further includes an AND gate circuit and an isolation amplifier circuit. The AND gate circuit is connected between the digital chip and the filter circuit. The AND gate circuit is used to isolate and amplify the PWM signal output by the digital chip and then output it to the filter circuit. The filter circuit is used to perform low-pass filtering on the PWM signal output from the AND gate circuit. The isolation amplifier circuit is connected to the filter circuit and is used to convert the trapezoidal wave signal output from the filter circuit into a square wave signal, and output the square wave signal as a driving voltage signal to the three-phase PFC circuit to be driven in the subsequent stage.

[0028] The drive delay compensation method, digital PWM module, chip, and three-phase PFC drive circuit of the present invention have the following beneficial effects: In the present invention, the digital PWM module obtains the delay time of the PWM signal caused by the action of the drive circuit, calculates the compensation count value corresponding to the delay time based on the switching period and counting frequency of the PWM signal, and calculates the theoretical count value corresponding to the ideal PWM signal. The compensation count value is used to compensate the theoretical count value to obtain the actual count value. The actual count value allows the PWM signal output based on the actual count value to compensate for the delay time in advance. Thus, through compensation, the PWM of the software PWM module will lead the phase, compensating for the phase delay of the drive circuit, thereby improving the phase margin and gain margin in the control loop compared to the case without PWM wave compensation, improving the anti-interference capability of the system, and resulting in a lower Thdi. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort:

[0030] Figure 1 This is a schematic diagram illustrating a general application scenario of the driving delay compensation method of the present invention;

[0031] Figure 2 This is a flowchart of the drive delay compensation method of the present invention;

[0032] Figure 3 This is a schematic diagram of the compensation process;

[0033] Figure 4 This is a schematic diagram illustrating the application of the present invention to an ACDC power module. Detailed Implementation

[0034] To address the issue of deteriorated Thdi in a three-phase PFC circuit due to the delay in the drive circuit, this invention proposes a phase delay compensation method. A digital PWM module acquires the delay time of the PWM signal caused by the drive circuit. Based on the switching period and counting frequency of the PWM signal, a compensation count value corresponding to the delay time is calculated, along with a theoretical count value corresponding to the ideal PWM signal. The compensation count value is used to compensate the theoretical count value to obtain an actual count value. This actual count value allows the PWM signal output based on the actual count value to compensate for the delay time in advance. Thus, through compensation, the PWM of the software PWM module leads the phase, compensating for the phase delay in the drive circuit. This improves the phase margin and gain margin in the control loop compared to the case without PWM wave compensation, enhancing the system's anti-interference capability and resulting in a lower Thdi.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0036] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Typical embodiments of the invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present invention more thorough and complete. It should be understood that the embodiments of the present invention and the specific features thereof are detailed descriptions of the technical solutions of this application, and not limitations thereof. Where there is no conflict, the embodiments of the present invention and the technical features thereof can be combined with each other.

[0037] refer to Figure 1 The drive delay compensation method of this invention can be implemented by a digital chip, specifically by a digital PWM module within the digital chip. The PWM signal (a periodic square wave signal) emitted by the digital PWM module of the digital chip is input to the drive circuit. The drive circuit filters this PWM signal, converting the square wave into a trapezoidal wave. Subsequently, the drive circuit converts the trapezoidal wave back into a square wave and outputs it to the power transistor and other structures. However, the output square wave at this point experiences a delay compared to the initial square wave emitted by the digital chip due to the waveform transformation by the filtering circuit. The purpose of this invention is to compensate for the emitted PWM square wave in advance at the digital chip side. After processing by the drive circuit, the compensated square wave, due to the delay, will produce the desired square wave output, which is an improvement compared to the case without PWM wave emission compensation. This enhances the system's anti-interference capability and results in a lower Thri (Thdi).

[0038] refer to Figure 2 The drive delay compensation method of the present invention includes:

[0039] S101: Obtain the delay time of the PWM signal caused by the action of the driving circuit;

[0040] Specifically, the delay time is obtained by the digital PWM module through input from the designer into the digital chip.

[0041] refer to Figure 3The digital PWM module controls the output level (high or low) based on theoretical count values, thereby achieving digital wave generation of an ideal PWM signal. Specifically, in this embodiment, the digital PWM module is configured to increment and decrement the counter. The counter of the digital PWM module counts periodically, first increasing and then decreasing the count in each cycle. Correspondingly, the theoretical count values ​​include a theoretical turn-on count value N1 and a theoretical turn-off count value N2. The theoretical turn-on count value N1 is pre-written into a first register, and the theoretical turn-off count value N2 is pre-written into a second register. The principle of the digital PWM module generating a PWM square wave is as follows: when the counter of the digital PWM module increases and equals the count value in the first register, the module controls the output PWM level to be high; when the counter of the digital PWM module decreases and equals the count value in the second register, the module controls the output PWM level to be low.

[0042] The delay time includes the turn-on delay T (Delay-on) and the turn-off delay T (Delay-off). Assuming the moment the PWM signal changes from low to high is denoted as the turn-on time Ton, and the moment it changes from high to low is denoted as the turn-off time Toff, then the PWM signal emitted by the digital PWM module, compared to the PWM signal output by the driver circuit, has both the turn-on time Ton and the turn-off time Toff delayed. The delay times for the turn-on time Ton and the turn-off time Toff are the turn-on delay time T (Delay-on) and the turn-off delay time T (Delay-off), respectively.

[0043] To compensate for the PWM signal delay caused by the subsequent drive circuit, this embodiment compensates for the turn-on delay T (Delay-on) and turn-off delay T (Delay-off) in advance when the digital PWM module generates the waveform. Therefore, this embodiment advances the turn-on time Ton and turn-off time Toff of the PWM signal when generating the waveform. In order to advance the turn-on time Ton and turn-off time Toff during waveform generation, we need to update the theoretical turn-on count value N1 and theoretical turn-off count value N2 corresponding to the turn-on time Ton and turn-off time Toff during waveform generation.

[0044] To update the count values ​​corresponding to the turn-on time Ton and turn-off time Toff during wave transmission, we first need to detect the turn-on delay time T(Delay-on) and turn-off delay time T(Delay-off). These two times can be detected from the trapezoidal signal output by the filter circuit. Specifically: detect the voltage output by the filter circuit, and time the time required for the voltage output by the filter circuit to rise from a low level to the turn-on voltage Von as the turn-on delay time T(Delay-on). Time the time required for the voltage output by the filter circuit to fall from a high level to the turn-off voltage Voff as the turn-off delay time T(Delay-off). Here, the turn-on voltage Von and turn-off voltage Voff are determined by the circuit after the filter circuit that converts the trapezoidal wave into a square wave (this square wave is the driving voltage signal we need). Therefore, different driving circuits will have different turn-on delay times T(Delay-on) and turn-off delay times T(Delay-off).

[0045] S102: Based on the switching period and counting frequency of the PWM signal, calculate the theoretical count value corresponding to the ideal PWM signal, and calculate the compensation count value corresponding to the delay time;

[0046] The compensation count values ​​include the turn-on compensation count value and the turn-off compensation count value. As mentioned in step S101 above, we need to update the theoretical turn-on count value N1 and the theoretical turn-off count value N2 corresponding to the turn-on time Ton and the turn-off time Toff during wave transmission. The turn-on compensation count value and the turn-off compensation count value are used to update the theoretical turn-on count value N1 and the theoretical turn-off count value N2, respectively.

[0047] Specifically, the calculation of the theoretical count value corresponding to the ideal PWM signal includes: first, obtaining the on-time T(PWM-on) = T*D and the off-time T(PWM-off) = T*(1-D) of each cycle of the ideal PWM signal based on the period T and duty cycle D of the PWM signal; then, calculating the theoretical on-count value N1 and the theoretical off-count value N2 based on N1 = TBCLK*T(PWM-on) and N2 = TBCLK*T(PWM-off).

[0048] Specifically, the calculation of the compensation count value corresponding to the delay time includes: calculating the on-time compensation count value N3 based on the formula N3 = TBCLK * T (Delay-on); and calculating the off-time compensation count value N4 based on the formula N4 = TBCLK * T (Delay-off).

[0049] Where TBCLK represents the operating frequency of the digital PWM module, which is the operating frequency of the digital chip, T(Delay-on) represents the turn-on delay time, and T(Delay-off) represents the turn-off delay time.

[0050] S103: The theoretical count value is compensated using the compensated count value to obtain the actual count value, so that the PWM signal output based on the actual count value can compensate for the delay time in advance;

[0051] Specifically, the method of using the compensation count value to compensate the theoretical count value to obtain the actual count value includes: subtracting the turn-on compensation count value from the theoretical turn-on count value N1 and writing the resulting count value N1-comp into a first register; and adding the turn-off compensation count value to the theoretical turn-off count value N2 and writing the resulting count value N2-comp into a second register.

[0052] S104: Output a PWM signal based on the actual count value.

[0053] Specifically, the method of outputting a PWM signal based on the actual count value includes: when the digital PWM module increases its counter count and equals the count value N1-comp of the first register, controlling the emitted PWM level to be high; when the digital PWM module decreases its counter count and equals the count value N2-comp of the second register, controlling the emitted PWM level to be low.

[0054] refer to Figure 3 When the counter counts up, because the value N1-comp of the first register is obtained by subtracting the turn-on compensation count value from the theoretical turn-on count value N1, it is equivalent to the value of the first register (N1-comp) decreasing compared to before compensation (N1). Therefore, the time when the low level switches to the high level will be earlier. When the counter counts down, because the value N2-comp of the second register is obtained by adding the turn-off compensation count value to the theoretical turn-off count value N2, it is equivalent to the value of the second register (N2-comp) increasing compared to before compensation (N2). Therefore, the time when the high level switches to the low level will be earlier.

[0055] Based on the same inventive concept, this invention also claims a digital PWM module, a digital chip, and a three-phase PFC drive circuit. The digital PWM module is used to implement the method described in Embodiment 1. The digital chip includes the aforementioned digital PWM module. The three-phase PFC drive circuit is used to convert the PWM signal output by the digital PWM module into a drive voltage signal for the power transistor, and includes the aforementioned digital chip and a filter circuit for filtering the PWM signal.

[0056] refer to Figure 4 Taking an ACDC power module as an example, the driving circuit includes an AND gate circuit, a filter circuit, and an isolation amplifier circuit connected in sequence. The AND gate circuit is also connected to the digital chip. The AND gate circuit is used to isolate and amplify the PWM signal output by the digital chip and then output it to the filter circuit. The filter circuit is used to perform low-pass filtering on the PWM signal output from the AND gate circuit. The isolation amplifier circuit is used to convert the trapezoidal wave signal output from the filter circuit into a square wave signal and output the square wave signal as a driving voltage signal to the three-phase PFC circuit to be driven in the subsequent stage.

[0057] The following is combined with Figure 4 This document details the application scenarios of the ACDC power module. The ACDC power module uses a three-phase VIENNA topology and is controlled and powered by a digital signal processing (DSP) chip. It employs SPWM modulation with a fixed carrier frequency of 20kHz. The DSP generates the PWM waveform, which is used by the drive circuit to drive the switching transistors. Resistor R1 and capacitor C1 form a low-pass filter circuit. VGS and GND are the drive voltage signals for the switching transistors.

[0058] Where R1 = 330Ω, C1 = 2.2nF, and the unit delay time T1 = R1 * C1 = 330 * 2.2e-9 = 726ns. The output signal voltage of the AND gate is 5V, the turn-on voltage Von of the driver chip in the isolation amplifier circuit is 2.4V, and the turn-off voltage Voff is 0.8V.

[0059] The voltage output of the filter circuit takes 1.6µs to rise from 0 to 2.4V and 4µs to drop from 5V to 0.8V after being turned on. Therefore, the turn-on delay T(Delay-on) is 1.6µs and the turn-off delay T(Delay-off) is 4µs. The DSP's PWM module counter operates at a frequency TBCLK of 60MHz and has a switching period Tpwm of 50µs. Therefore, the turn-on compensation count value N3 = TBCLK * T(Delay-on) = 1.6µs * 60MHz = 96, and the turn-off compensation count value N4 = TBCLK * T(Delay-off) = 4µs * 60MHz = 240.

[0060] The PWM module in the DSP chip is configured to increment and decrement using a counter. After calculating the duty cycle of the emitted waveform, the values ​​of N1 and N2 are obtained. To emit the waveform earlier, N1-96 is written to the first register, and N2-240 is written to the second register. The DSP chip's PWM module emits the waveform according to the first and second registers. After passing through the drive circuit, the actual drive voltage signal is consistent with the ideal PWM signal with the calculated duty cycle. This eliminates phase delay in the PWM module, improving phase margin and gain margin, enhancing anti-interference capability, and improving ThDI performance.

[0061] In summary, the drive delay compensation method, digital PWM module, chip, and three-phase PFC drive circuit of the present invention have the following beneficial effects: In the present invention, the digital PWM module obtains the delay time of the PWM signal caused by the action of the drive circuit, calculates the compensation count value corresponding to the delay time based on the switching period and counting frequency of the PWM signal, and calculates the theoretical count value corresponding to the ideal PWM signal. The compensation count value is used to compensate the theoretical count value to obtain the actual count value. The actual count value allows the PWM signal output based on the actual count value to compensate for the delay time in advance. Thus, through compensation, the PWM of the software PWM module will lead the phase, compensating for the phase delay of the drive circuit, thereby improving the phase margin and gain margin in the control loop compared to the case without PWM wave compensation, improving the anti-interference capability of the system, and resulting in a lower Thdi.

[0062] It should be noted that the term "connected" or "linked" as used in this article includes not only directly connecting two entities, but also indirectly connecting them through other entities that have beneficial improvement effects.

[0063] The terms "first," "second," and other ordinal numbers used in this specification are used to describe various constituent elements, but these constituent elements are not limited by these terms. The purpose of using these terms is solely to distinguish one constituent element from others. For example, without departing from the scope of the invention, a first constituent element may be named a second constituent element, and similarly, a second constituent element may be named a first constituent element.

[0064] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A delay compensation method based on a digital PWM module, implemented using a digital PWM module capable of outputting PWM signals, applicable to a three-phase PFC drive circuit, wherein the drive circuit converts the PWM signal into a drive voltage signal for the power transistor, and the drive circuit includes a filter circuit for filtering the PWM signal, characterized in that... The method includes: The digital PWM module acquires the delay time of the PWM signal caused by the action of the driving circuit; Based on the switching period and counting frequency of the PWM signal, calculate the theoretical count value corresponding to the ideal PWM signal, and calculate the compensation count value corresponding to the delay time. The actual count value is obtained by compensating the theoretical count value with the compensation count value, so that the PWM signal output based on the actual count value can compensate for the delay time in advance; Output a PWM signal based on the actual count value; The digital PWM module is configured to increment and decrement the counter. The delay time includes the turn-on delay time and the turn-off delay time. The compensation count value includes the turn-on compensation count value and the turn-off compensation count value. The theoretical count value includes the theoretical turn-on count value and the theoretical turn-off count value. The method further includes: Detect the voltage output by the filter circuit; The turn-on delay time is defined as the time required for the voltage output by the filter circuit to rise from a low level to the turn-on voltage. The time required for the voltage output by the filter circuit to drop from a high level to the turn-off voltage is used as the turn-off delay time. The calculation of the compensation count value corresponding to the delay time includes: The activation compensation count value is calculated based on the formula TBCLK * T(Delay-on); The shutdown compensation count value is calculated based on the formula TBCLK * T(Delay-off); Where TBCLK represents the operating frequency of the digital PWM module, T(Delay-on) represents the turn-on delay time, and T(Delay-off) represents the turn-off delay time.

2. The delay compensation method based on digital PWM module drive according to claim 1, characterized in that, The method of compensating the theoretical count value with the compensated count value to obtain the actual count value includes: Subtract the activation compensation count value from the theoretical activation count value and write the resulting count value into the first register; The theoretical shutdown count value is added to the shutdown compensation count value, and the resulting count value is written into the second register.

3. The delay compensation method based on digital PWM module drive according to claim 2, characterized in that, The method of outputting a PWM signal based on the actual count value includes: The digital PWM module controls the output PWM level to go high when its counter count increases and equals the count value of the first register; The digital PWM module controls the output PWM level to go low when its counter count decreases and equals the count value of the second register.

4. A digital PWM module, characterized in that, Used to implement the method as described in any one of claims 1-3.

5. A digital chip, characterized in that, Includes the digital PWM module as described in claim 4.

6. A three-phase PFC drive circuit for converting PWM signals into drive voltage signals for power transistors, characterized in that, It includes the digital chip as described in claim 5 and a filtering circuit for filtering the PWM signal.

7. The three-phase PFC drive circuit according to claim 6, characterized in that, The driving circuit further includes an AND gate circuit and an isolation amplifier circuit. The AND gate circuit is connected between the digital chip and the filter circuit. The AND gate circuit is used to isolate and amplify the PWM signal output by the digital chip and then output it to the filter circuit. The filter circuit is used to perform low-pass filtering on the PWM signal output from the AND gate circuit. The isolation amplifier circuit is connected to the filter circuit and is used to convert the trapezoidal wave signal output from the filter circuit into a square wave signal, and output the square wave signal as a driving voltage signal to the three-phase PFC circuit to be driven in the subsequent stage.

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