Clock signal generation

Abstract

Embodiments of the present disclosure relate to clock signal generation. An apparatus for generating first clock signals includes first circuits each including a ring oscillator that delivers one of the first clock signals and is connected to a first node configured to receive a first current. A circuit selects one of the first clock signals, and a phase-locked loop delivers a second signal that is a function of a difference between a frequency of the selected first clock signal and a setpoint frequency. When the first circuits deliver the selected clock signal and operate in a controlled mode, each of the first circuits provides a compensation current to the first node determined by the second signal.

Description

Technical Field

[0001] This disclosure generally relates to electronic circuits, and more specifically to generating multiple clock signals at different frequencies in such electronic circuits. Background Technology

[0002] Electronic clock generation circuits are known. For example, clock generation circuits currently known as RC oscillators are known. In an RC oscillator, a voltage ramp available across a capacitor element charged by a charging current is compared with a reference voltage. Each time the reference voltage crosses the voltage ramp, the voltage ramp is reset, and a new voltage ramp is then compared with the reference voltage again. The comparison is implemented by a comparator, which is typically an operational amplifier assembled from comparators. In such a circuit, the comparator's output signal, after being shaped, is used as a clock signal. The frequency of the clock signal thus generated is then determined by the capacitor value, the charging current of the capacitor element, and the reference voltage value.

[0003] When it is desired to generate multiple clock signals of different frequencies, for example, each clock signal is generated by a corresponding RC oscillator.

[0004] Known clock generation circuits, especially the aforementioned RC oscillator, have various drawbacks.

[0005] For example, the aforementioned RC oscillator is relatively power-intensive because the capacitors must be repeatedly charged. Therefore, RC oscillators are not suitable for so-called "low-power" applications or electronic circuits where reduced power consumption is desired. This is especially true when multiple clock signals need to be generated at different frequencies, because of the multiple capacitors; typically, at least one capacitor must be repeatedly charged for each generated clock signal. Summary of the Invention

[0006] Electronic clock generation circuits are known.

[0007] For example, a circuit for generating multiple clock signals is required that consumes less power than a circuit implemented using an RC oscillator to generate multiple clock signals.

[0008] For example, a circuit is needed to generate multiple clock signals, wherein the frequency of any of the generated clock signals can be controlled during a controlled operation phase and is not controlled during an uncontrolled operation phase, so that the frequency of the signal is more accurate than during the uncontrolled operation phase.

[0009] The embodiments overcome all or part of the shortcomings of known clock signal generation devices or circuits.

[0010] The embodiments overcome all or part of the shortcomings of known clock signal generation methods.

[0011] One embodiment provides an apparatus for generating a plurality of first clock signals, the apparatus comprising: Each of the first circuits includes a ring oscillator configured to transmit one of the plurality of first clock signals, and the oscillator is connected to a first node configured to receive a first current. The circuit is configured to receive a first clock signal and transmit a first clock signal selected from the first clock signals; and A phase-locked loop (PLL) is configured to transmit a second signal that varies based on the difference between the frequency of a selected first clock signal and a setpoint frequency, the setpoint frequency of which is determined by the frequency of a third signal, which is a clock signal received by the PLL. Each of the first circuits is configured to provide a compensation current determined by a second signal to the first node when the first circuit transmits a selected first clock signal and operates in a phase-locked loop controlled mode.

[0012] According to one embodiment, each first circuit includes: The first current source is configured to provide a first current to the first node; The second node is coupled to the first node; The second circuit is configured to provide a second current, determined by a second signal, to the second node; and The third circuit is configured to draw a third current from the second node.

[0013] According to one embodiment, in each first circuit: The first current source is configured such that the first current is equal to Ki multiplied by the reference current Iref; The second circuit is configured such that the second current equals Ki multiplied by B multiplied by a fourth current that is the same for all first circuits, where B is a factor determined by the second signal; and The third circuit is configured such that the third current is equal to Ki multiplied by A multiplied by the fifth current, which is the same for all first circuits and proportional to the reference current Iref.

[0014] According to one embodiment, each third circuit includes a current mirror, the current mirror including an input branch and at least one output branch associated with the input branch, the at least one output branch being configured to transmit a third current.

[0015] According to one embodiment, in each third circuit, the input branch of the current mirror includes a fifth current generator.

[0016] According to one embodiment, the input branch of the current mirror of each third circuit is shared by all third circuits.

[0017] According to one embodiment, in each third circuit, the at least one output branch includes circuitry controllable to modify the value of factor A.

[0018] According to one embodiment, each second circuit includes a current mirror, the current mirror including an input branch and at least one output branch associated with the input branch, the at least one output branch being configured to transmit a second current.

[0019] According to one embodiment, in each second circuit, the input branch is controlled by a second signal and configured such that a sixth current equal to B multiplied by the fourth current flows through it.

[0020] According to one embodiment, in each second circuit, the input branch includes a voltage-to-current converter controlled by a second signal.

[0021] According to one embodiment, the voltage-to-current converter includes a transistor connected in series with a resistor, the transistor being controlled by a second signal.

[0022] According to one embodiment, the input branch of the current mirror of the second circuit is shared by all second circuits.

[0023] According to one embodiment, the phase-locked loop includes: The frequency divider can be programmed according to a selected first signal and configured to receive the selected first signal and transmit a periodic signal at a frequency divided relative to the frequency of the selected first signal. A phase comparator is configured to transmit a first binary signal and a second binary signal, the first binary signal indicating when the periodic signal lags behind the second clock signal, and the second binary signal indicating when the periodic signal leads the second clock signal. A charge pump, controlled by a first binary signal and a second binary signal and configured to transmit a signal that varies according to the phase difference between a periodic signal and a second clock signal; and The filter is configured to transmit a second signal based on the signal delivered by the charge pump.

[0024] One embodiment provides a method for generating a plurality of first clock signals, the method comprising the steps of: The first signal is selected by the selection circuit; A second signal is transmitted via a phase-locked loop, and the second signal varies according to the difference between the frequency of the selected first signal and the setpoint frequency of the selected first signal. For each of the one or more first clock signals, a first current is provided to a first node of a first corresponding circuit, each first circuit including a ring oscillator connected to the first node and transmitting one of the first clock signals; and The compensation current determined by the second signal is provided to the first node of the first circuit that transmits the selected first signal only when the first circuit is operating in a phase-locked loop controlled mode.

[0025] According to one embodiment, the method is implemented by the described device.

[0026] According to one embodiment, the method includes: for each first circuit, determining a calibration value for a third circuit of the first circuit, wherein determining the calibration value includes: The first clock signal of the first circuit is selected by the selection circuit; The frequency divider is reprogrammed to account for variations in temperature and device power supply voltage at the frequency of the selected first clock signal. The third current is drawn from the first node, and the value of factor A is increased by controlling at least one output branch of the third circuit; and For each value of factor A, the frequency divider is reset, and based on the first and second binary signals, it is determined whether the periodic signal leads or lags the second clock signal in phase. The calibration value of factor A is the first value of factor A, where: When both the second and third currents are positive in the controlled mode, the periodic signal becomes phase-lagging relative to the second signal; or When the second and third currents are negative in the controlled mode, the periodic signal becomes phase-leading relative to the second signal. Attached Figure Description

[0027] The foregoing features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, in which:

[0028] Figure 1 An embodiment of a device for generating multiple clock signals is schematically shown in part, in the form of boxes;

[0029] Figure 2 schematically shown Figure 1 Examples of circuitry for the device; and

[0030] Figure 3 schematically shown Figure 1 Another embodiment of the device's circuitry. Detailed Implementation

[0031] In the various figures, the same features are designated by the same reference numerals. Specifically, structural and / or functional features common in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0032] For clarity, only steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. Specifically, various common electronic circuits, particularly integrated common applications, in which devices or circuits for generating one or more clock signals can be provided are not described in detail; the described embodiments are compatible with these common circuits and applications. Similarly, current uses of clock signals are not described in detail; these current uses are compatible with the described embodiments.

[0033] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0034] In the following disclosure, unless otherwise stated, when referring to absolute positional qualifiers such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative positional qualifiers such as the terms “above,” “below,” “up,” “down,” etc., or orientation qualifiers such as “horizontal,” “vertical,” etc., refer to the orientation shown in the figure.

[0035] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “on the order of” indicate within 10%, preferably within 5%.

[0036] In the following description, when current flows out of a node, it is said to be drawn from the node, and when current flows into a node, it is said to be supplied to the node, but in reality, the current can be positive or negative.

[0037] Figure 1 An embodiment of a device 1 for generating multiple clock signals clki is schematically shown, partially in box form, where i is an integer index in the range from 1 to N. The generated signals clki preferably have different frequencies.

[0038] Device 1 includes a signal selection circuit 5 for selecting one of the signals clki. Circuit 5 takes all or part of the signals clki as input and outputs a signal clk-sel corresponding to one of the signals clki it receives. Circuit 5 also receives a control signal that determines which of the signals clki received by circuit 5 is equal to the signal clk-sel available at the output of circuit 5.

[0039] Device 1 includes a phase-locked loop 2 or a PLL.

[0040] Phase-locked loop 2 is configured to transmit a signal sigF, which varies based on the difference between the frequency of signal clk-sel (i.e., the selected signal clki) and the setpoint frequency of clk-sel. In other words, signal sigF has a value modified by the difference between the frequency of signal clk-sel and the setpoint frequency of clk-sel. More specifically, in phase-locked loop 2, the frequency of signal clk-sel is divided to obtain a periodic signal clkfb at a lower frequency, and signal sigF varies based on the frequency difference between signal clkfb and clock signal clkref. The setpoint frequency of signal clk-sel is then determined by a factor and the frequency of signal clkref, obtained by dividing the frequency of signal clk-sel by the factor to obtain signal clkfb. As an example, signal sigF is a voltage, for example, positive and referenced to a reference potential, typically ground, applied to node or track 3. Signal sigF is available or transmitted, for example, at or from the output 203 of phase-locked loop 2.

[0041] Phase-locked loop 2, for example, receives the signal clk-sel at input 201.

[0042] Phase-locked loop 2 also receives a clock signal clkref at input 202, for example. Preferably, the signal clkref is obtained from a reference clock signal, such as a reference clock signal transmitted by a quartz crystal, such that its frequency is as accurate as possible. As an example, the signal clkref is obtained at the output of a frequency divider configured to transmit the signal clkref at a frequency divided relative to the frequency of the reference clock signal. According to another example, the signal clkref is mixed with the reference clock signal and is transmitted directly by a quartz crystal, for example.

[0043] While generally the signal clkref remains the same regardless of the signal clki selected by circuit 5, the signal clkref can have different frequencies depending on the signal clki selected by circuit 5. The signal clkref is based on a reference clock signal, for example, obtained at the output of a programmable frequency divider, and the frequency of the reference clock signal is divided to obtain a factor of the signal clkref, for example, depending on the signal clki selected by circuit 5.

[0044] According to one embodiment, the phase-locked loop 2 includes: Frequency divider circuit, or frequency divider 205 ( Figure 1 The box Mdiv in the middle can be adjusted according to the signal clki selected by circuit 5 and transmitted to phase-locked loop 2; Phase frequency detector or phase comparator 207 ( Figure 1 (in the box PFD). Charge pump 209; and Loop filter 211.

[0045] Frequency divider 205 is configured to divide the frequency of signal clk-sel by a number Mi, which is a function of the signal clkki selected by circuit 5. The setpoint frequency of the signal clkki selected by circuit 5 is then equal to Mi multiplied by the frequency of signal clkref.

[0046] Frequency divider 205 receives the signal clk-sel at input 2051 and transmits the signal clkfb at output 2052. The frequency of the signal clkfb at the output of frequency divider 205 is equal to the frequency of the signal clk-sel divided by the corresponding number Mi.

[0047] Phase comparator 207 is configured to compare the phase of signal clkfb with the phase of signal clkref. For example, phase comparator 207 is configured to transmit a first binary signal UP, for example, indicated by a high state, when signal clkfb lags in phase relative to clock signal clkref, and to transmit a second binary signal DW, for example, indicated by a high state, when signal clkfb leads in phase relative to signal clkref. Signal clkfb is received, for example, by input 2071 of phase comparator 207. Signal clkref is received, for example, by input 2072 of phase comparator 207. Signals UP and DW are transmitted, for example, by outputs 2074 and 2073 of phase comparator 207, respectively.

[0048] As an example, the phase comparator 207 is compared to the paper entitled "Contribution pour l'amélioration de la robustesse et du bruit de phase dessynthétiseurs de fréquence" submitted by M. Houdebine in March 2007. Figure 1 The phase comparators shown in .9.a are similar or identical.

[0049] The charge pump 209 is controlled by a phase comparator 207, for example, by binary signals UP and DW. The charge pump 209 is configured to generate a signal Δ (delta) based on signals UP and DW, the signal Δ (delta) varying according to the phase difference between signals clkref and clkfb; that is, the signal Δ is adjusted according to this phase difference. For example, the signal... It is a voltage, for example, positive and referenced to node 3 (i.e., ground). Signals UP and DW are received, for example, by inputs 2092 and 2091 of charge pump 209, respectively, and signal Δ is transmitted, for example, by output 2093 of charge pump 209.

[0050] According to one embodiment, the charge pump 209 includes a current source 2095, a switch SW1, a switch SW2, and a current source 2097 connected in series between nodes or tracks 4 where a power supply voltage Vdd (e.g., positive and referenced to the ground potential of node 3) is applied. For example, current source 2095 couples node 4 to switch SW1, switch SW1 couples current source 2095 to output 2093 of circuit 209, switch SW2 couples output 2093 to current source 2097, and current source 2097 couples switch SW2 to node 3. Both current sources 2095 and 2097 deliver the same current, or in other words, current source 2095 delivers a current with the same value as the current delivered by current source 2097. Switches SW1 and SW2 are controlled by the output signal of phase comparator 207.

[0051] According to one embodiment, charge pump 209 is configured to provide positive current on its output 2093 when signal clkfb lags in phase relative to signal clkref, and to draw positive current from its output 2093 when signal clkfb leads in phase relative to signal clkref. According to one embodiment, with the above and Figure 1 Taking the charge pump 209 as an example, switch SW1 is controlled by signal UP, such that when signal UP indicates that signal clkfb lags behind signal clkref in phase, switch SW1 is turned on; otherwise, it is turned off. Furthermore, switch SW2 is controlled by signal DW, such that when signal DW indicates that signal clkfb leads signal clkref in phase, switch SW2 is turned on; otherwise, it is turned off. Therefore, when signal clkfb lags behind signal clkref in phase, source 2095 provides current to the output 2093 of charge pump 209, and conversely, when signal clkfb leads signal clkref in phase, source 2097 draws current from the output 2093 of charge pump 209.

[0052] Filter 211 is configured to transmit a signal sigF based on a signal Δ delivered by charge pump 209 (e.g., from current drawn from or supplied by the output 2093 of charge pump 209). The output 2093 of charge pump 209 is coupled (e.g., connected) to the input 2111 of filter 211. The signal sigF is available, for example, at the output 2112 of filter 211.

[0053] As an example, filter 211 includes a capacitor element C1 that couples input 2111 to node 3, and a series connection of a resistor R1 and a capacitor element C2 that couples input 2111 to node 3 in parallel with capacitor element C1, and output 2112 is coupled, preferably to input 2111 of filter 211.

[0054] Therefore, in this embodiment, the charge pump 209 delivers positive current when the phase of the signal UP indicating signal clkfb lags behind that of the signal clkref, and draws positive current when the phase of the signal DW indicating signal clkfb leads that of the signal clkref. The value of the signal sigF increases or decreases respectively when the signal clkfb lags or leads the signal clkref. The signal sigF (i.e., its value) thus effectively varies according to the difference between the frequency of the signal clk-sel and the setpoint frequency of the signal clk-sel.

[0055] According to another embodiment, the charge pump 209 is configured to draw positive current from its output 2093 when the signal clkfb lags in phase relative to the signal clkref, and to provide positive current on its output 2093 when the signal clkfb leads in phase relative to the signal clkref. According to this embodiment, with the above and Figure 1 Taking the charge pump 209 shown as an example, switch SW1 is controlled by signal DW, such that when signal DW indicates that signal clkfb leads the phase of signal clkref, switch SW1 is turned on; otherwise, it is turned off. Furthermore, switch SW2 is controlled by signal UP, such that when signal UP indicates that signal clkfb lags the phase of signal clkref, switch SW2 is turned on; otherwise, it is turned off. In this embodiment, when signal clkfb lags or leads the phase of signal clkref, the value of signal sigF decreases or increases, respectively. Signal sigF (i.e., its value) thus effectively varies according to the difference between the frequency of signal clk-sel and the setpoint frequency of signal clk-sel.

[0056] In addition to the phase-locked loop 2, device 1 includes as many clock signal generation circuits 4i as the signal clki generated by device 1, that is, N circuits 4i in this example. In other words, for each clock signal clki generated by device 1, device 1 includes a corresponding circuit 4i. Figure 1 Only three circuits 41, 4i and 4N are shown in the figure to avoid overloading the attached diagram.

[0057] Each circuit 4i includes a ring oscillator 5i ( Figure 1 (See box ROi in the diagram). Each oscillator 5i is configured to transmit a corresponding signal clki. The oscillators 5i are different from each other, for example, such that the frequencies of the signals clki are different from each other.

[0058] Although this is in Figure 1 Not shown, but each oscillator 5i includes, for example, an odd number of logic gates connected in series to form a loop. Each of these logic gates is configured to invert the state of the binary signal it receives; that is, it transmits a binary signal in a low state when it receives a binary signal in a high state, and transmits a binary signal in a high state when it receives a binary signal in a low state. Due to the propagation time in these logic gates, the binary signal available at the output of each of these logic gates begins to oscillate between the low and high states at a frequency determined by the propagation time of the logic gates forming the ring oscillator. This signal is, for example, the signal clki transmitted by oscillator 5i.

[0059] In each circuit 4i, an oscillator 5i is connected to node 400i. Node 400i is configured to receive current Isupplyi.

[0060] More specifically, in each circuit 4i, the oscillator 5i draws current Ii from node 400i for its power supply. For example, the oscillator 5i is connected between node 400i and node 3 and is powered by the voltage available between these nodes 400i and 3.

[0061] Each circuit 4i is configured to operate selectively in either an uncontrolled mode or a controlled mode. When a circuit 4i operates in controlled mode, circuit 5 selects the signal clki of that circuit 4i; in other words, signal clk-sel corresponds to signal clki of that circuit 4i. The frequency of signal clki of circuit 4i when operating in controlled mode is controlled by phase-locked loop 2. Although a single circuit in circuit 4i can operate in controlled mode at any given time, all circuits 4i can operate simultaneously in uncontrolled mode.

[0062] More specifically, each circuit 4i is configured to supply a compensation current Icompi, determined by the signal sigF, to node 400i only when it operates in controlled mode. In other words, each circuit 4i is configured to provide the compensation current Icompi to node 400i when it operates in controlled mode, and not to provide the current Icompi to node 400i when it operates in uncontrolled mode. The value of the current Icompi is related to the value of the signal sigF. Depending on the value of the signal sigF, the current Icompi supplied to node 400i can be positive or negative.

[0063] In device 1, any circuit in circuit 4i can be selected to operate in a controlled mode without requiring a different phase-locked loop for each circuit 4i. This allows for a reduction in the size and power consumption of device 1 compared to similar devices where each circuit 4i would be associated with a different phase-locked loop.

[0064] When circuit 4i operates in uncontrolled mode, the current Ii received by its oscillator 5i is equal to the current Isupplyi, and the frequency of the transmitted signal clki is determined by the value of the current Isupplyi. Determining the structure of the oscillator 5i of each circuit 4i and the value of the current Isupplyi will be within the capabilities of those skilled in the art, such that the frequency of the signal clki transmitted by the oscillator 5i in uncontrolled mode is equal to its setpoint frequency, i.e., Mi multiplied by the frequency of the signal clkref corresponding to that signal clki.

[0065] However, when circuit 4i operates in controlled mode, the current Ii received by its oscillator 5i is related to the current Icompi supplied to node 400i, and therefore to the value of voltage sigF, which allows the frequency of signal clki to be controlled due to voltage sigF. The frequency of signal clki provided by circuit 4i in controlled mode is then equal to its setpoint value, with higher accuracy than when circuit 4i is in uncontrolled mode. Specifically, each circuit 4i is configured to decrease the value of current Icompi when operating in controlled mode, when the frequency of signal clki is greater than its setpoint value, and increase the value of current Icompi when the frequency of signal clki is less than its setpoint value. In other words, each circuit 4i is configured to decrease current Icompi based on signal sigF when signal clkfb leads the phase of signal clkref, and increase current Icompi when signal clfkb lags the phase of signal clkref.

[0066] In circuit 4i operating in controlled mode, a modification of the current Icompi causes a corresponding modification of the current Ii transmitted by the oscillator 5i of circuit 4i, which in turn leads to a corresponding modification of the frequency of the signal clki transmitted by the oscillator 5i. For example, a decrease in the current Icompi leads to a decrease in the current Ii, and thus a decrease in the frequency of the signal clki.

[0067] According to one embodiment, each circuit 4i includes a node 404i, which is coupled to a node 400i via a switch SW3i, such that when the switch SW3i is turned on, a current Icompi flows from node 404i to node 400i (controlled operation), and conversely, when the switch SW3i is turned off, node 400i is isolated from node 404i and the current Icompi does not flow from node 404i to node 400i (uncontrolled operation). In an alternative embodiment, the switch SW3i can be omitted by providing other means (e.g., other switches) to selectively supply current Icompi to node 400i based on the state of these switches. For example, a controlled switch can be provided during uncontrolled operation, such that the current Icompi is forced to a zero value.

[0068] According to one embodiment, each circuit 4i includes a current source 402i configured to supply a current Isupplyi to a node 400i. As an example, each current source 402i couples node 4 to a corresponding node 400i. According to one embodiment, the current source 402i of each circuit 4i is configured such that the current Isupplyi it supplies to node 400i is equal to Ki multiplied by a reference current Iref, where Ki is a different factor for each circuit 4i. Therefore, when the circuit 4i is in an uncontrolled mode, the frequency of the signal clki transmitted by each circuit 4i is determined at least in part by the factor Ki of the circuit 4i and the current Iref.

[0069] According to one embodiment, each circuit 4i includes a circuit 6i having a node 404i as an output, the circuit 6i being configured to supply current Icompi to the node 404i.

[0070] According to one embodiment, each circuit 4i, and more specifically its circuit 6i, includes a circuit 7i configured to provide a current I+i determined by the signal sigF to node 404i, and a circuit 8i configured to draw a current Ii from node 404i. The current Icompi is then equal to the current I+i minus the current Ii.

[0071] In embodiments where both currents Ii and I+i are positive, an increase in the current Ii drawn from node 400i results in a decrease in the frequency of signal clki, while an increase in the current I+i supplied to node 400i results in an increase in the frequency of signal clki.

[0072] In an alternative embodiment where both currents Ii and I+i are negative, an increase (absolute value) in the current Ii drawn from node 400i results in an increase in the frequency of signal clki, and an increase (absolute value) in the current I+i supplied to node 400i results in a decrease in the frequency of signal clki.

[0073] According to one embodiment, circuit 7i of each circuit 4i is configured such that current I+i equals Ki multiplied by B multiplied by current I', where B is a factor determined by the value of signal sigF. For all circuits 4i, current I' is the same. For example, for any given value of signal sigF, the factor B is the same regardless of the circuit 4i under consideration.

[0074] According to one embodiment, circuit 8i of each circuit 4i is configured such that current Ii is equal to Ki multiplied by A multiplied by current I''. Current I'' is, for example, proportional to current Iref.

[0075] For each circuit 4i, the value of factor A is determined such that the frequency of signal clki differs from its target value when the current Icompi is only equal to the current Ii (current I+i equals 0), and that the frequency of signal clki can recover to its target value when the current Icompi is equal to the difference between current I+i and Ii and current I+i is a function of the non-zero signal sigF. Therefore, when currents Ii and I+i are positive, factor A is determined such that the frequency of signal clki is less than its setpoint frequency when the current Icompi supplied to node 400i is only equal to current Ii. Conversely, when currents I+i and Ii are negative, factor A is determined such that the frequency of signal clki is greater than its setpoint frequency when the current Icompi supplied to node 400i is only equal to current Ii.

[0076] Furthermore, the determination of factor A is preferably performed by considering the possible operating conditions of device 1, namely, possible variations in its operating temperature and its power supply voltage Vdd, and the effect of these variations on the frequency of signal clki when the current Icompi is zero (uncontrolled). When the value of factor A is determined during the design phase of device 1, i.e., before its manufacture, the effect of manufacturing variations on the frequency of signal clki when the current Icompi is zero is also considered.

[0077] According to one embodiment, during the design phase of device 1, the value of factor A is determined taking into account PVT (“process, voltage, temperature”) variations. Preferably, in this embodiment, the value of factor A is the same for all circuits 4i. As an example, in such an embodiment, when currents I+i and Ii are positive and current Icompi is zero, the maximum frequency that signal clki can use as PVT varies is observed. Starting from this maximum frequency of signal clki, and when current I+i is zero, the value of factor A and the value of current Ii gradually increase until the frequency of signal clki becomes less than its setpoint frequency. This value of signal A is used when circuit 4i operates in controlled mode. According to another example, in such an embodiment, when currents I+i and Ii are negative, the minimum frequency that signal clki can use as PVT varies when current Icompi is zero is observed. Starting from this minimum frequency of signal clki, and when current I+i is zero, the value of factor A and the value of current Ii (absolute value) gradually increase until the frequency of signal clki becomes greater than its setpoint frequency. When circuit 4i operates in controlled mode, this value of signal A will be used.

[0078] According to another embodiment, a calibration phase is provided for each circuit 4i to determine the value of factor A for each circuit 4i, taking into account possible variations in temperature and voltage Vdd, with the effects of manufacturing variations suppressed due to this calibration phase. In such an embodiment, the value of factor A differs between the two circuits 4i. Each circuit 8i can then be configured to change the value of factor A for that circuit. Furthermore, the maximum effect of variations in temperature and voltage Vdd on the frequency of signal clki (i.e., the worst possible deviation of the frequency of signal clki from the frequency of temperature and voltage Vdd) is known. The value of factor A is determined by considering the worst-case variation in the frequency of signal clki with variations in temperature and voltage Vdd, while the current I+i is zero, such that when the current Icompi is only equal to the current Ii, the frequency of signal clki differs from its setpoint frequency, and when the current Icompi is equal to the difference between the current Ii and I+i, the frequency of signal clki can be restored to the setpoint frequency.

[0079] As an example, with currents I+i and Ii being positive or negative respectively, this means that when current Icompi is zero (uncontrolled operation), the maximum and minimum frequencies that signal clki might employ under variations in temperature and voltage vdd are known. With currents I+i and Ii being positive or negative respectively, the calibration phase of circuit 8i is implemented as follows: Block 205 of phase-locked loop 2 is programmed to divide the frequency of the received signal clki by a number Mi' (the number Mi' equals a decrease or increase of Mi by X%) to account for the worst-case effects of temperature and voltage Vdd variations on the frequency of the signal clki. In other words, frequency divider 205 is reprogrammed during the calibration phase to account for variations in temperature and supply voltage at the selected signal clki's frequency. When the current I+i is zero, the value of factor A, and therefore the value of the current Ii (absolute value), gradually increases, preferably by resetting the frequency divider 205 at each step on the rising or falling edge of the signal clkref (depending on the direction of the phase detector 205). That is, for each new value of factor A, resetting the frequency divider 205 includes, for example, resetting the output of the flip-flop that forms it. The final or calibrated value of factor A is determined when the signal clkfb lags behind (when currents I+i and Ii are positive) or leads (when currents I+i and Ii are negative) the signal clkref. The final or calibration value of factor A is then stored in memory (not shown). During controlled operation, circuit 8i is controlled such that factor A is at the calibration value determined during the calibration phase, and the phase-locked loop divider block 205 is then programmed using the number Mi, rather than the number Mi'.

[0080] As an example, this calibration phase can be implemented by a circuit (not shown) for controlling device 1, such as a state machine, based on signals UP and DW available at the output of phase comparator 207 of phase-locked loop 2, such that, due to these signals, it can be detected that the frequency of signal clkfb, obtained by dividing the frequency of signal clki by Mi', is less than or greater than the frequency of signal clkref, respectively. More precisely, signals UP and DW are used to detect when the frequency of signal clkfb becomes less than or greater than the frequency of signal clkref, respectively. Preferably, this control circuit is also configured to control circuit 5. Preferably, this control circuit is also configured to control circuit 4i to be in a controlled mode or an uncontrolled mode, for example, by controlling switch SW3i of circuit 4i.

[0081] Compared to generators that generate multiple clock signals using multiple RC oscillators, Device 1 consumes less power because it does not include a capacitor ramp generator. Therefore, Device 1 is particularly suitable for so-called "low-power" applications.

[0082] Device 1 has been described above in the case where device 1 is configured to generate N different signals clki. According to an unclaimed embodiment, device 1 is configured to generate a single clock signal, such as signal clk1. In this case, device 1 is related to... Figure 1The device described is the same, except that it does not include circuits 42 to 4N, i.e., circuit 4i, where i ranges from 2 to N, it does not include circuit 5, and the signal clk1 is received by input 201 of the phase-locked loop.

[0083] According to one embodiment, each circuit 7i includes a current mirror, which includes an input branch and at least one output branch associated with the input branch. The at least one output branch is configured to provide a current I+i. The input branch is controlled by a signal sigF. For example, the input branch includes a voltage-to-current converter controlled by a second signal. The input branch is configured such that a current equal to B multiplied by the current I' flows therein. According to one embodiment, the input branch is shared by all circuits 7i, or in other words, the same input branch is shared by all circuits 7i. This is particularly because, in order to obtain the current I+i of a given circuit 7i, the current mirror of that circuit 7i is configured to direct the current B flowing through the shared input branch... I' is multiplied by a factor Ki specific to that circuit 7i. Providing such an input branch that is shared by all circuits 7i, relative to the case where each circuit 7i will include different input branches, can reduce the size and power consumption of device 1.

[0084] According to an embodiment preferably combined with the above embodiments, each circuit 8i includes a current mirror, which includes an input branch and at least one output branch associated with the input branch. The at least one output branch is configured to carry a current Ii. The input branch is configured such that a current I'' flows through it. According to one embodiment, this input branch is shared by all circuits 8i, or in other words, all circuits 8i share the same input branch. This is specifically because, in order to obtain the current Ii of a given circuit 8i, the current mirror of that circuit 8i is configured to multiply the current I'' flowing through the shared input branch by a factor Ki multiplied by a factor A specific to that circuit 8i. Providing such a shared input branch for all circuits 8i, compared to the case where each circuit 8i would include different input branches, reduces the size and power consumption of the device 1. It should be noted that, for embodiments where the value of factor A for each circuit 8i is calibrated, the at least one output branch of the current mirror can be controlled to change the value of factor A, or in other words, includes circuitry controllable to change the value of factor A.

[0085] For example, by means of a current mirror, the circuit described above can be implemented based on the functional description of these circuits, which will be within the capabilities of those skilled in the art. The current mirror has a ratio Ki of the current present in the input branch of the current mirror and the current provided by one or more output branches of the current mirror associated with the input branch.

[0086] Figure 2 schematically shown Figure 1An embodiment of circuit 8i of device 1. In this example, circuit 8i is configured to allow calibration steps such as those previously described, and it is derived from node 404i ( Figure 1 The current Ii drawn is positive.

[0087] Circuit 8i includes a current mirror 805. The current mirror includes an input branch 806 and an output branch 804.

[0088] Input branch 806 is configured to allow current I'' to flow through it. As an example, input branch 806 includes a current generator 807 connected in series with a MOS ("metal-oxide-semiconductor") transistor T2, the current generator 807 being configured to carry current I''. For example, transistor T2 has an N-channel and couples one terminal of generator 807 to node 3, with the other terminal of generator 807 coupled, preferably, to node 4.

[0089] According to one embodiment, the input branch 806 of the current mirror 805 of circuit 8i is shared by all circuits 8i. In other words, the current mirror 805 of all circuits 8i shares the same input branch 806.

[0090] The output branch 804 of the current mirror 805 is configured to supply or generate current Ii, that is, to draw current Ii from the output of circuit 8i.

[0091] Branch 804 includes a MOS transistor T1, wherein the channel type is the same as that of transistor T2. Transistor T1 is assembled as a mirror image of transistor T2. In other words, the gates of transistors T1 and T2 are connected together and connected to the drain of transistor T2. For example, the first conductive terminal (e.g., the source) of transistor T1 is coupled (preferably connected) to node 3 at ground potential, and the second conductive terminal (e.g., its drain) of transistor T1 is coupled to the output of circuit 8i.

[0092] Transistor T1 is configured to provide a copy of the product of current I'' and factor Ki and factor Amax. In other words, transistor T1 is configured to provide a value equal to Amax. Ki The current of I''. In other words, the ratio of the size ratio of transistor T1 to the size ratio of transistor T2 is equal to the product of the coefficient Ki of circuit 8i and Amax.

[0093] In this embodiment, to allow for the calibration phase, circuit 8i further includes circuit 800, which is configured to controllably reduce the value of factor A relative to its maximum value Amax. In other words, transistor T1 and circuit 800 are configured together to provide or generate current Ii from current I''. Furthermore, the output branch 804 of current mirror 805 is controllably configured to change the value of factor A. In this example, circuit 800 includes a first terminal 801 coupled to, and preferably connected to, a second conductive terminal of transistor T1, and a second terminal 802 coupled to, for example, the output of circuit 8i.

[0094] According to one embodiment, circuit 800 includes a plurality of MOS transistors between its terminals 801 and 802. These MOS transistors, for example, have N-channel windings, are connected in series with each other, and are also connected in series with switch SW5. The series-connected transistors have their gates connected to each other and to the gate of transistor T1. Figure 2 In the example shown, circuit 800 includes two transistors T3 and T4, with transistor T4 coupled to terminal 802 via switch SW5. According to this embodiment, circuit 800 also includes switches connected in parallel with each of transistors T3 and T4. More specifically, in the example shown, circuit 800 includes a switch SW6 connected in parallel with transistor T3 and a switch SW7 connected in parallel with transistor T4.

[0095] According to this embodiment of circuit 800, when switch SW5 is off, the current Ii in branch 804 is zero. However, when switch SW5 is on, the current Ii is equal to Ki. Amax / (n+1) I'', n is a factor determined by the number of switches SW6 and SW7 that are turned on. In fact, the more the number of switches SW6 and SW7 that are turned on decreases, the more the equivalent resistance of circuit 800 between these terminals 801 and 802 increases, and therefore the more the value of factor n increases. The more the value of factor n increases, the more the value of factor A (which here equals Amax / (n+1)) decreases, and therefore the more the value of current Ii decreases. In other words, when a switch connected in parallel with one of the transistors in circuit 800 is turned off, that transistor is ultimately connected in series with transistor T1, which causes the current Ii to decrease.

[0096] The value of factor A is changed, for example, during the calibration phase described previously, by controlling the on and off states of the switches in control circuit 800, which is implemented to determine the value of factor A. As an example, during this calibration phase, switches SW5, SW6, and SW7 of circuit 800 are controlled by signals UP and DW. Figure 1For example, in the first step, switch SW5 is off and current Ii is zero, or in other words, factor A is zero. In the second step, switch SW5 is on and all other switches are off, and factor A is then at a non-zero minimum value. In the third step, to increase the value of factor A, the switches other than switch SW5 are sequentially turned on. The frequency divider 205 is preferably reset after each change in the value of factor A, and signals UP and DW are used to determine the value of factor A, with signal clfkb becoming phase-lagging relative to signal clkref for the value of factor A. This value is then used in the controlled mode by controlling the switching of circuit 800 in an appropriate manner.

[0097] An example of transistors connected in series in circuit 800 has been described herein. In another embodiment, not shown, the current mirror 805 may be specified to include multiple output branches connected in parallel, each output branch providing a current Amax. Ki Part of I''. In this case, circuit 800, for example, includes a switch for each output branch, such that the switching state of each output branch determines the current Amax supplied by that output branch. Ki Does the portion I'' contribute to the current Ii? In other words, the output branch of the current mirror is controllable to change the value of factor A.

[0098] The circuit 8i is suitable for implementing the calibration step to determine the value of factor A, as described above. If the design of device 1 determines the value of factor A and no calibration stage is provided to determine the value of factor A for each circuit 8i, circuit 800 can be omitted, and factor Amax is then equal to the factor A determined by the design of device 1.

[0099] The case where the current Ii drawn from the output of circuit 8i is positive has been described above. In the case where the current Ii drawn from the output of circuit 8i is negative, circuit 8i can be provided with an additional P-channel MOS transistor current mirror. The first MOS transistor of this additional current mirror is connected in series with the output branches(s) of the current mirror 805 of circuit 8i, and between node 4 and the output of circuit 8i, the second MOS transistor of this additional current mirror is assembled as a mirror of the first transistor. As a variation, nodes 3 and 4 can be reversed, as described above regarding... Figure 2 The channel type of each transistor in the described circuit 8i.

[0100] Figure 3 schematically shown Figure 1 An embodiment of circuit 7i of device 1. In this example, circuit 7i is configured such that it directs power to node 404i ( Figure 1The current I+i provided is positive, and when the signal clkfb lags or leads the signal clkref in phase, it operates with voltage sigF, which increases or decreases respectively.

[0101] Circuit 7i includes a current mirror 702. The current mirror 702 includes an input branch 703 and an output branch 701 associated with the input branch 703. The output branch is configured to supply current I+i.

[0102] Input branch 703 is controlled by voltage sigF. More specifically, branch 703 is configured such that the current I700 it conducts is equal to B times the current I'.

[0103] In this embodiment, input branch 703 includes a voltage-to-current converter 700 controlled by the signal sigF. In this example, the voltage-to-current converter includes a MOS transistor T7, which has an N-channel design and is connected in series with a resistor R2 between the two terminals 704 and 705 of the converter 700. Transistor T7 is controlled by the signal sigF, or in other words, the gate of transistor T7 receives the signal sigF. Transistor T7 has a first conductive terminal coupled to terminal 705 (e.g., its source) and a second conductive terminal coupled to terminal 704 (e.g., its drain). More specifically, in Figure 3 In the example, the source of transistor T7 is connected to terminal 706 of resistor R2, and the other terminal of resistor R2 is connected to terminal 705. Terminal 705 of converter 700 is coupled, preferably, to node 3, and terminal 704 of converter 700 is coupled to node 4.

[0104] Input branch 703 also includes a MOS transistor T6, which in this example has a P-channel and is connected in series with converter 700 between nodes 3 and 4. Transistor T6 couples terminal 704 of converter 700 to node 4.

[0105] According to one embodiment, the input branch 703 of the current mirror 702 of circuit 7i is shared by all circuits 7i. In other words, the current mirror 702 of all circuits 7i shares the same input branch 703.

[0106] The output branch 701 associated with input branch 703 is configured to supply current I+i from the current of I700. More precisely, branch 701 is configured to provide a copy of current I700 multiplied by a factor Ki, such that current I+i flows through branch 701. Therefore, branch 701 includes MOS transistor T5. Transistor T5 has the same type of channel as transistor T6. Transistor T5 is mirror-assembled with transistor T6. In other words, the gate of transistor T5 is connected to the gate of transistor T6, and the gate of transistor T6 is connected to the drain of transistor T6. A conductive terminal of transistor T5 (e.g., its source) is connected to node 4, and another conductive terminal of transistor T5 (e.g., its drain) is coupled, for example, to the output of circuit 7i. The size ratio of transistor T5 to transistor T6 is equal to the factor Ki.

[0107] In the circuit example above, when the voltage sigF increases, the voltage across resistor R2 (i.e., the voltage at terminal 706) increases. This causes the current through resistor R2 to increase, resulting in an increase in current I700, or in other words, an increase in the value of factor B. This leads to a corresponding increase in current I+i.

[0108] The case where the current mirror 702 includes a single output branch 701 has been described above. In another example, not shown, the current mirror 702 may be specified to include multiple output branches or multiple current replicas, each of which then supplies a portion of the current I+i.

[0109] An example of a circuit 8i configured to provide a positive current I+i and operate with a voltage sigF has been described above, where the voltage sigF increases or decreases as the signal clkfb lags or leads the signal clkref in phase. When the current I+i is negative and the voltage sigF increases or decreases, it would be sufficient, for example, to invert nodes 3 and 4 and the channel type of each transistor in the circuit 8i described above, when the signal clkfb lags or leads the signal clkref in phase. More generally, adapting the previously described circuit 8i to cases where the current I+i is negative and / or the voltage sigF increases or decreases in phase, when the signal clkfb lags or leads the signal clkref in phase, would be within the capabilities of those skilled in the art.

[0110] Therefore, in this disclosure, the clock signals clkl, ..., clki, ..., clkN are generated through the following steps: Circuit 5 is used to select one of the signals clki; The signal sigF is transmitted through phase-locked loop 2. The signal sigF varies according to the difference between the frequency of the signal clkfb obtained by dividing the selected signal clki and the frequency of the reference clock signal clkref. For each clock signal in the clock signals clk1, ..., clki, ..., clkN, currents Isuppli1, ..., Isupplyi, IsuppliN are supplied to nodes 4001, ..., 400i, ..., 400N of the corresponding circuits 41, ..., 4i, ..., 4N, including ring oscillators 51, ..., 5i, ..., 5N connected to nodes 4001, ..., 400i, ..., 400N to transmit clock signals clk1, ..., clki; and For circuit 4i that transmits the selected signal clki, selectively, i.e. only during the controlled operation phase of circuit 4i, the compensation currents Icomp1, ..., Icompi, ..., IcompN determined by the signal sigF are provided to node 400i of circuit 4i.

[0111] Embodiments and variations of device 1 and the circuitry forming it have been described above. Figure 1 , Figure 2 and Figure 3 The description has been provided. Other implementations of the device 1 and the circuitry forming it based on the given functional description are within the capabilities of those skilled in the art. For example, other implementations of the phase-locked loop 2, circuits 6i, 7i, 8i, 800, and / or 700 besides those previously described are within the capabilities of those skilled in the art.

[0112] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0113] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art. An apparatus for generating a plurality of first clock signals (clk1, clki, clkN), the apparatus (1) may be summarized as including: first circuits (41, 4i, 4N), each first circuit including a ring oscillator (51, 5i, 5N), the ring oscillator being configured to transmit one of the plurality of first clock signals (clk1, clki, clkN), the oscillator being connected to a first node (4001, 400i, 400N) configured to receive a first current (Isupply1, Isupplyi, IsupplN); and circuit (5) configured to receive the first clock signals (clk1, clki, clkN) and transmit from the first clock signal (clk1, clki, clkN). The first clock signal (clk-sel) selected from lk1, clki, clkN; and the phase-locked loop (2) are configured to transmit a second signal (sigF), which varies according to the difference between the frequency of the selected first clock signal and the setpoint frequency, the setpoint frequency being determined by the frequency of a third signal, the third signal being a clock signal (clkref) received by the phase-locked loop, wherein when the first circuit transmits the selected first clock signal and the first circuit operates in a mode controlled by the phase-locked loop, each first circuit (41, 4i, 4N) is configured to transmit a compensation current (Icomp1, Icompi, IcompN) determined by the second signal (sigF) to the first node. Each first circuit (41, 4i, 4N) may include: a first current source (4021, 402i, 402N) configured to provide a first current (Isupply1, Isupplyi, IsuppplyN) to a first node (4001, 400i, 400N); a second node (4041, 404i, 404N) coupled to the first node (4001, 400i, 400N); a second circuit (71, 7i, 7N) configured to provide a second current (I+1, I+i, I+N) determined by a second signal (sigF) to the second node (4041, 404i, 404N); and a third circuit (81, 8i, 8N) configured to draw a third current (I-1, Ii, IN) from the second node. In each first circuit (41, 4i, 4N): the first current source (4021, 402i, 402N) can be configured such that the first current (Isupply1, Isupplyi, IsuppplyN) is equal to Ki multiplied by the reference current Iref; the second circuit (71, 7i, 7N) can be configured such that the second current (I+1, I+i, I+N) is equal to Ki multiplied by B multiplied by the fourth current (I') which is the same for all first circuits, where B is a factor determined by the second signal (sigF); and the third circuit (81, 8i, 8N) can be configured such that the third current (I-1, Ii, IN) is equal to Ki multiplied by A multiplied by the fifth current (I''), which is the same for all first circuits (41, 4i, 4N) and proportional to the reference current Iref. Each third circuit (81, 8i, 8N) may include a current mirror (805), the current mirror (805) including an input branch (806) and at least one output branch (804) associated with the input branch, the at least one output branch being configured to provide a third current (I-1, Ii, IN). In each third circuit (81, 8i, 8N), the input branch (806) of the current mirror (805) may include a generator (807) for a fifth current (I''). The input branch (806) of the current mirror (805) of each third circuit (81, 8i, 8N) can be shared by all third circuits (81, 8i, 8N). In each third circuit (81, 8i, 8N), the at least one output branch (804) may include a circuit (800) that can be controlled to modify the value of factor A. Each second circuit (71, 7i, 7N) may include a current mirror (702), the current mirror (702) including an input branch (703) and at least one output branch (701) associated with the input branch, the last output branch being configured to provide a second current (I+1, I+i, I+N). In each of the second circuits (71, 7i, 7N), the input branch (703) can be controlled by a second signal (sigF) and can be configured such that the sixth current (I700) is equal to B multiplied by the fourth current (I') flowing therein. In each of the second circuits (71, 7i, 7N), the input branch (703) may include a voltage-to-current converter (700) controlled by a second signal (sigF). The voltage-to-current converter (700) may include a transistor (T7) connected in series with a resistor (R2), the transistor (T7) being controlled by a second signal (sigF). The input branch (701) of the current mirror (702) of the second circuit (71, 7i, 7N) can be shared by all the second circuits. The phase-locked loop (2) may include: a frequency divider (205) programmed according to a first selection signal (clk1, clki, clkN) and configured to receive the selected first signal and transmit a periodic signal (clkfb) at a specific frequency divided relative to the frequency of the selected first signal; a phase comparator (207) configured to transmit a first binary signal (UP) and a second binary signal (DW), the first binary signal (UP) indicating that the periodic signal (clkfb) is phase-lagging relative to a second clock signal (clkref), and the second binary signal (DW) indicating that the periodic signal (clkfb) is phase-leading relative to the second clock signal (clkref); a charge pump (209) controlled by the first binary signal and the second binary signal (UP, DW) and configured to transmit a signal (Δ) that varies according to the phase difference between the periodic signal (clkfb) and the second clock signal (clkref); and a filter (211) configured to transmit a second signal (sigF) based on the signal (Δ) transmitted by the charge pump (209). Each first circuit (41, 4i, 4N) may include: a first current source (4021, 402i, 402N) configured to provide a first current (Isupply1, Isupplyi, IsuppplyN) to a first node (4001, 400i, 400N); a second node (4041, 404i, 404N) coupled to the first node (4001, 400i, 400N); a second circuit (71, 7i, 7N) configured to provide a second current (I+1, I+i, I+N) determined by a second signal (sigF) to the second node (4041, 404i, 404N); and a third circuit (81, 8i, 8N) configured to draw a third current (I-1, Ii, IN) from the second node, wherein in each first circuit (41, 4i, 4N): the first current source (4021, 402i, 402N) is configured to provide a first current (Isupply1, Isupplyi, IsuppplyN) to a first node (4001, 400i, 400N); a second node (4041, 404i, 404N) coupled to the first node (4001, 400i, 400N); a second circuit (71, 7i, 7N) configured to provide a second current (I+1, I+i, I+N) to the second node (4041, 404i, 404N); and a third circuit (81, 8i, 8N) configured to draw a third current (I-1, Ii, IN) from the second node, wherein in each first circuit (41, 4i, 4N): the first current source (4021, 402i, 402N) is configured to provide a first current (Isupply1, Isu 402i, 402N) are configured such that the first current (Isupply1, Isupplyi, IsuppplyN) is equal to Ki multiplied by the reference current Iref; the second circuit (71, 7i, 7N) is configured such that the second current (I+1, I+i, I+N) is equal to Ki multiplied by B multiplied by the same fourth current (I') for all first circuits, where B is a factor determined by the second signal (sigF); and the third circuit (81, 8i, 8N) is configured such that the third current (I-1, Ii, IN) is equal to Ki multiplied by A multiplied by the same fifth current (I'') for all first circuits (41, 4i, 4N) and proportional to the reference current Iref, and wherein in each third circuit (81, 8i, 8N), the at least one output branch (804) includes a circuit (800) controllable to modify the value of factor A. A method for generating multiple first clock signals (clk1, clki, clkN) can be summarized as follows: selecting one of the first signals by a selection circuit (5); transmitting a second signal (sigF) by a phase-locked loop (2), the second signal (sigF) varying according to the difference between the frequency of the selected first signal and the setpoint frequency of the selected first signal; and for each of the one or more first clock signals (clk1, clki, clkN), providing a first current (Isupply1, Isupplyi, IsuppplyN) to the corresponding first circuit ( The first nodes (4001, 400i, 400N) of the first circuit (41, 4i, 4N) include a ring oscillator (51, 5i, 5N) connected to the first node (4001, 400i, 400N) and transmits one of the first clock signals (clk1, clki, clkN); and only when the first circuit operates in a mode controlled by the phase-locked loop (2), the first circuit provides a compensation current determined by the second signal (sigF) to the first node (4001, 400i, 400N) of the first circuit that transmits the selected first signal. The method can be implemented using the device (1) described in the embodiments herein. The method can be implemented by the device (1) according to the embodiments herein, the method comprising: for each first circuit (4i), determining a calibration value of factor A of the third circuit (8i) of the first circuit (4i), the determination of the calibration value comprising: selecting a first clock signal (clki) of the first circuit (4i) by means of a selection circuit (5); reprogramming a frequency divider (205) to take into account the temperature and power supply voltage of the device (1) at the frequency of the selected first clock signal (clk-sel); drawing a third current (Ii) from the first node (400i) and increasing the value of factor A by controlling the at least one output branch (804) of the third circuit (8i); and for each value of factor A, resetting the frequency divider (205) and determining whether the periodic signal (clkfb) is phase-leading or phase-lagging relative to the second clock signal (clkref) based on a first binary signal and a second binary signal (UP, DW), the calibration value of factor A being a first value of factor A, wherein: in the second current and the third current (I+ When i and Ii are positive in the controlled mode, the periodic signal (clkfb) lags behind the second clock signal (clkref) in phase; or when the second current and the third current (I+i, Ii) are negative in the controlled mode, the periodic signal (clkfb) leads the second signal (clkref) in phase.

[0114] The various embodiments described above can be combined to provide further embodiments.

[0115] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used herein should not be construed as limited to the specific embodiments disclosed in the specification, but should be interpreted to include all possible embodiments claimed herein and the full scope of their equivalents.

Claims

1. An apparatus for generating a plurality of first clock signals, the apparatus comprising: A plurality of first circuits, each of the first circuits including a ring oscillator configured to transmit one of the plurality of first clock signals, the ring oscillator being connected to a first node configured to receive a first current, wherein each first circuit includes: A first current source is configured to provide the first current to the first node; The second node is coupled to the first node; A second circuit is configured to provide a second current, determined by a second signal, to the second node; and The third circuit is configured to draw a third current from the second node; A signal selection circuit is configured to receive the first clock signal and transmit a first clock signal selected from the first clock signal; and A phase-locked loop is configured to transmit the second signal, which varies according to the difference between the frequency of a selected first clock signal and a setpoint frequency determined by the frequency of a third signal, the third signal being a clock signal received by the phase-locked loop.

2. The device of claim 1, wherein each first circuit is configured to transmit a compensation current determined by the second signal to the first node when the first circuit transmits the selected first clock signal and the first circuit operates in a mode controlled by the phase-locked loop.

3. The device according to claim 2, wherein in each first circuit: The first current source is configured such that the first current is equal to Ki multiplied by a reference current, where Ki is a corresponding factor for the first circuit among the plurality of first circuits. The second circuit is configured such that the second current equals Ki multiplied by B multiplied by a fourth current, wherein the fourth current is the same for all first circuits, and B is a factor determined by the second signal; and The third circuit is configured such that the third current is equal to Ki multiplied by A multiplied by the fifth current, which is the same for all first circuits and is proportional to the reference current.

4. The device of claim 3, wherein each third circuit includes a current mirror having an input branch and at least one output branch associated with the input branch, the at least one output branch being configured to provide the third current.

5. The device of claim 4, wherein in each third circuit, the input branch of the current mirror includes the generator of the fifth current.

6. The device of claim 5, wherein the input branch of the current mirror of each third circuit is shared by all third circuits.

7. The device of claim 4, wherein in each third circuit, the at least one output branch includes circuitry controllable to modify the value of factor A.

8. The device of claim 3, wherein each second circuit includes a current mirror having an input branch and at least one output branch associated with the input branch, the at least one output branch being configured to provide the second current.

9. The device of claim 8, wherein in each second circuit, the input branch is controlled by the second signal and configured such that a sixth current flows through it. The sixth current is equal to B multiplied by the fourth current.

10. The device of claim 8, wherein in each second circuit, the input branch includes a voltage-to-current converter controlled by the second signal.

11. The device of claim 10, wherein the voltage-to-current converter comprises a transistor connected in series with a resistor, the transistor being controlled by the second signal.

12. The device of claim 8, wherein the input branch of the current mirror of the second circuit is shared by all the second circuits.

13. The device according to claim 4, wherein the phase-locked loop comprises: A frequency divider, which is programmable according to the selected first clock signal and configured to receive the selected first clock signal and transmit a periodic signal at a frequency divided relative to the frequency of the selected first clock signal; A phase comparator is configured to transmit a first binary signal and a second binary signal, the first binary signal indicating when the periodic signal lags behind the third signal in phase, and the second binary signal indicating when the periodic signal leads the third signal in phase. A charge pump, controlled by the first binary signal and the second binary signal and configured to transmit a signal that varies according to the phase difference between the periodic signal and the third signal; as well as The filter is configured to transmit the second signal based on the signal transmitted by the charge pump.

14. The device of claim 13, wherein each first circuit comprises: The first current source is configured to provide the first current to the first node; The second node is coupled to the first node; The second circuit is configured to provide the second current, determined by the second signal, to the second node; as well as The third circuit is configured to draw the third current from the second node. In each of the first circuits: The first current source is configured such that the first current is equal to Ki multiplied by a reference current Iref, where Ki is a corresponding factor for the first circuit among the plurality of first circuits; The second circuit is configured such that the second current is equal to Ki multiplied by B multiplied by a fourth current, the fourth current being the same for all first circuits, and B being a factor determined by the second signal. and The third circuit is configured such that the third current is equal to Ki multiplied by A multiplied by the fifth current, which is the same for all first circuits and is proportional to the reference current Iref. Furthermore, in each of the third circuits, the at least one output branch includes circuitry controllable to modify the value of factor A.

15. A method for generating a plurality of first clock signals, comprising: The selection circuit selects one of the first clock signals from the first clock signals; A second signal is transmitted via a phase-locked loop, the second signal varying according to the difference between the frequency of the selected first clock signal and the setpoint frequency of the selected first clock signal; For each of the one or more first clock signals, a first current is provided to a first node of the corresponding first circuit, each first circuit comprising: A first current source is configured to provide the first current to the first node; The second node is coupled to the first node; A second circuit is configured to provide a second current determined by the second signal to the second node; and The third circuit is configured to draw a third current from the second node; A ring oscillator, connected to the first node and transmitting a first clock signal from the first clock signals; and The compensation current determined by the second signal is provided by the first circuit to the first node of the first clock signal selected by the first circuit only when the first circuit is operating in the mode controlled by the phase-locked loop.

16. The method of claim 15, wherein the method comprises: For each first circuit, a calibration value for factor A of the third circuit of the first circuit is determined, wherein the third circuit includes a current mirror having an input branch and at least one output branch associated with the input branch, the at least one output branch being configured to provide a third current, and wherein the determination of the calibration value includes: The first clock signal of the first circuit is selected by the selection circuit; The frequency divider of the phase-locked loop is reprogrammed to take into account the temperature and power supply voltage of the device used to generate the plurality of first clock signals at the selected frequency of the first clock signal; The third current is drawn from the first node, and the value of factor A is increased by controlling at least one output branch of the third circuit; and For each value of factor A, the frequency divider is reset and a first binary signal and a second binary signal are used to determine whether the periodic signal is phase-leading or phase-lagging relative to a third signal, wherein the third signal is a clock signal received by the phase-locked loop, the first binary signal indicating when the periodic signal is phase-lagging relative to the third signal, and the second binary signal indicating when the periodic signal is phase-leading relative to the third signal. The calibration value of factor A is the first value of factor A, wherein: When the second current and the third current are positive in the controlled mode, the periodic signal becomes phase-lagging relative to the second signal; or When the second current and the third current are negative in the controlled mode, the periodic signal becomes phase-leading relative to the second signal; The selected first clock signal is determined by the frequency of the third signal.

17. An apparatus for generating a plurality of first clock signals, the apparatus comprising: A first circuit includes a ring oscillator configured to transmit one of the plurality of first clock signals, the ring oscillator being connected to a first node configured to receive a first current. The first circuit includes: A first current source is configured to provide the first current to the first node; The second node is coupled to the first node; A second circuit is configured to provide a second current, determined by a second signal, to the second node; and The third circuit is configured to draw a third current from the second node; A signal selection circuit is configured to receive the first clock signal and transmit a first clock signal selected from the plurality of first clock signals; and A phase-locked loop (PLL) is configured to transmit a second signal that varies based on the difference between the frequency of a selected first clock signal and a setpoint frequency determined by the frequency of a third signal, which is a clock signal received by the PLL. The first circuit is configured to transmit a compensation current determined by the second signal to the first node when the first circuit transmits the selected first clock signal and operates in a mode controlled by the phase-locked loop.

18. The device of claim 17, wherein in the first circuit: The first current source is configured such that the first current is equal to the first factor multiplied by the reference current; The second circuit is configured such that the second current is equal to the first factor multiplied by the second factor multiplied by the fourth current, where the second factor is a factor determined by the second signal; and The third circuit is configured such that the third current is equal to the first factor multiplied by the third factor multiplied by the fifth current, the fifth current being proportional to the reference current.

19. The device of claim 17, wherein the third circuitry includes a current mirror having an input branch and at least one output branch associated with the input branch, the at least one output branch being configured to provide the third current.

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