Semiconductor devices and methods

Abstract

The present disclosure relates to semiconductor devices and methods. In an embodiment, a method includes forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration in a range of 5% to 30%; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing reducing the nitrogen concentration of the liner layer to a range of 1% to 5%; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer being formed of silicon oxynitride with a nitrogen concentration in the range of 5% to 30%; depositing a filler material formed of silicon on the liner layer; annealing the liner layer and the filler material, the annealing converting the filler material to silicon oxynitride, the annealing reducing the nitrogen concentration of the liner layer to the range of 1% to 5%; and recessing the liner layer and the filler material to form an isolation region between the first fin and the second fin.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a first fin and a second fin extending from a semiconductor substrate; depositing a first dielectric material using an atomic layer deposition (ALD) process to form a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate; depositing a second dielectric material using a flowable chemical vapor deposition (FCVD) process to form a filler material on the liner layer, the second dielectric material being different from the first dielectric material, a portion of the liner layer being converted to the second dielectric material during the FCVD process; and recessing the liner layer and the filler material to form an isolation region between the first fin and the second fin.

[0006] According to another embodiment of this disclosure, a semiconductor structure is provided, comprising: a first fin extending from a substrate; a second fin extending from the substrate; and an isolation region between the first fin and the second fin, the isolation region comprising: a main layer of silicon oxide; and a liner layer of silicon oxynitride with a nitrogen concentration in the range of 1% to 5%, the liner layer being disposed between the main layer and each of the first fin, the second fin, and the substrate, wherein the top surfaces of the liner layer and the main layer are coplanar. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a FinFET according to some embodiments is shown in a 3D view.

[0009] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A and Figure 6B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 7 This is a flowchart of an example method for forming fins and STI regions according to some embodiments.

[0011] Figure 8 This is a graph showing the nitrogen concentration in the STI region according to some embodiments.

[0012] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B This is a cross-sectional view of other intermediate stages in the fabrication of a FinFET according to some embodiments.

[0013] Figure 16 These are charts of experimental data from different processes used to form the STI region. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "below," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0016] According to some embodiments, a shallow trench isolation (STI) region is formed having a silicon oxynitride liner and a silicon oxide filler. The silicon oxynitride has a selected nitrogen concentration to protect underlying features (e.g., semiconductor fins) from oxidation during subsequent processing. For example, annealing may be performed during the process of forming the filler material for the STI region. The liner has a sufficient nitrogen concentration to protect the semiconductor fins from oxidation during annealing, but its nitrogen concentration is also low enough to avoid etch load during subsequent processing.

[0017] Figure 1 A simplified example of a FinFET according to some embodiments is shown in a three-dimensional view. For clarity of illustration, certain other features of the FinFET (discussed below) are omitted. The FinFET shown can be electrically coupled in one manner to operate, for example, as a single transistor or multiple transistors (e.g., four transistors).

[0018] The FinFET includes fins 54 extending from a substrate 50. STI regions 66 are disposed on the substrate 50, and fins 54 protrude over and between adjacent STI regions 66. Although the isolation regions 66 are described / shown as separate from the substrate 50, as used herein, the term "substrate" can be used to refer to a semiconductor substrate only or a semiconductor substrate including the isolation regions. Additionally, although fins 54 are shown as a single continuous material of the substrate 50, fins 54 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fin 54 refers to the portion extending over and between adjacent STI regions 66.

[0019] Gate structure 110 is located above the channel region of fin 54. Gate structure 110 includes gate dielectric 112 and gate electrode 114. Gate dielectric 112 is located along the sidewall of fin 54 and above its top surface, and gate electrode 114 is located above gate dielectric 112. Source / drain regions 94 are disposed on the opposite side of fin 54 relative to gate structure 110. Gate spacer 92 separates source / drain regions 94 from gate structure 110. In embodiments forming multiple transistors, source / drain regions 94 may be shared among various transistors. In embodiments where a transistor is formed by multiple fins 54, adjacent source / drain regions 94 may be electrically coupled, for example, by merging source / drain regions 94 using epitaxial growth, or by coupling source / drain regions 94 to the same source / drain contact. One or more interlayer dielectric (ILD) layers (discussed further below) are formed over the source / drain region 94 and / or the gate electrode 114, and contacts (discussed further below) are formed through the ILD layers to the source / drain region 94 and the gate electrode 114.

[0020] Figure 1 Several reference cross-sections are further shown. Cross-section AA is along the longitudinal axis of gate electrode 114. Cross-section BB is perpendicular to cross-section AA and along the longitudinal axis of fin 54. Cross-section CC is parallel to cross-section AA and extends through the source / drain region 94 of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0021] Some embodiments discussed herein are described in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices (e.g., planar FETs).

[0022] Figures 2A to 6B This is a cross-sectional view of an intermediate stage in the manufacturing of FinFETs according to some embodiments. Figure 2A , Figure 3A , Figure 4A , Figure 5A and Figure 6A It shows Figure 1 The reference cross section AA is shown, and multiple fins 54 are also shown. Figure 2A , Figure 3A , Figure 4A , Figure 5A and Figure 6A The characteristics of both the n-type region 50N and the p-type region 50P are shown (discussed further below). Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B It shows Figure 1 The reference cross-section BB shown includes multiple fins 54. Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B Features of either the n-type region 50N or the p-type region 50P are shown. For example, Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B The structure shown can be applied to both n-type region 50N and p-type region 50P, and the structural differences between n-type region 50N and p-type region 50P (if any) are described in the text accompanying each figure.

[0023] As will be discussed in more detail below, Figures 2A to 6B The formation of fin 54 is shown (see Figure 2A and Figure 2B And an STI region 66 is formed around fin 54 (see...) Figure 6A and Figure 6B The process of ). Figure 7 This is a flowchart of an example method 200 for forming fins 54 and STI regions 66 according to some embodiments. This is achieved by first forming a liner layer 62 (see...). Figure 3A and Figure 3B ) and filler material 64 (see Figure 4A and Figure 4BThe STI region 66 is formed by depositing a first material and then subsequently converting it into a second material, such as an oxide. Advantageously, the liner layer 62 is formed of a dielectric material that helps protect the fin 54 from oxidation during the conversion of the filler material 64. Such a dielectric material is said to have good "oxidation resistance" because it helps avoid or reduce oxidation of underlying features such as the fin 54. During the conversion process, the composition of the dielectric material in the liner layer 62 is changed. After the conversion process, the material of the liner layer 62 has a similar etching rate to the filler material 64 relative to the etching process used to recess the STI region 66. Therefore, the etching load in subsequent processing steps can be avoided or reduced.

[0024] exist Figure 2A and Figure 2B In step 202 of method 200, a substrate 50 is provided, and fins 54 extending from the substrate 50 are formed. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0025] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, or an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, or a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P.

[0026] Fins 54 are formed in substrate 50. Fins 54 are semiconductor strips. In some embodiments, fins 54 can be formed in substrate 50 by etching trenches 52 in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof, and can be performed using a mask 56 patterned with fins 54. Etching can be anisotropic.

[0027] Mask 56 can be a single-layer mask or a multi-layer mask, such as a multi-layer mask each including a first mask layer 56A and a second mask layer 56B. Both the first mask layer 56A and the second mask layer 56B can be formed of a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. The material of the first mask layer 56A can have high etch selectivity relative to the etching of the material of the second mask layer 56B. For example, the first mask layer 56A can be formed of silicon oxide, and the second mask layer 56B can be formed of silicon nitride.

[0028] The fin 54 can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fin 54. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 54. In some embodiments, a mask 56 may be retained on the fin 54.

[0029] exist Figure 3A and Figure 3B In step 204 of method 200, a liner layer 62 is deposited in trenches 52 in the substrate 50, for example, on the top surface of the substrate 50, the sidewalls of the fin 54, and on the mask 56 (if present) or the top surface of the fin 54. The liner layer 62 is formed of a dielectric material that will be changed during subsequent processing. Examples of dielectric materials include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc. The liner layer 62 can be formed by deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), etc. In some embodiments, the liner layer 62 is formed of silicon oxynitride by ALD, and the nitrogen concentration of the silicon oxynitride (e.g., atomic percentage) will be reduced in subsequent processing.

[0030] As an example of forming the liner layer 62, the substrate 50 can be placed in an ALD chamber, where an ALD cycle is performed by sequentially introducing source precursor gas into the ALD chamber to deposit the liner layer 62. The ALD process is a conformal deposition process. Therefore, the thickness of the horizontal portion of the liner layer 62 is equal to the thickness of the vertical portion of the liner layer 62. The thickness T1 of the liner layer 62 is discussed in more detail below.

[0031] In step 206 of method 200, a first pulse of the ALD cycle is performed by exposing the substrate 50 to the silicon source precursor by introducing the silicon source precursor into the ALD chamber. In some embodiments, the silicon source precursor is hexachlorosilane (Si₂Cl₆, HCD), but other silicon source precursors can be used. The first pulse can be performed at a temperature in the range of about 450°C to about 700°C and a pressure in the range of about 50 Pa to about 200 Pa (e.g., which the ALD chamber can maintain). In some embodiments, no plasma is turned on when the silicon source precursor is introduced into the ALD chamber. During the first pulse, OH bonds at the surface of the substrate 50 are broken. OH bonds may be present at the surface of the substrate 50 due to the formation of native oxides and / or exposure to moisture prior to the ALD process. When the OH bonds break, silicon atoms from the silicon source precursor (along with the chlorine atoms bonded thereto) bond to oxygen atoms to form O-Si-Cl bonds, wherein each silicon atom is bonded to three chlorine atoms. The silicon source precursor can be held in the ALD chamber for a duration ranging from about 5 seconds to about 120 seconds. The silicon source precursor is then purged from the ALD chamber, for example, by an acceptable vacuum process and / or by allowing an inert gas to flow into the ALD chamber.

[0032] In step 208 of method 200, a second pulse of the ALD cycle is performed by exposing the substrate 50 to the oxygen source precursor by introducing it into the ALD chamber. In some embodiments, the oxygen source is oxygen dioxide (O2), but other oxygen source precursors can be used. The second pulse can be performed at a temperature ranging from about 450°C to about 700°C and at a pressure ranging from about 600 Pa to about 2000 Pa (e.g., which the ALD chamber can maintain). In some embodiments, no plasma is turned on when the oxygen source precursor is introduced into the ALD chamber. During the second pulse, some Si-Cl bonds break. When the Si-Cl bonds break, oxygen atoms from the oxygen source precursor bond to silicon atoms to form O-Si-O bonds. Some O-Si-Cl bonds are retained such that each silicon atom is bonded to two oxygen atoms and one chlorine atom. The oxygen source precursor can be maintained in the ALD chamber for a duration ranging from about 5 seconds to about 100 seconds. Then, the oxygen source precursor is removed from the ALD chamber, for example, by an acceptable vacuum process and / or by allowing an inert gas to flow into the ALD chamber.

[0033] In step 210 of method 200, a third pulse of the ALD cycle is performed by exposing the substrate 50 to a nitrogen source precursor by introducing the precursor into the ALD chamber. In some embodiments, the nitrogen source precursor is ammonia (NH3), but other nitrogen source precursors can be used. The third pulse can be performed at a temperature ranging from about 450°C to about 700°C and a pressure ranging from about 600 Pa to about 1500 Pa (e.g., where the ALD chamber can maintain). In some embodiments, no plasma is turned on when the nitrogen source precursor is introduced into the ALD chamber. During the third pulse, the remaining Si-Cl bonds break. As the Si-Cl bonds break, nitrogen atoms from the nitrogen source precursor bond with silicon atoms to form O-Si-N bonds. As a result, each silicon atom bonds to two oxygen atoms and one nitrogen atom. Hydrogen atoms from the nitrogen source precursor also bond with oxygen atoms to form OH bonds. The nitrogen source precursor can be maintained in the ALD chamber for a duration ranging from about 5 seconds to about 100 seconds. Then, the nitrogen source precursor is removed from the ALD chamber, for example by an acceptable vacuum process and / or by allowing an inert gas to flow into the ALD chamber.

[0034] In the above process, the pulses executed sequentially in steps 206, 208, and 210 can be referred to as an ALD cycle. The ALD cycle leads to the growth of an atomic layer (sometimes called a monolayer), which comprises silicon atoms and correspondingly bonded nitrogen and oxygen atom groups. The thickness of the atomic layer produced by the ALD cycle can be approximately... to approximately Within the range.

[0035] The ALD cycle is then repeated by repeating steps 206, 208, and 210, resulting in the deposition of multiple atomic layers to form the liner layer 62. In subsequent ALD cycles, due to the pulsing effect of the silicon source precursor, the OH bonds formed in the previous ALD cycle break, and O-Si-Cl bonds are formed. Then, due to the pulsing effect of the oxygen source precursor, some O-Si-Cl bonds are replaced by Si-O bonds. Then, due to the pulsing effect of the nitrogen source precursor, other Si-Cl bonds are replaced by Si-N bonds, and more OH bonds are formed.

[0036] Repeat the ALD cycle until the liner layer 62 has the desired thickness T1. Thickness T1 can be approximately... to approximately Within this range. As will be discussed in more detail below, depositing the liner layer 62 to have a thickness T1 within this range helps to provide sufficient protection against oxidation of the fin 54 and helps to avoid etch loads during subsequent processing steps. It should be understood that many atomic layers can be deposited depending on the desired thickness T1 of the liner layer 62. For example, to form a liner layer 62 with the aforementioned thickness T1, an ALD cycle can be repeated from about 5 to about 100 times. The number of times the ALD cycle is repeated within this range allows the liner layer 62 to form with such a thickness T1. The number of times the ALD cycle is repeated beyond this range may not allow the liner layer 62 to form with such a thickness T1.

[0037] After the ALD process is completed, the silicon concentration of the liner layer 62 is in the range of about 20% to about 50%, the oxygen concentration is in the range of about 20% to about 50%, and the nitrogen concentration is in the range of about 5% to about 30%. As will be discussed in more detail below, forming a liner layer 62 with a nitrogen concentration within this range helps to provide sufficient protection against oxidation of the fins 54 and helps to avoid etch loads during subsequent processing steps. The pulses of the ALD process performed at the temperatures and for the durations discussed above allow the liner layer 62 to form with such a nitrogen concentration. Pulses of the ALD process performed outside the temperatures or for the durations discussed above may not allow the liner layer 62 to form with such a nitrogen concentration.

[0038] Subsequently, in step 212 of method 200, a filler material 64 will be formed on the lining layer 62 (see...). Figures 4A to 5B The filler material 64 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), FCVD, etc. Specifically, and as discussed further below, the filler material 64 is initially formed from a first material and subsequently converted to a second material. In some embodiments, an FCVD process is performed, wherein the filler material 64 is initially formed from a semiconductor material and subsequently converted to a dielectric material by post-curing. Examples of semiconductor materials include silicon, germanium, etc. Examples of dielectric materials include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0039] exist Figure 4A and Figure 4B In step 214 of method 200, a first layer for filler material 64 is deposited on liner layer 62. In the illustrated embodiment, filler material 64 is an amorphous silicon layer deposited by CVD-based material deposition in a remote plasma. As discussed further below, the silicon will be transformed into another material, such as an oxide, through post-curing.

[0040] exist Figure 5A and Figure 5BIn step 216 of method 200, the liner layer 62 and the filler material 64 are annealed to convert the filler material 64 into a dielectric material. In some embodiments, annealing is performed using a wet annealing process with steam (H2O) as the process gas, but other process gases can be used. The process gas (e.g., H2O) can be generated by in-situ steam generation (ISSG), but other techniques can be used to generate the process gas. The wet annealing process drives oxygen from the process gas (e.g., water / steam) into the filler material 64, thereby converting the filler material 64 into a dielectric material. In some embodiments, the filler material 64 is silicon before the wet annealing process and silicon oxide after the wet annealing process. The wet annealing process is performed at a high temperature (e.g., a temperature in the range of about 400°C to about 750°C). The wet annealing process can be performed for a duration in the range of about 1 hour to about 5 hours. Performing a wet annealing process at temperatures below about 400°C or for a duration of less than about 1 hour may result in insufficient oxidation of the filler material 64, while performing a wet annealing process at temperatures above about 750°C or for a duration of more than about 5 hours may result in oxidation of the fin 54. In some embodiments, the wet annealing temperature may be lower when the fin 54 is formed to a smaller average critical size (e.g., less than about 5 nm).

[0041] The liner layer 62 protects the fins 54 from oxidation during the wet annealing process. As described above, the liner layer 62 can be formed of a dielectric material with good oxidation resistance, such as silicon oxynitride with a nitrogen concentration of at least about 5%. Forming the liner layer 62 from this dielectric material allows the liner layer 62 to prevent oxygen atoms from being driven from the filler material 64 into the fins 54, as the presence of nitrogen helps to prevent oxidation. Therefore, oxidation of the fins 54 can be avoided or reduced, which can improve the performance of the FinFET.

[0042] During the wet annealing process, the composition of the dielectric material of the liner 62 is altered. In embodiments where the liner 62 is formed of silicon oxynitride, the wet annealing process removes nitrogen from the liner 62 to reduce the nitrogen concentration of the silicon oxynitride. For example, after the wet annealing process is complete, the liner 62 may have a silicon concentration in the range of about 20% to about 50%; an oxygen concentration in the range of about 20% to about 50%; and a nitrogen concentration of less than 10%, for example less than 5%, for example in the range of about 1% to about 5%. The final nitrogen concentration of the liner 62 may be reduced to about 10% of the initial nitrogen concentration of the liner 62. In some embodiments, the wet annealing process removes some nitrogen from the liner 62, such that the liner 62 is silicon oxynitride with a lower nitrogen concentration after the wet annealing process than before the wet annealing process. In some embodiments, the wet annealing process removes all nitrogen from the liner 62, such that the liner 62 is silicon oxide after the wet annealing process.

[0043] As described above, the liner layer 62 is formed such that the initial composition of the dielectric material of the liner layer 62 has a nitrogen concentration in the range of about 5% to about 30%. If the initial nitrogen concentration of the liner layer 62 is less than about 5%, the liner layer 62 may not have sufficient oxidation resistance to protect the fins 54 from oxidation during the wet annealing process. Specifically, all nitrogen may be driven out of the liner layer 62 before the wet annealing process is completed. Undesirable oxidation of the fins 54 may therefore occur. If the initial nitrogen concentration of the liner layer 62 is greater than about 30%, the liner layer 62 and the filler material 64 may have different etching rates. Specifically, too much nitrogen may remain in the liner layer 62 after the wet annealing process is completed. The material of the liner layer 62 may therefore have high etch selectivity in the etching of the filler material 64. Undesirable etch loads may therefore occur during subsequent processing steps. Reducing the nitrogen concentration of the liner layer 62 reduces the etch selectivity between the liner layer 62 and the filler material 64. The liner layer 62 is formed to have an initial nitrogen concentration in the range of about 5% to about 30%, which helps to avoid or reduce undesirable oxidation of the fin 54 and helps to ensure sufficient reduction of etch selectivity between the liner layer 62 and the filler material 64 to avoid subsequent etch load.

[0044] Reducing the nitrogen concentration of liner 62 can improve its electrical properties. Specifically, when liner 62 is initially formed with a higher nitrogen concentration, it can have a larger effective oxide charge relative to substrate 50, but reducing the nitrogen concentration of liner 62 also reduces the effective oxide charge relative to substrate 50. For example, the interface between liner 62 and substrate 50 (e.g., each fin 54) can have a charge as high as about 5 × 10⁻⁶ before the wet annealing process. 11 Coulomb's effective oxide charge (Q) eff However, after wet annealing, the temperature can be reduced to approximately 2×10⁻⁶.11 Coulomb's effective oxide charge (Q) eff Reducing the effective oxide charge at the interface between the liner layer 62 and the substrate 50 can reduce channel leakage and improve the channel mobility of the resulting FinFET.

[0045] During the wet annealing process, the thickness of the liner 62 is reduced. This reduction in thickness occurs because a portion of the liner 62 is converted to the filler material 64. Specifically, the upper portion of the liner 62 (e.g., those portions closest to the filler material 64) can be converted from the material of the liner 62 (e.g., silicon oxynitride) to the material of the filler material 64 (e.g., silicon oxide). Conversely, the lower portion of the liner 62 (e.g., those portions furthest from the filler material 64) remains the material of the liner 62 (e.g., silicon oxynitride, although with a reduced nitrogen concentration). For example, after the wet annealing process is completed, the thickness T2 of the remaining portion of the liner 62 can be approximately... to approximately Within the range. The final thickness T2 of the lining layer 62 can be approximately 10% to approximately 30% of the initial thickness T1 of the lining layer 62.

[0046] As described above, a lining layer 62 is formed such that the initial thickness T1 is approximately to approximately Within the range. If the initial thickness T1 is less than approximately The liner layer 62 may not have sufficient oxidation resistance to protect the fins 54 from oxidation during the wet annealing process. Specifically, the thickness of the liner layer 62 may be reduced too much before the wet annealing process is complete, and therefore the liner layer 62 may not be able to prevent oxygen atoms from being driven from the filler material 64 into the fins 54. Undesirable oxidation of the fins 54 may therefore occur. If the initial thickness T1 is greater than approximately The liner 62 and the filler material 64 may have different etch rates. Specifically, the lower portion of the liner 62 (e.g., those portions far from the filler material 64) may not have enough nitrogen expelled from it, and therefore too much nitrogen may remain in the liner 62 after the wet annealing process is complete. The material of the liner 62 can therefore have high etch selectivity in the etching of the filler material 64. Therefore, undesirable etch loads may occur during subsequent processing steps. The liner 62 is formed to have approximately to approximately The initial thickness T1 is within the range, which helps to avoid or reduce unwanted oxidation of fin 54 and subsequent etching load.

[0047] exist Figure 6A and Figure 6BIn step 218 of method 200, the liner layer 62 and the filler material 64 are recessed to form an STI region 66 between the fins 54. The liner layer 62 and the filler material 64 can be recessed by planarization, etching, or a combination thereof. For example, the liner layer 62 and the filler material 64 can be planarized and then subsequently etched.

[0048] The liner layer 62 and filler material 64 can be planarized first. This removes excess portions of the liner layer 62 and filler material 64 above the fin 54. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be used. The planarization process exposes the fin 54 such that, after the planarization process is completed, the top surfaces of the fin 54, liner layer 62, and filler material 64 are coplanar (within process variations). In embodiments where the mask 56 remains on the fin 54, the planarization process can expose or remove the mask 56 such that, after the planarization process is completed, the top surfaces of either the mask 56 or the fin 54, liner layer 62, and filler material 64 are coplanar (within process variations).

[0049] After planarization, the liner layer 62 and filler material 64 can be etched to form the STI region 66. This causes the liner layer 62 and filler material 64 to be recessed, such that the upper portion of the fin 54 in the n-type region 50N and p-type region 50P protrudes between adjacent STI regions 66. Furthermore, the top surface of the STI region 66 can have a flat surface, a raised surface, a recessed surface (e.g., a depression), or a combination thereof, as shown. The top surface of the STI region 66 can be formed as flat, raised, and / or recessed through appropriate etching. The STI region 66 can be etched using an acceptable etching process, such as an etching process selective for the materials of the liner layer 62 and filler material 64 (e.g., etching the materials of the liner layer 62 and filler material 64 at a faster rate than etching the materials of the fin 54). For example, wet etching using, for example, dilute hydrofluoric acid (dHF) can be used. As described above, the final nitrogen concentration of the liner layer 62 is low enough that the liner layer 62 has a similar etching rate to the filler material 64 relative to the etching process used to recess the STI region 66. For example, in some embodiments, the etching process used to recess the STI region 66 removes one or more materials of the liner layer 62 and the filler material 64 at substantially the same rate. Thus, after the STI region 66 is formed, the top surfaces of the liner layer 62 and the filler material 64 are coplanar (within process variations). Each resulting STI region 66 includes a liner or liner layer (including the recessed portion of the liner layer 62) and a main layer (including the recessed portion of the filler material 64).

[0050] about Figures 2A to 6BThe described process is merely one example of how the fin 54 can be formed. In some embodiments, the fin 54 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes from the dielectric layer to form the fin 54. Furthermore, in some embodiments, heteroethelic structures can be used for the fin 54. For example, the fin 54 can be recessed before the STI region 66 is fully recessed (e.g., after planarization but before etching), and a material different from the fin 54 can be epitaxially grown over the recessed fin 54. In such embodiments, the fin 54 comprises the recessed material and an epitaxially grown material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer. The heteroepitaxial structure can then be epitaxially grown in the trench using a material different from that of the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fin 54. In some embodiments of epitaxial growth of homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be doped in situ during growth, which avoids prior and subsequent implantation, but in-situ and implantation doping can be used together.

[0051] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., the PMOS region) in the n-type region 50N (e.g., the NMOS region). In various embodiments, the upper portion of the fin 54 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0052] Furthermore, suitable wells (not shown) may be formed in the fin 54 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N, and an N-well may be formed in the p-type region 50P. In some embodiments, either a P-well or an N-well may be formed in both the n-type region 50N and the p-type region 50P.

[0053] In embodiments with different well types, photoresist and / or other masks (not shown) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fin 54 and STI region 66 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin coating technique, and the photoresist can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be equal to or less than 10 18 cm -3 (For example, in about 10) 16 cm -3 To about 10 18 cm -3 Phosphorus, arsenic, antimony, etc., are injected into the region at concentrations between [a certain range]. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0054] Following implantation into the p-type region 50P, a photoresist is formed over the fins 54 and STI region 66 within the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be equal to or less than 10 18 cm -3 (For example, in about 10) 16 cm -3 To about 10 18 cm -3 Boron, boron fluoride, indium, etc., are implanted into the region at concentrations between [a certain range]. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0055] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation; however, in-situ and implantation doping can be used together.

[0056] Figure 8This is a graph illustrating the nitrogen concentration in the STI region 66 at different distances from the substrate 50 according to some embodiments. As shown, the concentration through the liner layer 62 at a first distance D1 is constant, corresponding to a first concentration C1. The first concentration C1 is the final nitrogen concentration of the liner layer 62 (e.g., in the range of about 1% to about 5%). The first distance D1 is the final thickness T2 of the liner layer 62 (e.g., in the range of about 1%). to approximately (within the range). Some nitrogen removed from liner 62 during annealing diffuses into filler 64 near the interface between liner 62 and filler 64. Thus, the nitrogen concentration through filler 64 decreases (e.g., with a negative gradient) to a second concentration C2 at the second distance D2. The second concentration C2 can be approximately zero. The second distance D2 can be approximately... to approximately Within the range.

[0057] Figures 9A to 15B This is a cross-sectional view of other intermediate stages in the fabrication of a FinFET according to some embodiments. Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A It shows Figure 1 The reference cross section AA is shown, and multiple fins 54 are also shown. Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15B It shows Figure 1 The reference cross-section BB shown is excluding the single fin 54. Figure 9C and Figure 9D It shows Figure 1 The reference cross section AA is shown, and multiple fins 54 are also shown. Figures 9A to 15B The characteristics of either the n-type region 50N or the p-type region 50P are shown. For example, Figures 9A to 15B The structure shown can be applied to both n-type region 50N and p-type region 50P, and the structural differences between n-type region 50N and p-type region 50P (if any) are described in the text accompanying each figure.

[0058] exist Figure 9A and Figure 9BIn this embodiment, a dummy dielectric 70 is formed on fin 54, and a dummy gate 72 is formed on dummy dielectric 70. The dummy gate 72 extends along the sidewalls and top surface of fin 54. As an example of forming the dummy dielectric 70 and dummy gate 72, a dummy dielectric layer is formed on fin 54. For example, the dummy dielectric layer can be silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a mask layer is formed on the dummy gate layer. The dummy gate layer can be deposited on the dummy dielectric layer and then (e.g., by CMP) planarized. The mask layer can be deposited on the dummy gate layer. The dummy gate layer can be a conductive or non-conductive material and can be selected from the group consisting of: amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing conductive materials. The dummy gate layer can be made of other materials that have high etch selectivity in etching the isolation region. The mask layer can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer and a single mask layer are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer is shown covering only fin 54. In some embodiments, the dummy dielectric layer can be deposited such that it covers the STI region 66, extending between the dummy gate layer and the STI region 66. The mask layer is then patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of mask 74 is then transferred to the dummy gate layer using acceptable etching techniques to form a dummy gate 72. In some embodiments, the pattern of mask 74 is further transferred to the dummy dielectric layer to form a dummy dielectric 70. A dummy gate 72 covers the corresponding channel region 68 of the fin 54. The pattern of the mask 74 can be used to separate each dummy gate 72 from the adjacent dummy gate entity. The dummy gate 72 may also have a length direction substantially perpendicular to the length direction of the fin 54.

[0059] Gate spacer 92 is formed on the exposed surfaces of dummy gate 72, mask 74, and / or fin 54. Gate spacer 92 can be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material of gate spacer 92 can be silicon nitride, silicon carbonitride, silicon oxycarbonitride, combinations thereof, etc., and can be formed by thermal oxidation, deposition, combinations thereof, etc. In some embodiments, gate spacer 92 is formed of a multilayer insulating material and includes multiple layers. For example, gate spacer 92 can include multiple layers of silicon carbonitride, can include multiple layers of silicon oxycarbonitride, or can include a silicon oxide layer disposed between two layers of silicon nitride. The etching of gate spacer 92 can be anisotropic. After etching, gate spacer 92 can have straight sidewalls or curved sidewalls.

[0060] Implantation for lightly doped source / drain (LDD) regions can be performed before or during the formation of the gate spacer 92. In embodiments with different device types, similar to the above... Figure 8 The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 54 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have a density of approximately 10... 15 cm -3 To about 10 19 cm -3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0061] Epitaxial source / drain regions 94 are formed in fin 54. The epitaxial source / drain regions 94 are formed in fin 54 such that each dummy gate 72 is disposed between adjacent pairs of the corresponding epitaxial source / drain regions 94. In some embodiments, the epitaxial source / drain regions 94 may extend into fin 54 and may also penetrate fin 54. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain regions 94 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 94 do not short-circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 94 can be selected to apply stress in the corresponding channel region 68, thereby improving performance.

[0062] The epitaxial source / drain region 94 in the n-type region 50N can be formed by masking the p-type region 50P and etching the source / drain region of the fin 54 in the n-type region 50N to form a groove in the fin 54. The epitaxial source / drain region 94 in the n-type region 50N is then epitaxially grown in the groove. The epitaxial source / drain region 94 can comprise any acceptable material (e.g., suitable for an n-type FinFET). For example, if the fin 54 is silicon, the epitaxial source / drain region 94 in the n-type region 50N can comprise a material to which tensile strain is applied in the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 94 in the n-type region 50N can have a surface protruding from the corresponding surface of the fin 54 and can have facets.

[0063] The epitaxial source / drain region 94 in the p-type region 50P can be formed by masking the n-type region 50N and etching the source / drain region of the fin 54 in the p-type region 50P to form a groove in the fin 54. The epitaxial source / drain region 94 in the p-type region 50P is then epitaxially grown in the groove. The epitaxial source / drain region 94 can comprise any acceptable material (e.g., suitable for a p-type FinFET). For example, if the fin 54 is silicon, the epitaxial source / drain region 94 in the p-type region 50P can comprise a material that applies compressive stress in the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 94 in the p-type region 50P can have a surface protruding from the corresponding surface of the fin 54 and can have a facet.

[0064] The epitaxial source / drain regions 94 and / or fins 54 can be implanted with dopants to form the source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19 cm -3 To about 10 21 cm -3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 94 can be doped in situ during growth.

[0065] As a result of the epitaxial process used to form the epitaxial source / drain regions 94 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions has small planes that extend laterally outward beyond the sidewalls of the fin 54. In some embodiments, these small planes cause adjacent epitaxial source / drain regions 94 of the same FinFET to merge, such as... Figure 9CAs shown. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 94 remain separated, as shown. Figure 9D As shown. In Figure 9C and Figure 9D In the illustrated embodiment, a gate spacer 92 is formed to cover a portion of the sidewall of the fin 54 extending above the STI region 66, thereby blocking epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 92 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 66.

[0066] Note that the above disclosure generally describes the process for forming spacers, LDD regions, and source / drain regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, or steps can be performed in different sequences (e.g., spacers can be formed and removed), etc. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0067] exist Figure 10A and Figure 10B In this process, a first ILD layer 98 is deposited over a mask 74 (if present) or a dummy gate 72, an epitaxial source / drain region 94, and a gate spacer 92. The first ILD layer 98 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 96 is disposed between the first ILD layer 98 and the epitaxial source / drain region 94, the mask 74 (if present) or the dummy gate 72, and the gate spacer 92. The CESL 96 can be formed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has high etch selectivity in the etching of the first ILD layer 98.

[0068] exist Figure 11A and Figure 11BIn this process, a planarization process such as CMP can be performed to make the top surface of the first ILD layer 98 flush with the top surface of the mask 74 (if present) or the dummy gate 72. The planarization process can also remove the mask 74 over the dummy gate 72, as well as portions of the gate spacer 92 along the sidewalls of the mask 74. The planarization process can also remove portions of the CESL 96 located above the gate spacer 92 and the mask 74 (if present) or the dummy gate 72. After the planarization process, the top surfaces of the first ILD layer 98, the gate spacer 92, and the mask 74 (if present) or the dummy gate 72 are coplanar (within a process variation). Therefore, the top surface of the mask 74 (if present) or the dummy gate 72 is exposed through the first ILD layer 98. In the illustrated embodiment, the mask 74 is retained, in which case the planarization process makes the top surface of the first ILD layer 98 flush with the top surface of the mask 74. In another embodiment, mask 74 is removed, in which case a planarization process makes the top surface of the first ILD layer 98 flush with the top surface of the dummy gate 72.

[0069] exist Figure 12A and Figure 12B In one or more etching steps, the mask 74 (if present) and dummy gate 72 are removed to form a recess 100. A portion of the dummy dielectric 70 within the recess 100 may also be removed. In some embodiments, the dummy gate 72 is removed, and the dummy dielectric 70 remains and is exposed by the recess 100. In some embodiments, the dummy dielectric 70 is removed from the recess 100 in a first region of the die (e.g., a core logic region) and remains in the recess 100 in a second region of the die (e.g., an input / output region). In some embodiments, the mask 74 and dummy gate 72 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the material of the mask 74 and dummy gate 72 at a faster rate than etching the material of the first ILD layer 98 and the gate spacer 92. Each recess 100 exposes and / or overlays a channel region 68 of the corresponding fin 54. Each channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 94. During removal, the dummy dielectric 70 can be used as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric 70 can then be optionally removed after the dummy gate 72 has been removed.

[0070] exist Figure 13A and Figure 13BIn this process, a gate dielectric 112 and a gate electrode 114 are formed to replace the gate. One or more layers of the gate dielectric 112 are deposited in the recess 100, for example, on the top surface and sidewalls of the fin 54 and on the sidewalls of the gate spacer 92. The gate dielectric 112 may also be formed on the top surface of the first ILD layer 98. In some embodiments, the gate dielectric 112 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric 112 comprises an interface layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric 112 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric 112 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy dielectric 70 is retained in the recess 100, the gate dielectric 112 comprises the material of the dummy dielectric 70 (e.g., silicon oxide).

[0071] As described above, the gate dielectric 112 may include an interface layer of silicon oxide. The interface between the gate dielectric 112 and the substrate 50 (e.g., each fin 54) may have a density reduced to approximately 2.9 × 10⁻⁶. 11 Coulomb's effective oxide charge (Q) eff As mentioned above, lining layer 62 exhibits good electrical properties after wet annealing (see above reference). Figure 5A and Figure 5B (Discussion). In some embodiments, the liner layer 62 has a smaller effective oxide charge relative to the substrate 50 than the gate dielectric 112. In other words, the interface between the liner layer 62 and the substrate 50 may have a smaller effective oxide charge (Q) than the interface between the gate dielectric 112 and the substrate 50. eff ).

[0072] Gate electrodes 114 are deposited on top of gate dielectric 112 and fill the remainder of trench 100. Gate electrode 114 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 114 is shown, gate electrode 114 may include any number of liner layers, any number of work function adjustment layers, and filler material. After filling trench 100, a planarization process such as CMP may be performed to remove excess material from gate dielectric 112 and gate electrode 114 located above the top surface of the first ILD layer 98. The remaining portion of one or more materials of gate dielectric 112 and gate electrode 114 thus forms the replacement gate of the resulting FinFET. Gate dielectric 112 and gate electrode 114 may be collectively referred to as gate structure 110 or “gate stack”. Gate structure 110 extends along the sidewall of channel region 68 of fin 54.

[0073] The formation of the gate dielectric 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric 112 in each region is formed of the same material, and the formation of the gate electrode 114 can occur simultaneously, such that the gate electrode 114 in each region is formed of the same material. In some embodiments, the gate dielectric 112 in each region can be formed by different processes, such that the gate dielectric 112 can be made of different materials, and / or the gate electrode 114 in each region can be formed by different processes, such that the gate electrode 114 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0074] exist Figure 14A and Figure 14B In this configuration, a second ILD layer 118 is deposited on top of a first ILD layer 98. In some embodiments, the second ILD layer 118 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer 118 is formed of a dielectric material (e.g., PSG, BSG, BPSG, USG, etc.) and can be deposited by any suitable method (e.g., CVD and PECVD). In some embodiments, an etch stop layer is formed between the first ILD layer 98 and the second ILD layer 118.

[0075] In some embodiments, prior to forming the second ILD layer 118, a gate mask 116 is formed over the respective gate stacks (including gate dielectric 112 and corresponding gate electrodes 114). The gate mask 116 is disposed between opposing pairs of gate spacers 92. In some embodiments, forming the gate mask 116 includes recessing the gate dielectric 112 and gate electrode 114 such that a groove is formed between opposing pairs of gate spacers 92. One or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., are filled in the groove, and a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD layer 98. The gate mask 116 includes the remaining portion of the dielectric material in the groove. A subsequently formed gate contact penetrates the second ILD layer 118 and the gate mask 116 to contact the top surface of the recessed gate electrode 114.

[0076] exist Figure 15A and Figure 15B Source / drain contacts 122 and gate contacts 124 are formed to the epitaxial source / drain regions 94 and 114, respectively. Openings for the source / drain contacts 122 are formed through the second ILD layer 118, the first ILD layer 98, and CESL 96. Openings for the gate contacts 124 are formed through the second ILD layer 118 and the gate mask 116. Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown), such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed within the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the second ILD layer 118. The remaining liner and conductive material form the source / drain contacts 122 and gate contacts 124 within the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 94 and the source / drain contact 122. The source / drain contact 122 is physically and electrically coupled to the epitaxial source / drain region 94, and the gate contact 124 is physically and electrically coupled to the gate electrode 114. The source / drain contact 122 and the gate contact 124 can be formed using different processes or the same process. Although each of the source / drain contact 122 and the gate contact 124 is shown as having the same cross-section, it should be understood that each of the source / drain contact 122 and the gate contact 124 can be formed with different cross-sections, which can prevent short circuits of the contacts.

[0077] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning an alternating stack of channel and sacrificial layers. The dummy gate stack and source / drain regions are formed in a manner similar to those described in the embodiments above. After the dummy gate stack is removed, the sacrificial layer may be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to those described in the embodiments above, and the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and contacts to the replacement gate structure and source / drain regions can be formed in a manner similar to those described in the embodiments above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0078] When the liner 62 is formed, performing the ALD process pulses at the above-mentioned temperature and for the above-mentioned duration can cause the liner 62 to form with the desired nitrogen concentration. Figure 16 These are charts of experimental data from different processes used to form liner layer 62. Specifically, Figure 16 The diagram shows the initial and final nitrogen concentrations of liner 62 (e.g., before and after the wet annealing process) when the third pulse of the ALD process is performed for different durations. The data points in region 102 are for liner layers formed by maintaining the oxygen source precursor within the ALD chamber for the durations described above. The initial nitrogen concentrations of these liner layers range from about 5% to about 30%, and the final nitrogen concentrations range from about 1% to about 5%. The data points in region 104 are for liner layers formed by maintaining the oxygen source precursor within the ALD chamber for durations exceeding the aforementioned range. The initial and final nitrogen concentrations of this liner layer are outside the desired range.

[0079] The embodiments can achieve advantages. Formation is achieved with an initial nitrogen concentration in the range of about 5% to about 30% and... to approximately The initial thickness of the liner layer 62 within the specified range helps provide sufficient oxidation resistance to protect the fins 54 during the wet annealing process used to form the filler material 64, and also helps ensure a sufficient reduction in etch selectivity between the liner layer 62 and the filler material 64 after the wet annealing process. Avoiding oxidation of the fins 54 helps improve the channel mobility of the resulting FinFET. Furthermore, forming a silicon oxynitride liner layer 62 may be superior to forming a liner layer 62 of other dielectric materials such as silicon nitride. For example, silicon oxynitride suffers less charge effect than silicon nitride, which helps reduce channel leakage in the resulting FinFET.

[0080] In one embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer being formed of silicon oxynitride with a nitrogen concentration in the range of 5% to 30%; depositing a filler material formed of silicon on the liner layer; annealing the liner layer and the filler material, the annealing converting the filler material to silicon oxynitride and reducing the nitrogen concentration of the liner layer to the range of 1% to 5%; and recessing the liner layer and the filler material to form an isolation region between the first fin and the second fin.

[0081] In some embodiments of the method, annealing the lining layer and filler material reduces the thickness of the lining layer. In some embodiments of the method, the thickness of the lining layer before annealing is... to Within the range, and the thickness of the lining layer after annealing is within... to Within the range of [specific ranges]. In some embodiments of the method, depositing the liner layer includes: placing a semiconductor substrate in a deposition chamber; performing an atomic layer deposition (ALD) cycle, including: introducing hexachlorosilane into the deposition chamber; removing hexachlorosilane from the deposition chamber; introducing oxygen into the deposition chamber; removing oxygen from the deposition chamber; introducing ammonia into the deposition chamber; removing ammonia from the deposition chamber; and repeating the ALD cycle. In some embodiments of the method, the hexachlorosilane is held in the deposition chamber for a duration ranging from 5 seconds to 120 seconds, the oxygen is held in the deposition chamber for a duration ranging from 5 seconds to 100 seconds, the ammonia is held in the deposition chamber for a duration ranging from 5 seconds to 100 seconds, and the ALD cycle is repeated 5 to 100 times. In some embodiments of the method, the introduction of hexachlorosilane, the introduction of oxygen, and the introduction of ammonia are each performed at a temperature ranging from 450°C to 700°C. In some embodiments of the method, annealing the lining and filler materials includes performing a wet annealing process at a temperature ranging from 400°C to 750°C for a duration ranging from 1 hour to 5 hours. In some embodiments of the method, the wet annealing process is performed using steam generated via in-situ steam generation (ISSG).

[0082] In one embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a first dielectric material using an atomic layer deposition (ALD) process to form a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate; depositing a second dielectric material using a flowable chemical vapor deposition (FCVD) process to form a filler material on the liner layer, the second dielectric material being different from the first dielectric material, and a portion of the liner layer being converted to the second dielectric material during the FCVD process; and recessing the liner layer and the filler material to form an isolation region between the first fin and the second fin.

[0083] In some embodiments of the method, recessing the liner and filler material includes etching the liner and filler material such that, after etching, the top surfaces of the liner and filler material are coplanar. In some embodiments of the method, etching the liner and filler material includes performing a wet etching using dilute hydrofluoric acid (dHF) to remove the liner and filler material at the same rate. In some embodiments of the method, prior to the FCVD process, the first dielectric material is silicon oxynitride with a nitrogen concentration in the range of 5% to 30%, and after the FCVD process, the first dielectric material is silicon oxynitride with a nitrogen concentration in the range of 1% to 5%. In some embodiments of the method, prior to the FCVD process, the thickness of the liner is... to Within the range, and after the FCVD process, the remaining thickness of the liner layer is within... to Within the range. In some embodiments of the method, depositing the second dielectric material using an FCVD process includes: depositing silicon using a chemical vapor deposition (CVD) process; and performing a wet annealing process to convert the silicon into silicon oxide. In some embodiments of the method, the first fin or the second fin does not oxidize during the wet annealing process. In some embodiments, the method further includes: forming a gate structure on the first fin, the second fin, and the isolation region; forming a first pair of source / drain regions in the first fin and adjacent to the gate structure; and forming a second pair of source / drain regions in the second fin and adjacent to the gate structure.

[0084] In one embodiment, a structure includes: a first fin extending from a substrate; a second fin extending from the substrate; and an isolation region between the first and second fins, the isolation region including: a main layer of silicon oxide; and a liner layer of silicon oxynitride with a nitrogen concentration in the range of 1% to 5%, the liner layer being disposed between the main layer and each of the first fin, the second fin, and the substrate, the top surfaces of the liner layer and the main layer being coplanar.

[0085] In some embodiments of this structure, the thickness of the lining layer is... to Within the range. In some embodiments, the structure further includes: a gate dielectric, an interface layer of silicon oxide including the first fin, the second fin, and the isolation region; and a gate electrode on the gate dielectric. In some embodiments of this structure, the interface between the liner layer and each of the first fin and the second fin has a first effective oxide charge, and the interface between the interface layer and each of the first fin and the second fin has a second effective oxide charge, the second effective oxide charge being greater than the first effective oxide charge.

[0086] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0087] Example 1 is a method of forming a semiconductor device, comprising: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer being formed of silicon oxynitride with a nitrogen concentration in the range of 5% to 30%; depositing a filler material formed of silicon on the liner layer; annealing the liner layer and the filler material, the annealing converting the filler material to silicon oxynitride, the annealing reducing the nitrogen concentration of the liner layer to the range of 1% to 5%; and recessing the liner layer and the filler material to form an isolation region between the first fin and the second fin.

[0088] Example 2 is the method described in Example 1, wherein annealing the lining layer and the filler material reduces the thickness of the lining layer.

[0089] Example 3 is the method described in Example 2, wherein the thickness of the lining layer prior to the annealing is... to Within the range, and the thickness of the lining layer after the annealing is within... to Within the range.

[0090] Example 4 is the method of Example 1, wherein depositing the liner layer includes: placing the semiconductor substrate in a deposition chamber; performing an atomic layer deposition (ALD) cycle, including: introducing hexachlorosilane into the deposition chamber; removing the hexachlorosilane from the deposition chamber; introducing oxygen into the deposition chamber; removing the oxygen from the deposition chamber; introducing ammonia into the deposition chamber; removing the ammonia from the deposition chamber; and repeating the ALD cycle.

[0091] Example 5 is the method of Example 4, wherein the hexachlorosilane is maintained in the deposition chamber for a duration ranging from 5 seconds to 120 seconds, the oxygen is maintained in the deposition chamber for a duration ranging from 5 seconds to 100 seconds, the ammonia is maintained in the deposition chamber for a duration ranging from 5 seconds to 100 seconds, and the ALD cycle is repeated 5 to 100 times.

[0092] Example 6 is the method described in Example 4, wherein the introduction of hexachlorosilane, the introduction of oxygen, and the introduction of ammonia are each performed at a temperature in the range of 450°C to 700°C.

[0093] Example 7 is the method described in Example 1, wherein annealing the lining layer and the filler material comprises performing a wet annealing process at a temperature in the range of 400°C to 750°C for a duration in the range of 1 hour to 5 hours.

[0094] Example 8 is the method described in Example 7, wherein the wet annealing process is performed using steam generated by in-situ steam generation (ISSG).

[0095] Example 9 is a method of forming a semiconductor device, comprising: forming a first fin and a second fin extending from a semiconductor substrate; depositing a first dielectric material using an atomic layer deposition (ALD) process to form a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate; depositing a second dielectric material using a flowable chemical vapor deposition (FCVD) process to form a filler material on the liner layer, the second dielectric material being different from the first dielectric material, a portion of the liner layer being converted to the second dielectric material during the FCVD process; and recessing the liner layer and the filler material to form an isolation region between the first fin and the second fin.

[0096] Example 10 is the method of Example 9, wherein recessing the lining layer and the filler material comprises: etching the lining layer and the filler material such that, after the etching, the top surfaces of the lining layer and the filler material are coplanar.

[0097] Example 11 is the method of Example 10, wherein etching the liner layer and the filler material comprises: performing a wet etching using dilute hydrofluoric acid (dHF) acid, the wet etching removing the liner layer and the filler material at the same rate.

[0098] Example 12 is the method described in Example 9, wherein, prior to the FCVD process, the first dielectric material is silicon oxynitride with a nitrogen concentration in the range of 5% to 30%, and after the FCVD process, the first dielectric material is silicon oxynitride with a nitrogen concentration in the range of 1% to 5%.

[0099] Example 13 is the method described in Example 9, wherein, prior to the FCVD process, the thickness of the liner layer is... to Within the range, and after the FCVD process, the remaining thickness of the liner layer is within... to Within the range.

[0100] Example 14 is the method described in Example 9, wherein depositing the second dielectric material using the FCVD process includes: depositing silicon using a chemical vapor deposition (CVD) process; and performing a wet annealing process to convert the silicon into silicon oxide.

[0101] Example 15 is the method described in Example 14, wherein the first fin and the second fin do not oxidize during the wet annealing process.

[0102] Example 16 is the method of Example 9, further comprising: forming a gate structure on the first fin, the second fin, and the isolation region; forming a first pair of source / drain regions in the first fin and adjacent to the gate structure; and forming a second pair of source / drain regions in the second fin and adjacent to the gate structure.

[0103] Example 17 is a semiconductor structure comprising: a first fin extending from a substrate; a second fin extending from the substrate; and an isolation region between the first fin and the second fin, the isolation region comprising: a main layer of silicon oxide; and a liner layer of silicon oxynitride with a nitrogen concentration in the range of 1% to 5%, the liner layer being disposed between the main layer and each of the first fin, the second fin, and the substrate, the top surfaces of the liner layer and the main layer being coplanar.

[0104] Example 18 is the structure described in Example 17, wherein the thickness of the lining layer is... to Within the range.

[0105] Example 19 is the structure described in Example 17, further comprising: a gate dielectric, including an interface layer of silicon oxide on the first fin, the second fin, and the isolation region; and a gate electrode on the gate dielectric.

[0106] Example 20 is the structure described in Example 19, wherein the interface between the liner layer and each of the first fin and the second fin has a first effective oxide charge, and the interface layer has a second effective oxide charge at the interface with each of the first fin and the second fin, the second effective oxide charge being greater than the first effective oxide charge.

Claims

1. A method for forming a semiconductor device, comprising: Form a first fin and a second fin extending from the semiconductor substrate; A liner layer is deposited along the first sidewall of the first fin, the second sidewall of the second fin, and the top surface of the semiconductor substrate. The liner layer is formed of silicon oxynitride with a nitrogen concentration in the range of 5% to 30%. A filler material formed of silicon is deposited on the liner layer; The lining layer and the filler material are annealed, the annealing converting the filler material into silicon oxide, and the annealing reducing the nitrogen concentration of the lining layer to a range of 1% to 5%, wherein the nitrogen concentration is based on atomic percentage; as well as The lining layer and the filler material are recessed to form an isolation area between the first fin and the second fin.

2. The method according to claim 1, wherein, Annealing the lining layer and the filler material reduces the thickness of the lining layer.

3. The method according to claim 2, wherein, The thickness of the lining layer before annealing is in the range of 15 Å to 50 Å, and the thickness of the lining layer after annealing is in the range of 1 Å to 10 Å.

4. The method according to claim 1, wherein, Depositing the lining layer includes: The semiconductor substrate is placed in the deposition chamber; Performing an atomic layer deposition (ALD) cycle includes: Hexachlorosilane is introduced into the deposition chamber; Remove the hexachlorosilane from the deposition chamber; Oxygen is introduced into the deposition chamber; Remove the oxygen from the deposition chamber; Ammonia is introduced into the deposition chamber; and Remove the ammonia from the deposition chamber; and Repeat the ALD loop.

5. The method according to claim 4, wherein, The hexachlorosilane is maintained in the deposition chamber for a duration ranging from 5 seconds to 120 seconds, the oxygen is maintained in the deposition chamber for a duration ranging from 5 seconds to 100 seconds, the ammonia is maintained in the deposition chamber for a duration ranging from 5 seconds to 100 seconds, and the ALD cycle is repeated 5 to 100 times.

6. The method according to claim 4, wherein, The introduction of hexachlorosilane, oxygen, and ammonia is carried out at temperatures ranging from 450°C to 700°C.

7. The method according to claim 1, wherein, Annealing the lining layer and the filler material includes: The wet annealing process is performed at a temperature ranging from 400°C to 750°C for a duration ranging from 1 hour to 5 hours.

8. The method according to claim 7, wherein, The wet annealing process is performed using steam generated by the ISSG through in-situ steam generation.

9. A method for forming a semiconductor device, comprising: Form a first fin and a second fin extending from the semiconductor substrate; A first dielectric material is deposited using atomic layer deposition (ALD) to form a liner layer along the first sidewall of the first fin, the second sidewall of the second fin, and the top surface of the semiconductor substrate. A second dielectric material is deposited using a flowable chemical vapor deposition (FCVD) process to form a filler material on the liner layer. The second dielectric material is different from the first dielectric material, and a portion of the liner layer is converted to the second dielectric material during the FCVD process. as well as The lining layer and the filler material are recessed to form an isolation area between the first fin and the second fin. Prior to the FCVD process, the first dielectric material is silicon oxynitride with a nitrogen concentration in the range of 5% to 30%, and after the FCVD process, the first dielectric material is silicon oxynitride with a nitrogen concentration in the range of 1% to 5%, wherein the nitrogen concentration is based on atomic percentage.

10. The method according to claim 9, wherein, Making the lining layer and the filling material recessed includes: The lining layer and the filler material are etched, and after the etching, the top surfaces of the lining layer and the filler material are coplanar.

11. The method according to claim 10, wherein, Etching the lining layer and the filler material includes performing a wet etching process using dilute hydrofluoric acid (dHF), which removes the lining layer and the filler material at the same rate.

12. The method according to claim 9, wherein, Before the FCVD process, the thickness of the liner layer is in the range of 15 Å to 50 Å, and after the FCVD process, the thickness of the remaining portion of the liner layer is in the range of 1 Å to 10 Å.

13. The method according to claim 9, wherein, Depositing the second dielectric material using the FCVD process includes: Silicon is deposited using chemical vapor deposition (CVD) processes; and A wet annealing process is performed to convert the silicon into silicon oxide.

14. The method according to claim 13, wherein, During the wet annealing process, the first fin and the second fin do not oxidize.

15. The method of claim 9, further comprising: A gate structure is formed on the first fin, the second fin, and the isolation region; A first pair of source / drain regions are formed in the first fin and adjacent to the gate structure; as well as A second pair of source / drain regions are formed in the second fin and adjacent to the gate structure.

16. A semiconductor structure comprising: The first fin extends from the substrate; A second fin extends from the substrate; An isolation region, located between the first fin and the second fin, the isolation region comprising: The main layer is silicon dioxide; and A liner layer, comprising silicon oxynitride with a nitrogen concentration ranging from 1% to 5%, is disposed between the main layer and each of the first fin, the second fin, and the substrate. The top surfaces of the liner layer and the main layer are coplanar, wherein the nitrogen concentration is based on atomic percentage. The semiconductor structure further includes: A gate dielectric, comprising a silicon oxide interface layer on the first fin, the second fin, and the isolation region; and Gate electrode, on the gate dielectric, The interface between the lining layer and each of the first fin and the second fin has a first effective oxide charge, and the interface layer has a second effective oxide charge at the interface with each of the first fin and the second fin, the second effective oxide charge being greater than the first effective oxide charge.

17. The structure according to claim 16, wherein, The thickness of the lining layer is in the range of 1 Å to 10 Å.

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