Method of manufacturing a semiconductor device

Abstract

The present disclosure relates to methods of fabricating semiconductor devices. One method includes forming dummy gate stacks on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stacks, forming a first interlayer dielectric, wherein the gate spacers and the dummy gate stacks are located in the first interlayer dielectric, removing the dummy gate stacks to form trenches between the gate spacers, forming replacement gate stacks in the trenches, and depositing a dielectric cap layer. A bottom surface of the dielectric cap layer contacts a first top surface of the replacement gate stacks and a second top surface of the first interlayer dielectric. A second interlayer dielectric is deposited over the dielectric cap layer. Source / drain contact plugs are formed extending into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric.

Description

Technical Field

[0001] This disclosure relates to methods for manufacturing semiconductor devices. Background Technology

[0002] Metal-oxide-semiconductor (MOS) devices are fundamental building blocks in integrated circuits. Recent developments in MOS devices involve forming replacement gates, which comprise a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. Forming the replacement gate typically involves depositing a high-k gate dielectric layer and a metal layer over the high-k gate dielectric layer, and then performing chemical mechanical polishing (CMP) to remove excess portions of the high-k gate dielectric layer and the metal layer. The remaining portion of the metal layer forms the metal gate. The metal gate can be recessed to form recesses between adjacent gate spacers, and then a self-aligned dielectric hard mask is formed in the trench. Summary of the Invention

[0003] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a dummy gate stack on a semiconductor fin; forming gate spacers on sidewalls of the dummy gate stack; forming a first interlayer dielectric, wherein the gate spacers and the dummy gate stack are located in the first interlayer dielectric; removing the dummy gate stack to form a trench between the gate spacers; forming a replacement gate stack in the trench; depositing a dielectric capping layer, wherein a bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric; depositing a second interlayer dielectric over the dielectric capping layer; and forming source / drain contact plugs extending into the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric.

[0004] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a metal gate in a first interlayer dielectric (ILD); performing a planarization process to make a first top surface of the metal gate flush with a second top surface of the first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is located on and in contact with both the first top surface and the second top surface; depositing a second ILD on the dielectric cap layer; and in an etching process, etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the contact opening passes through both the second ILD and the dielectric cap layer.

[0005] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a metal gate in a first interlayer dielectric (ILD); depositing a dielectric cap layer, wherein the dielectric cap layer is planar and is located over and in contact with both the metal gate and the first ILD; depositing a second ILD over and in contact with the dielectric cap layer, wherein both the first ILD and the second ILD are thicker than the dielectric cap layer; etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the etching is performed continuously until a top surface of an underlying feature is exposed; and forming a contact plug extending into the contact opening. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1-6 , Figure 7A , Figure 7B and Figure 8-19 Perspective views and cross-sectional views of intermediate stages in the formation of a fin field-effect transistor (FinFET) according to some embodiments are shown.

[0008] Figure 20A and Figure 20B The structures and schematic oxygen distributions according to some embodiments are shown respectively.

[0009] Figure 21 A comparison of X-ray photoelectron spectroscopy results for samples with and without capping layers according to some embodiments is shown.

[0010] Figure 22 A process flow for forming a FinFET is shown according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). Besides the orientations shown in the figures, spatially related terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0013] A fin field-effect transistor (FinFET) and a method for forming the same are provided. According to some embodiments of this disclosure, an oxygen-free dielectric capping layer capable of preventing oxygen diffusion is deposited on and in contact with a metal gate before forming an oxygen-containing interlayer dielectric. The interlayer dielectric is then deposited on the dielectric capping layer. Because the dielectric capping layer prevents oxygen diffusion, the underlying metal gate is not oxidized in a subsequent annealing process. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. The same reference numerals are used to denote the same elements throughout the various views and illustrative embodiments. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figure 1-6 , Figure 7A , Figure 7B as well as Figure 8-19 Cross-sectional and perspective views of intermediate stages in the fabrication of a fin field-effect transistor (FinFET) according to some embodiments of the present disclosure are shown. The processes illustrated in these figures are also schematically reflected in, for example... Figure 22 The process flow shown is 200.

[0015] exist Figure 1A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The semiconductor substrate 20 can be part of a wafer 10 (e.g., a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate 20 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0016] Further reference Figure 1 A well region 22 is formed in the substrate 20. The corresponding process is as follows: Figure 22 The process flow 200 shown is referred to as process 202. According to some embodiments of this disclosure, the well region 22 is an n-type well region formed by implanting an n-type impurity (which may be phosphorus, arsenic, antimony, etc.) into the substrate 20. According to other embodiments of this disclosure, the well region 22 is a p-type well region formed by implanting a p-type impurity (which may be boron, indium, etc.) into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The concentration of the n-type or p-type impurity may be equal to or less than 10. 18 cm -3 For example, in about 10 17 cm -3 To about 10 18 cm -3 Within the range between.

[0017] refer to Figure 2 The isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. The corresponding process is described in... Figure 22The process flow 200 shown is referred to as process 204. The portion of substrate 20 located between adjacent STI regions 24 is referred to as semiconductor strip 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then the pad oxide layer 28 and the hard mask layer 30 are patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of this disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of this disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of this disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The patterned photoresist is then used as an etch mask to pattern the hard mask layer 30 to form, as shown in the image. Figure 2 The hard mask 30 shown.

[0018] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with one or more dielectric materials. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material are STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, etc., formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 24 may also include a dielectric material on top of the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material on top of the liner dielectric may include silicon oxide.

[0019] The top surface of the hard mask 30 and the top surface of the STI region 24 can be substantially flush with each other. A semiconductor strip 26 lies between adjacent STI regions 24. According to some embodiments of this disclosure, the semiconductor strip 26 is a portion of the original substrate 20, and therefore the material of the semiconductor strip 26 is the same as that of the substrate 20. According to an alternative embodiment of this disclosure, the semiconductor strip 26 is a replacement strip formed by etching the portion of the substrate 20 located between the STI regions 24 to form a recess, and performing epitaxy to regrow another semiconductor material in the recess. Therefore, the semiconductor strip 26 is formed of a semiconductor material different from the semiconductor material of the substrate 20. According to some embodiments, the semiconductor strip 26 is formed of silicon-germanium, silicon-carbon, or a group III-V compound semiconductor material.

[0020] refer to Figure 3 The STI region 24 is recessed, causing the top of the semiconductor strip 26 to protrude above the top surface 24A of the remaining portion of the STI region 24, forming a protruding fin 36. The corresponding process is described in... Figure 22 The process flow 200 shown is designated as process 206. Etching can be performed using a dry etching process, where a mixture of HF3 and NH3 is used as the etching gas, for example. Plasma can be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess in the STI region 24 is performed using a wet etching process. For example, the etching chemicals may include HF.

[0021] In the above embodiments, the fins can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can then be used to pattern the fins.

[0022] refer to Figure 4 The dummy gate stack 38 is formed to extend on the top surface and sidewalls of the (protruding) fin 36. The corresponding process is... Figure 22 The process flow 200 shown is referred to as process 208. The dummy gate stack 38 may include a dummy gate dielectric 40 (in... Figure 7B(shown in the diagram) and a dummy gate electrode 42 over the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon or amorphous silicon, and may also use other materials. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 over the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may span over one or more protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the protruding fins 36.

[0023] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. The corresponding process is as follows: Figure 22 The process flow 200 shown is referred to as process 208. According to some embodiments of this disclosure, the gate spacer 46 is formed of one or more dielectric materials (e.g., silicon nitride, silicon carbonitride, etc.) and may have a single-layer structure or a multilayer structure including multiple dielectric layers.

[0024] Then, the portion of the protruding fin 36 not covered by the dummy gate stack 38 and the gate spacer 46 is etched to obtain... Figure 5 The structure shown. The corresponding process is... Figure 22 The process flow 200 is shown as process 210. The recess can be anisotropic, and thus the portion of fin 36 located directly below the dummy gate stack 38 and gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 can be lower than the top surface 24T of the STI region 24. A recess 50 is formed accordingly. The recess 50 includes a portion located on the opposite side of the dummy gate stack 38 and a portion between the remaining portions of the protruding fin 36.

[0025] Next, an epitaxial region (source / drain region) 52 is formed by selectively growing semiconductor material in the recess 50 (by epitaxy), thereby obtaining... Figure 6 The structure within. The corresponding processes are... Figure 22The process flow 200 shown is referred to as process 212. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in situ as epitaxy progresses. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc., can be grown. According to an alternative embodiment of this disclosure, the epitaxial region 52 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiples thereof. After the recess 50 is filled with the epitaxial region 52, further epitaxial growth of the epitaxial region 52 causes the epitaxial region 52 to extend horizontally and can form a small facet. Further growth of the epitaxial region 52 can also cause adjacent epitaxial regions 52 to merge with each other. Possible voids (air gaps) 53.

[0026] Following the epitaxial step, the epitaxial region 52 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated by reference numeral 52. According to an alternative embodiment of this disclosure, when the epitaxial region 52 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0027] Figure 7A A perspective view of the structure after the formation of the contact etch stop layer (CESL) 58 and the interlayer dielectric (ILD) 60 is shown. The corresponding process is described in... Figure 22 The process flow 200 shown is referred to as process 214. Figure 7B It shows Figure 7A The reference cross section BB of the structure is a vertical plane. CESL58 can be formed from silicon oxide, silicon nitride, silicon carbonitride, aluminum oxide, aluminum nitride, etc., and can be formed using CVD, ALD, etc. ILD 60 can include a dielectric material formed using, for example, PECVD, FCVD, spin coating, CVD, or another deposition method. According to some embodiments, for example when using PECVD, plasma is used to perform ILD deposition. ILD 60 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process (e.g., CMP or mechanical polishing) can be performed to make the top surfaces of ILD 60, dummy gate stack 38, and gate spacer 46 flush with each other.

[0028] In formation Figure 7A and Figure 7BFollowing the structure shown, the dummy gate stack 38 is replaced with replacement gate stacks, which include replacement gate electrodes and replacement gate dielectrics, such as... Figure 8 and Figure 9 As shown. Figure 8 and Figure 9 And subsequently Figures 10 to 19 The cross-sectional view shown is from Figure 7A Obtained from the same vertical plane in the reference section BB. Figure 7B as well as Figure 8-19 The diagram shows the horizontal plane of the top surface 24T and the bottom surface 24B of the STI region 24. Since the STI region is not in the plane shown, it is not explicitly shown. The semiconductor fin 36 lies above the horizontal plane of the top surface 24T.

[0029] When replacing the gate stack, the gate is first removed in one or more etching steps, such as... Figure 7A and Figure 7B The hard mask layer 44, dummy gate electrode 42, and dummy gate dielectric 40 shown herein result in the following: Figure 8 The groove / opening 62 is shown. The corresponding process is... Figure 22 The process flow 200 is shown as process 216. The top surface and sidewalls (not shown in the plane) of the protruding semiconductor fin 36 are exposed to the trench 62.

[0030] Next, the replacement gate stack 76 is formed. The corresponding process is as follows: Figure 22 The process flow shown in 200 is designated as process 218. (Reference) Figure 9 Forming (replacing) the gate dielectric 68, which extends into the trench 62. Figure 8 According to some embodiments of this disclosure, the gate dielectric 68 includes an interface layer (IL) 64 as its lower portion. The IL 64 is formed on the exposed surface of the protruding fin 36. Each IL 64 may include an oxide layer, such as a silicon oxide layer, formed by a thermal oxidation, chemical oxidation, or deposition process of the corresponding protruding fin 36. The gate dielectric 68 may also include a high-k dielectric layer 66 formed on the corresponding IL 64. The high-k dielectric layer 66 may be formed of or include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0. The high-k dielectric layer 66 covers and is in contact with the IL 64. The high-k dielectric layer 66 is formed as a conformal layer and, during deposition, extends on the sidewalls of the protruding fin 36 and the top surface and sidewalls of the gate spacer 46. According to some embodiments of this disclosure, the high-k dielectric layer 66 is formed using ALD or CVD.

[0031] Further reference Figure 9 A stacked layer 70 is deposited. Sublayers within the stacked layer 70 are not shown individually, but they can be distinguished from one another. This deposition can be performed using a conformal deposition process such as ALD, CVD, etc., such that the thickness of the vertical portions of the stacked layer 70 (and each sublayer) is substantially equal to the thickness of the horizontal portions. During deposition, the stacked layer 70 extends into trench 62 ( Figure 8 (in, and includes some parts above ILD 60).

[0032] Stacked layer 70 may include a diffusion barrier layer and one (or more) work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layers determine the work function of the gate and include at least one layer, or multiple layers formed of different materials. The material of the work function layer is selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer, a TiN layer above the TaN layer, and a TiAl layer above the TiN layer. After depositing one or more work function layers, a conductive capping layer is formed, which may be another TiN layer.

[0033] Next, a metallic filler material 72, which can be formed of, for example, tungsten or cobalt, is deposited. The filler material 72 completely fills the remaining trench 62. Figure 8 The deposited gate dielectric 68, stacked layer 70, and filler material 72 include portions located within trench 62 and other portions located above ILD 60. In subsequent processes, planarization steps such as CMP or mechanical polishing are performed to remove the portions of the deposited layers above ILD 60. As a result, a metal gate electrode 74 is formed, which includes the remaining portions of stacked layer 70 and filler material 72. The replacement gate dielectric 68 and replacement gate electrode 74 are collectively referred to below as replacement gate stack 76. Figure 9 As shown, the top surfaces of the replacement gate stack 76, gate spacer 46, CESL 58, and ILD 60 can now be substantially coplanar. Therefore, the individual layers in the replacement gate stack 76 are exposed, including the high-k dielectric layer 66, the stacked layer 70 (including the work function layer and the metal cap layer), and the filler material 72.

[0034] Figure 10 The formation of the cap layer 78 is shown. The corresponding process is as follows: Figure 22The process flow 200 shown is referred to as process 220. According to some embodiments, the capping layer 78 is formed of an oxygen-free material and may be formed of or include silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), etc. The deposition of the capping layer 78 can be performed using CVD, ALD, PECVD, plasma-enhanced CVD (PECVD), PVD, etc.

[0035] ILD 80 is formed on top of the cap layer 78. The corresponding process is as follows: Figure 22 The process flow 200 shown is designated as process 222. ILD 80 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, PECVD, or another deposition method. ILD 80 may be formed of or include an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using TEOS as a precursor, PSG, BSG, BPSG, etc. ILD 80 may include Si, O, C, N, etc., and may include other elements.

[0036] It should be understood that the process performed after depositing the capping layer 78 may include multiple thermal treatments. If the capping layer 78 is not formed and the ILD 80 contacts the top surface of the gate electrode 74, the thermal treatment may cause oxygen in the ILD 80 to diffuse into the top of the metal gate electrode 74, resulting in oxidation of the top of the metal gate electrode 74. Furthermore, plasma may be used to perform the deposition of the ILD 80, which accelerates the diffusion and oxidation processes. Oxidation of the metal gate electrode 74 may cause an undesirable shift in the threshold voltage of the resulting FinFET. In embodiments of this disclosure, the capping layer 78 has the function of preventing oxygen in the ILD 80 from penetrating through the top of the metal gate electrode 74 and oxidizing the top of the metal gate electrode 74. The oxygen barrier capability of the capping layer 78 is related to the material and thickness of the capping layer 78. For example, silicon nitride-containing materials have good oxygen barrier capabilities and can be used to form the capping layer 78. The capping layer 78 should not be too thin or too thick. When the capping layer 78 is too thin (e.g., thinner than about 3 nm), it does not have sufficient oxygen barrier capacity. When the capping layer 78 is too thick (e.g., thicker than about 5 nm), its oxygen barrier capacity saturates, and negative effects begin to dominate. For example, negative effects include... Figure 11 and Figure 15 The etching process shown makes it difficult to etch through the capping layer 78. Furthermore, due to the high dielectric constant of the capping layer 78, a thick capping layer 78 may result in higher parasitic capacitance between adjacent conductive features. According to some embodiments, the thickness T1 of the capping layer 78 is in the range of about 3 nm to about 5 nm. The thickness T2 of the ILD 80 can be greater than about 30 nm, or in the range of about 30 nm to about 500 nm. The ratio T2 / T1 can be greater than 10, and can be greater than 20.

[0037] Figures 11 to 16 The formation of the source / drain contact plug and the gate contact plug is illustrated. In the example shown, the source / drain contact plug and the gate contact plug are shown in the same plane. In other embodiments, the source / drain contact plug and the gate contact plug are formed in different planes, spaced far apart from each other, to prevent electrical short circuits between adjacent source / drain contact plugs and gate contact plugs.

[0038] Figures 11 to 13 The formation of the source / drain contact plug is shown. (Reference) Figure 11 An etching mask 82 (which may be a photoresist or may include a photoresist) is applied / deposited and patterned. Next, an etching process 84 is performed to form source / drain contact openings 86. The corresponding process is described in... Figure 22 The process flow 200 shown is designated as process 224. Etching process 84 is anisotropic and can be a dry etching process performed, for example, using reactive ion etching (RIE). The etching gas is selected based on the materials of ILD80, capping layer 78, ILD 60, and CESL 58.

[0039] According to some embodiments, etching passes through ILD 80, capping layer 78, and ILD 60, and the etching process stops at CESL 58. During the etching process, etching may not (or may) stop at capping layer 78 and may not stop at ILD 60. In other words, etching process 84 can proceed continuously without stopping until CESL 58 is reached. For example, the etching gas may include a mixture of a first etching gas for etching ILD 80 and 60 and a second etching gas for etching capping layer 78. According to some embodiments, the first etching gas is capable of etching ILD 80 and 60 but not capping layer 78, while the second etching gas is capable of etching capping layer 78 but not ILD 80 and 60. The first etching gas may be selected from a mixture of NF3 and NH3, a mixture of HF and NH3, or combinations thereof. The second etching gas may be a fluorine-containing gas, such as a mixture of CF4, O2, and N2, a mixture of NF3 and O2, SF6, a mixture of SF6 and O2, etc. Alternatively, the bias power in the etching process can be increased to ensure that etching does not stop on cap layer 78 and ILD 60, and a process gas such as Ar can be added to prevent etching from stopping on cap layer 78. For example, ILD 80 and 60 can be etched in a chemical reaction, while cap layer 78 is partially removed during the etching process by a bombardment effect. The etching gas and the material of CESL 58 are selected so that etching can stop on CESL 58. Another etching process is then performed to etch through CESL 58. Etching of CESL 58 can be performed using a dry etching process or a wet etching process, and can be anisotropic or isotropic. The etching gas used to etch CESL 58 is different from the etching gas used to etch ILD 80, cap layer 78, and ILD 60.

[0040] According to an alternative embodiment, the formation of opening 86 includes multiple etching processes, including a first etching process for etching ILD 80, a second etching process for etching capping layer 78, a third etching process for etching ILD 60, and a fourth etching process for etching CESL 58. The first, second, and third etching processes can be anisotropic (and dry) etching processes, while the fourth etching process can be a wet or dry process. After forming opening 86, etching mask 82 is removed. According to these embodiments, the etching gas for each of capping layer 78, ILD 60, and CESL 58 can be different from the etching gas used to etch the layer directly overlying it.

[0041] refer to Figure 12 According to some embodiments, a dielectric contact spacer 88 is formed. The corresponding process is as follows: Figure 22The process flow 200 shown is designated as process 226. The formation process includes, for example, depositing a blanket dielectric layer using a conformal deposition method (e.g., CVD or ALD). The dielectric layer can be a high-k dielectric layer with a k value greater than 3.9, thus providing good insulation. Candidate materials include Al. x O y Materials such as HfO2, SiN, and SiOCN are used. The thickness of the dielectric layer can range from about 2 nm to about 4 nm. Depending on the specific requirements of the circuit, the dielectric layer may also include silicon oxide or a low-k dielectric layer to reduce parasitic capacitance. Anisotropic etching is then performed to remove the horizontal portions of the dielectric layer, and the remaining vertical portions in the opening 86 form contact spacers 88, each of which forms a ring when viewed from the top of the wafer 10. According to an alternative embodiment, the formation of the dielectric contact spacers 88 is skipped.

[0042] Figure 13 The formation of the source / drain contact plug 96 is shown. The corresponding process is described in... Figure 22 The process flow 200 is shown as process 228. In the corresponding formation process, for example, PVD is used to deposit a metal layer 90 (e.g., a titanium or cobalt layer), which is formed as a blanket layer including extensions to opening 86 ( Figure 12 The portion of the contact source / drain region 52 and some portions above the ILD 80 are then formed on the metal layer 90. The barrier layer 92 can be a metal nitride layer such as titanium nitride or tantalum nitride. The barrier layer 92 can be formed by nitriding the top layer of the metal layer 90 while leaving the bottom layer unnitrided, or it can be formed using a deposition method such as CVD. Layers 90 and 92 are conformal and extend into the opening 86.

[0043] An annealing process is then performed to form the source / drain silicide region 97. This annealing process can be performed by rapid thermal annealing (RTA), furnace annealing, or the like. Therefore, the bottom of the metal layer 90 reacts with the source / drain region 52 to form the silicide region 97. The sidewall portions of the metal layer 90 are retained after the silicide process. According to some embodiments of this disclosure, the top surface of the silicide region 97 is in contact with the bottom surface of the barrier layer 92.

[0044] Next, as Figure 13As shown, metal material 94 is deposited on and in contact with barrier layer 92. Metal material 94 may include tungsten, cobalt, etc. A planarization process, such as CMP or mechanical polishing, is then performed to remove the portions of layers 90, 92, and 94 located above ILD 80. The remaining portions of layers 90, 92, and 94 are called source / drain contact plugs 96. This forms FinFET 95.

[0045] Figure 14 The formation of the etch stop layer (ESL) 98 and the dielectric layer (ILD) 100 is shown. The corresponding process is described in... Figure 22 The process flow 200 shown is designated as process 230. The etch stop layer 98 can be oxygen-containing or oxygen-free, and can be formed from aluminum nitride, aluminum oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, etc., or multiple layers thereof, and can be formed using deposition methods such as CVD, ALD, etc. The ILD 100 can include materials selected from PSG, BSG, BPSG, fluorine-doped silicon glass (FSG), silicon oxide, etc. The dielectric layer 100 can be formed using spin coating, FCVD, etc., or by deposition processes such as PECVD or LPCVD.

[0046] refer to Figure 15 The ILD 100 and etch stop layer 98 are etched to form openings 102, 104, and 106. The corresponding process is described in... Figure 22 The process flow 200 is shown as process 232. An etch mask 101, which may include a photoresist, is formed and patterned. The etching process is shown as etching process 108. It should be understood that although openings 102, 104, and 106 are shown as tapered, they may also have vertical edges. Etching process 84 may be anisotropic and may be a dry etching process performed, for example, using a RIE. The etching gas is selected based on the materials of ILD 100, etch stop layer 98, ILD 80, and CESL 78. According to some embodiments, opening 106 includes portions 106A and 106B, wherein portion 106A extends to the corresponding underlying gate electrode 74, and portion 106B extends to the corresponding underlying source / drain contact plug 96.

[0047] According to some embodiments, in order to form opening 104 and opening portion 106B, the dielectric layer (including ILD 100, etch stop layer 98, ILD 80, and cap layer 78) is etched through without stopping during the etching process, and the etching process stops at the gate electrode 74. For example, the etching gas may include a mixture of a first etching gas for etching ILD 100 and 80 and a second etching gas for etching etch stop layer 78. According to some embodiments, the first etching gas is capable of etching ILD 100 and 80 but not ILD 98 and cap layer 78, while the second etching gas is capable of etching ILD 98 and cap layer 78 but not ILD 100 and 80. The first etching gas may be selected from a mixture of NF3 and NH3, a mixture of HF and NH3, or combinations thereof. The second etching gas may be a fluorine-containing gas, such as a mixture of CF4, O2, and N2, a mixture of NF3 and O2, SF6, a mixture of SF6 and O2, etc.

[0048] According to alternative embodiments, in order to form opening 104 and opening portion 106A, the dielectric layer (including ILD 100, etch stop layer 98, and ILD 80) is etched through without stopping during the etching process, and the etching process stops at cap layer 78. According to these embodiments, cap layer 78 is formed of a material different from that of ILD 100, etch stop layer 98, and ILD 80. For example, the etching gas may include a first etching gas for etching ILD 100 and 80 and a second etching gas for etching etch stop layer 98, neither of which can etch cap layer 78. The first etching gas may be selected from a mixture of NF3 and NH3, a mixture of HF and NH3, or combinations thereof. The second etching gas may be a fluorine-containing gas, such as a mixture of CF4, O2, and N2, a mixture of NF3 and O2, SF6, or a mixture of SF6 and O2, etc. After etching stops on cap layer 78, another etching process is performed using an etching gas different from the etching gas used to etch ILD 100, etch stop layer 98, and ILD 58 to etch through cap layer 78. Etching of cap layer 78 can be performed using a dry etching process or a wet etching process, and can be anisotropic or isotropic.

[0049] According to an alternative embodiment, the formation of openings 102, 104, and 106B includes multiple etching processes, including a first etching process for etching ILD100, a second etching process for etching the etch stop layer 98, a third etching process for etching ILD80, and a fourth etching process for etching the cap layer 78. The first, second, and third etching processes can be anisotropic (and dry) etching processes, while the fourth etching process can be a wet or dry process. After forming openings 102, 104, and 106, the etch mask 101 is removed.

[0050] The formation of opening 102 and opening portion 106B can be performed using the same etching mask (e.g., Figure 15 (As shown), or alternatively, the same etching mask as for opening 104 and opening portion 106A is used to form opening 102, and a separate etching mask is used to form opening portion 106B. During etching of opening 102 (and possibly opening portion 106B), an etch stop layer 98 may be used for etch stopping, and this etching includes etching of ILD 100 and stopping on etch stop layer 98, and then etching through etch stop layer 98 in another etching process using etching chemicals (gas or chemical solution) different from the etching gas used to etch ILD 100.

[0051] In subsequent processes, openings 102, 104, and 106 are filled with one or more conductive materials to form contact plugs 108, 110, and 112, as shown below. Figure 16 As shown. The corresponding process is in Figure 22 The process flow 200 shown is illustrated as process 234. The formation process includes depositing a desired conductive material / layer and then performing a planarization process to remove excess material. According to some embodiments, contact plugs 108, 110, and 112 are formed of a homogeneous conductive material, and the entire conductive material has the same composition and may be formed of titanium nitride, tungsten, cobalt, etc. According to alternative embodiments, each of contact plugs 108, 110, and 112 has a composite structure, including, for example, a barrier layer and a metallic material situated above the barrier layer. The barrier layer may be formed of titanium nitride, titanium, tantalum nitride, tantalum, etc., and the metallic material may be formed of tungsten, cobalt, copper, etc. Contact plug 112 electrically and physically interconnects the gate electrode 74 and the source / drain contact plug 96.

[0052] Figure 17The formation of an etch stop layer 114, a dielectric layer 116 (also referred to as an intermetallic dielectric (IMD)), and a metal line 118 is illustrated. The etch stop layer 114 may be formed of SiON, alumina, aluminum nitride, or a composite thereof. According to some embodiments of this disclosure, the dielectric layer 116 may be formed of a low-k dielectric material with a dielectric constant (k value) below about 3.0. The dielectric layer 116 may be formed of or include the following: Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of this disclosure, the formation of the dielectric layer 116 includes depositing a dielectric material containing a pore-forming agent and then performing a curing process to remove the pore-forming agent, and thus the remaining dielectric layer 116 is porous.

[0053] Metal lines 118 are formed in dielectric layer 116. This formation process may include an inlay process, such as... Figure 17 The single damascene process is shown. This formation process may include: etching the dielectric layer 116 and the etch stop layer 114 to form trenches; filling the trenches with conductive material; and performing a CMP process to remove excess conductive material. Each metal line 118 may include a diffusion barrier layer and a metallic material above the diffusion barrier layer. The diffusion barrier layer may be formed of or include titanium nitride, tantalum nitride, titanium, tantalum, etc. The metallic material may include copper or a copper alloy.

[0054] Figure 18 The formation of etch stop layer 120, dielectric layer 122, and via 124 is shown. Etch stop layer 120 can be formed of a material similar to that of etch stop layer 114. Dielectric layer 122 can be formed of a material similar to that of dielectric layer 116. Via 124 can be formed using a similar process to that used to form metal line 118, and via 124 can be formed using a single damascene process. The structure and material of via 124 can be similar to those of metal line 118, except that metal line 118 is longer than via 124.

[0055] Figure 19 The formation of etch stop layer 126, dielectric layer 128, via 130, and metal line 132 is illustrated. Etch stop layer 126 may be formed of a material similar to that of etch stop layer 114 and / or etch stop layer 120. Dielectric layer 128 may be formed of a material similar to that of dielectric layer 116 and / or dielectric layer 122. Via 130 and metal line 132 can be formed using a dual damascene process, which includes: forming via openings and trenches, filling the via openings and trenches with a diffusion barrier layer and a copper-containing material, and then performing a CMP process.

[0056] Figure 20A A portion of the structure, including gate stack 76 and STI region 24, is shown. Figure 19 The gate stack shown is elongated and extends onto STI region 24, where Figure 20A The cross-sectional view shown illustrates the corresponding portion. Figure 20B The schematic percentage of oxygen atoms is shown based on the depth from the top surface of ILD 80 to the gate electrode 74 (as indicated by arrow 81). The extent of ILD 80, cap layer 78, and gate electrode 74 is schematically shown. It should be understood that cap layer 78 may be oxygen-free during deposition. However, after subsequent processes (which may include heat treatment and / or plasma processes), oxygen diffuses downwards into cap layer 78 and gate electrode 74. Therefore, as... Figure 20B As shown, along arrow 81 ( Figure 20A The oxygen atom percentage decreases in the direction of ( ). It should be understood that, according to some embodiments, it can also be along the direction of ( ). Figure 19 Arrow 81' as shown is used to obtain... Figure 20B The oxygen distribution curve shown.

[0057] Figure 21 X-ray photoelectron spectroscopy (XPS) spectra of several samples with different structures are shown. Line 140 is the spectrum of deposited (without heat treatment) tungsten used in the gate electrode. Line 142 is the spectrum of the surface portion of the deposited tungsten after treatment with N2O, which simulates the result of oxygen diffusion from the ILD to the underlying metal gate electrode under the influence of plasma deposition in the ILD. Two peaks 144 are found, which are peaks of tungsten oxide. Line 146 is the XPS spectrum of the top of the gate electrode of the corresponding sample with a SiN capping layer, where N2O treatment was performed after the SiN capping layer was deposited. It can be observed that the tungsten oxide peaks are no longer present in line 146, indicating that the SiN capping layer is effective in preventing oxidation of the metal gate electrode.

[0058] Multiple samples were also formed to determine the effect of the dielectric capping layer 78 on the threshold voltage of the corresponding transistors. The samples included n-type FinFETs and p-type FinFETs. The samples also included reference n-type FinFETs and p-type FinFETs where no capping layer was formed, and the ILD 80 was in direct contact with the corresponding underlying metal gate electrode 74, thus forming a metal oxide, such as... Figure 21As shown. The threshold voltages of the reference n-type FinFET and p-type FinFET will be referred to as the reference n-type threshold voltage and reference p-type threshold voltage, respectively. Experimental results show that when 2nm and 3nm SiN capping layers are formed, the threshold voltages of the obtained sample n-type FinFETs are reduced by 67mV and 18mV, respectively, compared to the reference n-type threshold voltage. This indicates that the capping layer can significantly improve the threshold voltage of the n-type FinFET. Experimental results also show that when 2nm and 3nm capping layers are formed, the threshold voltages of the obtained p-type FinFETs are increased by 11mV and 5mV, respectively, compared to the reference p-type threshold voltage. This indicates that the capping layer can also significantly improve the threshold voltage of the p-type FinFET. The results also show that both 2nm and 3nm capping layers can improve the corresponding FinFETs, with the 3nm capping layer showing significantly better results than the 2nm capping layer. The results discussed above are obtained from short-channel FinFETs. A sample long-channel FinFET was also formed, and the results were similar to those obtained from the short-channel FinFET.

[0059] The embodiments of this disclosure have several advantageous features. Oxidation of the metal gate electrode is reduced by forming a capping layer that prevents oxygen diffusion to the metal gate electrode. This eliminates or at least reduces undesirable threshold voltage shift caused by oxidation of the metal gate electrode.

[0060] According to some embodiments of this disclosure, a method includes: forming a dummy gate stack on a semiconductor fin; forming gate spacers on the sidewalls of the dummy gate stack; forming a first interlayer dielectric, wherein the gate spacers and the dummy gate stack are located in the first interlayer dielectric; removing the dummy gate stack to form a trench between the gate spacers; forming a replacement gate stack in the trench; depositing a dielectric capping layer, wherein the bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric; depositing a second interlayer dielectric over the dielectric capping layer; and forming a source / drain contact plug extending into the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric. In one embodiment, forming the source / drain contact plug includes: performing a first etching process to etch the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric to form a contact opening, wherein the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric are etched using the same process gas. In one embodiment, the same process gas includes a first etch gas for etching the second interlayer dielectric and the first interlayer dielectric, and a second etch gas for etching the dielectric capping layer. In one embodiment, the method further includes: depositing a contact etch stop layer prior to forming the first interlayer dielectric, wherein the contact etch stop layer contacts a source / drain region located on the side of the replacement gate stack, and wherein the first etch process stops on the contact etch stop layer. In one embodiment, the first etch process does not stop on the dielectric capping layer and the first interlayer dielectric. In one embodiment, the method further includes: etching the second interlayer dielectric and the dielectric capping layer to form a gate contact opening, wherein the second interlayer dielectric and the dielectric capping layer are etched using the same process gas in a continuous etch process; and forming a gate contact plug filling the gate contact opening. In one embodiment, forming the dielectric capping layer includes depositing an oxygen-free dielectric layer, and depositing the second interlayer dielectric includes depositing an oxygen-containing dielectric layer. In one embodiment, forming the dielectric capping layer includes depositing silicon nitride. In one embodiment, forming the dielectric capping layer includes depositing silicon carbide. In one embodiment, the thickness of the dielectric cap layer is in the range of about 3 nm to about 5 nm.

[0061] In one embodiment, the deposition of the dielectric capping layer is performed using atomic layer deposition. In one embodiment, forming a replacement gate stack includes: depositing a gate dielectric layer and a stacked conductive layer into a trench; and performing a planarization process to remove excess portions of the gate dielectric layer and the stacked conductive layer, wherein the dielectric capping layer is deposited on the planarized top surface of the stacked conductive layer.

[0062] According to some embodiments of this disclosure, a method includes: forming a metal gate in a first ILD; performing a planarization process to make a first top surface of the metal gate flush with a second top surface of the first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is located over and in contact with both the first and second top surfaces; depositing a second ILD over the dielectric cap layer; and in an etching process, etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the contact opening extends through both the second ILD and the dielectric cap layer. In one embodiment, the second ILD and the dielectric cap layer are etched using the same etching gas. In one embodiment, the same etching gas includes a first etching gas for etching the second ILD and a second etching gas for etching the dielectric cap layer. In one embodiment, the etching process is performed continuously without stopping at the dielectric cap layer. In one embodiment, the etching process is performed until the metal gate is exposed. In one embodiment, the contact opening further extends through the first ILD, and the etching process stops on a contact etch stop layer below the first ILD, and the method further includes: in an additional etching process, etching through the contact etch stop layer to expose the source / drain regions located on the side of the metal gate.

[0063] According to some embodiments of this disclosure, a method includes: forming a metal gate in a first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is planar and is situated over and in contact with both the metal gate and the first ILD; depositing a second ILD over and in contact with the dielectric cap layer, wherein both the first ILD and the second ILD are thicker than the dielectric cap layer; etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the etching is performed continuously until a top surface of an underlying feature is exposed; and forming a contact plug extending into the contact opening. In one embodiment, the underlying feature includes a metal gate, and the etching stops on the metal gate.

[0064] According to some embodiments of this disclosure, a device includes: a semiconductor region; a gate stack over the semiconductor region, wherein the gate stack includes a gate electrode; a gate spacer located on a sidewall of the gate stack; a first interlayer dielectric, wherein the gate stack and the gate spacer are located in the first interlayer dielectric; a dielectric cap layer including a bottom surface contacting a top surface of the gate electrode, the gate spacer, and the first interlayer dielectric; and a second interlayer dielectric located over the dielectric cap layer. In one embodiment, the device further includes: a source / drain contact plug extending continuously into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric. In one embodiment, in the region directly above the gate stack, the percentage of oxygen atoms in the dielectric cap layer continuously decreases from the top surface to the bottom surface of the dielectric cap layer. In one embodiment, the second interlayer dielectric has a first oxygen atom percentage equal to the second oxygen atom percentage at the top of the dielectric cap layer.

[0065] According to some embodiments of this disclosure, a device includes: a semiconductor region; a gate stack located above the semiconductor region; a first gate spacer and a second gate spacer contacting opposite sidewalls of the gate stack; a first interlayer dielectric located opposite to the gate stack; a dielectric cap layer contacting the gate stack, wherein the dielectric cap layer further extends into the region directly above the first interlayer dielectric; and a second interlayer dielectric located above and in solid contact with the dielectric cap layer, wherein the dielectric cap layer has a lower percentage of oxygen atoms than the second interlayer dielectric layer. In one embodiment, the dielectric cap layer comprises silicon nitride, and the percentage of oxygen atoms in the dielectric cap layer continuously decreases from the top surface to the bottom surface of the dielectric cap layer. In one embodiment, the device further includes a source / drain contact plug that continuously extends into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric. In one embodiment, the dielectric cap layer comprises silicon carbide, and the percentage of oxygen atoms in the dielectric cap layer decreases continuously from the top surface to the bottom surface of the dielectric cap layer.

[0066] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0067] Example 1. A method of manufacturing a semiconductor device, comprising: forming a dummy gate stack on a semiconductor fin; forming gate spacers on sidewalls of the dummy gate stack; forming a first interlayer dielectric, wherein the gate spacers and the dummy gate stack are located in the first interlayer dielectric; removing the dummy gate stack to form a trench between the gate spacers; forming a replacement gate stack in the trench; depositing a dielectric capping layer, wherein a bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric; depositing a second interlayer dielectric over the dielectric capping layer; and forming source / drain contact plugs extending into the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric.

[0068] Example 2. According to the method of Example 1, wherein forming the source / drain contact plug includes: performing a first etching process to etch the second interlayer dielectric, the dielectric cap layer and the first interlayer dielectric to form a contact opening, wherein the second interlayer dielectric, the dielectric cap layer and the first interlayer dielectric are etched using the same process gas.

[0069] Example 3. The method according to Example 2, wherein the same process gas includes a first etching gas for etching the second interlayer dielectric and the first interlayer dielectric, and a second etching gas for etching the dielectric cap layer.

[0070] Example 4. The method according to Example 2 further includes: depositing a contact etch stop layer prior to forming the first interlayer dielectric, wherein the contact etch stop layer contacts a source / drain region located on the side of the alternative gate stack, and wherein the first etch process is stopped on the contact etch stop layer.

[0071] Example 5. The method according to Example 4, wherein the first etching process is not stopped on the dielectric cap layer and the first interlayer dielectric.

[0072] Example 6. The method according to Example 1 further includes: etching the second interlayer dielectric and the dielectric capping layer to form a gate contact opening, wherein the second interlayer dielectric and the dielectric capping layer are etched using the same process gas in a continuous etching process; and forming a gate contact plug that fills the gate contact opening.

[0073] Example 7. The method according to Example 1, wherein forming the dielectric cap layer includes depositing a non-oxygen-containing dielectric layer, and depositing the second interlayer dielectric includes depositing an oxygen-containing dielectric layer.

[0074] Example 8. The method according to Example 7, wherein forming the dielectric cap layer comprises depositing silicon nitride.

[0075] Example 9. The method according to Example 1, wherein forming the dielectric cap layer comprises depositing silicon carbide.

[0076] Example 10. The method according to Example 1, wherein the thickness of the dielectric cap layer is in the range of 3 nm to 5 nm.

[0077] Example 11. The method according to Example 1, wherein the deposition of the dielectric capping layer is performed using a process selected from atomic layer deposition, chemical vapor deposition and physical vapor deposition.

[0078] Example 12. The method according to Example 1, wherein forming the replacement gate stack comprises: depositing a gate dielectric layer and a stacked conductive layer into the trench; and performing a planarization process to remove excess portions of the gate dielectric layer and the stacked conductive layer, wherein the dielectric capping layer is deposited on the planarized top surface of the stacked conductive layer.

[0079] Example 13. A method of manufacturing a semiconductor device, comprising: forming a metal gate in a first interlayer dielectric (ILD); performing a planarization process to make a first top surface of the metal gate flush with a second top surface of the first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is located over and in contact with both the first top surface and the second top surface; depositing a second ILD over the dielectric cap layer; and in an etching process, etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the contact opening passes through both the second ILD and the dielectric cap layer.

[0080] Example 14. The method according to Example 13, wherein the second ILD and the dielectric cap layer are etched using the same etching gas.

[0081] Example 15. The method according to Example 14, wherein the same etching gas includes a first etching gas for etching the second ILD and a second etching gas for etching the dielectric cap layer.

[0082] Example 16. The method according to Example 13, wherein the etching process is performed continuously without stopping on the dielectric cap layer.

[0083] Example 17. The method according to Example 13, wherein the etching process is performed until the metal gate is exposed.

[0084] Example 18. The method according to Example 13, wherein the contact opening further extends through the first ILD, and the etching process stops on a contact etch stop layer below the first ILD, and the method further includes: in an additional etching process, etching through the contact etch stop layer to expose the source / drain regions located on the side of the metal gate.

[0085] Example 19. A method of manufacturing a semiconductor device, comprising: forming a metal gate in a first interlayer dielectric (ILD); depositing a dielectric cap layer, wherein the dielectric cap layer is planar and is situated over and in contact with both the metal gate and the first ILD; depositing a second ILD over and in contact with the dielectric cap layer, wherein both the first ILD and the second ILD are thicker than the dielectric cap layer; etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the etching is performed continuously until a top surface of an underlying feature is exposed; and forming a contact plug extending into the contact opening.

[0086] Example 20. The method according to Example 19, wherein the following features include the metal gate, and the etching stops on the metal gate.

Claims

1. A method for manufacturing a semiconductor device, comprising: A dummy gate stack is formed on the semiconductor fin; Gate spacers are formed on the sidewalls of the dummy gate stack; A first interlayer dielectric is formed, wherein the gate spacer and the dummy gate stack are located in the first interlayer dielectric; Remove the dummy gate stack to form a trench between the gate spacers; A replacement gate stack is formed in the trench; A dielectric cap layer is deposited, wherein the bottom surface of the dielectric cap layer contacts the first top surface of the replacement gate stack and the second top surface of the first interlayer dielectric; A second interlayer dielectric is deposited on the dielectric cap layer; and Forming source / drain contact plugs that extend into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric; The formation of the source / drain contact plug includes: A first etching process is performed using an etching gas to etch the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric to form a contact opening. The etching gas includes a first etching gas and a second etching gas. The second interlayer dielectric and the first interlayer dielectric are etched by the first etching gas faster than the dielectric capping layer, and the dielectric capping layer is etched by the second etching gas faster than the second interlayer dielectric and the first interlayer dielectric.

2. The method according to claim 1, further comprising: Prior to forming the first interlayer dielectric, a contact etch stop layer is deposited, wherein the contact etch stop layer contacts the source / drain regions located on the side of the replacement gate stack, and wherein the first etch process is stopped on the contact etch stop layer.

3. The method according to claim 2, wherein, The first etching process did not stop on the dielectric cap layer and the first interlayer dielectric.

4. The method according to claim 1, further comprising: The second interlayer dielectric and the dielectric capping layer are etched to form a gate contact opening, wherein the second interlayer dielectric and the dielectric capping layer are etched using process gases in a continuous etching process; and A gate contact plug is formed to fill the gate contact opening.

5. The method according to claim 1, wherein, Forming the dielectric cap layer includes depositing a non-oxygen-containing dielectric layer, and depositing the second interlayer dielectric includes depositing an oxygen-containing dielectric layer.

6. The method according to claim 5, wherein, Forming the dielectric cap layer includes depositing silicon nitride.

7. The method according to claim 1, wherein, Forming the dielectric cap layer includes depositing silicon carbide.

8. The method according to claim 1, wherein, The thickness of the dielectric cap layer is in the range of 3 nm to 5 nm.

9. The method according to claim 1, wherein, The deposition of the dielectric capping layer is performed using a process selected from atomic layer deposition, chemical vapor deposition, and physical vapor deposition.

10. The method according to claim 1, wherein, Forming the replacement gate stack includes: A gate dielectric layer and a stacked conductive layer are deposited into the trench; and A planarization process is performed to remove excess portions of the gate dielectric layer and the stacked conductive layers, wherein the dielectric cap layer is deposited on the planarized top surface of the stacked conductive layers.

11. A method for manufacturing a semiconductor device, comprising: A metal gate is formed in the first interlayer dielectric (ILD); A planarization process is performed to make the first top surface of the metal gate flush with the second top surface of the first ILD; A dielectric cap layer is deposited, wherein the dielectric cap layer is located on and in contact with both the first top surface and the second top surface; A second ILD is deposited on the dielectric cap layer; and In an etching process using etching gas, both the second ILD and the dielectric cap layer are etched to form a contact opening, wherein the contact opening passes through both the second ILD and the dielectric cap layer. The etching gas includes a first etching gas and a second etching gas. The second ILD is etched by the first etching gas faster than the dielectric cap layer, and the dielectric cap layer is etched by the second etching gas faster than the second ILD.

12. The method according to claim 11, wherein, The etching process is performed continuously without stopping on the dielectric cap layer.

13. The method according to claim 11, wherein, The etching process is performed until the metal gate is exposed.

14. The method according to claim 11, wherein, The contact opening further extends through the first ILD, and the etching process stops on a contact etch stop layer below the first ILD. The method further includes: in an additional etching process, etching through the contact etch stop layer to expose the source / drain regions located on the side of the metal gate.

15. A method for manufacturing a semiconductor device, comprising: A metal gate is formed in the first interlayer dielectric (ILD); A dielectric cap layer is deposited, wherein the dielectric cap layer is planar and is located above and in contact with both the metal gate and the first ILD; A second ILD is deposited on and in contact with the dielectric cap layer, wherein both the first ILD and the second ILD are thicker than the dielectric cap layer; An etching process is performed using etching gases to etch both the second ILD and the dielectric cap layer to form a contact opening, wherein the etching process is performed continuously until the top surface of the underlying feature is exposed, the etching gases comprising a first etching gas and a second etching gas, wherein the second ILD is etched by the first etching gas faster than the dielectric cap layer, and the dielectric cap layer is etched by the second etching gas faster than the second ILD; and A contact plug is formed that extends into the contact opening.

16. The method according to claim 15, wherein, The following features include the metal gate, and the etching process stops on the metal gate.

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