Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor structures and methods of manufacturing the same. Semiconductor structures and methods are provided. According to the present disclosure, a semiconductor structure includes: a first fin structure and a second fin structure over a substrate; a first source / drain feature and a second source / drain feature, the first source / drain feature disposed over the first fin structure and the second source / drain feature disposed over the second fin structure; a dielectric feature disposed over the first source / drain feature; and a contact structure formed over the first source / drain feature and the second source / drain feature. The contact structure is electrically coupled to the second source / drain feature and is separated from the first source / drain feature by the dielectric feature.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor structures and methods of manufacturing them. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In IC development, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs, or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). Multi-gate devices generally refer to devices where the gate structure (or a portion of the gate structure) is disposed over more than one side of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices, and they have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a raised channel surrounded by gates on more than one side (e.g., the gate surrounds the top and sidewalls of a semiconductor material “fin” extending from the substrate). MBC transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because their gate structure surrounds the channel region, MBC transistors can also be called gate-all-around (SGT) transistors or gate-all-around (GAA) transistors.

[0004] In scaling down, efforts are made to reduce the number of metal lines while maintaining the same connectivity. Some example structures include elongated source / drain contacts that span more than one active region. As a trade-off, these elongated source / drain contacts may overlap with adjacent gate structures, leading to an increase in parasitic capacitance between the source / drain contacts and the gate structure. Therefore, while the source / drain contacts of existing multi-gate devices are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a first fin structure and a second fin structure on a substrate; a first source / drain feature and a second source / drain feature, the first source / drain feature being disposed on the first fin structure and the second source / drain feature being disposed on the second fin structure; a dielectric feature disposed on the first source / drain feature; and a contact structure formed on the first source / drain feature and the second source / drain feature, wherein the contact structure is electrically coupled to the second source / drain feature and separated from the first source / drain feature by the dielectric feature.

[0006] According to another aspect of this disclosure, a contact structure is provided, comprising: a first source / drain feature and a second source / drain feature; a dielectric fin disposed between the first source / drain feature and the second source / drain feature; a dielectric feature disposed on the first source / drain feature and extending along the sidewall of the dielectric fin; and a contact feature including a first portion disposed on the dielectric feature and the dielectric fin and a second portion electrically coupled to the second source / drain feature, wherein the first portion hangs over the first source / drain feature.

[0007] According to another aspect of this disclosure, a method of manufacturing a semiconductor structure is provided, comprising: receiving a workpiece including: a first fin structure and a second fin structure on a substrate; a gate structure surrounding the first fin structure and the second fin structure; a first source / drain feature on the first fin structure; and a second source / drain feature on the second fin structure; selectively forming a dielectric feature on the first source / drain feature; and after the selective formation, forming a contact structure on the first source / drain feature and the second source / drain feature such that the contact structure is electrically connected to the second source / drain feature and separated from the first source / drain feature by the dielectric feature. Attached Figure Description

[0008] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to one or more aspects of this disclosure.

[0010] Figure 2 It is based on one or more aspects of this disclosure and will be based on Figure 1 A partial top view of a workpiece manufactured using the method described in the article.

[0011] Figures 3-22 Based on one or more aspects of this disclosure Figure 1 The method described in the text is a partial cross-sectional view of the workpiece at various manufacturing stages.

[0012] Figure 23 This is a schematic perspective view of an example contact structure including a first number of metal wires according to one or more aspects of this disclosure.

[0013] Figure 24 This is a schematic perspective view of a contact structure including a second number of metal wires according to one or more aspects of this disclosure.

[0014] Figure 25 This is a schematic perspective view of the contact structure according to one or more aspects of this disclosure. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0017] Furthermore, when using terms such as “about,” “approximately,” etc., to describe numbers or ranges of numbers, the term is intended to cover numbers within a reasonable range (taking into account the variations inherent during manufacturing, as understood by those skilled in the art). For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number, a number or range of numbers covers a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of “about 5 nm” can cover a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Further, this disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe relationships between the various embodiments and / or configurations discussed.

[0018] In IC design, multiple devices can be combined together as cells or standard cells to perform certain circuit functions. Such cells or standard cells can perform logic operations, such as NAND, AND, OR, NOR, or inverters, or be used as memory cells, such as static random access memory (SRAM) cells. The number of metal lines required for interconnect cells is a factor in determining cell size (e.g., cell height). One way to reduce cell height is to implement local interconnect structures to reposition contact vias, thereby reinforcing the connection between the contact vias and the metal lines. In some prior art, elongated source / drain contacts can be formed, allowing contact vias to couple to more distant metal lines. Contact via repositioning allows the elimination of one or more metal lines and a reduction in cell height. This technique is not without challenges. For example, elongated source / drain contacts may extend along the gate structure, leading to increased parasitic capacitance (e.g., gate-to-drain capacitance) and undesirable ring oscillator (RO) performance.

[0019] This disclosure provides a source / drain contact that spans more than one active region (e.g., a fin element of a FinFET) without increasing parasitic capacitance. The source / drain contact of this disclosure includes a first portion coupled to a first source / drain feature and a second portion overhanging or “flying over” a second source / drain feature adjacent to the first source / drain feature. The second portion is spaced from the second source / drain feature by a dielectric feature. The contour of the second portion and the presence of the dielectric feature reduce area overlap with adjacent gate structures, thereby reducing parasitic capacitance.

[0020] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. Here, Figure 1This is a flowchart illustrating a method 100 for forming a semiconductor structure from a workpiece according to an embodiment of the present disclosure. Method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figure 2 ( Figure 2 A partial top view of workpiece 200 is shown. Figures 3-22 ( Figures 3-22 It is based on Figure 1 The method 100 is described by referring to partial cross-sectional views of workpiece 200 at different manufacturing stages in an embodiment of the method 100. Because workpiece 200 will be manufactured as a semiconductor device, it may be referred to herein as semiconductor device 200, depending on the context. For convenience, Figures 2-22 The X, Y, and Z directions are perpendicular to each other. Throughout this disclosure, unless otherwise expressly stated, the same reference numerals denote the same features.

[0021] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 Method 100 includes block 102, wherein a workpiece 200 is received. Figure 2 A partial top view of workpiece 200 is shown. Figure 3 A partial sectional view of workpiece 200 along line A-A' is shown, and Figure 4 A partial sectional view of workpiece 200 along line B-B' is shown. Figure 2 and Figure 4 As shown, workpiece 200 includes a first active region 204 and a second active region 204' on substrate 202. Substrate 202 may be a semiconductor substrate such as a silicon substrate. Substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 may include various doping configurations according to design requirements known in the art. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, in some embodiments, substrate 202 may include an epitaxial layer, substrate 202 may be strained for performance enhancement, substrate 202 may include a silicon-on-insulator (SOI) structure, and / or substrate 202 may have other suitable enhancement features.

[0022] In the case of an MBC transistor, the first active region 204 and the second active region 204' may comprise a vertically stacked channel member, or in the case of a FinFET, they may comprise a fin structure (i.e., a fin or fin element). In the depicted embodiment, each of the first active region 204 and the second active region 204' is a fin structure, and the semiconductor device 200 may comprise a FinFET. The first active region 204 and the second active region 204' may comprise: silicon (Si) or other elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium phosphide arsenide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or combinations thereof. Figure 2 and Figure 3 As shown, the first active region 204 and the second active region 204' extend longitudinally along the X direction. The first active region 204 and the second active region 204' can be fabricated using suitable processes including photolithography and etching. The photolithography process can include forming a photoresist layer overlying the substrate 202, exposing the photoresist layer to radiation reflected from or transmitted through the photomask, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, an electron beam lithography process can be used to pattern the photoresist layer to form the masking element. The masking element can then be used to protect areas of the substrate 202 while an etching process forms recesses in the substrate 202, thereby forming the first active region 204 and the second active region 204'. Dry etching (e.g., chemical oxide removal), wet etching, and / or other suitable processes can be used to etch the recesses. Many other embodiments of the method for forming active regions (e.g., first active region 204 and second active region 204') on substrate 202 can also be used. The active regions are separated from each other by isolation feature 203. Isolation feature 203 may also be referred to as shallow trench isolation (STI) feature and may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof and / or other suitable materials.

[0023] refer to Figure 3Each of the first active region 204 and the second active region 204' includes a channel region 204C surrounded by a gate structure 208. The first active region 204 includes a source / drain region 204SD, on which a first source / drain feature 220-1 is formed. The second active region 204' includes a source / drain region 204SD, on which a fourth source / drain feature 220-4 is formed. The sidewalls of the gate structure 208 are lined by gate spacers 210. The gate spacers 210 separate the gate structure 208 from the first source / drain feature 220-1 and the fourth source / drain feature 220-4. The gate structure surrounds the channel region 204C of the first active region 204 and the channel region 204C of the second active region 204'. Figure 2 As shown, the gate structure 208 extends longitudinally along the Y direction, which is perpendicular to the X direction. Although Figure 2 Although not explicitly shown, gate structure 208 includes an interface layer, a gate dielectric layer, one or more work function layers, and a metal fill layer. In some embodiments, the interface layer may include a dielectric material such as silicon oxide or hafnium oxide. The gate dielectric layer is formed of a high-k dielectric material (i.e., a dielectric constant greater than about 3.9), which may include hafnium oxide (HfO), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. One or more work function layers may include n-type work function layers and p-type work function layers. Example n-type work function layers may be formed of aluminum, titanium aluminide, titanium aluminum carbide, tantalum silicon carbide, tantalum silicon aluminum carbide, tantalum silicon carbide, tantalum silicide, or hafnium carbide. Example p-type work function layers may be formed of titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbonitride, or molybdenum. The metal filler layer may be formed of metal, such as tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). Because the gate dielectric layer is formed of a high-k dielectric material and metal is used in the gate structure 208, the gate structure 208 may also be referred to as a high-k metal gate structure 208 or a metal gate structure 208.

[0024] like Figure 2As shown, the workpiece 200 may include a plurality of gate structures 208 extending longitudinally along the Y direction. Each gate structure 208 includes a first width W1 along the X direction and is spaced apart from adjacent gate structures by a first spacing S1. The gate structures 208 are disposed with a first pitch P1. In some embodiments, the first width W1 is between about 5 nm and about 80 nm, the first spacing S1 is between about 10 nm and about 200 nm, and the first spacing P1 is between about 15 nm and about 280 nm. Considering the limitations of photolithography process and production cost, the ranges of the first width W1, the first spacing S1, and the first spacing P1 are selected to minimize device size. Figure 2 In some embodiments shown, the first active region 204 and the second active region 204' may have similar or different widths along the Y direction. In the depicted embodiments, the first active region 204 has a third width W3, and the second active region 204' has a fourth width W4 greater than the third width W3. The wider width of the second active region 204' allows the transistors above the second active region 204' to have larger on-state currents, and the smaller width of the first active region 204 allows the transistors above the first active region 204 to have less leakage. In one embodiment, the workpiece 200 is used to fabricate a static random access memory (SRAM) device, the first active region 204 is used to form p-type transistors, and the second active region 204' is used to form n-type transistors. In some cases, the third width W3 is between about 5 nm and about 100 nm, and the fourth width W4 is between about 5 nm and about 100 nm. In the depicted embodiments, the first active region 204 and the second active region 204' may be separated by a second interval S2 and may be set with a second pitch P2. In some embodiments, the second interval S2 may be between about 20 nm and about 200 nm, and the second pitch P2 may be between about 25 nm and about 300 nm. Considering the limitations of photolithography process and production cost, the ranges of the third width W3, the fourth width W4, the second interval S2 and the second pitch P2 are selected to minimize device size. The ranges of the first width W1, the first interval S1, the first pitch P1, the third width W3, the fourth width W4, the second interval S2 and the second pitch P2 may appear wide because the semiconductor device fabricated on the workpiece 200 may be a small and densely packaged logic device, a densely packaged memory device, a relatively large electrostatic discharge (ESD) device, or a relatively large input / output (I / O) device.

[0025] Figure 2 and Figure 3The gate spacer 210 shown can be a single layer or multiple layers. Example materials for the gate spacer 210 include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, silicon carbonitride, and / or combinations thereof. In one example, the gate spacer 210 is formed of silicon nitride. Figure 3 As shown, when viewed along the Y direction, the sidewalls of each gate structure 208 are lined with gate spacers 210, such that each gate structure 208 is sandwiched between two gate spacers 210. Each gate structure 208 and the gate spacers 210 sandwiching it are capped by a self-aligned cap (SAC) layer 214. The SAC layer 214 may be formed of hafnium silicide, silicon oxycarbide, aluminum oxide, zirconium silicide, aluminum oxynitride, zirconium oxide, hafnium oxide, titanium oxide, zirconium alumina, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, tantalum carbonitride, silicon nitride, silicon oxycarbonitride, silicon, zirconium nitride, or silicon carbonitride. In one embodiment, the SAC layer 214 is formed of silicon nitride.

[0026] Figures 2-4 The source / drain features shown (including first source / drain feature 220-1, second source / drain feature 220-2, third source / drain feature 220-3, and fourth source / drain feature 220-4) can be epitaxially grown on the source / drain region 204SD of the active region (e.g., first active region 204 and second active region 204'). Depending on the device type and design requirements, the source / drain features of this disclosure can be n-type or p-type. For example, an n-type source / drain feature may include silicon (Si) doped with an n-type dopant (e.g., phosphorus (P) or arsenic (As)), and a p-type source / drain feature may include silicon germanium (SiGe) doped with a p-type dopant (e.g., boron (B), boron difluoride (BF2), or gallium (Ga)). Figure 3 As shown, the first source / drain feature 220-1, the second source / drain feature 220-2, and the third source / drain feature 220-3 are disposed on the source / drain region 204SD of the first active region 204. The fourth source / drain feature 220-4 is disposed on the source / drain region 204SD of the second active region 204', as shown... Figure 2 and Figure 4 As shown. In Figure 2 and Figure 4In some embodiments illustrated, the first active region 204 and the second active region 204' may have different widths along the Y direction, which may result in different widths for the first source / drain feature 220-1 and the fourth source / drain feature 220-4. In the depicted embodiments, a p-type FinFET can be formed over the narrower first active region 204, and an n-type FinFET can be formed over the wider second active region 204' to increase the drive current of the n-type FinFET. In this embodiment, the fourth source / drain feature 220-4 is wider along the Y direction than the first source / drain feature 220-1.

[0027] refer to Figure 2 and Figure 4 The dielectric fin 230 can be disposed between the first active region 204 and the second active region 204'. The dielectric fin 230 is also disposed between the first source / drain feature 220-1 and the fourth source / drain feature 220-4. One function of the dielectric fin 230 is to prevent the first source / drain feature 220-1 and the fourth source / drain feature 220-4 from merging during their epitaxial growth. Figure 4 In some embodiments shown, the dielectric fin 230 may include a first layer 232 and a second layer 234 above the first layer 232. The first layer 232 and the second layer 234 may have different compositions. In some cases, the first layer 232 may include silicon oxide, silicon oxycarbonitride, or silicon carbonitride, and the second layer 234 may include silicon nitride, aluminum oxide, zirconium oxide, hafnium oxide, metal oxide, or a suitable dielectric material. The dielectric constant of the second layer 234 may be greater than that of the first layer 232. Figure 4 As shown, the top surface of the dielectric fin 230 is higher than the top surfaces along the Z-direction of the first source / drain feature 220-1 and the fourth source / drain feature 220-4. In some embodiments, the dielectric fin 230 may have a fifth width W5 between about 5 nm and about 100 nm. The fifth width W5 of the dielectric fin 230 depends largely on the region in which the dielectric fin 230 is deployed. When implemented in densely packaged logic device regions or memory device regions, the dielectric fin 230 may have a relatively small width. When implemented in ESD device regions or I / O device regions, the dielectric fin 230 may have a much larger width.

[0028] The workpiece 200 also includes a contact etch stop layer (CESL) 216 over the source / drain features (including the first source / drain feature 220-1, the second source / drain feature 220-2, the third source / drain feature 220-3, and the fourth source / drain feature 220-4), a first interlayer dielectric (ILD) layer 218 over the CESL 216, and a second ILD layer 222 over the first ILD layer 218. Figure 3 As shown, CESL 216 contacts the top surface of the source / drain features (including the first source / drain feature 220-1, the second source / drain feature 220-2, the third source / drain feature 220-3, and the fourth source / drain feature 220-4), the sidewalls of the gate spacer 210, and the sidewalls of the SAC layer 214. The first ILD layer 218 is separated from the source / drain features (including the first source / drain feature 220-1, the second source / drain feature 220-2, the third source / drain feature 220-3, and the fourth source / drain feature 220-4), the gate spacer 210, and the SAC layer 214 via CESL 216. CESL 216 may include a nitrogen-containing dielectric material. In some cases, CESL 216 may include silicon nitride or silicon carbonitride. The first ILD layer 218 and the second ILD layer 222 may comprise silicon oxide, or a low-k dielectric material with a k-value (dielectric constant) less than that of silicon oxide (which is about 3.9). In some examples, the low-k dielectric material includes porous organosilicon films (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide (e.g., borophosphosilicate glass (BPSG)), fused silica glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon carbonitride (SiCN), silicon carbon oxycarbide (SiOC), spin-coated silicon-based polymer dielectrics, or combinations thereof.

[0029] To distinguish the source / drain contacts to be formed, the workpiece 200 may also include multiple contact cutting features 224. For example... Figure 3 and Figure 4 As shown, each contact dicing feature 224 rises above the top surface of the SAC layer 214. The contact dicing feature 224 may have a different composition than the first ILD layer 218 and the second ILD layer 222 to allow selective etching of the first ILD layer 218 and the second ILD layer 222. In some embodiments, the contact dicing feature 224 may include silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, or combinations thereof. Figure 3In some embodiments shown, a portion of the contact cut feature 224 may extend above the top surface of the adjacent SAC layer 214. The contact cut feature 224 may be deposited using atomic layer deposition (ALD) or flowable chemical vapor deposition (FCVD). In some implementations of forming the contact cut feature 224 using ALD, the contact cut feature 224 may include a seam 226, which is created due to premature merging of the dielectric material above the seam 226. Although the seam 226 is shown as being sealed after a planarization process (e.g.) Figure 3 (As shown), however, after planarization following the deposition of the second ILD layer 222, the seam 226 can be open. In some cases, the contact cut feature 224 can be seamless. The contact cut feature 224 is also... Figure 2 As shown, it can have a second width W2 along the X direction. Note that, although Figure 2 The contact cut feature 224 appears to be connected to two adjacent gate spacers 210 disposed along two adjacent gate structures 208, but the top portion of each contact cut feature 224 may span over the gate spacers 210 and the SAC layer 214, as shown. Figure 3 As shown. In some cases, the second width W2 can be between approximately 10 nm and approximately 190 nm. For example... Figure 2 and Figure 3 As shown, each contact cut feature 224 extends longitudinally along the Y direction, parallel to the gate structure 208. According to this disclosure, the top surface of the contact cut feature 224 is coplanar with the second ILD layer 222 and higher than the top surface of the SAC layer 214, ensuring that the contact cut feature 224 effectively divides the source / drain contacts into segments. Without the contact cut feature 224, the source / drain contacts deposited on the source / drain features could extend continuously along the Y direction, leading to undesirable connections from a design perspective.

[0030] refer to Figure 1 , Figure 5 and Figure 6Method 100 includes block 104, in which a first ILD layer 218 and a second ILD layer 222 are removed to expose source / drain features. In some embodiments, at block 104, a patterned photoresist layer is used as an etching mask to dry etch the workpiece 200 to etch the first ILD layer 218 and the second ILD layer 222 to form contact openings 228. Example dry etching processes at block 104 can be implemented using oxygen, oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, NF3, BF3, CH2F2, CHF3, CH3F, C4H8, C4F6 and / or C2F6), carbon-containing gases (e.g., CO, CH4 and / or C3H8), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. Figure 5 and Figure 6 As shown, the etching process at box 104 can selectively etch the first ILD layer 218 and the second ILD layer 222, and at a slower rate etch the source / drain features (including the first source / drain feature 220-1, the second source / drain feature 220-2, the third source / drain feature 220-3, and the fourth source / drain feature 220-4), the contact cut feature 224, and the dielectric fin 230. At the end of the operation at box 104, a portion of the first source / drain feature 220-1, a portion of the fourth source / drain feature 220-4, and the dielectric fin 230 are exposed in the contact opening 228. Figure 6 In some of the implementations shown, the portions of CESL 216 above the first source / drain feature 220-1 and the fourth source / drain feature 220-4 are also removed.

[0031] refer to Figure 1 , Figure 7 , Figure 8 , Figure 9 and Figure 10 Method 100 includes a frame 106 in which a patterned photoresist layer 2400 is formed. In an example process, a photoresist layer 238 may be deposited on a workpiece 200. The photoresist layer 238 may be a single layer or multiple layers. Figure 7 and Figure 8In some embodiments, the photoresist layer 238 is a three-layer structure and may include a bottom layer 240, an intermediate layer 242 above the bottom layer 240, and a top layer 244 above the intermediate layer 242. In one embodiment, the bottom layer 240 may be a carbon-rich polymer layer comprising carbon (C), hydrogen (H), and oxygen; the intermediate layer 242 may be a silicon-rich polymer layer comprising silicon (Si), carbon (C), hydrogen (H), and oxygen (O); and the top layer 244 may be a photosensitive polymer layer comprising carbon (C), hydrogen (H), oxygen (O), and a photosensitive component. To pattern the photoresist layer 238, the top layer 244 is first exposed to radiation reflected from or transmitted through the photomask, baked in a post-exposure baking process, developed in a development process, and rinsed. Thus, the pattern of the photomask is transferred to the top layer 244 to form a patterned top layer 244, which includes an opening 246 above the first source / drain feature 220-1, such as... Figure 7 and Figure 8 As shown. According to this disclosure, the opening 246 is located directly above the first source / drain feature 220-1 and has an area projection larger than that of the first source / drain feature 220-1. That is, some portions of the opening 246 overlap vertically with the contact cut feature 224, the dielectric fin 230, and the SAC layer 214 above the adjacent gate structure 208. Although in Figure 7 The opening 246 is depicted as existing only on a first source / drain feature 220-1, but the opening 246 may extend along the X direction over multiple source / drain features and may have an elongated shape. In some embodiments, the opening 246 includes a sixth width W6 along the X direction (e.g., Figure 7 (as shown) and the seventh width W7 along the Y direction (as shown) Figure 8 (As shown). The sixth width W6 is greater than the X-direction dimension of the first source / drain feature 220-1, and the seventh width W7 is greater than the Y-direction dimension of the first source / drain feature 220-1. In some cases, the sixth width W6 can be between approximately 20 nm and approximately 10 μm (i.e., 10,000 nm), and the seventh width W7 can be between approximately 15 nm and approximately 300 nm. Reference Figure 9 and Figure 10The patterned top layer 244 serves as an etching mask to etch the intermediate layer 242 and the bottom layer 240, thereby forming a patterned photoresist layer 2400. The patterned photoresist layer 2400 includes an entry opening 2460 exposing a first source / drain feature 220-1. In the depicted embodiment, the entry opening 2460 may have a tapered side profile such that the top opening of the entry opening 2460 (having a seventh width W7) is wider than the bottom opening adjacent to the first source / drain feature 220-1. In some cases, the entry opening 2460 is characterized by a tapering angle θ between approximately 0° and approximately 30°. Figure 10 As shown, the second source / drain feature 220-2 and the fourth source / drain feature 220-4 remain covered by a patterned photoresist layer 2400.

[0032] refer to Figure 1 , Figure 11 and Figure 12 Method 100 includes block 108, wherein a dielectric feature 248 is formed in an access opening 2460. In some embodiments, a dielectric material is first deposited in the access opening 2460 using CVD, FCVD, or ALD. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, or combinations thereof. In one embodiment, the dielectric material for the dielectric feature 248 includes silicon oxide. The deposited dielectric material is then etched back to form the dielectric feature 248. Figure 12 As shown, although the top surface of dielectric feature 248 is lower than the top surface of contact cut feature 224, the top surface of dielectric feature 248 can be higher than the top surface of dielectric fin 230. In addition... Figure 12 In some alternative embodiments shown, the dielectric feature 248 may have an alternative top surface 248' that is lower than the top surface of the dielectric fin 230. For example... Figure 11 As shown, when viewed along the Y direction, the dielectric feature 248 is disposed between the two gate spacers 210 and is at least partially disposed on the first source / drain feature 220-1. (Reference) Figure 12When viewed along the X-direction, dielectric feature 248 is in direct contact with the adjacent contact cut feature 224 and extends along the sidewall of the dielectric fin 230 that separates the first source / drain feature 220-1 and the fourth source / drain feature 220-4. In the depicted embodiment, dielectric feature 248 sits on both isolation feature 203 and the first source / drain feature 220-1. Measured from the top surface of the first source / drain feature 220-1, dielectric feature 248 has a first height H1. The top surface of dielectric feature 248 is lower than the top surface of contact cut feature 224 to allow the source / drain contact feature to extend above dielectric feature 248. In some embodiments, the first height H1 may be between about 5 nm and about 50 nm. The top surface of contact cut feature 224 is between about 5 nm and about 65 nm higher than the top surface of dielectric feature 248. Measured from the top surface of the first source / drain feature 220-1, the height of the contact cut feature 224 can be between approximately 10 nm and approximately 70 nm.

[0033] After forming the dielectric feature 248, the patterned photoresist layer 2400 is removed by etching, ashing, or a suitable method, such as... Figure 13 and Figure 14 As shown. Removing the patterned photoresist layer 2400 leaves a contact opening 249 exposing the fourth source / drain feature 220-4. When viewed along the X direction, the contact opening 249 is defined between two contact cut features 224, one of which is adjacent to the first source / drain feature 220-1, and the other is adjacent to the fourth source / drain feature 220-4. Figure 14 As shown, dielectric feature 248 and dielectric fin 230 are exposed in contact opening 249 and form the shape of contact opening 249. The contour of dielectric feature 248 generally follows... Figure 10 The tapered side profile of the entry opening 2460 is shown. As a result, the dielectric feature 248 may include an edge portion 2480 that slightly overhangs the dielectric fin 230. Depending on the taper angle and the seventh width W7, the edge portion 2480 may overhang the dielectric fin 230 by approximately 0 nm to approximately 100 nm when the top surface of the dielectric feature 248 is higher than the top surface of the dielectric fin 230.

[0034] refer to Figure 1 , Figure 15 and Figure 16Method 100 includes a frame 110 in which a liner 250 is formed along the sidewalls of the contact opening 249. In an example process, a liner material is conformally deposited on the workpiece 200. The liner material may include silicon nitride (SiN) or a suitable nitrogen-containing dielectric material. Subsequently, the deposited liner material is etched back to remove the liner material on the top-facing surface, thereby forming the liner 250 along the sidewalls of the contact opening 249 (including the sidewalls of the dielectric fin 230, the sidewalls of the dielectric feature 248, and the sidewalls of the contact cut feature 224).

[0035] refer to Figure 1 , Figure 17 and Figure 18 Method 100 includes block 112, wherein a silicide feature 253 is formed over an exposed fourth source / drain feature 220-4. In an example process, a metal precursor layer 252 is conformally deposited over a contact opening 249, including over the fourth source / drain feature 220-4 and the liner 250. In some cases, the metal precursor layer 252 is deposited using physical vapor deposition (PVD), CVD, or ALD. The metal precursor layer 252 may include nickel (Ni), cobalt (Co), tantalum (Ta), or titanium (Ti). The workpiece 200 is then annealed to induce a silicide reaction between the silicon in the fourth source / drain feature 220-4 and the metal precursor layer 252. The silicide reaction produces the silicide feature 253 on the fourth source / drain feature 220-4. In some examples, the silicide feature 253 may include nickel silicide, cobalt silicide, tantalum silicide, or titanium silicide. Silicide feature 253 can reduce the fourth source / drain feature 220-4 and the metal filler layer 254 to be deposited on silicide feature 253 (e.g. Figure 19 The contact resistance between (as shown). In one embodiment, silicide feature 253 is formed of titanium silicide.

[0036] refer to Figure 1 , Figure 19 and Figure 20 Method 100 includes block 114, wherein a metal filler layer 254 is deposited over a silicide feature 253 and a dielectric feature 248. In some embodiments, at block 114, the metal filler layer 254 is in direct contact with the silicide feature 253 and is electrically connected to a fourth source / drain feature 220-4 through the silicide feature 253. In some cases, the metal filler layer 254 may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), or nickel (Ni), and may be deposited using PVD or a suitable deposition method. Figure 19 As shown, a metal filler layer 254 can be deposited on the SAC layer 214 and the contact cut feature 224. (Reference) Figure 20 The metal filling layer 254 is separated from the first source / drain feature 220-1 by the dielectric feature 248.

[0037] refer to Figure 1 , Figure 21 and Figure 22 Method 100 includes block 116, in which workpiece 200 is planarized. At block 116, a metal filler layer 254 is planarized until the SAC layer 214 and contact cut feature 224 are exposed on the top flat surface of workpiece 200. Figure 21 and Figure 22 As shown, planarization removes the connection portions of the metal filler layer 254 and allows the contact cut feature 224 and the SAC layer 214 to divide the metal filler layer 254 into individual contact features. For example, after planarization at box 116, a first source / drain contact 2542 is formed over the first source / drain feature 220-1 and the fourth source / drain feature 220-4, and a second source / drain contact 2544 is formed over the second source / drain feature 220-2. (See reference...) Figure 22 Along the Y-direction and between two contact cut features 224, the first source / drain contact 2542 includes a first portion 2542A and a second portion 2542B. The first portion 2542A overhangs the first source / drain feature 220-1, and the second portion 2542B is electrically coupled to the fourth source / drain feature 220-4 via a silicide feature 253. In other words, the first source / drain contact 2542 spans over both the first and fourth source / drain features 220-1, and the first portion 2542A "flies" over the first source / drain feature 220-1. As indicated by the double arrows, the first portion 2542A is spaced apart from the first source / drain feature 220-1 by a dielectric feature 248. The boundary between the first portion 2542A and the second portion 2542B generally falls above the edge of the dielectric fin 230, as shown by the dashed line. Part 2542A extends over the dielectric fin 230. (Brief reference) Figure 21 The operation at frame 116 can also form a second source / drain contact 2544, which is electrically coupled to the second source / drain feature 220-2 via a silicide feature 253 disposed on the second source / drain feature 220-2. As described above, planarization can expose the seam 226 in the contact cut feature 224, such as Figure 21 As shown.

[0038] Still referencing Figure 22The first source / drain contact 2542 follows the topography of the first source / drain feature 220-1 and the fourth source / drain feature 220-4. The first portion 2542A includes a first thickness T1 measured from the top surface of the dielectric feature 248 and a second thickness T2 measured from the top surface of the dielectric fin 230. The second portion 2542B includes a third thickness T3 measured from the top surface of the silicide feature 253. The third thickness T3 is greater than either the first thickness T1 or the second thickness T2. In some embodiments, the first thickness T1 may be between about 5 nm and about 65 nm, the second thickness T2 may be between about 5 nm and about 65 nm, and the third thickness T3 may be between about 10 nm and about 70 nm. According to this disclosure, the first thickness T1 of the first portion 2542A is less than the third thickness T3 of the second portion 2542B, thereby reducing the parasitic capacitance between the first source / drain contact 2542 and the adjacent gate structure 208. For Method 100 to be valuable, the ratio of the first thickness T1 to the third thickness T3 should be between approximately 0.1 and approximately 0.7. If the ratio of the first thickness T1 to the third thickness T3 is greater than 0.7, the resulting reduction in parasitic capacitance may not be sufficient to justify the additional time and cost associated with performing the operations in Method 100. If the ratio of the first thickness T1 to the third thickness T3 is less than 0.1, the resistance of the thinner first portion 2542A may become too high, affecting performance. This is especially true when the first portion 2542A is elongated along the Y direction.

[0039] refer to Figure 1 Method 100 includes block 118, in which further processes are performed. Such further processes may include forming contact vias over source / drain contacts (e.g., first source / drain contact 2542 and second source / drain contact 2544), forming gate contacts, and forming interconnect structures over workpiece 200. The interconnect structures include multiple metal layers embedded in multiple inter-metal dielectric (IMD) layers. Each of the multiple metal layers includes multiple metal lines and multiple contact vias. The interconnect structures functionally connect the gate contacts and source / drain contacts (e.g., first source / drain contact 2542 and second source / drain contact 2544) and allow the semiconductor device 200 to perform its intended function.

[0040] The embodiments of this disclosure offer benefits. For example, the source / drain contacts of this disclosure allow for a reduction in the number of metal wires. Figure 23A first semiconductor structure 300 is shown. The first semiconductor structure 300 includes a first active region 204 and a second active region 204'. A standard source / drain contact 400 and a third source / drain contact 2546 are coupled to different source / drain features on the second active region 204'. A second source / drain contact 2544 is coupled to the source / drain features on the first active region 204'. Because the standard source / drain contact 400 is not short-circuited with the third source / drain feature, they are not electrically coupled to the same metal line. Figure 23 As shown, the standard source / drain contact 400 is electrically coupled to the second metal line 274 through the first contact via 262, the third source / drain contact 2546 is coupled to the third metal line 276 through the third contact via 266, and the second source / drain contact 2544 is coupled to the first metal line 272 through the second contact via 264. The second gap S2 between the first active region 204 and the second active region 204' needs to accommodate three metal lines (i.e., the first metal line 272, the second metal line 274, and the third metal line 276). Figure 24 A second semiconductor structure 302 is shown. Unlike... Figure 23 The first semiconductor structure 300 and the second semiconductor structure 302 include a first source / drain contact 2542 of this disclosure, instead of a standard source / drain contact 400. A first portion 2542A extends the first source / drain contact 2542 toward the first active region 204 and repositions the first contact via 262. This repositioning allows the first contact via 262 to couple to a first metal line 272. This repositioning also allows the elimination of a second metal line 274 (shown in dashed lines). The elimination of the second metal line 274 reduces the second spacing S2 between the first active region 204 and the second active region 204'. That is, Figure 24 The second interval S2 is less than Figure 23 The second interval S2. For a cell or standard cell having a cell height (along the longitudinal direction of the gate structure) and a cell width (along the longitudinal direction of the active region), the reduction of the interval between the active regions can be translated into a reduction of the cell height of the corresponding cell or standard cell. It has been observed that the implementation of the source / drain contact of this disclosure can reduce the ratio of cell height to cell width to a range between about 1.1 and about 1.4, including a range between 1.2 and 1.3.

[0041] In another example, the source / drain contacts of this disclosure allow for the repositioning of contact vias without incurring additional parasitic capacitance. Reference Figure 21Because the top surface of dielectric feature 248 is higher than the top surface of adjacent gate structure 208, the first portion 2542A does not overlap with the adjacent gate structure 208 along the X direction. In other words, the bottom surface of the first portion 2542A is higher than the top surface of the adjacent gate structure 208. Figure 25 The spatial relationship between the first portion 2542A and the adjacent gate structure 208 is shown. Because of the presence of the dielectric feature 248, the first portion 2542A is spaced from the first active region 204 (or the source / drain contacts above the first active region 204) by more than the height of the adjacent gate structure 208. The dielectric feature 248 below the first portion 2542A (e.g., ...) Figure 21 (As shown) This reduces the area overlap with adjacent gate structures 208, thereby reducing parasitic capacitance. Compared to other source / drain contacts that overlap with adjacent gate structures, the source / drain contacts of this disclosure can increase the ring oscillator speed of the semiconductor device by about 0.5% to about 1%.

[0042] Therefore, one embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes: a first fin structure and a second fin structure on a substrate; a first source / drain feature and a second source / drain feature, the first source / drain feature being disposed on the first fin structure and the second source / drain feature being disposed on the second fin structure; a dielectric feature disposed on the first source / drain feature; and a contact structure formed on the first source / drain feature and the second source / drain feature. The contact structure is electrically coupled to the second source / drain feature and separated from the first source / drain feature by the dielectric feature.

[0043] In some embodiments, the semiconductor structure may further include a dielectric fin disposed on a substrate and between a first source / drain feature and a second source / drain feature, wherein the dielectric feature extends along the dielectric fin. In some implementations, the top surface of the dielectric feature is higher than the top surface of the dielectric fin. In some cases, the semiconductor structure may further include a spacer disposed between the sidewall of the dielectric fin and the contact structure. In some embodiments, the spacer comprises silicon nitride or silicon oxynitride. In some implementations, the semiconductor structure may further include a silicide layer disposed between the second source / drain feature and the contact structure. In some embodiments, the contact structure extends longitudinally along a direction from above the first source / drain feature to above the second source / drain feature, and along this direction, the contact structure is disposed between two dielectric cleaving features. In some implementations, each of the two dielectric cleaving features includes a seam. In some cases, the semiconductor structure may further include a gate structure surrounding the first and second fin structures, and the top surface of the dielectric feature is higher than the top surface of the gate structure. In some cases, the gate structure is spaced apart from the dielectric feature by a gate spacer.

[0044] In another embodiment, a contact structure is provided. The contact structure includes: a first source / drain feature and a second source / drain feature; a dielectric fin disposed between the first and second source / drain features; a dielectric feature disposed above the first source / drain feature and extending along the sidewall of the dielectric fin; and a contact feature including a first portion disposed above the dielectric feature and the dielectric fin, and a second portion electrically coupled to the second source / drain feature. The first portion hangs over the first source / drain feature.

[0045] In some embodiments, the contact structure may further include contact vias disposed on the first portion. In some implementations, the dielectric fin includes a first layer and a second layer disposed above the first layer. The first layer includes silicon oxide, and the second layer includes silicon and nitrogen. In some embodiments, the dielectric feature includes silicon oxide. In some embodiments, the contact structure may further include a gate structure adjacent to the first source / drain feature and the second source / drain feature, and the bottom surface of the first portion is higher than the top surface of the gate structure. In some implementations, the second portion is spaced apart from the dielectric fin by a liner.

[0046] In another embodiment, a method is provided. The method includes receiving a workpiece comprising: a first fin structure and a second fin structure on a substrate; a gate structure surrounding the first and second fin structures; a first source / drain feature on the first fin structure; and a second source / drain feature on the second fin structure. The method further includes: selectively forming a dielectric feature on the first source / drain feature; and, after selectively forming the dielectric feature, forming a contact structure on the first and second source / drain features such that the contact structure is electrically connected to the second source / drain feature and separated from the first source / drain feature by the dielectric feature.

[0047] In some embodiments, selective formation includes: forming a photoresist layer over a first source / drain feature and a second source / drain feature; patterning the photoresist layer to form a patterned photoresist layer including an opening exposing the first source / drain feature; depositing a dielectric material in the opening; and etching back the dielectric material to form the dielectric feature. In some cases, the etching back removes the patterned photoresist layer. In some implementations, the method may further include forming a liner along the sidewalls of the dielectric feature prior to forming the contact structure.

[0048] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0049] Example 1. A semiconductor structure comprising: a first fin structure and a second fin structure on a substrate; a first source / drain feature and a second source / drain feature, the first source / drain feature being disposed on the first fin structure and the second source / drain feature being disposed on the second fin structure; a dielectric feature disposed on the first source / drain feature; and a contact structure formed on the first source / drain feature and the second source / drain feature, wherein the contact structure is electrically coupled to the second source / drain feature and separated from the first source / drain feature by the dielectric feature.

[0050] Example 2. The semiconductor structure according to Example 1 further includes: a dielectric fin disposed on the substrate and between the first source / drain feature and the second source / drain feature, wherein the dielectric feature extends along the dielectric fin.

[0051] Example 3. The semiconductor structure according to Example 2, wherein the top surface of the dielectric feature is higher than the top surface of the dielectric fin.

[0052] Example 4. The semiconductor structure according to Example 2 further includes: a spacer disposed between the sidewall of the dielectric fin and the contact structure.

[0053] Example 5. The semiconductor structure according to Example 4, wherein the spacer comprises silicon nitride or silicon oxynitride.

[0054] Example 6. The semiconductor structure according to Example 1 further includes: a silicide layer disposed between the second source / drain feature and the contact structure.

[0055] Example 7. The semiconductor structure according to Example 1, wherein the contact structure extends longitudinally along a direction from above the first source / drain feature to above the second source / drain feature, wherein the contact structure is disposed between two dielectric cut features along the direction.

[0056] Example 8. The semiconductor structure according to Example 7, wherein each of the two dielectric cleaving features includes a seam.

[0057] Example 9. The semiconductor structure according to Example 1 further includes: a gate structure surrounding the first fin structure and the second fin structure, wherein the top surface of the dielectric feature is higher than the top surface of the gate structure.

[0058] Example 10. The semiconductor structure according to Example 9, wherein the gate structure is spaced apart from the dielectric feature by a gate spacer.

[0059] Example 11. A contact structure comprising: a first source / drain feature and a second source / drain feature; a dielectric fin disposed between the first source / drain feature and the second source / drain feature; a dielectric feature disposed on the first source / drain feature and extending along the sidewall of the dielectric fin; and a contact feature including a first portion disposed on the dielectric feature and the dielectric fin and a second portion electrically coupled to the second source / drain feature, wherein the first portion hangs over the first source / drain feature.

[0060] Example 12. The contact structure according to Example 11 further includes: a contact through hole disposed on the first part.

[0061] Example 13. The contact structure according to Example 11, wherein the dielectric fin includes a first layer and a second layer disposed on the first layer, wherein the first layer includes silicon oxide, and wherein the second layer includes silicon and nitrogen.

[0062] Example 14. The contact structure according to Example 11, wherein the dielectric feature comprises silicon oxide.

[0063] Example 15. The contact structure according to Example 11 further includes: a gate structure adjacent to the first source / drain feature and the second source / drain feature, wherein the bottom surface of the first portion is higher than the top surface of the gate structure.

[0064] Example 16. The contact structure according to Example 11, wherein the second portion is spaced apart from the dielectric fin by a liner.

[0065] Example 17. A method of manufacturing a semiconductor structure, comprising: receiving a workpiece including: a first fin structure and a second fin structure on a substrate; a gate structure surrounding the first fin structure and the second fin structure; a first source / drain feature on the first fin structure; and a second source / drain feature on the second fin structure; selectively forming a dielectric feature on the first source / drain feature; and after the selective formation, forming a contact structure on the first source / drain feature and the second source / drain feature such that the contact structure is electrically connected to the second source / drain feature and separated from the first source / drain feature by the dielectric feature.

[0066] Example 18. The method according to Example 17, wherein the selective formation comprises: forming a photoresist layer over the first source / drain feature and the second source / drain feature; patterning the photoresist layer to form a patterned photoresist layer, the patterned photoresist layer including an opening exposing the first source / drain feature; depositing a dielectric material in the opening; and etching back the dielectric material to form the dielectric feature.

[0067] Example 19. The method according to Example 18, wherein the etchback removes the patterned photoresist layer.

[0068] Example 20. The method according to Example 17 further includes: forming a liner along the sidewall of the dielectric feature prior to forming the contact structure.

Claims

1. A semiconductor structure, comprising: The first fin structure and the second fin structure are on the substrate; First source / drain feature and second source / drain feature, wherein the first source / drain feature is disposed on the first fin structure and the second source / drain feature is disposed on the second fin structure; A dielectric feature is disposed on the first source / drain feature, and the dielectric feature contacts the top surface and sidewall of the first source / drain feature; as well as The contact structure is formed on the first source / drain feature and the second source / drain feature. The contact structure is electrically coupled to the second source / drain feature and separated from the first source / drain feature by the dielectric feature.

2. The semiconductor structure according to claim 1, further comprising: A dielectric fin is disposed on the substrate and between the first source / drain feature and the second source / drain feature, wherein the dielectric feature extends along the dielectric fin.

3. The semiconductor structure according to claim 2, wherein, The top surface of the dielectric feature is higher than the top surface of the dielectric fin.

4. The semiconductor structure according to claim 2, further comprising: A spacer is disposed between the sidewall of the dielectric fin and the contact structure.

5. The semiconductor structure according to claim 4, wherein, The spacer includes silicon nitride or silicon oxynitride.

6. The semiconductor structure according to claim 1, further comprising: A silicide layer is disposed between the second source / drain feature and the contact structure.

7. The semiconductor structure according to claim 1, in, The contact structure extends longitudinally along a direction from above the first source / drain feature to above the second source / drain feature. Along the stated direction, the contact structure is disposed between two dielectric cutting features.

8. The semiconductor structure according to claim 7, wherein, Each of the two dielectric cutting features includes a seam.

9. The semiconductor structure according to claim 1, further comprising: A gate structure surrounds the first fin structure and the second fin structure. The top surface of the dielectric feature is higher than the top surface of the gate structure.

10. The semiconductor structure according to claim 9, wherein, The gate structure is separated from the dielectric feature by a gate spacer.

11. A contact structure, comprising: First source / drain characteristics and second source / drain characteristics; A dielectric fin is disposed between the first source / drain feature and the second source / drain feature; A dielectric feature is disposed on the first source / drain feature and extends along the sidewall of the dielectric fin, the dielectric feature contacting the top surface and sidewall of the first source / drain feature; as well as The contact feature includes a first portion disposed on the dielectric feature and the dielectric fin, and a second portion electrically coupled to the second source / drain feature. The first portion hangs over the first source / drain feature.

12. The contact structure according to claim 11, further comprising: A contact via is provided on the first part.

13. The contact structure according to claim 11, in, The dielectric fin includes a first layer and a second layer disposed on top of the first layer. The first layer includes silicon oxide. The second layer comprises silicon and nitrogen.

14. The contact structure according to claim 11, wherein, The dielectric features include silicon oxide.

15. The contact structure according to claim 11, further comprising: The gate structure is adjacent to the first source / drain feature and the second source / drain feature. The bottom surface of the first portion is higher than the top surface of the gate structure.

16. The contact structure according to claim 11, wherein, The second portion is spaced apart from the dielectric fin by a liner.

17. A method for manufacturing a semiconductor structure, comprising: Receive a workpiece, the workpiece comprising: The first fin structure and the second fin structure are on the substrate. A gate structure surrounds the first fin structure and the second fin structure. The first source / drain characteristics are located on top of the first fin structure, and The second source / drain feature is located on top of the second fin structure; A dielectric feature is formed on the first source / drain feature, the dielectric feature contacting the top surface and sidewalls of the first source / drain feature; and After the dielectric feature is formed, a contact structure is formed on the first source / drain feature and the second source / drain feature, such that the contact structure is electrically connected to the second source / drain feature and separated from the first source / drain feature by the dielectric feature.

18. The method according to claim 17, wherein, The dielectric features include: A photoresist layer is formed on the first source / drain feature and the second source / drain feature; The photoresist layer is patterned to form a patterned photoresist layer, the patterned photoresist layer including an opening that exposes the first source / drain feature; Dielectric material is deposited in the opening; and The dielectric material is etched back to form the dielectric feature.

19. The method according to claim 18, wherein, The etch-back process removes the patterned photoresist layer.

20. The method of claim 17, further comprising: Before forming the contact structure, a liner is formed along the sidewalls of the dielectric feature.

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