Semiconductor devices

Abstract

This invention provides a semiconductor device comprising multiple semiconductor elements and suitable for miniaturization. Multiple transistors are arranged in one direction on one side of a substrate, and the transistors are connected in parallel. Each of the multiple transistors includes a collector layer, a base layer, and an emitter layer stacked sequentially from the substrate side. At least one region between two adjacent transistors is provided with a passive element. A collector electrode electrically connected to the collector layer is disposed between the collector layer of each transistor and the substrate.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Heterojunction bipolar transistors (HBTs) are used in high-frequency power amplifiers in mobile devices. Due to the high output of power amplifiers, the self-heating of HBTs increases. If the temperature of the HBT rises due to self-heating, the collector current increases. This increase in collector current can lead to a further rise in temperature, eventually resulting in thermal runaway.

[0003] To suppress thermal runaway of HBTs, it is desirable to improve their heat dissipation characteristics. Patent Document 1 discloses a semiconductor device that suppresses chip size enlargement and possesses high heat dissipation characteristics. The semiconductor device disclosed in Patent Document 1 has multiple HBTs arranged in a row on a substrate made of semi-insulating materials such as GaAs, and connected in parallel. For each of the multiple HBTs, a collector electrode is disposed at a position sandwiching the HBT in the arrangement direction. Furthermore, a diode is disposed between two adjacent HBTs in the arrangement direction. This diode forms a heat conduction path from the HBT to the substrate made of semi-insulating materials such as GaAs.

[0004] Patent Document 1: International Publication No. 2005 / 096365 Summary of the Invention

[0005] With the increasing number of components in mobile terminals, there is a desire to further miniaturize semiconductor devices such as power amplifiers. The object of this invention is to provide a semiconductor device comprising multiple semiconductor elements that is suitable for miniaturization.

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0007] substrate;

[0008] Multiple transistors are arranged in one direction on one side of the substrate and connected in parallel. Each of the multiple transistors includes a collector layer, a base layer, and an emitter layer sequentially stacked starting from the substrate side.

[0009] At least one passive element is disposed in at least one region between two adjacent transistors in the plurality of transistors.

[0010] The semiconductor device further includes a collector electrode disposed between the collector layer of each of the plurality of transistors and the substrate, and electrically connected to the collector layer.

[0011] Since each of the multiple transistors has a collector electrode disposed between itself and the substrate, miniaturization can be achieved compared to a structure where the collector electrode is disposed next to the transistor on the substrate. Furthermore, to suppress temperature rise in the multiple transistors, it is preferable to maintain a certain spacing between adjacent transistors. Since passive components are disposed within the space where this spacing is provided, efficient utilization of space on the substrate is achieved. This efficient use of space further promotes miniaturization. Attached Figure Description

[0012] Figure 1 This is a diagram showing the positional relationship of the electrodes and wiring of the semiconductor device of the first embodiment when viewed from above.

[0013] Figure 2A This is an equivalent circuit diagram of a transistor and passive components connected thereto in the semiconductor device of the first embodiment. Figure 2B This is a cross-sectional view showing the connection relationship of a transistor, an input capacitor, and a ballast resistor element in the semiconductor device of the first embodiment.

[0014] Figures 3A to 3F The image is a cross-sectional view of a semiconductor device during the manufacturing process.

[0015] Figures 4A to 4C The image is a cross-sectional view of a semiconductor device during the manufacturing process. Figure 4D This is a cross-sectional view of the completed semiconductor device.

[0016] Figure 5 This is a diagram showing the positional relationship of the electrodes and wiring of the semiconductor device of the second embodiment when viewed from above.

[0017] Figure 6A This is an equivalent circuit diagram of a transistor and passive components connected thereto in the semiconductor device of the second embodiment. Figure 6B This is a cross-sectional view showing the connection relationship of a transistor, an input capacitor, and an emitter-base capacitor in the semiconductor device of the second embodiment.

[0018] Figure 7 This is a diagram showing the positional relationship of the electrodes and wiring of the semiconductor device according to the third embodiment when viewed from above.

[0019] Figure 8A This is an equivalent circuit diagram of a transistor and passive components connected thereto in the semiconductor device of the third embodiment. Figure 8B This is a cross-sectional view showing the connection relationship of a transistor, an input capacitor, a base-collector inter-electrode capacitor, and a base-collector inter-electrode resistive element in the semiconductor device of the third embodiment.

[0020] Figure 9 This is a diagram showing the positional relationship of the electrodes and wiring of the semiconductor device according to the fourth embodiment when viewed from above.

[0021] Figure 10A This is an equivalent circuit diagram of a transistor and passive components connected thereto in the semiconductor device of the fourth embodiment. Figure 10B This is a cross-sectional view showing the connection relationship of a transistor, an input capacitor, and a collector-emitter capacitor in the semiconductor device of the fourth embodiment.

[0022] Figure 11 This is a diagram showing the positional relationship of the electrodes and wiring of the semiconductor device according to the fifth embodiment when viewed from above.

[0023] Figure 12A This is an equivalent circuit diagram of a transistor and passive components connected thereto in the semiconductor device of the fifth embodiment. Figure 12B This is a cross-sectional view showing the connection relationships of a transistor, an input capacitor, an inductor, and other capacitors in the semiconductor device of the fifth embodiment.

[0024] Figure 13 This is a diagram showing the positional relationship of the electrodes and wiring of the semiconductor device according to the sixth embodiment when viewed from above.

[0025] Figure 14A This is an equivalent circuit diagram of a transistor and passive components connected thereto in the semiconductor device of the sixth embodiment. Figure 14B This is a cross-sectional view showing the connection relationship of a transistor, an input capacitor, and an ESD protection diode in the semiconductor device of the sixth embodiment.

[0026] Figure 15 This is a cross-sectional view showing the connection relationship of a transistor, an input capacitor, and an ESD protection diode in a modified semiconductor device according to the sixth embodiment.

[0027] Figure 16A as well as Figure 16B This is an equivalent circuit diagram of a transistor and passive components connected thereto in a semiconductor device of another variation of the sixth embodiment.

[0028] Figure 17A This is an equivalent circuit diagram of a transistor and passive components connected thereto in the semiconductor device of the seventh embodiment. Figure 17B This is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment.

[0029] Explanation of reference numerals in the attached figures

[0030] 20…Transistor, 20B…Base layer, 20C…Collector layer, 20E…Emitter layer, 25…Passive component, 28…High-order harmonic termination circuit, 30B…Base electrode, 30BC…Base contact, 30D…Upper electrode, 30E…Emitter electrode, 30X, 30Y, 30Z…Conductor pattern, 31B…First layer base wiring, 31BB…Base bias wiring, 31BC, 31CE, 31CH…Lower electrode, 31D…Conductor pattern Case, 31E…first layer emitter wiring, 31X…conductor pattern, 32BC, 32CE…upper electrode, 32D…conductor pattern, 32E…second layer emitter wiring, 32EB…electrode, 32LH…wiring, 32RF…high-frequency signal input wiring, 33E…third layer emitter wiring, 41…first layer interlayer insulating film, 41A, 41B, 41C…openings, 42…second layer interlayer insulating film, 42A…opening, 43…third layer interlayer insulating film 43A, 43B, 43C, 43D… openings, 50… substrate semiconductor layer, 50A, 50B, 50C, 50D, 50E, 50F… conductive regions, 50Z… component separation region, 60… first component, 61… substrate, 62… adhesive layer, 62A, 62B, 62C, 62D, 62E, 62F… metal regions, 62Z… insulating region, 63… multilayer wiring structure, 63A, 63F… conductive components, 64… switching element, 6 5…Control circuit, 68…Second component, 70…ESD protection diode, 70A…Anode layer, 70C…Cathode layer, 71…Protection diode, 82W…Emitter pad, 82W…Interconnection wiring, 83E…Emitter conductor protrusion, 84…Solder, 86…Interlayer insulating film, 87…Protective film, 87A…Opening, 90…Semiconductor device, 200…Main substrate, 201…Release layer, 202…Component forming layer, 204…Connection support. Detailed Implementation

[0031] [First Embodiment]

[0032] Reference Figures 1 to 4D The accompanying drawings illustrate the semiconductor device of the first embodiment.

[0033] Figure 1 This is a top view showing the positional relationship of the electrodes and wiring of the semiconductor device according to the first embodiment. A plurality of transistors 20 having substantially the same characteristics are arranged in one direction on one side (hereinafter referred to as the upper surface) of a first component such as a semiconductor substrate. Each of the plurality of transistors 20 is, for example, a heterojunction bipolar transistor (HBT), and the plurality of transistors 20 are connected in parallel with each other. The structure formed by connecting a plurality of transistors having substantially the same characteristics in parallel is called a multi-cell structure.

[0034] A passive element 25 is disposed between two adjacent transistors 20. Each passive element 25 is electrically connected to one of the two transistors 20 disposed on both sides. The passive element 25 connected to one of the transistors 20 located at both ends is not disposed between the transistor 20 at one end and its adjacent transistor 20, but is disposed outside the column of the plurality of transistors 20. In the first embodiment, an input capacitor Cin and a ballast resistor element Rb are disposed as passive elements 25.

[0035] Each transistor 20 is connected to two emitter electrodes 30E and a base electrode 30B. The emitter electrodes 30E and the base electrode 30B are in contact with the semiconductor portion. Figure 1 In the diagram, the metal patterns in contact with the semiconductor portion are marked with relatively dense, upward-sloping shading lines. Furthermore, the number of emitter electrodes 30E connected to each transistor 20 can be one or more. The top view of each emitter electrode 30E indicates that it is elongated in a direction orthogonal to the direction in which the multiple transistors 20 are arranged, for example, it is roughly rectangular.

[0036] The base electrode 30B has a roughly T-shaped shape when viewed from above. The portion corresponding to the longitudinally extending line of the roughly T-shape is disposed between the two emitter electrodes 30E, and the portion corresponding to the laterally extending line (hereinafter referred to as the base contact portion 30BC) is disposed spaced apart from the ends of the two emitter electrodes 30E in the long side direction of the emitter electrode 30E.

[0037] On transistor 20, emitter electrode 30E, and base electrode 30B, a multilayer wiring structure comprising multiple interlayer insulating films and multiple wiring layers is configured to cover approximately the entire area of ​​the substrate. Figure 1 In the diagram, the metal patterns disposed on the first wiring layer are marked with relatively sparse, downward-sloping shaded lines, while the metal patterns disposed on the second wiring layer are represented by relatively thicker outlines. The ballast resistor element Rb is disposed on the first wiring layer without interfering with the interlayer insulating film. Figure 1 In the diagram, the ballast resistor element Rb is marked with a relatively sparse, upward-sloping shaded line.

[0038] The first layer base wiring 31B is connected to the base contact portion 30BC through an opening in the interlayer insulating film disposed below it. Figure 1 In the diagram, the openings in the interlayer insulating film are shown in dashed lines. The base wiring 31B includes a portion extending from the base contact portion 30BC to the outside of the transistor 20 in a direction orthogonal to the arrangement direction of the plurality of transistors 20, a portion disposed between two adjacent transistors 20, and a portion connecting the two.

[0039] A high-frequency signal input wiring 32RF is arranged on one side of the column of transistors 20, and a base bias wiring 31BB is arranged on the opposite side. The high-frequency signal input wiring 32RF is contained in a second wiring layer, and the base bias wiring 31BB is contained in a first wiring layer.

[0040] Viewed from above, the high-frequency signal input wiring 32RF has a comb-like shape, with multiple teeth extending into the region between two adjacent transistors 20. Viewed from above, multiple teeth of the high-frequency signal input wiring 32RF overlap with the first-layer base wiring 31B. An input capacitor Cin is formed in the overlapping region.

[0041] The portion of base wiring 31B positioned between transistors 20 is connected to base bias wiring 31BB via ballast resistor element Rb. When viewed from above, ballast resistor element Rb overlaps with the first layer base wiring 31B and base bias wiring 31BB without passing through the interlayer insulating film, thereby electrically connecting to the base wiring 31B and base bias wiring 31BB.

[0042] The first emitter wiring 31E and the second emitter wiring 32E are configured, when viewed from above, to include two emitter electrodes 30E connected to a transistor 20. The second emitter wiring 32E is electrically connected to the two emitter electrodes 30E via the first emitter wiring 31E.

[0043] Figure 2A This is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in the semiconductor device of the first embodiment. An input capacitor Cin is connected between the base of transistor 20 and the high-frequency signal input wiring 32RF. Furthermore, a ballast resistor element Rb is connected between the base of transistor 20 and the base bias wiring 31BB.

[0044] The emitter of transistor 20 is grounded. A power supply voltage is applied to the collector of transistor 20, and an amplified high-frequency signal is output from the collector.

[0045] Figure 2B This is a cross-sectional view showing the connection relationship of a transistor 20, an input capacitor Cin, and a ballast resistor element Rb in the semiconductor device of the first embodiment. Furthermore, Figure 2B The diagram shown is a representation of electrical connections. Figure 2B The cross-section of the structure shown may not actually exist.

[0046] The semiconductor device of the first embodiment includes a first component 60 and a second component 68. The first component 60 includes a substrate 61 and an adhesive layer 62 disposed on one surface of the substrate 61, wherein the substrate 61 includes a single-element semiconductor such as silicon or germanium. A silicon substrate, a silicon-on-insulator (SOI) substrate, or the like can be used as the substrate 61. Furthermore, a multilayer wiring structure can be disposed between the silicon substrate, the SOI substrate, and the adhesive layer 62 as the substrate 61. In top view, the adhesive layer 62 is divided into a metal region 62A and an insulating region 62Z.

[0047] The second component 68 includes a substrate semiconductor layer 50, which is in surface contact with the adhesive layer 62, thereby bonding the second component 68 to the first component 60. The substrate semiconductor layer 50 is divided into a conductive region 50A and a component separation region 50Z. In top view, the conductive region 50A overlaps with the metal region 62A and the two are electrically connected. The substrate semiconductor layer 50 is, for example, made of GaAs. The conductive region 50A is formed of n-type GaAs, and the component separation region 50Z is formed by ion implantation of insulating impurities into the n-type GaAs layer.

[0048] A transistor 20 is disposed on a conductive region 50A. The transistor 20 comprises a collector layer 20C, a base layer 20B, and an emitter layer 20E, sequentially stacked starting from the conductive region 50A. The emitter layer 20E is disposed on a portion of the base layer 20B. As an example, the collector layer 20C is formed of n-type GaAs, and the base layer 20B is formed of p-type GaAs. The emitter layer 20E, for example, comprises an n-type InGaP layer and an n-type GaAs layer on top of that InGaP layer. That is, the transistor 20 is a heterojunction bipolar transistor.

[0049] A base electrode 30B is disposed on the base layer 20B and is electrically connected to the base layer 20B. An emitter electrode 30E is disposed on the emitter layer 20E and is electrically connected to the emitter layer 20E. The collector layer 20C is electrically connected to the metal region 62A via a conductive region 50A. The metal region 62A functions as the collector electrode. Thus, when viewed from the substrate semiconductor layer 50, the collector electrode is positioned on the opposite side of the transistor 20, and when viewed from above, the collector layer 20C overlaps with the collector electrode.

[0050] On the substrate semiconductor layer 50, a first interlayer insulating film 41 is configured to cover the transistor 20, the base electrode 30B, and the emitter electrode 30E. The first interlayer insulating film 41 is formed, for example, from an inorganic insulating material such as SiN. Multiple openings are provided in the interlayer insulating film 41.

[0051] On the interlayer insulating film 41, a first layer of emitter wiring 31E, base wiring 31B, base bias wiring 31BB, and ballast resistor element Rb are disposed. Emitter wiring 31E is connected to emitter electrode 30E through an opening in the interlayer insulating film 41. Base wiring 31B is connected to base electrode 30B through other openings in the interlayer insulating film 41.

[0052] The base wiring 31B extends into the area where no transistor 20 is configured, and its front end overlaps with one end of the ballast resistor element Rb. In the overlapping portion, the base wiring 31B is electrically connected to the ballast resistor element Rb. The other end of the ballast resistor element Rb overlaps with the base bias wiring 31BB. In the overlapping portion, the ballast resistor element Rb is electrically connected to the base bias wiring 31BB.

[0053] On the interlayer insulating film 41, a second interlayer insulating film 42 is configured to cover the first layer emitter wiring 31E, base wiring 31B, ballast resistor element Rb, and base bias wiring 31BB. The second interlayer insulating film 42 is also formed of an inorganic insulating material such as SiN.

[0054] A second emitter wiring 32E and a high-frequency signal input wiring 32RF are disposed on the interlayer insulating film 42. The second emitter wiring 32E is connected to the first emitter wiring 31E through an opening in the interlayer insulating film 42. In top view, a portion of the high-frequency signal input wiring 32RF overlaps with the first base wiring 31B. An input capacitor Cin is formed in the overlapping area. The first base wiring 31B, the high-frequency signal input wiring 32RF disposed on the second wiring layer, and the second interlayer insulating film 42 function as the lower electrode, upper electrode, and dielectric film of the input capacitor Cin, respectively.

[0055] Although Figure 2B The diagram is omitted, but it includes the second emitter wiring 32E, the high-frequency signal input wiring 32RF, the third wiring layer disposed on the interlayer insulating film 42, and multiple conductor protrusions for connection to external circuits. For example, conductor protrusions can be Cu pillar bumps with solder placed on them, pillars with no solder placed on them (like Au bumps), posts with conductor pillars erected on pads, or ball bumps that allow solder reflow into a spherical shape.

[0056] Next, refer to Figures 3A to 4D The accompanying drawings illustrate a method for manufacturing a semiconductor device according to a first embodiment. Figures 3A to 4C The attached figure is a cross-sectional view of a semiconductor device during the manufacturing process. Figure 4D It is a cross-sectional view of a completed semiconductor device.

[0057] like Figure 3AAs shown, a release layer 201 is epitaxially grown on a single-crystal mother substrate 200 of a compound semiconductor such as GaAs, and a device forming layer 202 is formed on the release layer 201. A device forming layer 202 containing... Figure 2B The diagram shows a device structure consisting of a substrate semiconductor layer 50, a plurality of transistors 20, and a multilayer wiring layer on the transistors 20. These device structures are formed using conventional semiconductor processes. Figure 3A The device structure formed on the device formation layer 202 is omitted from the description. At this stage, a device structure equivalent to multiple semiconductor devices is formed on the device formation layer 202, but it is not separated into individual semiconductor devices.

[0058] Next, as Figure 3B As shown, a resist pattern (not shown) is used as an etching mask to pattern the device formation layer 202 and the release layer 201. In this stage, the device formation layer 202 is separated for each semiconductor device.

[0059] Next, as Figure 3C As shown, a connecting support 204 is attached to the separated component forming layer 202. Thus, multiple component forming layers 202 are interconnected via the connecting support 204. Alternatively, it is also possible to leave [something] on [the surface]. Figure 3B The resist pattern used as an etching mask in the patterning process is sandwiched between the element forming layer 202 and the connecting support 204.

[0060] Next, as Figure 3D As shown, the release layer 201 is selectively etched onto the mother substrate 200 and the device forming layer 202. As a result, the device forming layer 202 and the bonding support 204 are peeled off from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor with etching resistance different from both the mother substrate 200 and the device forming layer 202 is used as the release layer 201.

[0061] like Figure 3E As shown, an adhesive layer 62 is formed on the upper surface of the substrate 61. The adhesive layer 62 includes a plurality of metal regions 62A and insulating regions 62Z distributed in the plane. The adhesive layer 62 can be formed, for example, by a metal inlay process.

[0062] like Figure 3F As shown, the element forming layer 202 is bonded to the adhesive layer 62. The bonding between the element forming layer 202 and the adhesive layer 62 is achieved through van der Waals bonds or hydrogen bonds. Alternatively, the element forming layer 202 can be bonded to the adhesive layer 62 via electrostatic forces, covalent bonds, eutectic alloy bonds, etc. For example, when forming the metal region 62A using Au, the two can also be bonded by pressing the element forming layer 202 tightly against the Au film.

[0063] Next, as Figure 4A As shown, the connecting support 204 is peeled off from the component forming layer 202. After peeling off the connecting support 204, as... Figure 4B As shown, an interlayer insulating film 86 and a redistribution layer are formed on the adhesive layer 62 and the component forming layer 202. The redistribution layer includes emitter wiring 32E disposed on the second layer. Figure 2B The interconnecting wiring 82W between the emitter pad 82E on the first component 60 and the circuit contained in the connecting element forming layer 202 and a metal region 62A of the adhesive layer 62, etc. The interconnecting wiring 82W connects the first component 60 (…). Figure 2B The circuitry contained in the second component 68 ( Figure 2B The circuits contained therein.

[0064] Next, as Figure 4C As shown, a protective film 87 is formed on the redistribution layer, and a plurality of openings 87A are formed in the protective film 87. In top view, the plurality of openings 87A are respectively contained within a plurality of emitter pads 82E. Emitter conductor protrusions 83E are formed within the openings 87A and on the protective film 87. Solder 84 is placed on the top surface of the emitter conductor protrusions 83E and reflow processing is performed. The emitter conductor protrusions 83E are formed, for example, of copper, and Cu pillar bumps are formed by the emitter conductor protrusions 83E and the solder 84.

[0065] Finally, as Figure 4D As shown, substrate 61 is cut. This yields a monolithically formed semiconductor device 90 comprising substrate 61, adhesive layer 62, element forming layer 202, emitter pads 82E, emitter conductor protrusions 83E, interconnecting wiring 82W, etc. In top view, the first component 60 of each element in the monolithically formed semiconductor device 90 is larger than the element forming layer 202 (second component 68). The monolithically formed semiconductor device 90 is flip-chip mounted on a module substrate, etc.

[0066] Next, the superior effects of the first embodiment will be explained.

[0067] In the first embodiment, the metal region 62A functions as the collector electrode. Figure 2B The collector electrode is disposed between the transistor 20 and the substrate 61. Conventionally, the collector electrode is typically disposed on the conductive region 50A. Therefore, the transistor 20 and the collector electrode cannot be configured to overlap when viewed from above. For example, in... Figure 1 In this configuration, the collector electrode is positioned between two adjacent transistors 20.

[0068] In contrast, in the first embodiment, since the metal region 62A and the transistor 20, which function as collector electrodes, are arranged in an overlapping manner, the size of the semiconductor device when viewed from above can be reduced.

[0069] Additionally, if a passive component 25 is not placed between two adjacent transistors 20 ( Figure 1 When two transistors 20 are arranged close together, the heat source is concentrated in a narrower area. As a result, the temperature of the transistors 20 tends to rise. In contrast, in the first embodiment, since passive elements 25 that do not become heat sources are arranged between adjacent transistors 20, the spacing between the transistors 20 is ensured to be wider to a certain extent. Because the heat source is not concentrated in a narrower area, excessive temperature rise of the transistors 20 can be suppressed.

[0070] To suppress temperature rise, simply increasing the spacing between the transistors 20 would increase the size of the semiconductor device when viewed from above. In the first embodiment, by arranging passive components in the expanded area between the transistors 20, the space is effectively utilized, thus suppressing the increase in the size of the semiconductor device when viewed from above.

[0071] Next, a variation of the first embodiment will be described.

[0072] In the first embodiment, the substrate 61, which is the first component 60, Figure 2B It can use substrates containing elemental semiconductors such as silicon and germanium, but it can also use compound semiconductors, such as substrates containing GaAs and SiC.

[0073] Next, from the perspective of heat dissipation characteristics, for the first component 60 ( Figure 2B The preferred material for the substrate 61 will be described below. Heat generated by the transistor 20 is conducted to the first component 60 and diffuses within the first component 60. The heat diffused within the first component 60 is dissipated to the outside from the surface of the first component 60. To improve the heat dissipation characteristics via the first component 60, it is preferable to use a semiconductor material with high thermal conductivity as the substrate 61 of the first component 60. In particular, as the substrate 61, it is preferable to use a substrate containing a semiconductor material with a thermal conductivity higher than that of the compound semiconductor constituting the transistor 20. From the viewpoint of heat dissipation characteristics, preferred semiconductor materials mainly used in the first component 60 include elemental semiconductors, SiC, etc. Examples of elemental semiconductors include Si and Ge.

[0074] Furthermore, in the first embodiment, the emitter uses a conductor protrusion 83E ( Figure 4D It serves as a heat conduction path from transistor 20 to the module substrate. Since two paths are formed, namely a heat conduction path from transistor 20 toward substrate 61 and a heat conduction path via emitter conductor protrusion 83E toward module substrate, high heat dissipation characteristics can be achieved.

[0075] Next, other variations of the first embodiment will be described.

[0076] In the first embodiment ( Figure 1 In this configuration, passive elements 25 are arranged in all regions between adjacent pairs of transistors 20 arranged in one direction. In this variation, passive elements 25 are arranged in at least one region among the multiple regions between adjacent pairs of transistors 20, and not in other regions. As an example, passive elements 25 are arranged in every other region among the multiple regions between adjacent pairs of transistors 20. The spacing between two adjacent transistors 20 that do not contain passive elements 25 is narrower than the spacing between two adjacent transistors 20 that do contain passive elements 25.

[0077] For example, an input capacitor Cin and a ballast resistor element Rb are arranged in every other region between two adjacent transistors 20. In this case, a ballast resistor element Rb and an input capacitor Cin are shared by the two transistors 20 on both sides.

[0078] In this variation, the distribution density of the transistors 20 is reduced compared to a structure in which multiple transistors 20 are arranged close together without sandwiching passive components 25. Therefore, as in the first embodiment, excessive temperature rise of the transistors 20 can be suppressed. Furthermore, by having the passive components 25, such as the input capacitor Cin and the ballast resistor element Rb, arranged between two adjacent transistors 20 by the transistors on both sides, the top-view size of the semiconductor device can be further reduced.

[0079] [Second Embodiment]

[0080] Next, refer to Figure 5 , Figure 6A as well as Figure 6B The semiconductor device of the second embodiment will now be described. Hereinafter, the device will be compared with that described above. Figures 1 to 4D The description of the common structure of the semiconductor device in the first embodiment of the accompanying drawings is omitted.

[0081] Figure 5 This is a top view showing the positional relationship of the electrodes and wiring of the semiconductor device in the second embodiment. In the first embodiment, the passive element 25 ( ) is disposed between two adjacent transistors 20. Figure 1 The passive element 25 includes an input capacitor Cin and a ballast resistor element Rb, but in the second embodiment, the passive element 25 includes an emitter-base inter-electrode capacitor Ceb.

[0082] An electrode 32EB, comprising a second wiring layer, is disposed between the two transistors 20. A first base wiring layer 31B extends to the region overlapping with the electrode 32EB when viewed from above. An emitter-base capacitor Ceb is formed in the region where the base wiring 31B overlaps with the electrode 32EB.

[0083] The third-layer emitter wiring 33E is configured to overlap with multiple transistors 20 and multiple passive components 25. Figure 5 In the diagram, the third emitter wiring 33E is shown with a thicker outline than the second metal pattern. The third emitter wiring 33E is electrically connected to the emitter electrode 30E via the second emitter wiring 32E and the first emitter wiring 31E. That is, the third emitter wiring 33E interconnects the emitter electrodes 30E of different transistors 20 among the plurality of transistors 20. Furthermore, the third emitter wiring 33E is connected to the electrode 32EB of the emitter-base capacitor Ceb through an opening 43A in the interlayer insulating film disposed beneath it.

[0084] In the first embodiment ( Figure 1 In one embodiment, a high-frequency signal input wiring 32RF is arranged on one side of a column composed of multiple transistors 20, and a base bias wiring 31BB is arranged on the other side. In contrast, in the second embodiment, the high-frequency signal input wiring 32RF and the base bias wiring 31BB are arranged on the same side relative to the column composed of multiple transistors 20. The high-frequency signal input wiring 32RF is positioned closer to the transistors 20 than the base bias wiring 31BB.

[0085] The first-layer base wiring 31B, originating from transistor 20, protrudes across the high-frequency signal input wiring 32RF to the opposite side of 32RF. One end of the ballast resistor element Rb is connected to this protrusion. The other end of the ballast resistor element Rb is connected to the base bias wiring 31BB. An input capacitor Cin is formed in the overlapping area of ​​the first-layer base wiring 31B and the high-frequency signal input wiring 32RF.

[0086] Figure 6A This is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in the semiconductor device of the second embodiment. In the second embodiment, except for the first embodiment ( Figure 2A In addition to the structure of transistor 20, an emitter-base capacitor Ceb is connected between the base and emitter of transistor 20.

[0087] Figure 6B This is a cross-sectional view showing the connection relationship of a transistor 20, an input capacitor Cin, and an emitter-base capacitor Ceb in the semiconductor device of the second embodiment. The connection structure of transistor 20 and input capacitor Cin is the same as that of the first embodiment (…). Figure 2B The connection structure is the same as that in the first layer. In the second embodiment, in addition to the high-frequency signal input wiring 32RF and the emitter wiring 32E, the second wiring layer also includes an electrode 32EB. In top view, the electrode 32EB overlaps with the first layer base wiring 31B.

[0088] A third interlayer insulating film 43 is configured on the interlayer insulating film 42 to cover the second emitter wiring 32E, the high-frequency signal input wiring 32RF, and the electrode 32EB. The third emitter wiring 33E is disposed on the interlayer insulating film 43. The third emitter wiring 33E is connected to the electrode 32EB through an opening 43A in the interlayer insulating film 43. Furthermore, the third emitter wiring 33E is connected to the second emitter wiring 32E through other openings 43B in the interlayer insulating film 43.

[0089] The third interlayer insulating film 43 is equivalent to the interlayer insulating film 86. Figure 4D The third-layer emitter wiring 33E is equivalent to emitter pad 82E ( Figure 4D In the second embodiment, an interlayer insulating film 86 is shown. Figure 4D An example of a surface that has been flattened.

[0090] Next, the superior effects of the second embodiment will be explained.

[0091] Similar to the first embodiment, the second embodiment enables miniaturization of the semiconductor device and suppresses excessive temperature rise of the transistor 20. Furthermore, in the second embodiment, efficiency improvement is achieved through input waveform modulation by connecting the emitter-base inter-electrode capacitor Ceb.

[0092] Next, a variation of the second embodiment will be described.

[0093] In the second embodiment, the third layer emitter wiring 33E ( Figure 6B ) included in through Figure 4B The redistribution layer formed by the process shown can also be created using other methods. Figure 3A In the stage shown, a third interlayer insulating film 43 and a third emitter wiring 33E are formed on the component forming layer 202. In this case, emitter pads 82E are disposed on the third emitter wiring 33E. Figure 4D ).

[0094] In the second embodiment, the third emitter wiring 33E is electrically connected to the emitter electrode 30E via the second emitter wiring 32E and the first emitter wiring 31E. As a variation, the first emitter wiring 31E and the second emitter wiring 32E can be omitted, and the third emitter wiring 33E is directly connected to the emitter electrode 30E through an opening penetrating the three interlayer insulating films 41, 42, and 43. Alternatively, the first emitter wiring 31E can be omitted, and the second emitter wiring 32E can be directly connected to the emitter electrode 30E. Or, the second emitter wiring 32E can be omitted, and the third emitter wiring 33E can be directly connected to the first emitter wiring 31E.

[0095] [Third Embodiment]

[0096] Next, refer to Figure 7 , Figure 8A as well as Figure 8B The semiconductor device of the third embodiment will be described below. Hereinafter, the semiconductor device will be compared with that described above. Figure 5 , Figure 6A as well as Figure 6B The structure common to the semiconductor device in the second embodiment described herein is omitted.

[0097] Figure 7 This is a top view showing the positional relationship of the electrodes and wiring of the semiconductor device according to the third embodiment. In the second embodiment, the passive element 25 disposed between two adjacent transistors 20 ( Figure 5 The passive element 25 includes an emitter-base capacitor Ceb, but in the third embodiment, the passive element 25 includes a base-collector capacitor Cbc and a base-collector resistive element Rbc.

[0098] The base-collector inter-capacitor Cbc includes a lower electrode 31BC included in the first wiring layer, an upper electrode 32BC included in the second wiring layer, and a second interlayer insulating film 42 disposed between the two. Figure 8B When viewed from above, a portion of the upper electrode 32BC overlaps with a portion of the first layer base wiring 31B. In this overlapping area, the upper electrode 32BC is connected to the base wiring 31B through an opening 42A.

[0099] A portion of the lower electrode 31BC overlaps with one end of the base-collector inter-resistive element Rbc. The other end of the base-collector inter-resistive element Rbc overlaps with the conductor pattern 31X contained in the first wiring layer. The conductor pattern 30X is configured to overlap with the conductor pattern 31X when viewed from above. The conductor pattern 31X is connected to the conductor pattern 30X below it through the opening 41A.

[0100] Figure 8AThis is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in the semiconductor device of the third embodiment. In the third embodiment, in addition to the first embodiment ( Figure 2A In addition to the structure of the transistor 20, a base-collector capacitor Cbc and a base-collector resistor Rbc are connected in series between the base and collector of the transistor 20.

[0101] Figure 8B This is a cross-sectional view showing the connection relationship of a transistor 20, an input capacitor Cin, a base-collector capacitor Cbc, and a base-collector resistive element Rbc in the semiconductor device of the third embodiment. The connection structure of transistor 20 and input capacitor Cin is similar to that of the second embodiment (…). Figure 6B The connection structure is the same as that in ).

[0102] In the third embodiment, the adhesive layer 62 includes a metal region 62B in addition to the metal region 62A. Furthermore, the substrate semiconductor layer 50 includes a conductive region 50B in addition to the conductive region 50A. In top view, the conductive region 50B overlaps with the metal region 62B and the two are electrically connected. A conductor pattern 30X is disposed on the conductive region 50B. The conductor pattern 30X is electrically connected to the conductive region 50B.

[0103] In addition to the emitter wiring 31E and the base wiring 31B, the first wiring layer also includes a lower electrode 31BC and a conductor pattern 31X. The conductor pattern 31X is connected to the conductor pattern 30X through an opening 41A in the interlayer insulating film 41. Besides the first wiring layer, a base-collector inter-resistor element Rbc is disposed on the interlayer insulating film 41. No interlayer insulating film is disposed between the first wiring layer and the base-collector inter-resistor element Rbc. One end of the base-collector inter-resistor element Rbc overlaps with the lower electrode 31BC, and the other end overlaps with the conductor pattern 31X.

[0104] The base-collector inter-resistive element Rbc is electrically connected to the metal region 62B via conductor patterns 31X, 30X, and conductive region 50B. Metal region 62B is connected via... Figure 8B The area not shown in the cross-section, for example in Figure 7 The path connecting the conductor pattern 30X and the transistor 20 via the shortest path is continuous with the metal region 62A. Thus, the base-collector inter-resistive element Rbc is electrically connected to the collector layer 20C of the transistor 20.

[0105] In addition to the emitter wiring 32E and the high-frequency signal input wiring 32RF, the second wiring layer also includes an upper electrode 32BC. When viewed from above, the upper electrode 32BC overlaps with the lower electrode 31BC, and the upper electrode 32BC is connected to the base wiring 31B through an opening 42A provided in the interlayer insulating film 42.

[0106] Next, the superior effects of the third embodiment will be explained.

[0107] Similar to the second embodiment, the third embodiment enables miniaturization of the semiconductor device and suppresses excessive temperature rise of the transistor 20. Furthermore, in the third embodiment, by connecting the base-collector inter-electrode capacitor Cbc and the base-collector inter-electrode resistor Rbc, excellent effects of suppressing oscillations, improving stability, and reducing deformation can be achieved. Alternatively, the base-collector inter-electrode resistor Rbc can be omitted.

[0108] Next, a variation of the third embodiment will be described.

[0109] In the third embodiment, the conductor pattern 30X disposed on the substrate semiconductor layer 50 is electrically connected to the metal region 62B in the adhesive layer 62 via the conductive region 50B. As a variation, an opening can be formed in the substrate semiconductor layer 50, through which the conductor pattern 30X is connected to the metal region 62B. By adopting this structure, the resistance can be reduced.

[0110] [Fourth Embodiment]

[0111] Next, refer to Figure 9 , Figure 10A as well as Figure 10B The semiconductor device of the fourth embodiment will now be described. Hereinafter, the device will be compared with that described above. Figure 5 , Figure 6A as well as Figure 6B The structure common to the semiconductor device in the second embodiment described herein is omitted.

[0112] Figure 9 This is a top view showing the positional relationship of the electrodes and wiring of the semiconductor device according to the fourth embodiment. In the second embodiment, the passive element 25 disposed between two adjacent transistors 20 ( Figure 5 The passive element 25 includes an emitter-base capacitor Ceb, but in the fourth embodiment, the passive element 25 includes a collector-emitter capacitor Cce.

[0113] The collector-emitter capacitor Cce includes a lower electrode 31CE contained in the first wiring layer, an upper electrode 32CE contained in the second wiring layer, and an interlayer insulating film 42 between the two. Figure 10BThe third-layer emitter wiring 33E passes through the interlayer insulating film 43 disposed below it. Figure 10B The opening 43C is connected to the upper electrode 32CE.

[0114] The conductor pattern 30Y is configured to overlap a portion of the lower electrode 31CE when viewed from above. The lower electrode 31CE is separated from it by an interlayer insulating film 41. Figure 10B The opening 41B is connected to the conductor pattern 30Y.

[0115] Figure 10A This is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in the semiconductor device of the fourth embodiment. In the fourth embodiment, except for the first embodiment ( Figure 2A In addition to the structure of transistor 20, a collector-emitter capacitor Cce is connected between the collector and emitter of transistor 20.

[0116] Figure 10B This is a cross-sectional view showing the connection relationship of a transistor 20, an input capacitor Cin, and a collector-emitter capacitor Cce in the semiconductor device of the fourth embodiment. The connection structure of transistor 20 and input capacitor Cin is similar to that of the second embodiment (…). Figure 6B The connection structure is the same as that in ).

[0117] In addition to the metal region 62A, the adhesive layer 62 includes a metal region 62C. In addition to the conductive region 50A, the substrate semiconductor layer 50 includes a conductive region 50C. In top view, the conductive region 50C overlaps with the metal region 62C, and the two are electrically connected. A conductor pattern 30Y is disposed on the conductive region 50C. The conductor pattern 30Y is electrically connected to the conductive region 50C.

[0118] The first wiring layer includes a lower electrode 31CE in addition to the emitter wiring 31E and the base wiring 31B. The lower electrode 31CE is connected to the conductor pattern 30Y through an opening 41B in the interlayer insulating film 41. The second wiring layer includes an upper electrode 32CE in addition to the emitter wiring 32E and the high-frequency signal input wiring 32RF. When viewed from above, the upper electrode 32CE overlaps with the lower electrode 31CE, forming a collector-emitter capacitor Cce in the overlapping area.

[0119] The third emitter wiring 33E is connected to the upper electrode 32CE through an opening 43C in the third interlayer insulating film 43. The emitter layer 20E of the transistor 20 is electrically connected to the upper electrode 32CE of the collector-emitter capacitor Cce through the third emitter wiring 33E.

[0120] Metal region 62C via in Figure 10BThe area not shown in the cross-section, for example Figure 9 The path connecting the conductor pattern 30Y and the transistor 20 via the shortest path is continuous with the metal region 62A. Thus, the lower electrode 31CE of the collector-emitter capacitor Cce is electrically connected to the collector layer 20C of the transistor 20.

[0121] Next, the superior effects of the fourth embodiment will be explained.

[0122] Similar to the second embodiment, the fourth embodiment enables miniaturization of the semiconductor device and suppresses excessive temperature rise of the transistor 20. Furthermore, in the fourth embodiment, by connecting a collector-emitter capacitor Cce, oscillations can be suppressed, improving stability.

[0123] Next, a variation of the fourth embodiment will be described.

[0124] In the fourth embodiment, the conductor pattern 30Y disposed on the substrate semiconductor layer 50 is electrically connected to the metal region 62C in the adhesive layer 62 via the conductive region 50C. As a variation, an opening may be formed in the substrate semiconductor layer 50, through which the conductor pattern 30Y is connected to the metal region 62C. By employing this structure, resistance can be reduced.

[0125] [Fifth Embodiment]

[0126] Next, refer to Figure 11 , Figure 12A as well as Figure 12B The semiconductor device of the fifth embodiment will now be described. Hereinafter, the device will be compared with that described above. Figure 5 , Figure 6A as well as Figure 6B The structure common to the semiconductor device in the second embodiment described herein is omitted.

[0127] Figure 11 This is a top view showing the positional relationship of the electrodes and wiring of the semiconductor device according to the fifth embodiment. In the second embodiment, the passive element 25 disposed between two adjacent transistors 20 ( Figure 5 The first embodiment includes an emitter-base capacitor Ceb, but in the fifth embodiment, the passive element 25 includes a capacitor Ch and an inductor Lh that constitute the higher harmonic termination circuit 28. The capacitor Ch and the inductor Lh are connected in series.

[0128] The inductor Lh is formed by a tortuous wiring 32LH contained in the second wiring layer. The third emitter wiring 33E is formed by an interlayer insulating film 43 disposed below it. Figure 12BThe opening 43D of the wiring 32LH is connected to one end of the wiring 32LH. In top view, the other end of the wiring 32LH overlaps with the lower electrode 31CH contained in the first wiring layer. This overlapping area forms the capacitor Ch.

[0129] The conductor pattern 30Z is configured to overlap a portion of the lower electrode 31CH. The lower electrode 31CH is separated from it by an interlayer insulating film 41 disposed below it. Figure 12B The opening 41C is connected to the conductor pattern 30Z.

[0130] Figure 12A This is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in the semiconductor device of the fifth embodiment. In the fifth embodiment, except for the first embodiment ( Figure 2A In addition to the structure of the transistor 20, a capacitor Ch and an inductor Lh, which constitute the high-order harmonic termination circuit 28, are connected in series between the collector and the ground line (emitter) of the transistor 20.

[0131] Figure 12B This is a cross-sectional view showing the connection relationships of a transistor 20, an input capacitor Cin, an inductor Lh, and a capacitor Ch in the semiconductor device of the fifth embodiment. The connection structure of transistor 20 and input capacitor Cin is similar to that of the second embodiment (…). Figure 6B The connection structure is the same as that in ).

[0132] In addition to the metal region 62A, the adhesive layer 62 includes a metal region 62D. In addition to the conductive region 50A, the substrate semiconductor layer 50 includes a conductive region 50D. In top view, the conductive region 50D overlaps with the metal region 62D, and the two are electrically connected. A conductor pattern 30Z is disposed on the conductive region 50D. The conductor pattern 30Z is electrically connected to the conductive region 50D.

[0133] The first wiring layer includes the emitter wiring 31E, the base wiring 31B, and a lower electrode 31CH. The lower electrode 31CH is connected to the conductor pattern 30Z through an opening 41C in the interlayer insulating film 41. The second wiring layer includes the emitter wiring 32E, the high-frequency signal input wiring 32RF, and wiring 32LH. In top view, one end of wiring 32LH overlaps with the lower electrode 31CH, forming a capacitor Ch in the overlapping area. Wiring 32LH functions as an inductor Lh.

[0134] The third-layer emitter wiring 33E is connected to the other end of wiring 32LH through an opening 43D in the third-layer interlayer insulating film 43. Through the third-layer emitter wiring 33E, the emitter layer 20E of transistor 20 is electrically connected to inductor Lh.

[0135] Metal region 62D via in Figure 12B The area not shown in the cross-section, for example Figure 11 The path connecting the conductor pattern 30Z and the transistor 20 via the shortest path is continuous with the metal region 62A. Thus, the lower electrode 31CH of the capacitor Ch is electrically connected to the collector layer 20C of the transistor 20.

[0136] Next, the superior effects of the fifth embodiment will be explained.

[0137] Similar to the second embodiment, the fifth embodiment enables miniaturization of the semiconductor device and suppresses excessive temperature rise of the transistor 20. Furthermore, in the fifth embodiment, each of the plurality of transistors 20 is connected to a high-order harmonic termination circuit 28 composed of a capacitor Ch and an inductor Lh. The high-order harmonic termination circuit 28 is positioned near the transistor 20. Therefore, the influence of parasitic inductance can be reduced, improving the effect of high-order harmonic termination.

[0138] Next, a variation of the fifth embodiment will be described.

[0139] In the fifth embodiment, the conductor pattern 30Z disposed on the substrate semiconductor layer 50 is electrically connected to the metal region 62D in the adhesive layer 62 via the conductive region 50D. As a variation, an opening may be formed in the substrate semiconductor layer 50, through which the conductor pattern 30Z is connected to the metal region 62D. By employing this structure, resistance can be reduced.

[0140] [Sixth Embodiment]

[0141] Next, refer to Figure 13 , Figure 14A as well as Figure 14B The semiconductor device of the sixth embodiment will be described below. Hereinafter, the semiconductor device will be compared with that described above. Figure 5 , Figure 6A as well as Figure 6B The structure common to the semiconductor device in the second embodiment described herein is omitted.

[0142] Figure 13 This is a top view showing the positional relationship of the electrodes and wiring of the semiconductor device according to the sixth embodiment. In the second embodiment, the passive element 25 disposed between two adjacent transistors 20 ( Figure 5 The passive element 25 includes an emitter-base inter-electrode capacitor Ceb, but in the sixth embodiment, the passive element 25 includes an ESD (electrostatic discharge) protection diode 70.

[0143] The conductor pattern 31D contained in the first wiring layer and the conductor pattern 32D contained in the second wiring layer are configured to substantially overlap with the upper electrode 30D of the ESD protection diode 70. The third emitter wiring 33E is connected to the conductor pattern 32D through an opening in the interlayer insulating film disposed below it.

[0144] Figure 14A This is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in the semiconductor device of the sixth embodiment. In the sixth embodiment, except for the first embodiment ( Figure 2A In addition to the structure of the transistor 20, an ESD protection diode 70 is connected between the collector and the ground line (emitter) of the transistor 20 with the polarity from the ground line toward the collector as positive.

[0145] Figure 14B This is a cross-sectional view showing the connection relationship of a transistor 20, an input capacitor Cin, and an ESD protection diode 70 in the semiconductor device of the sixth embodiment. The connection structure of transistor 20 and input capacitor Cin is similar to that of the second embodiment (…). Figure 6B The connection structure is the same as that in ).

[0146] In addition to the metal region 62A, the adhesive layer 62 includes a metal region 62E. In addition to the conductive region 50A, the substrate semiconductor layer 50 includes a conductive region 50E. In top view, the conductive region 50E overlaps with the metal region 62E and the two are electrically connected. An ESD protection diode 70 is disposed on the conductive region 50E. The ESD protection diode 70 includes a cathode layer 70C connected to the conductive region 50E and an anode layer 70A disposed on the cathode layer 70C. The cathode layer 70C is formed of the same semiconductor material as the collector layer 20C of the transistor 20, such as n-type GaAs, and the anode layer 70A is formed of the same semiconductor material as the base layer 20B of the transistor 20, such as p-type GaAs.

[0147] An upper electrode 30D is disposed on the anode layer 70A. The upper electrode 30D is electrically connected to the anode layer 70A. The third emitter wiring 33E is electrically connected to the upper electrode 30D via the conductor pattern 32D included in the second wiring layer and the conductor pattern 31D included in the first wiring layer. The anode layer 70A of the ESD protection diode 70 is electrically connected to the emitter layer 20E of the transistor 20 via the emitter wiring 33E.

[0148] The cathode layer 70C is electrically connected to the metal region 62E via the conductive region 50E. The upper electrode 30D and the metal region 62E function as the anode and cathode electrodes of the ESD protection diode 70, respectively.

[0149] Metal region 62E via in Figure 14BThe area not shown in the cross-section, for example Figure 13 The path connecting the ESD protection diode 70 and the transistor 20 via the shortest path is continuous with the metal region 62A. Thus, the cathode layer 70C of the ESD protection diode 70 is electrically connected to the collector layer 20C of the transistor 20.

[0150] Next, the superior effects of the sixth embodiment will be explained.

[0151] Similar to the second embodiment, the sixth embodiment enables miniaturization of the semiconductor device and suppresses excessive temperature rise of the transistor 20. Furthermore, in the sixth embodiment, ESD protection can be provided for each of the plurality of transistors 20.

[0152] Next, refer to Figure 15 A variation of the sixth embodiment will be described.

[0153] Figure 15 This diagram shows the cross-sectional structure of a transistor 20, an input capacitor Cin, and an ESD protection diode 70 in a modified semiconductor device according to the sixth embodiment. In the sixth embodiment ( Figure 14B In the diagram, viewed from above, the third-layer emitter wiring 33E extends from the area overlapping with transistor 20 to the area overlapping with ESD protection diode 70, and the two are connected via the third-layer emitter wiring 33E. In contrast, in... Figure 15 In the variant shown, the second emitter wiring 32E extends from the region overlapping with transistor 20 when viewed from above, through the region not overlapping with high-frequency signal input wiring 32RF, to the region overlapping with ESD protection diode 70. According to this structure, a third emitter wiring 33E is not necessarily required, allowing for a two-layer wiring configuration.

[0154] Next, refer to Figure 16A as well as Figure 16B Another variation of the sixth embodiment will be described. Figure 16A as well as Figure 16B This is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in a semiconductor device of another variation of the sixth embodiment.

[0155] exist Figure 16A In the variant shown, two ESD protection diodes 70 are connected in series. Viewed from above, the two ESD protection diodes 70 are positioned between two adjacent transistors 20. Multiple ESD protection diodes 70 can also be connected as needed.

[0156] exist Figure 16BIn the illustrated variation, a plurality of protection diodes 71 are connected in series with polarity from the collector to the ground line as positive. Viewed from above, the plurality of protection diodes 71 are arranged between two adjacent transistors 20. The number of protection diodes 71 is determined such that the series circuit of the plurality of protection diodes 71 conducts when a voltage exceeding the upper limit of the permissible voltage is generated between the collector and emitter of the transistor 20.

[0157] [Seventh Embodiment]

[0158] Next, refer to Figure 17A as well as Figure 17B The semiconductor device of the seventh embodiment will be described below. Hereinafter, the semiconductor device of the fifth embodiment (…) Figure 11 , Figure 12A , Figure 12B The shared structure is omitted.

[0159] Figure 17A This is an equivalent circuit diagram of a transistor 20 and passive components connected thereto in the semiconductor device of the seventh embodiment. In the fifth embodiment ( Figure 12A In the first embodiment, a high-order harmonic terminating circuit 28 is connected between the collector of transistor 20 and ground. However, in the seventh embodiment, two high-order harmonic terminating circuits 28 are connected in parallel. A switching element 64 is connected in series with one of the high-order harmonic terminating circuits 28. The control circuit 65 controls the switching element 64 to turn on and off.

[0160] Figure 17B This is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment. The first component 60 includes a substrate 61, a plurality of switching elements 64, a multilayer wiring structure 63 disposed on the substrate 61, an adhesive layer 62 disposed on the multilayer wiring structure 63, and a control circuit 65. Figure 17A A plurality of switching elements 64 are formed on the surface layer of the substrate 61. The switching elements 64 are, for example, MOSFETs. Figure 17B The rectangle representing the switching element 64 extends into the interior of the substrate 61, while the remaining portion protrudes from the surface of the substrate 61. For example, the source and drain of the MOSFET are disposed in a very shallow region below the surface of the substrate 61, and the gate electrode is disposed on the surface of the substrate 61.

[0161] Control circuit 65 ( Figure 17A It includes transistors formed on the surface of substrate 61 and wiring within multilayer wiring structure 63.

[0162] The second component 68 includes a substrate semiconductor layer 50, a plurality of transistors 20 disposed on the substrate semiconductor layer 50, and a high-order harmonic termination circuit 28. Each high-order harmonic termination circuit 28 is disposed between two adjacent transistors 20. The substrate semiconductor layer 50 includes a plurality of conductive regions 50A and 50F. Metal regions 62A and 62F are disposed within the adhesive layer 62 corresponding to each of the plurality of conductive regions 50A and 50F. Furthermore, conductive components 63A and 63F, consisting of vias and inner layer pads, are disposed within the multilayer wiring structure 63 corresponding to each of the plurality of metal regions 62A and 62F.

[0163] Transistor 20 is connected to switching element 64 via conductive region 50A, metal region 62A, and conductive component 63A. High-order harmonic terminating circuit 28 is connected to switching element 64 via conductive region 50F, metal region 62F, and conductive component 63F.

[0164] Next, the superior effects of the seventh embodiment will be explained.

[0165] Similar to the fifth embodiment, the seventh embodiment enables miniaturization of the semiconductor device and suppresses excessive temperature rise of the transistor 20. Furthermore, it reduces the impact of parasitic inductance and improves the effectiveness of high-order harmonic termination. In the seventh embodiment, by switching the switching element 64 on and off, the frequency of the high-order harmonic to be terminated can be selected.

[0166] Next, a variation of the seventh embodiment will be described.

[0167] Although in the seventh embodiment two higher harmonic termination circuits 28 are connected in parallel between the collector and ground of transistor 20, three or more higher harmonic termination circuits 28 may also be connected in parallel. Furthermore, although in the seventh embodiment one of the two higher harmonic termination circuits 28 is connected to a switching element 64, multiple higher harmonic termination circuits 28 may each be connected to a switching element 64.

[0168] Alternatively, all of the higher harmonic terminating circuits 28 can be configured between two adjacent transistors 20, or only a portion of the higher harmonic terminating circuits 28 can be configured between two adjacent transistors 20.

[0169] Although in the seventh embodiment, the object controlled by the switching element 64 to turn on and off is the high-order harmonic terminal circuit 28, the object to be controlled can also be other circuits composed of passive components.

[0170] The above embodiments are illustrative examples, and of course, partial substitutions or combinations of the structures shown in different embodiments are possible. The same effects resulting from the same structure in multiple embodiments are not mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, it will be apparent to those skilled in the art that various changes, improvements, combinations, etc., are possible.

Claims

1. A semiconductor device comprising: substrate; Multiple transistors are arranged in one direction on one side of the substrate and connected in parallel. Each of the multiple transistors includes a collector layer, a base layer, and an emitter layer sequentially stacked starting from the substrate side. At least one passive element is disposed in at least one region between two adjacent transistors of the plurality of transistors. The semiconductor device further includes a collector electrode disposed between the collector layer of each of the plurality of transistors and the substrate, and electrically connected to the collector layer.

2. The semiconductor device according to claim 1, wherein, The aforementioned passive components each include a first capacitor, and one electrode of the first capacitor is electrically connected to the base layer of one of the two transistors disposed on both sides.

3. The semiconductor device according to claim 1, wherein, The aforementioned passive components each include a first resistive element, one end of which is electrically connected to the base layer of one of the two transistors disposed on both sides.

4. The semiconductor device according to claim 2, wherein, The aforementioned passive components each include a first resistive element, one end of which is electrically connected to the base layer of one of the two transistors disposed on both sides.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The passive components mentioned above each include a second capacitor and a second resistor connected in series. The series circuit of the second capacitor and the second resistor is electrically connected between the base layer and the collector layer of one of the two transistors disposed on both sides.

6. The semiconductor device according to any one of claims 1 to 4, wherein, The aforementioned passive components each include a third capacitor, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

7. The semiconductor device according to claim 5, wherein, The aforementioned passive components each include a third capacitor, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

8. The semiconductor device according to any one of claims 1 to 4, wherein, The passive components mentioned above each include a fourth capacitor and a fourth inductor connected in series. The series circuit of the fourth capacitor and the fourth inductor is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

9. The semiconductor device according to claim 5, wherein, The passive components mentioned above each include a fourth capacitor and a fourth inductor connected in series. The series circuit of the fourth capacitor and the fourth inductor is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

10. The semiconductor device according to any one of claims 1 to 4, wherein, It also includes an interlayer insulating film that covers the areas of the substrate where the plurality of transistors are not disposed, as well as the plurality of transistors themselves. The aforementioned passive components are disposed on the aforementioned interlayer insulating film.

11. The semiconductor device according to claim 5, wherein, It also includes an interlayer insulating film that covers the areas of the substrate where the plurality of transistors are not disposed, as well as the plurality of transistors themselves. The aforementioned passive components are disposed on the aforementioned interlayer insulating film.

12. The semiconductor device according to claim 6, wherein, It also includes an interlayer insulating film that covers the areas of the substrate where the plurality of transistors are not disposed, as well as the plurality of transistors themselves. The aforementioned passive components are disposed on the aforementioned interlayer insulating film.

13. The semiconductor device according to claim 7, wherein, It also includes an interlayer insulating film that covers the areas of the substrate where the plurality of transistors are not disposed, as well as the plurality of transistors themselves. The aforementioned passive components are disposed on the aforementioned interlayer insulating film.

14. The semiconductor device according to claim 8, wherein, It also includes an interlayer insulating film that covers the areas of the substrate where the plurality of transistors are not disposed, as well as the plurality of transistors themselves. The aforementioned passive components are disposed on the aforementioned interlayer insulating film.

15. The semiconductor device according to claim 9, wherein, It also includes an interlayer insulating film that covers the areas of the substrate where the plurality of transistors are not disposed, as well as the plurality of transistors themselves. The aforementioned passive components are disposed on the aforementioned interlayer insulating film.

16. The semiconductor device according to any one of claims 1 to 4, wherein, The aforementioned passive components each include a first diode, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

17. The semiconductor device according to claim 5, wherein, The aforementioned passive components each include a first diode, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

18. The semiconductor device according to claim 6, wherein, The aforementioned passive components each include a first diode, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

19. The semiconductor device according to claim 7, wherein, The aforementioned passive components each include a first diode, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

20. The semiconductor device according to claim 8, wherein, The aforementioned passive components each include a first diode, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

21. The semiconductor device according to claim 9, wherein, The aforementioned passive components each include a first diode, which is electrically connected between the collector layer and the emitter layer of one of the two transistors disposed on both sides.

22. The semiconductor device according to any one of claims 1 to 4, wherein, The substrate comprises a semiconductor material having a higher thermal conductivity than the semiconductor material forming the collector layer, base layer, and emitter layer of the plurality of transistors.

23. The semiconductor device according to any one of claims 1 to 4, wherein, It also has: Multiple switching elements are disposed on the surface of the substrate on which the multiple transistors are arranged, with at least one element corresponding to each of the multiple transistors; and A multilayer wiring structure is configured to cover the plurality of switching elements between the substrate and the collector electrode. The aforementioned multilayer wiring structure includes conductive components, which are connected via corresponding switching elements to the collector electrode of each of the plurality of transistors and the at least one passive component.

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