Semiconductor devices and methods

Abstract

The present disclosure relates to semiconductor devices and methods. In an embodiment, a device includes: a first semiconductor strip, over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip, over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a dielectric fin disposed between the first semiconductor fin and the second semiconductor fin, the dielectric fin including a void; and an isolation region disposed between the dielectric fin and the substrate, the isolation region extending along a sidewall of the dielectric fin, a sidewall of the first semiconductor fin, and a sidewall of the second semiconductor fin.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a first semiconductor strip on a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip on the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, the width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including gaps; and a gate structure extending along the first channel region, along the second channel region, and along the top surface and sidewalls of the dielectric strip.

[0006] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a first semiconductor fin and a second semiconductor fin, each extending along a first direction remote from a substrate; forming an insulating material between the first semiconductor fin and the second semiconductor fin, the insulating material having a groove, the width of the groove decreasing along the first direction; depositing a first dielectric layer in the groove to form a void, the void including a portion of the groove not filled by the first dielectric layer; and recessing the insulating material to form a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin including the void and a remaining portion of the first dielectric layer in the groove, the remaining portion of the first dielectric layer surrounding the void. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B and Figure 15C This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 16 This is a cross-sectional view of a FinFET according to some embodiments.

[0011] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0012] Figure 25A and Figure 25B This is a cross-sectional view of a FinFET according to some other embodiments.

[0013] Figure 26 and Figure 27 This is a cross-sectional view of a FinFET according to some other embodiments.

[0014] Figure 28 This is a cross-sectional view of an NSFET according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "below," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0017] According to some embodiments, dummy fins are formed between the active fins of the FinFET. The dummy fins have a similar height to the active fins and can help reduce pattern loading effects during FinFET formation. Furthermore, the dummy fins are formed to include gaps, which can help increase electrical isolation between adjacent FinFETs.

[0018] Figure 1 A simplified example of a FinFET (Fin Field-Effect Transistor) in a three-dimensional view according to some embodiments is shown. For clarity of illustration, certain other features of the FinFET (discussed below) are omitted. The FinFET shown can be electrically coupled in one manner to operate, for example, as a single transistor or multiple transistors (e.g., four transistors).

[0019] The FinFET includes a fin 52 extending from a substrate 50. Shallow trench isolation (STI) regions 66 are disposed on the substrate 50, and the fin 52 protrudes over and between adjacent STI regions 66. Although the isolation regions 66 are described / shown as separate from the substrate 50, as used herein, the term "substrate" can be used to refer to a semiconductor substrate alone or a semiconductor substrate including the isolation regions. Additionally, although the fin 52 is shown as a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fin 52 refers to the portion extending between adjacent STI regions 66.

[0020] Gate structure 110 is located above the channel region of fin 52. Gate structure 110 includes gate dielectric 112 and gate electrode 114. Gate dielectric 112 is located along the sidewall of fin 52 and above its top surface, and gate electrode 114 is located above gate dielectric 112. Source / drain regions 98 are disposed on opposite sides of fin 52 relative to gate dielectric 112 and gate electrode 114. Gate spacer 96 separates source / drain regions 98 from gate structure 110. In embodiments forming multiple transistors, source / drain regions 98 may be shared among various transistors. In embodiments where a transistor is formed by multiple fins 52, adjacent source / drain regions 98 may be electrically coupled, for example, by merging source / drain regions 98 using epitaxial growth, or by coupling source / drain regions 98 to the same source / drain contact. One or more interlayer dielectric (ILD) layers (discussed further below) are formed over the source / drain region 98 and / or the gate electrode 114, and contacts to the source / drain region 98 and the gate electrode 114 are formed through the ILD layers (discussed further below).

[0021] Figure 1Several reference cross-sections are further shown. Cross-section AA is along the longitudinal axis of gate electrode 114. Cross-sections B / CB / C are perpendicular to cross-section AA and along the longitudinal axis of fin 52. Cross-section DD is parallel to cross-section AA and extends through the source / drain region 98 of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0022] Some embodiments discussed herein are described in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices (e.g., planar FETs).

[0023] Figures 2 to 15C This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A It shows Figure 1 The reference cross-section AA shown is different in that it has multiple fins / FinFETs. Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15B It shows Figure 1 The reference cross-sections B / CB / C shown are different in that they have multiple fins / FinFETs. Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C and Figure 15C It shows Figure 8 The reference cross-section CC shown is different in that it has multiple fins / FinFETs. Figure 9D It shows Figure 1 The reference cross-section DD shown is different in that it has multiple fins / FinFETs.

[0024] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0025] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, or an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, or a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P.

[0026] Then, fins 52 are formed in the substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof, and can be performed using a mask 54 patterned with fins 52. The etching can be anisotropic.

[0027] The fins can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fin 52. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask 54 (or other layer) may be retained on the fin 52.

[0028] According to some embodiments, some regions of substrate 50 are not patterned to have fins 52. For example, invalid regions 50R of substrate 50 are not covered by mask 54 and do not include fins. Invalid regions 50R can be any region of substrate 50 where devices (e.g., FinFETs) are not desired or not formed. In the illustrated embodiment, invalid regions 50R are part of p-type regions 50P and are disposed between adjacent p-type FinFETs in p-type regions 50P. In another embodiment (discussed further below), invalid regions 50R are part of n-type regions 50N and are disposed between adjacent n-type FinFETs in n-type regions 50N. In yet another embodiment (discussed further below), both n-type regions 50N and p-type regions 50P include invalid regions 50R. The width of invalid regions 50R can be greater than the spacing between fins 52 outside invalid regions 50R. For example, the fins 52 outside the invalid region 50R can be spaced apart by a distance D1, which can be in the range of about 10 nm to about 50 nm, while the fins 52 bordering the invalid region 50R can be spaced apart by a distance D2, which can be about 2 to about 3 times the distance D1.

[0029] As discussed further below, dummy fins are formed in the invalid region 50R to help reduce patterning effects in subsequent processing. Unlike fins 52, which are used to form FinFETs and are also referred to as active fins or semiconductor fins, dummy fins are not used to form FinFETs and are also referred to as invalid fins or dielectric fins. In addition to helping reduce patterning effects in subsequent processing, dummy fins are also formed to have a high relative permittivity and therefore also help to electrically isolate adjacent devices (e.g., adjacent FinFETs) from each other. A single dummy fin is shown formed in a single invalid region 50R; however, it should be understood that multiple dummy fins can be formed in the same invalid region 50R, and it should also be understood that multiple invalid regions 50R can be formed.

[0030] exist Figure 3In this embodiment, one or more layers of insulating material 64 are formed on the substrate 50 and between adjacent effective fins 52. The insulating material 64 includes oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and combinations thereof, and can be formed by chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, followed by post-curing to convert it into another material, such as oxide), atomic layer deposition (ALD), and combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 64 includes a liner 64A on the surfaces of the substrate 50 and the effective fins 52, and a filler material 64B on the liner 64A. The liner 64A can be amorphous silicon, silicon oxide, silicon nitride, etc., formed by an ALD process, and the filler material 64B can be silicon oxide formed by an FCVD process. In another embodiment, a single layer of insulating material 64 is formed. Once the insulating material is formed, an annealing process can be performed. The annealing process can be performed in an environment containing H2 or O2. Liner 64A can be oxidized by the annealing process so that, after annealing, liner 64A is a material similar to filler material 64B. In embodiments, insulating material 64 is formed such that excess insulating material 64 covers the effective fin 52 or mask 54 (if present).

[0031] The insulating material 64 has a varying thickness across the entire substrate 50 and may not fill the gaps between all effective fins 52. Specifically, this is because the spacing distance D2 is greater than the spacing distance D1 (see...). Figure 2 The insulating material 64 may not completely fill the ineffective region 50R. For example, the distribution volume of the insulating material 64 may be insufficient to completely fill the ineffective region 50R. Alternatively, the insulating material 64 in the ineffective region 50R may conformally liner the substrate 50 and the sidewalls of the effective fin 52 bordering the ineffective region 50R. The portion of the insulating material 64 in the ineffective region 50R thus includes a groove 56 between the effective fin 52 bordering the ineffective region 50R. The shape and dimensions of the groove 56 will be described below regarding... Figure 5 Further discussion.

[0032] exist Figure 4In this process, a dielectric layer 58 is formed on an insulating material 64. The dielectric layer 58 is lined within a recess 56. The dielectric layer 58 may be formed of silicon oxynitride, silicon carbonitride, silicon nitride, etc., and may be formed by ALD, CVD, etc. The dielectric layer 58 is formed of a material having high etch selectivity relative to the etching of the insulating material 64. Furthermore, the material of the dielectric layer 58 has a larger relative permittivity than one or more materials of the insulating material 64. For example, the insulating material 64 may be formed of a material with a relative permittivity in the range of about 10 to about 12, and the dielectric layer 58 may be formed of a material with a relative permittivity in the range of about 4 to about 7. In some embodiments, the dielectric layer 58 is silicon oxynitride formed by ALD. In another embodiment, the material of the dielectric layer 58 has a smaller relative permittivity than one or more materials of the insulating material 64.

[0033] Figure 5 yes Figure 4 A detailed view of the invalid region 50R is shown. The shape and dimensions of the groove 56 are shown more clearly. Due to the method of forming the insulating material 64, the groove 56 has a reentrant profile shape, wherein the width W1 of the groove 56 decreases along the direction D3 extending from the bottom of the filler material 64B to the top of the filler material 64B. In other words, the width W1 at the bottom of the groove 56 is greater than the width W1 at the top of the groove 56. For example, the width W1 can be in the range of about 10 nm to about 30 nm, and the width W1 at the bottom of the groove 56 can be about 0% to about 30% greater than the width W1 at the top of the groove 56. The groove 56 can be formed as a reentrant profile shape when the filler material 64B is silicon oxide formed by an FCVD process.

[0034] In other embodiments, the filler material 64B is formed by depositing amorphous silicon using CVD and then oxidizing the amorphous silicon to form silicon oxide. The oxidation can be performed using a plasma oxidation process, where the oxidation occurs directionally. Thus, the upper portion 64B of the filler material 64B... U The lower part of 64B is more than the filler material 64B L More is oxidized. In other words, when plasma oxidation is used, the oxygen concentration of filler material 64B increases throughout filler material 64B in direction D3, extending from the bottom to the top of filler material 64B. When silicon is oxidized, the volume of silicon increases. This is because the upper part of filler material 64B... U The lower part of 64B is more than the filler material 64B L It is oxidized more, so oxidation causes the upper part of the 64B filler material to oxidize. U The volume ratio of the lower part of the filler material 64B is 64B LThe volume increases further. Therefore, after oxidation, the width W1 at the bottom of the groove 56 is greater than the width W1 at the top of the groove 56. In some embodiments, before oxidation, the width W1 at the bottom of the groove 56 is less than or equal to the width W1 at the top of the groove 56, and after oxidation, the width W1 at the bottom of the groove 56 is greater than the width W1 at the top of the groove 56.

[0035] Because the groove 56 has a recessed profile shape, shrinkage occurs at the top of the groove 56 during the deposition of the dielectric layer 58. In some embodiments, insulating material 64 is deposited until a void 60 is formed. The void 60 includes the portion of the groove 56 that is not filled by the dielectric layer 58. Depending on the processing conditions during the deposition of the dielectric layer 58, the void 60 may be in a vacuum or filled with a gas (e.g., air). The void 60 has a profile shape similar to the groove 56, such as a recessed profile shape. The shape and dimensions of the void 60 will be described below regarding... Figure 16 Further discussion.

[0036] exist Figure 6 In this process, a removal process is applied to the dielectric layer 58 and the insulating material 64 to remove excess portions of the dielectric layer 58 and the insulating material 64 above the effective fin 52. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be used. This removal process forms dummy fins 62, which include the remaining portion of the dielectric layer 58 in the groove 56 (see [link to documentation]). Figure 5 The dummy fin 62 is a dielectric strip. After the removal process, some portions of the dielectric layer 58 remain above the void 60, so that the void 60 is not destroyed. The dummy fin 62 is disposed between the effective fins 52 that are adjacent to the invalid region 50R. In the illustrated embodiment, the dummy fin 62 is disposed between the effective fins 52 in the p-type region 50P. The planarization process exposes the effective fins 52 and the dummy fin 62, such that the top surfaces of the effective fins 52, the dummy fin 62, and the insulating material 64 are coplanar after the planarization process is completed. In embodiments where the mask 54 remains on the effective fins 52, the planarization process may expose or remove the mask 54, such that the top surfaces of the mask 54 or the effective fins 52, the dummy fin 62, and the insulating material 64 are coplanar after the planarization process is completed.

[0037] The dummy fin 62 is equidistant from the adjacent active fin 52, and the top surfaces of both the dummy fin 62 and the active fin 52 are set at the same distance from the substrate 50. In this way, the dummy fin 62 helps to reduce pattern loading effects in subsequent processes (e.g., subsequent CMP or etching processes). The shape and dimensions of the dummy fin 62 will be discussed below. Figure 16Further discussion. The dummy fin 62 includes a dielectric layer 58 and a void 60, wherein the dielectric layer 58 surrounds the void 60. In this embodiment, the void 60 is continuously surrounded by the dielectric layer 58. The void 60 is filled with air or is in a vacuum, and therefore has a low relative permittivity, for example, a relative permittivity of about 1. In some embodiments, the relative permittivity of the void 60 is less than the relative permittivity of the dielectric layer 58 and the relative permittivity of the STI region 66. Forming the void 60 reduces the total effective conductance of the dummy fin 62. The dummy fin 62 thus provides a greater amount of electrical isolation than a dummy fin formed of a semiconductor material or a single dielectric material. Thus, in addition to helping to reduce pattern loading effects in subsequent processing, the dummy fin 62 also helps to electrically isolate adjacent effective fins 52 (and the FinFETs they generate) from each other. Specifically, the dielectric layer 58 and the void 60 serve as the dielectric medium for a parasitic capacitor network disposed between the effective fins 52 bordering the ineffective region 50R. Forming a gap 60 can help reduce the effective capacitance of the capacitor network by about 10% to about 14%. Therefore, the parasitic capacitance of the resulting FinFET can be reduced, thereby improving the performance of the FinFET.

[0038] exist Figure 7 In this process, the insulating material 64 is recessed to form STI regions 66. The insulating material 64 is recessed such that the upper portions of the active fins 52 and dummy fins 62 protrude above and between adjacent STI regions 66. Further, the top surface of the STI region 66 may have a flat surface (as shown), a convex surface, a concave surface (e.g., disc-shaped), or a combination thereof. The top surface of the STI region 66 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 66 can be recessed using an acceptable etching process, such as an etching process selectively etching one or more materials of the insulating material 64. For example, it can be removed using an oxide, for example, dilute hydrofluoric acid (dHF). The etching process selectively etches one or more materials of the insulating material 64 at a faster rate than etching one or more materials of the active fins 52 and dummy fins 62. For example, the materials of the dielectric layer 58 (e.g., silicon oxynitride) and the insulating material 64 (e.g., silicon and silicon oxide) can have an etch selectivity of about 20:1 to about 1000:1 relative to the etching process. Therefore, the dielectric layer 58 can be protected from damage during the formation of the dummy fin 62. The dummy fin 62 helps to reduce the pattern loading effect during the recess, and thus, the portion of the insulating material 64 surrounding the dummy fin 62 is recessed by the same amount as the portion of the insulating material 64 surrounding the active fin 52.

[0039] about Figures 2 to 7The described process is merely one example of how the effective fin 52 can be formed. In some embodiments, the fin 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the homoethelic structure protrudes from the dielectric layer to form the effective fin 52. Furthermore, in some embodiments, heteroethelic structures can be used for the effective fin 52. For example, Figure 7 The effective fin 52 can be recessed, and a different material can be epitaxially grown on the recessed effective fin 52. In such an embodiment, the effective fin 52 comprises a recessed material and an epitaxially grown material disposed on the recessed material. In a further embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the effective fin 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be in-situ doped during growth, which avoids prior and subsequent implantation, but in-situ doping and implantation doping can be used together.

[0040] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., the PMOS region) in the n-type region 50N (e.g., the NMOS region). In various embodiments, the upper portion of the effective fin 52 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0041] Furthermore, in Figure 7 In this process, suitable wells (not shown) may be formed in the effective fin 52 and / or the substrate 50. In some embodiments, a p-type well may be formed in an n-type region 50N, and an n-type well may be formed in a p-type region 50P. In some embodiments, either a p-type well or an n-type well may be formed in both the n-type region 50N and the p-type region 50P.

[0042] In embodiments with different well types, photoresist and / or other masks (not shown) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the effective fin 52 and STI region 66 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region at concentrations up to about 10. 18 cm -3 (For example, in about 10) 16 cm -3 To about 10 18 cm -3 (within the range). After injection, the photoresist is removed, for example, by an acceptable ashing process.

[0043] Following implantation into the p-type region 50P, a photoresist is formed over the effective fin 52 and STI region 66 within the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at concentrations up to approximately 10. 18 cm -3 (For example, in about 10) 16 cm -3 To about 10 18 cm -3 (within the range). After injection, the photoresist is removed, for example, by an acceptable ashing process.

[0044] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0045] In some embodiments, an implantation process for forming a trap is performed prior to the formation of the dummy fin 62. Therefore, in this processing step, the dummy fin 62 may be free of implanted impurities. However, as discussed in more detail below, the dummy fin 62 may be implanted with impurities in subsequent processing steps.

[0046] exist Figure 8 In this process, a dummy dielectric layer 80 is formed on the active fin 52 and the dummy fin 62. The dummy dielectric layer 80 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. The dummy dielectric layer 80 is formed of a material with high etch selectivity relative to the etching of the dielectric layer 58. A dummy gate layer 82 is formed on the dummy dielectric layer 80, and a mask layer 84 is formed on the dummy gate 82. The dummy gate layer 82 can be deposited on the dummy dielectric layer 80 and then planarized, for example, by CMP. The dummy fin 62 helps to reduce pattern loading effects during the planarization of the dummy gate layer 82. The mask layer 84 can be deposited on the dummy gate layer 82. The dummy gate layer 82 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 82 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 82 can be made of other materials with high etch selectivity relative to the etching of the isolation regions (e.g., STI region 66 and / or dummy dielectric layer 80). The mask layer 84 can include one or more layers such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 82 and a single mask layer 84 are formed on the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 80 is deposited such that it covers the active fin 52, the dummy fin 62, and the STI region 66, extending over the STI region 66 and between the dummy gate layer 82 and the STI region 66. In another embodiment, for example when the dummy dielectric layer 80 is formed by thermal growth, the dummy dielectric layer 80 covers only the active fin 52 and not the dummy fin 62.

[0047] Figures 9A to 15C Other intermediate stages in the manufacturing of FinFETs are shown. Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15B Features of either the n-type region 50N or the p-type region 50P are shown. For example, Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15B The structure shown can be applied to both n-type region 50N and p-type region 50P. Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C and Figure 15C Features within invalid region 50R are shown. As described above, invalid region 50R can be part of p-type region 50P or n-type region 50N. The structural differences (if any) between n-type region 50N and p-type region 50P are described in the accompanying text of each figure.

[0048] exist Figures 9A to 9C In this process, acceptable photolithography and etching techniques can be used to process mask layer 84 (see...). Figure 8 The mask 94 is patterned to form a mask 94. The pattern of the mask 94 can then be transferred to a dummy gate layer 82 using an acceptable etching technique to form a dummy gate 92. In some embodiments, the pattern of the mask 94 can also be transferred to a dummy dielectric layer 80 using an acceptable etching technique to form a dummy dielectric 90. The dummy gate 92 covers the dummy fin 62 and the corresponding channel region 68 of the active fin 52. The pattern of the mask 94 can be used to separate each dummy gate 92 from adjacent dummy gate entities. The dummy gate 92 may also have a length direction substantially perpendicular to the length direction of the corresponding active fin 52 / dummy fin 62.

[0049] A gate spacer 96 is formed along the sidewalls of the dummy gate 92 and the mask 94. The gate spacer 96 can be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacer 96 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. For example, the gate spacer 96 can comprise multiple layers of silicon oxycarbonitride, or a silicon nitride layer can be included between two layers of silicon oxide.

[0050] Implantation for lightly doped source / drain (LDD) regions can be performed during or after the formation of the gate spacer 96. In embodiments with different device types, similar to the above... Figure 7The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an appropriate type (e.g., p-type) of impurity into the exposed effective fins 52 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have a doping density of approximately 10. 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0051] The implantation used to form the LDD region can also implant impurities into the dummy fin 62. For example, when the dummy fin 62 is formed in the p-type region 50P, the upper part of the dummy fin 62 (e.g., the portion of the dummy fin 62 above the surface of the STI region 66) can be implanted with p-type impurities implanted in the p-type region 50P. Similarly, when the dummy fin 62 is formed in the n-type region 50N, the upper part of the dummy fin 62 (e.g., the portion of the dummy fin 62 above the surface of the STI region 66) can be implanted with n-type impurities implanted in the n-type region 50N.

[0052] Epitaxial source / drain regions 98 are then formed in the effective fin 52. The epitaxial source / drain regions 98 are formed in the effective fin 52 such that each dummy gate 92 is disposed between adjacent pairs of the corresponding epitaxial source / drain regions 98. In some embodiments, the epitaxial source / drain regions 98 may extend into and through the effective fin 52. In some embodiments, gate spacers 96 are used to separate the epitaxial source / drain regions 98 from the dummy gates 92 by an appropriate lateral distance such that the epitaxial source / drain regions 98 do not short-circuit the gate of the subsequently formed FinFET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel region 68, thereby improving performance.

[0053] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P and etching the source / drain regions of the active fin 52 in the n-type region 50N to form a groove in the active fin 52. This etching is selective for the active fin 52, such that no groove is formed in the dummy fin 62 (and therefore no epitaxial source / drain region). The epitaxial source / drain region 98 in the n-type region 50N is then epitaxially grown in the groove. The epitaxial source / drain region 98 can comprise any acceptable material (e.g., suitable for an n-type FinFET). For example, if the active fin 52 is silicon, the epitaxial source / drain region 98 in the n-type region 50N can comprise a material to which tensile strain is applied in the corresponding channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 98 in the n-type region 50N may have a surface that protrudes from the corresponding surface of the effective fin 52 and may have a facet.

[0054] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N and etching the source / drain regions of the active fin 52 in the p-type region 50P to form a trench in the active fin 52. The etching is selective for the active fin 52, such that no trench is formed in the dummy fin 62 (and therefore no epitaxial source / drain region). The epitaxial source / drain region 98 in the p-type region 50P is then epitaxially grown in the trench. The epitaxial source / drain region 98 can include any acceptable material (e.g., suitable for a p-type FinFET). For example, if the active fin 52 is silicon, the epitaxial source / drain region 98 in the p-type region 50P can include a material to which compressive strain is applied in the corresponding channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 98 in the p-type region 50P may have a surface that protrudes from the corresponding surface of the effective fin 52 and may have a small facet.

[0055] The epitaxial source / drain regions 98 and / or effective fins 52 can be implanted with dopants to form the source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19 cm -3 To about 10 21 cm -3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0056] As a result of the epitaxial process used to form epitaxial source / drain regions 98 in n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions has small facets that extend laterally outward beyond the sidewalls of the effective fin 52. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 98 of the same FinFET to merge. In some embodiments, adjacent epitaxial source / drain regions 98 remain separated after the epitaxial process is completed. In some embodiments, adjacent epitaxial source / drain regions 98 of the same FinFET merge in a first region (e.g., n-type region 50N) and adjacent epitaxial source / drain regions 98 remain separated in a second region (e.g., p-type region 50P), such as... Figure 9D As shown. In Figure 9D In the illustrated embodiment, a gate spacer 96 is formed to cover a portion of the sidewall of the effective fin 52 extending above the STI region 66, thereby blocking epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 96 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 66.

[0057] Note that the above disclosure generally describes the process for forming the dummy gate, spacers, LDD region, and source / drain region. Other processes and sequences can be used. For example, fewer or additional spacers can be used, steps can be performed in different sequences, spacers can be formed and removed, and so on. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0058] exist Figures 10A to 10CIn this configuration, a first interlayer dielectric (ILD) layer 104 is deposited over the epitaxial source / drain region 98, gate spacer 96, dummy gate 92 or mask 94 (if present), and dummy fin 62. The first ILD layer 104 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, the first ILD layer 104 is a flowable film formed by a flowable CVD method. In some embodiments, a contact etch stop layer (CESL) 102 is disposed between the first ILD layer 104 and the epitaxial source / drain region 98, gate spacer 96, dummy gate 92 or mask 94 (if present), and dummy fin 62. CESL 102 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., with an etch rate lower than that of the material of the first ILD layer 104. Since no epitaxial source / drain regions are formed in the dummy fin 62, CESL 102 may extend along the top surface of the dummy fin 62 between adjacent gate spacers 96.

[0059] exist Figures 11A to 11C In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD layer 104 flush with the top surface of the dummy gate 92 or mask 94 (if present). The dummy fin 62 helps to reduce pattern loading effects during the planarization of the first ILD layer 104. The planarization process also removes the mask 94 (if present) on the dummy gate 92, as well as portions of the gate spacer 96 along the sidewalls of the mask 94. After this planarization process, the dummy gate 92, the gate spacer 96, and the top surface of the first ILD layer 104 are flush. Therefore, the top surface of the dummy gate 92 is exposed through the first ILD layer 104. In some embodiments, the mask 94 can be retained, in which case the planarization process makes the top surface of the first ILD layer 104 flush with the top surface of the mask 94.

[0060] exist Figures 12A to 12CIn one or more etching steps, a dummy gate 92 and a mask 94 (if present) are removed to form a recess 106. A portion of the dummy dielectric 90 in the recess 106 may also be removed. In some embodiments, only the dummy gate 92 is removed, and the dummy dielectric 90 remains and is exposed by the recess 106. In some embodiments, the dummy dielectric 90 is removed from the recess 106 in a first region of the die (e.g., a core logic region) and remains in the recess 106 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 92 is removed by an anisotropic dry etching process. For example, this etching process may include a dry etching process using one or more reactive gases that selectively etch the material of the dummy gate 92 at a rate faster than etching the material of the first ILD layer 104, the gate spacer 96, and the dielectric layer 58. Each recess 106 exposes and / or covers the channel region 68 of the effective fin 52. Each channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 98. Each recess 106 also exposes the top surface and sidewalls of the upper portion of the dummy fin 62 (e.g., the portion of the dummy fin 62 above the surface of the STI region 66). During removal, the dummy dielectric 90 can be used as an etch stop layer when the dummy gate 92 is etched. The dummy dielectric 90 can then be optionally removed after the dummy gate 92 has been removed.

[0061] exist Figures 13A to 13C In this process, a gate dielectric 112 and a gate electrode 114 are formed to replace the gate. The gate dielectric 112 is deposited in a recess 106, for example on the top surface and sidewalls of the active fin 52, on the top surface and sidewalls of the dummy fin 62, and on the sidewalls of the gate spacer 96. The gate dielectric 112 may also be formed on the top surface of the first ILD layer 104. In some embodiments, the gate dielectric 112 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric 112 comprises an interface layer of silicon oxide formed by thermal oxidation or chemical oxidation, and an overlying high-k dielectric material, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric 112 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric 112 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy dielectric 90 is retained in the recess 106, the gate dielectric 112 comprises the material of the dummy dielectric 90 (e.g., silicon oxide).

[0062] Gate electrodes 114 are deposited on top of gate dielectric 112 and fill the remainder of trench 106. Gate electrode 114 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 114 is shown, gate electrode 114 may include any number of liner layers, any number of work function adjustment layers, and filler material. After filling trench 106, a planarization process such as CMP may be performed to remove excess material from gate dielectric 112 and gate electrode 114 above the top surface of the first ILD layer 104. Dummy fins 62 help reduce pattern loading effects during the planarization of gate dielectric 112 and gate electrode 114. The remaining material from gate dielectric 112 and gate electrode 114 thus forms the replacement gate of the resulting FinFET. Gate dielectric 112 and gate electrode 114 may be collectively referred to as gate structure 110 or “gate stack”. The gate structure 110 extends along the top surface and sidewalls of the channel region 68 of the active fin 52. The gate structure 110 also extends along the top surface and sidewalls of the dummy fin 62.

[0063] The formation of the gate dielectric 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric 112 in each region is formed of the same material, and the formation of the gate electrode 114 can occur simultaneously, such that the gate electrode 114 in each region is formed of the same material. In some embodiments, the gate dielectric 112 in each region can be formed by different processes, such that the gate dielectric 112 can be made of different materials, and / or the gate electrode 114 in each region can be formed by different processes, such that the gate electrode 114 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0064] exist Figures 14A to 14CIn this configuration, a second ILD layer 124 is deposited on top of a first ILD layer 104. The second ILD layer 124 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped heterosilicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, the second ILD layer 124 is a flowable film formed by a flowable CVD method. In some embodiments, an etch stop layer (not shown) is disposed between the second ILD layer 124 and the first ILD layer 104. The etch stop layer may include a dielectric material with an etch rate lower than that of the second ILD layer 124, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0065] In some embodiments, a gate mask 116 is formed over a respective gate structure (including a gate dielectric 112 and a corresponding gate electrode 114). The gate mask 116 is disposed between opposing pairs of gate spacers 96. In some embodiments, the gate mask 116 is formed by recessing the gate dielectric 112 and the gate electrode 114 such that a groove is formed between opposing pairs of gate spacers 96. One or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., are filled in the groove, and a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD layer 104. The gate mask 116 includes the remaining portion of the dielectric material. A subsequently formed gate contact passes through the second ILD layer 124 and the gate mask 116 to contact the top surface of the recessed gate electrode 114.

[0066] exist Figures 15A to 15CIn the process, source / drain contacts 126 and gate contacts 128 are formed for the epitaxial source / drain regions 98 and 114, respectively. An opening for the source / drain contacts 126 is formed through the second ILD layer 124, the first ILD layer 104, and CESL 102. An opening for the gate contacts 128 is formed through the second ILD layer 124 and the gate mask 116. Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown), such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the top surface of the second ILD layer 124. Dummy fins 62 help reduce pattern loading effects during the planarization of the second ILD layer 124. The remaining liner and conductive material form source / drain contacts 126 and gate contacts 128 in the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 98 and the source / drain contact 126. The source / drain contact 126 is physically coupled and electrically coupled to the epitaxial source / drain region 98, and the gate contact 128 is physically coupled and electrically coupled to the gate electrode 114. The source / drain contact 126 and the gate contact 128 can be formed using different processes or the same process. Although each of the source / drain contact 126 and the gate contact 128 is shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 126 and the gate contact 128 can be formed in different cross-sections, which avoids short circuits in the contacts.

[0067] Figure 16 yes Figure 15A A detailed view of area 16. The shape and dimensions of the dummy fin 62 are shown more clearly. Both the dummy fin 62 and the void 60 have grooves 56 (see [reference]). Figure 5 A similar contour shape, such as a concave contour shape. Thus, the sidewalls of the dummy fin 62 form an angle θ1 with a plane parallel to the main surface of the substrate 50. Angle θ1 can range from about 75 degrees to about 100 degrees. In some embodiments, angle θ1 is an acute angle. In contrast, the sidewalls of the active fin 52 form an angle θ2 with a plane parallel to the main surface of the substrate 50. Angle θ2 can range from about 80 degrees to about 90 degrees. In some embodiments, angle θ1 is smaller than angle θ2. For example, angle θ1 can be about 0% to about 10% smaller than angle θ2.

[0068] Because angle θ1 is acute, the width W2 of the dummy fin 62 decreases along the direction D3 extending away from the substrate 50. The width W2 of the dummy fin 62 can range from about 10 nm to about 40 nm, and the width W2 at the bottom of the dummy fin 62 can be about 0% to about 30% greater than the width W2 at the top of the dummy fin 62. Similarly, the width W3 of the void 60 decreases along the direction D3. The width W3 of the void 60 can range from about 1.5 nm to about 2.5 nm, and the width W3 at the bottom of the void 60 can be about 0% to about 30% greater than the width W3 at the top of the void 60.

[0069] As described above, the top surfaces of the dummy fin 62 and the active fin 52 are set at the same distance from the substrate 50. Specifically, the top surfaces of the dummy fin 62 and the active fin 52 are set at a distance D4 from the substrate 50, which can be in the range of about 73 nm to about 85 nm. The dummy fin 62 has a total height H1, which can be in the range of about 48 nm to about 60 nm. The dummy fin 62 extends into the STI region 66, for example, the STI region 66 has a portion disposed between the dummy fin 62 and the substrate 50, and the STI region 66 extends along the lower sidewall of the dummy fin 62 and the active fin 52. The portion of the STI region 66 between the dummy fin 62 and the substrate 50 has a height H2, which can be in the range of about 15 nm to about 35 nm. The distance D4 is equal to the sum of the heights H1 and H2.

[0070] The dielectric layer 58 has a thickness T1 along the sidewalls of the void 60, which can range from about 5 nm to about 20 nm. The dielectric layer 58 has a thickness T2 along the bottom of the void 60, which can range from about 2 nm to about 20 nm. The dielectric layer 58 has a thickness T3 along the top of the void 60, which can range from about 0 nm to about 20 nm. The relatively small thicknesses T2 and T3 result in a relatively large height H3 for the void 60, which can range from about 48 nm to about 60 nm. In some embodiments, the height H3 is about 70% to about 98% of the total height H1 of the dummy fin 62. The height H1 is equal to the sum of the height H3, the thickness T2, and the thickness T3.

[0071] As described above, the dummy fin 62 is equidistant from the adjacent effective fin 52. Specifically, the dummy fin 62 is spaced from the adjacent effective fin 52 by a distance D5, which can be in the range of about 10 nm to about 40 nm. In some embodiments, the distance D5 is equal to the distance D1 between adjacent effective fins 52. In some embodiments, the distance D5 is not equal to the distance D1; for example, the distance D5 can be about 5% to about 30% greater than the distance D1.

[0072] Figures 17 to 24This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments. In this embodiment, the dummy fin 62 includes multiple dielectric layers 58A, 58B, 58C (see [link to other embodiments]). Figure 22 ) and void 60, wherein dielectric layers 58A, 58B, and 58C surround void 60 in combination. Figures 17 to 24 It shows Figure 1 The reference cross-section AA shown is different in that it has multiple fins / FinFETs.

[0073] exist Figure 17 In the middle, something similar was obtained Figure 3 The structure is shown. A first dielectric layer 58A is then formed on the insulating material 64 and in the groove 56. The first dielectric layer 58A can be formed of silicon oxynitride, silicon carbonitride, silicon nitride, etc., and can be formed by ALD, CVD, etc. The first dielectric layer 58A is formed of a material with high etch selectivity relative to the etching of the insulating material 64. Furthermore, the material of the first dielectric layer 58A has a larger relative permittivity than one or more materials of the insulating material 64. For example, the insulating material 64 can be formed of a material with a relative permittivity in the range of about 10 to about 12, and the first dielectric layer 58A can be formed of a material with a relative permittivity in the range of about 4 to about 7. In some embodiments, the first dielectric layer 58A is silicon oxynitride formed by ALD. In another embodiment, the material of the first dielectric layer 58A has a smaller relative permittivity than one or more materials of the insulating material 64.

[0074] exist Figure 18 In this process, an etch-back process is performed to remove the portion of the first dielectric layer 58A outside the groove 56 and to recess the portion of the first dielectric layer 58A within the groove 56. This etch-back can be performed using an acceptable etching process, such as an etching process that selectively etches the material of the first dielectric layer 58A at a faster rate than etching one or more materials of the insulating material 64. See below for details. Figure 25A and Figure 25B Further discussion reveals that, after this etch-back process, the top surface of the first dielectric layer 58A can be flat or angled.

[0075] exist Figure 19In this process, a second dielectric layer 58B is formed on the first dielectric layer 58A and the insulating material 64. The second dielectric layer 58B can be formed of a high-k dielectric material, such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, metal oxides or silicates, and can be formed by ALD, CVD, etc. The second dielectric layer 58B is formed of a material with high etch selectivity relative to the etching of the first dielectric layer 58A and the insulating material 64. Furthermore, the material of the second dielectric layer 58B has a larger relative permittivity than the material of the first dielectric layer 58A. For example, the second dielectric layer 58B can be formed of a material with a relative permittivity in the range of about 7 to about 35. In some embodiments, the second dielectric layer 58B is hafnium oxide formed by ALD.

[0076] exist Figure 20 In this process, an etch-back process is performed to remove the portion of the second dielectric layer 58B outside the groove 56 and to recess the portion of the second dielectric layer 58B within the groove 56. This etch-back can be performed using an acceptable etching process, such as an etching process that selectively etches the material of the second dielectric layer 58B at a faster rate than etching one or more materials of the first dielectric layer 58A and the insulating material 64. See below regarding... Figure 25A and Figure 25B Further discussion reveals that, after this etch-back process, the top surface of the second dielectric layer 58B can be flat or angled.

[0077] exist Figure 21 In this process, a third dielectric layer 58C is formed on the second dielectric layer 58B and the insulating material 64. The third dielectric layer 58C can be formed from silicon oxynitride, silicon carbonitride, silicon nitride, etc., and can be formed by ALD, CVD, etc. The third dielectric layer 58C is formed from a material with high etch selectivity relative to the etching of the second dielectric layer 58B and the insulating material 64. Furthermore, the material of the third dielectric layer 58C has a smaller relative permittivity than the material of the second dielectric layer 58B. For example, the third dielectric layer 58C can be formed from a material with a relative permittivity in the range of about 4 to about 7. In some embodiments, the third dielectric layer 58C is silicon oxynitride formed by ALD. The first dielectric layer 58A and the third dielectric layer 58C can be similar or different. In some embodiments, the first dielectric layer 58A and the third dielectric layer 58C are each formed from silicon oxynitride with different oxygen and nitrogen compositions.

[0078] exist Figure 22In this process, a removal process is applied to the third dielectric layer 58C and the insulating material 64 to remove excess portions of the third dielectric layer 58C and the insulating material 64 above the effective fin 52. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be used. This removal process forms a dummy fin 62, which includes the remaining portions of the dielectric layers 58A, 58B, and 58C in the groove 56. The dummy fin 62 includes a void 60. A first dielectric layer 58A surrounds the lower portion of the void 60, a second dielectric layer 58B surrounds the middle portion of the void 60, and a third dielectric layer 58C surrounds the upper portion of the void 60.

[0079] Dielectric layers 58A, 58B, and 58C are formed of dielectric materials with different relative permittivity. In some embodiments, the material of each of dielectric layers 58A, 58B, and 58C has a larger relative permittivity than one or more of the materials of insulating material 64. Dielectric layers 58A, 58B, and 58C and void 60 serve as the dielectric medium for a parasitic capacitor network disposed between the effective fins 52 and the ineffective region 50R. Forming dielectric layers 58A, 58B, and 58C with dielectric materials having different relative permittivity can help reduce the effective capacitance of the capacitor network by about 11% to about 20%. Therefore, the parasitic capacitance of the resulting FinFET can be further reduced, thereby improving the performance of the FinFET.

[0080] exist Figure 23In this process, insulating material 64 is recessed to form STI regions 66. The insulating material 64 is recessed such that the upper portions of the active fins 52 and dummy fins 62 protrude above and between adjacent STI regions 66. The STI regions 66 can be recessed using an acceptable etching process, such as an etching process selective for one or more materials of insulating material 64. Each of the dielectric layers 58A, 58B, 58C is formed of a material with high etch selectivity relative to the etching of insulating material 64. For example, it can be removed using, for example, an oxide of dilute hydrofluoric acid (dHF). The etching process selectively etches one or more materials of insulating material 64 at a faster rate than etching one or more materials of active fins 52 and dummy fins 62. For example, the materials of each of the dielectric layers 58A, 58B, 58C and one or more materials of insulating material 64 can have etch selectivity in the range of about 20:1 to about 1000:1 relative to the etching process used to recess insulating material 64. Therefore, dielectric layers 58A, 58B, and 58C can be protected from damage during the formation of the dummy fin 62. In some embodiments, the etching rate of dielectric layers 58B and 58C is lower than the etching rate of the first dielectric layer 58A relative to the etching process used to recess the insulating material 64. For example, in the illustrated embodiment, the first dielectric layer 58A remains buried after the formation of the STI region 66 and therefore may not be etched during the recessing of the insulating material 64.

[0081] exist Figure 24 In the middle, it is possible to execute commands related to... Figures 8 to 15C The processing steps described are similar to those steps. Therefore, the formation of a FinFET can be completed.

[0082] Figure 25A and Figure 25B According to various embodiments Figure 24 A detailed view of area 25. The shape and dimensions of the dummy fin 62 are shown more clearly. Both the dummy fin 62 and the void 60 have features related to... Figure 16 The described embodiments have similar contour shapes and dimensions. Dielectric layers 58A, 58B, and 58C each have different heights. The first dielectric layer 58A may have a height H4 in the range of about 8 nm to about 30 nm, the second dielectric layer 58B may have a height H5 in the range of about 10 nm to about 50 nm, and the third dielectric layer 58C may have a height H6 in the range of about 2 nm to about 8 nm. Height H5 may be greater than each of height H4 and height H6. In some embodiments, the second dielectric layer 58B has a recessed contour shape, such as... Figure 25AAs shown. When the second dielectric layer 58B has a recessed profile shape, the top and bottom surfaces of the second dielectric layer 58B are parallel to the main surface of the substrate 50. In some embodiments, the second dielectric layer 58B has a V-shaped profile shape, such as... Figure 25B As shown. When the second dielectric layer 58B has a V-shaped profile, the bottom surfaces of the second dielectric layer 58B each form an acute angle θ3 with a plane parallel to the main surface of the substrate 50, and the top surfaces of the second dielectric layer 58B each form an acute angle θ4 with a plane parallel to the main surface of the substrate 50. Angles θ3 and θ4 can each be up to about 50 degrees. In some embodiments, angle θ3 is smaller than angle θ4.

[0083] Figure 26 This is a cross-sectional view of a FinFET according to some other embodiments. Figure 26 It shows Figure 1 The reference cross-section AA shown differs in that it contains multiple fins / FinFETs. In this embodiment, the invalid region 50R is part of the n-type region 50N and is disposed between adjacent n-type FinFETs in the n-type region 50N. The invalid region 50R includes dummy fins 62, which can be similar to those regarding... Figure 16 , Figure 25A and Figure 25B The description is of an arbitrary, fictitious fin.

[0084] Figure 27 This is a cross-sectional view of a FinFET according to some other embodiments. Figure 27 It shows Figure 1 The reference cross-section AA shown differs in that it contains multiple fins / FinFETs. In this embodiment, both the n-type region 50N and the p-type region 50P include invalid regions 50R. Each invalid region 50R includes a dummy fin 62, which can be similar to the one shown above. Figure 16 , Figure 25A and Figure 25B The description is of an arbitrary, fictitious fin.

[0085] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructure (e.g., nanosheets, nanowires, all-gate-around, etc.) field-effect transistors (NSFETs). Figure 28 This is a cross-sectional view of an NSFET according to some other embodiments. Figure 28 It shows the relationship with Figure 1The cross-section shown in the figure is similar to the reference cross-section AA, except that a nanostructure / NSFET is shown instead of a fin / FinFET. In this embodiment, the effective fin 52 is replaced by a nanostructure 152, which is formed by patterning an alternating stack of channel layers and sacrificial layers. The nanostructure 152 is a semiconductor strip formed on the substrate 50, and dummy fins 62 are formed in the ineffective regions 50R between some nanostructures 152. The dummy fins 62 can be similar to those shown in the figure. Figure 16 , Figure 25A and Figure 25B The description describes an arbitrary dummy fin. In the illustrated embodiment, the invalid region 50R is part of the p-type region 50P, but the invalid region 50R can also be part of the n-type region 50N, or the invalid region 50R can exist in both the n-type region 50N and the p-type region 50P. The dummy gate stack and source / drain regions are formed in a manner similar to that described in the above embodiment. After the dummy gate stack is removed, the sacrificial layer in the channel region 68 can be partially or completely removed. The replacement gate structure is formed in a manner similar to that described in the above embodiment, and the replacement gate structure can partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or completely surround the dummy fin 62 of the NSFET device and the channel layer in the channel region 68. The ILD and contacts to the replacement gate structure and source / drain regions can be formed in a manner similar to that described in the above embodiment. The nanostructured device can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0086] The embodiments can achieve advantages. Forming dummy fins 62 helps reduce pattern loading effects that may be caused by forming empty invalid regions 50R. For example, loading effects in subsequent CMP or (one or more) etching processes can be reduced. Furthermore, forming dummy fins 62 to include gaps 60 can help reduce the relative permittivity of dummy fins 62 and reduce the total effective conductance of dummy fins 62. Thus, in addition to helping reduce pattern loading effects in subsequent processing, dummy fins 62 also help electrically isolate adjacent FinFETs from each other. Specifically, forming gaps 60 can help reduce the effective capacitance between adjacent FinFETs by up to about 20%.

[0087] In one embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a dielectric fin disposed between the first and second semiconductor fins, the dielectric fin including a void; and an isolation region disposed between the dielectric fin and the substrate, the isolation region extending along the sidewalls of the dielectric fin, the sidewalls of the first and second semiconductor fins.

[0088] In some embodiments of the device, the top surfaces of the first semiconductor fin, the second semiconductor fin, and the dielectric fin are coplanar. In some embodiments, the device further includes a gate structure extending along the top surfaces and sidewalls of the dielectric fin, the first semiconductor fin, and the second semiconductor fin. In some embodiments of the device, the dielectric fin further includes a first dielectric layer surrounding the void, the first dielectric layer comprising a first dielectric material, and an isolation region comprising a second dielectric material, the first dielectric material being different from the second dielectric material. In some embodiments of the device, the first dielectric material is silicon oxynitride, the second dielectric material is silicon oxide, and the void is filled with air or is in a vacuum. In some embodiments of the device, the first dielectric material has a first relative permittivity, the second dielectric material has a second relative permittivity, and the void has a third relative permittivity less than the second relative permittivity, the second relative permittivity being less than the first relative permittivity. In some embodiments of the device, the dielectric fin further includes: a first dielectric layer on the substrate, the first dielectric layer surrounding the lower portion of the gap, the first dielectric layer comprising a first dielectric material; a second dielectric layer on the first dielectric layer, the second dielectric layer surrounding the middle portion of the gap, the second dielectric layer comprising a second dielectric material; and a third dielectric layer on the second dielectric layer, the third dielectric layer surrounding the upper portion of the gap, the third dielectric layer comprising a third dielectric material, wherein the isolation region comprises a fourth dielectric material, and each of the first, second, third, and fourth dielectric materials is different. In some embodiments of the device, the first dielectric material is silicon oxynitride, the second dielectric material is a high-k material, the third dielectric material is silicon oxynitride, the fourth dielectric material is silicon oxide, and the gap is filled with air or is in a vacuum. In some embodiments of the device, a first dielectric material has a first relative permittivity, a second dielectric material has a second relative permittivity, a third dielectric material has a third relative permittivity, a fourth dielectric material has a fourth relative permittivity, and the void has a fifth relative permittivity, the fifth relative permittivity being less than the fourth relative permittivity, the fourth relative permittivity being less than each of the first, second, and third relative permittivity.

[0089] In one embodiment, a device includes: a first semiconductor strip on a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip on the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, the width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including gaps; and a gate structure extending along the first channel region, along the second channel region, and along the top surface and sidewalls of the dielectric strip.

[0090] In some embodiments of the device, a first semiconductor stripe is a first fin extending from a substrate, and a second semiconductor stripe is a second fin extending from a substrate. In some embodiments of the device, the first semiconductor stripe is a first nanostructure on the substrate, and the second semiconductor stripe is a second nanostructure on the substrate. In some embodiments of the device, the width of the void decreases along a first direction. In some embodiments of the device, the width of the void is in the range of 1.5 nm to 2.5 nm. In some embodiments of the device, the height of the void is in the range of 48 nm to 60 nm.

[0091] In one embodiment, a method includes: forming a first semiconductor fin and a second semiconductor fin, each extending along a first direction remote from a substrate; forming an insulating material between the first semiconductor fin and the second semiconductor fin, the insulating material having a groove whose width decreases along the first direction; depositing a first dielectric layer in the groove to form a void, the void including a portion of the groove not filled by the first dielectric layer; and recessing the insulating material to form a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin including the void and a remaining portion of the first dielectric layer in the groove, the remaining portion of the first dielectric layer surrounding the void.

[0092] In some embodiments of the method, the first dielectric layer is the only dielectric layer deposited in the groove. In some embodiments, the method further includes: depositing a second dielectric layer in the groove; and depositing a third dielectric layer on the second dielectric layer in the groove, wherein the first dielectric layer is deposited on the third dielectric layer. In some embodiments, recessing the insulating material includes: recessing the insulating material using a first etching process, the first etching process etching the insulating material at a faster rate than etching the first dielectric layer. In some embodiments of the method, the groove has a first width at the bottom of the groove and a second width at the top of the groove, the first width being 0% to 30% larger than the second width.

[0093] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0094] Example 1. A semiconductor device comprising: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a dielectric fin disposed between the first semiconductor fin and the second semiconductor fin, the dielectric fin including a void; and an isolation region disposed between the dielectric fin and the substrate, the isolation region extending along a sidewall of the dielectric fin, a sidewall of the first semiconductor fin, and a sidewall of the second semiconductor fin.

[0095] Example 2. The semiconductor device according to Example 1, wherein the top surface of the first semiconductor fin, the top surface of the second semiconductor fin, and the top surface of the dielectric fin are coplanar.

[0096] Example 3. The semiconductor device according to Example 2 further includes: a gate structure extending along the top surface and sidewall of the dielectric fin, the top surface and sidewall of the first semiconductor fin, and the top surface and sidewall of the second semiconductor fin.

[0097] Example 4. The semiconductor device according to Example 1, wherein the dielectric fin further includes a first dielectric layer surrounding the gap, the first dielectric layer comprising a first dielectric material, and the isolation region comprising a second dielectric material, the first dielectric material being different from the second dielectric material.

[0098] Example 5. The semiconductor device according to Example 4, wherein the first dielectric material is silicon oxynitride, the second dielectric material is silicon oxide, and the voids are filled with air or are in a vacuum.

[0099] Example 6. The semiconductor device according to Example 4, wherein the first dielectric material has a first relative permittivity, the second dielectric material has a second relative permittivity, and the void has a third relative permittivity, the third relative permittivity being less than the second relative permittivity, and the second relative permittivity being less than the first relative permittivity.

[0100] Example 7. A semiconductor device according to Example 1, wherein the dielectric fin further comprises: a first dielectric layer on the substrate, the first dielectric layer surrounding the lower portion of the gap, the first dielectric layer comprising a first dielectric material; a second dielectric layer on the first dielectric layer, the second dielectric layer surrounding the middle portion of the gap, the second dielectric layer comprising a second dielectric material; and a third dielectric layer on the second dielectric layer, the third dielectric layer surrounding the upper portion of the gap, the third dielectric layer comprising a third dielectric material, wherein the isolation region comprises a fourth dielectric material, and each of the first dielectric material, the second dielectric material, the third dielectric material, and the fourth dielectric material is different.

[0101] Example 8. The semiconductor device according to Example 7, wherein the first dielectric material is silicon oxynitride, the second dielectric material is a high-k material, the third dielectric material is silicon oxynitride, the fourth dielectric material is silicon oxide, and the voids are filled with air or are in a vacuum.

[0102] Example 9. A semiconductor device according to Example 7, wherein the first dielectric material has a first relative permittivity, the second dielectric material has a second relative permittivity, the third dielectric material has a third relative permittivity, the fourth dielectric material has a fourth relative permittivity, and the void has a fifth relative permittivity, the fifth relative permittivity being less than the fourth relative permittivity, the fourth relative permittivity being less than each of the first relative permittivity, the second relative permittivity, and the third relative permittivity.

[0103] Example 10. A semiconductor device comprising: a first semiconductor strip on a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip on the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, the width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along the top surface and sidewalls of the dielectric strip.

[0104] Example 11. The semiconductor device according to Example 10, wherein the first semiconductor strip is a first fin extending from the substrate, and the second semiconductor strip is a second fin extending from the substrate.

[0105] Example 12. The semiconductor device according to Example 10, wherein the first semiconductor strip is a first nanostructure on the substrate, and the second semiconductor strip is a second nanostructure on the substrate.

[0106] Example 13. The semiconductor device according to Example 10, wherein the width of the gap decreases along the first direction.

[0107] Example 14. The semiconductor device according to Example 10, wherein the width of the gap is in the range of 1.5 nm to 2.5 nm.

[0108] Example 15. The semiconductor device according to Example 10, wherein the height of the gap is in the range of 48 nm to 60 nm.

[0109] Example 16. A method of manufacturing a semiconductor device, comprising: forming a first semiconductor fin and a second semiconductor fin, each extending along a first direction remote from a substrate; forming an insulating material between the first semiconductor fin and the second semiconductor fin, the insulating material having a groove, the width of the groove decreasing along the first direction; depositing a first dielectric layer in the groove to form a void, the void including a portion of the groove not filled by the first dielectric layer; and recessing the insulating material to form a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin including the void and a remaining portion of the first dielectric layer in the groove, the remaining portion of the first dielectric layer surrounding the void.

[0110] Example 17. The method according to Example 16, wherein the void is continuously surrounded by the first dielectric layer.

[0111] Example 18. The method according to Example 16 further includes: depositing a second dielectric layer in the groove; and depositing a third dielectric layer on the second dielectric layer in the groove, wherein the first dielectric layer is deposited on the third dielectric layer.

[0112] Example 19. The method according to Example 16, wherein recessing the insulating material comprises: using a first etching process to recess the insulating material, the first etching process etching the insulating material at a faster rate than etching the first dielectric layer.

[0113] Example 20. The method according to Example 16, wherein the groove has a first width at the bottom of the groove and a second width at the top of the groove, the first width being 0% to 30% larger than the second width.

Claims

1. A semiconductor device, comprising: The first semiconductor fin extends from the substrate; A second semiconductor fin extends from the substrate; A dielectric structure is disposed between the first semiconductor fin and the second semiconductor fin, the dielectric structure including a gap; as well as An isolation region is disposed between the dielectric structure and the substrate, and the isolation region extends along the sidewall of the dielectric structure, the sidewall of the first semiconductor fin, and the sidewall of the second semiconductor fin; The dielectric structure further includes: A first dielectric layer is placed on the substrate and surrounds the lower portion of the void. The first dielectric layer comprises a first dielectric material. A second dielectric layer, situated above the first dielectric layer, surrounds the center of the void, and the second dielectric layer comprises a second dielectric material; and A third dielectric layer, situated above the second dielectric layer, surrounds the upper portion of the void, and the third dielectric layer comprises a third dielectric material. The isolation region includes a fourth dielectric material, and each of the first dielectric material, the second dielectric material, the third dielectric material, and the fourth dielectric material is different.

2. The semiconductor device according to claim 1, wherein, The top surfaces of the first semiconductor fin, the second semiconductor fin, and the dielectric structure are coplanar.

3. The semiconductor device according to claim 2, further comprising: The gate structure extends along the top surface and sidewalls of the dielectric structure, the top surface and sidewalls of the first semiconductor fin, and the top surface and sidewalls of the second semiconductor fin.

4. The semiconductor device according to claim 1, wherein, The first dielectric material is silicon oxynitride, the second dielectric material is a high-k material, the third dielectric material is silicon oxynitride, the fourth dielectric material is silicon oxide, and the voids are filled with air or are in a vacuum.

5. The semiconductor device according to claim 1, wherein, The first dielectric material has a first relative permittivity, the second dielectric material has a second relative permittivity, the third dielectric material has a third relative permittivity, the fourth dielectric material has a fourth relative permittivity, and the void has a fifth relative permittivity, the fifth relative permittivity being less than the fourth relative permittivity, and the fourth relative permittivity being less than each of the first relative permittivity, the second relative permittivity, and the third relative permittivity.

6. A semiconductor device, comprising: A first semiconductor strip, on a substrate, includes a first channel region; A second semiconductor strip, on the substrate, includes a second channel region; A dielectric strip is disposed between a first semiconductor strip and a second semiconductor strip, the width of the dielectric strip decreasing along a first direction extending away from the substrate, and the dielectric strip includes gaps; as well as The gate structure extends along the first channel region, along the second channel region, and along the top surface and sidewalls of the dielectric strip; The dielectric strip further includes: A first dielectric layer is placed on the substrate and surrounds the lower portion of the void. The first dielectric layer comprises a first dielectric material. A second dielectric layer, situated above the first dielectric layer, surrounds the center of the void, and the second dielectric layer comprises a second dielectric material; and A third dielectric layer, situated above the second dielectric layer, surrounds the upper portion of the void, and the third dielectric layer comprises a third dielectric material. Each of the first dielectric material, the second dielectric material, and the third dielectric material is different.

7. The semiconductor device according to claim 6, wherein, The first semiconductor strip is a first fin extending from the substrate, and the second semiconductor strip is a second fin extending from the substrate.

8. The semiconductor device according to claim 6, wherein, The first semiconductor strip is a first nanostructure on the substrate, and the second semiconductor strip is a second nanostructure on the substrate.

9. The semiconductor device according to claim 6, wherein, The width of the gap decreases along the first direction.

10. The semiconductor device according to claim 6, wherein, The width of the void is in the range of 1.5 nm to 2.5 nm.

11. The semiconductor device according to claim 6, wherein, The height of the void is in the range of 48 nm to 60 nm.

12. A method for manufacturing a semiconductor device, comprising: Form a first semiconductor fin and a second semiconductor fin, each extending along a first direction away from the substrate; An insulating material is formed between the first semiconductor fin and the second semiconductor fin, the insulating material having a groove, the width of which decreases along the first direction; A first dielectric layer is deposited in the groove, a second dielectric layer is deposited on the first dielectric layer in the groove, and a third dielectric layer is deposited on the second dielectric layer in the groove to form a void, the void including the portion of the groove that is not filled by the first dielectric layer, the second dielectric layer and the third dielectric layer; as well as The insulating material is recessed to form a dielectric structure between the first semiconductor fin and the second semiconductor fin. The dielectric structure includes the gap and the remaining portions of the first dielectric layer, the second dielectric layer and the third dielectric layer in the recess, with the remaining portions of the first dielectric layer, the second dielectric layer and the third dielectric layer surrounding the gap. The first dielectric layer includes a first dielectric material, the second dielectric layer includes a second dielectric material, and the third dielectric layer includes a third dielectric material, wherein each of the first dielectric material, the second dielectric material, and the third dielectric material is different.

13. The method according to claim 12, wherein, The gap is continuously surrounded by the first dielectric layer, the second dielectric layer and the third dielectric layer.

14. The method according to claim 12, wherein, Making the insulating material recessed includes: The insulating material is recessed using a first etching process, which etches the insulating material at a faster rate than etching the first dielectric layer, the second dielectric layer, and the third dielectric layer.

15. The method according to claim 12, wherein, The groove has a first width at the bottom and a second width at the top, the first width being 0% to 30% larger than the second width.

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