Surface damage control of diodes

Abstract

The present disclosure relates generally to surface damage control of diodes. A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type dopant, the second well region includes a second type dopant different from the first type dopant, and the array of well regions includes the second type dopant. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

Description

Technical Field

[0001] This disclosure generally relates to surface damage control of diodes. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry is constantly scaling down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and finFETs. This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a substrate; a first well region disposed within the substrate, wherein the first well region includes a first type of dopant; a second well region disposed adjacent to the first well region and within the substrate, wherein the second well region includes a second type of dopant different from the first type of dopant; a well region array disposed within the first well region, wherein the well region array includes the second type of dopant; a metal silicide layer disposed on the well region array and within the substrate; a metal silicide nitride layer disposed on the metal silicide layer and within the substrate; and a contact structure disposed on the metal silicide nitride layer.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a substrate; a first well region disposed within the substrate; a second well region disposed adjacent to the first well region and within the substrate; a well region array disposed within the first well region; a silicide layer disposed on the well region array and within the substrate; a silicide nitride layer disposed on the substrate; and a contact structure disposed on the silicide nitride layer.

[0005] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first well region having a first type of dopant in a substrate; forming a well region array having a second type of dopant in the first well region, wherein the second type of dopant is different from the first type of dopant; forming a metal silicide layer on the well region array and in the substrate; forming a metal silicide nitride layer on the metal silicide layer and in the substrate; and forming a contact structure on the metal silicide nitride layer. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1A-Figure 1B A cross-sectional view of a diode according to some embodiments is shown.

[0008] Figure 1C The device characteristics of a diode according to some embodiments are shown.

[0009] Figure 2 This is a flowchart of a method for manufacturing a diode according to some embodiments.

[0010] Figures 3-19 Cross-sectional views of a diode at various stages of its manufacturing process, according to some embodiments, are shown.

[0011] Figures 20-21 The crystal structure of the cap layer used in the manufacture of diodes is shown according to some embodiments.

[0012] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Unless otherwise stated, the discussion of elements with the same reference numerals applies to each other. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a process for forming a first feature over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. As used herein, forming a first feature over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition, in itself, does not indicate a relationship between the embodiments and / or configurations discussed herein.

[0014] Spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) are used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein will be interpreted accordingly.

[0015] Note that references to "an embodiment," "embodiment," "example embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0016] It should be understood that the terms or terminology used herein are for descriptive purposes and not for limitation, and that the terms or terminology used herein will be understood by one or more persons skilled in the art based on the teachings herein.

[0017] In some embodiments, the terms “about” and “substantially” can mean that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to percentages of values ​​understood by one or more people skilled in the art based on the teachings herein.

[0018] This disclosure provides example diodes (e.g., Schottky barrier diodes) and example methods of forming them. The diode may include a metallization layer disposed on a semiconductor substrate. In some embodiments, the metallization layer may include a metal silicide nitride layer and a stack of metal silicide layers. Nitrogen atoms in the metal silicide nitride layer prevent or mitigate the formation of surface traps on the metal silicide nitride layer that could cause current leakage in the diode. Surface traps may be due to dangling surface bonds formed during the formation of the metallization layer. Surface traps on the metallization layer can trap charge and reduce the Schottky barrier between the metallization layer and the semiconductor material of the substrate. A reduction in the Schottky barrier can cause current leakage during the diode's off-state. In some embodiments, surface current leakage in a diode having a stack of metal silicide nitride layers and metal silicide layers can be reduced by about 10% to about 50% compared to a diode without a metal silicide nitride layer in the metallization layer. In some embodiments, the diode may include an etch stop layer disposed on the metallization layer and a contact structure disposed on the metallization layer through the etch stop layer.

[0019] In some embodiments, the metal silicide layer can be formed by a silicide process between a metal layer and a semiconductor material of a substrate. In some embodiments, during a surface treatment process of the metallization layer performed concurrently with the silicide process, the top of the metal silicide layer can be converted into a metal silicide nitride layer. The surface treatment process may include introducing nitrogen atoms into the metallization layer through a capping layer disposed on the metallization layer. The capping layer may include a metal nitride material and may prevent oxidation of the metallization layer during the silicide process.

[0020] In some embodiments, to allow sufficient diffusion of nitrogen atoms through the capping layer during the surface treatment process, the metal nitride material of the capping layer is formed with a cubic crystal structure. The cubic packing arrangement of the metal and nitrogen atoms in the capping layer allows nitrogen gas to flow through the capping layer during the surface treatment process. In some embodiments, forming the capping layer with a cubic crystal structure may include using a gas mixture of argon and nitrogen-based gases to form a metal nitride layer in which the concentration ratio of metal to nitrogen is in the range of about 1:3 to about 1:4. In some embodiments, the nitrogen to argon ratio in the gas mixture is in the range of about 2 to about 4 to form the metal nitride material of the capping layer with a cubic crystal structure. If the metal to nitrogen concentration ratio is outside the range of about 1:3 to about 1:4 and / or if the nitrogen to argon ratio in the gas mixture is outside the range of about 2 to about 4, the metal and nitrogen atoms of the capping layer may form other crystal structures, such as a hexagonal close-packed (HCP) crystal structure. The HCP packing arrangement of the metal and nitrogen atoms may prevent nitrogen atom diffusion through the capping layer during the surface treatment process.

[0021] Figure 1A and Figure 1B Different cross-sectional views of a diode 100 according to some embodiments are shown. In some embodiments, the diode 100 may be a Schottky barrier diode. Figure 1A-Figure 1B Discussions of elements with the same labeling apply to each other unless otherwise stated.

[0022] refer to Figure 1A-Figure 1B Diode 100 may be formed on substrate 102. Other semiconductor devices (e.g., FETs) and / or other diodes may be formed on substrate 102. Substrate 102 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), silicon-on-insulator (SOI) structures, other suitable semiconductor materials, and combinations thereof. In some embodiments, substrate 102 may include an epitaxial semiconductor layer, a gradient semiconductor layer, or a semiconductor layer on another type of semiconductor layer, such as a silicon layer on a silicon-germanium layer. In some embodiments, substrate 102 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0023] In some embodiments, diode 100 may include (i) a first well region 104, (ii) a second well region 106, (iii) a third well region 108, (iv) a fourth well region 110, (v) a first doped region 112, (vi) a second doped region 114, (vii) metallization layers 116A, 118A and 120A, (viii) a shallow trench isolation (STI) region 122, (ix) a dielectric layer 124, (x) an etch stop layer (ESL) 126, (xi) an interlayer dielectric (ILD) layer 128, and (xii) contact structures 130, 132 and 134.

[0024] The diode 100 may form an anode region 101A within region 101A, a cathode region 101B within region 101B, and a body region 101C within region 101C. In some embodiments, the anode region 101A may include a fourth well region 110, a metal layer 116A, a contact structure 130, and portions of a second well region 106, ESL 126, and ILD layer 128 within region 101A. In some embodiments, the cathode region 101B may include a first doped region 112, a metal layer 118A, a contact structure 132, and portions of a second well region 106, ESL 126, and ILD layer 128 within region 101B. In some embodiments, the body region 101C may include a second doped region 114, a metal layer 120A, a contact structure 134, and portions of a third well region 108, ESL 126, and ILD layer 128 within region 101C. The diode 100 can be configured to allow current to flow from the anode region 101A to the cathode region 101B during operation and to electrically connect the body region 101C to the substrate 102.

[0025] The first well region 104 may be a deep well region disposed within the substrate 102. In some embodiments, the first well region 104 may be doped with a dopant type different from that in the substrate 102 (i.e., n-type or p-type). In some embodiments, the first well region 104 may be doped with an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants, wherein the doping concentration is approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 17 atoms / cm 3 Within the range. In some embodiments, the first well region 104 may be about 4 μm to about 6 μm below the ESL 126 and may have a thickness in the range of about 0.5 μm to about 4 μm.

[0026] The second well region 106 may be disposed on the first well region 104 and located within the substrate 102. In some embodiments, the dimensions (e.g., widths) of the first well region 104 and the second well region 106 along the X-axis may be substantially equal to each other. In some embodiments, the second well region 106 may be doped with the same type of dopant as the first well region 104 (i.e., n-type or p-type), but with a lower doping concentration than the first well region 104. In some embodiments, the second well region 106 may be doped with an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants, wherein the doping concentration is approximately 1 × 10⁻⁶. 13 atoms / cm 3 To approximately 1×10 16 atoms / cm 3 Within the range.

[0027] The third well region 108 may be disposed within the substrate 102 and adjacent to and / or laterally surrounding the second well region 106. In some embodiments, the third well region 108 may be doped with a dopant type different from that in the second well region 106 (i.e., n-type or p-type), and the doping concentration may be greater than that of the second well region 106 and the substrate 102. In some embodiments, the third well region 108 may be doped with a p-type dopant, such as boron, indium, aluminum, gallium, and other suitable p-type dopants, wherein the doping concentration is approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 18 atoms / cm 3 Within the range.

[0028] In some embodiments, the fourth well region 110 may include an array of well regions arranged within the second well region 106, such as Figure 1A As shown. The well region array may include more than five and less than fifteen well regions so that the diode 100 can function fully without affecting device size and manufacturing cost. In some embodiments, the fourth well region 110 may be doped with a different type of dopant (i.e., n-type or p-type) than the dopant type in the second well region 106, and the doping concentration is greater than that of the second well region 106 and the substrate 102. In some embodiments, the fourth well region 110 may be doped with a p-type dopant, such as boron, indium, aluminum, gallium, and other suitable p-type dopants, wherein the doping concentration is approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 18 atoms / cm 3 Within the range. In some embodiments, the dimension (e.g., height) of the fourth well region 110 along the Z-axis may be greater than the dimension of the STI region 122.

[0029] The first doped region 112 may be disposed within the second well region 106. In some embodiments, the first doped region 112 may be doped with a dopant type different from that in the fourth well region 110 (i.e., n-type or p-type), and the doping concentration may be substantially equal to or greater than that in the fourth well region 110. In some embodiments, the first doped region 112 may be doped with an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants, wherein the doping concentration is approximately 1 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 Within the range. In some embodiments, the first doped region 112 can be used as the cathode of the diode 100, and the cathode region 101B can be electrically coupled to a cathode terminal (not shown). The doping concentration of the first doped region 112 can be used to control the electrical characteristics of the cathode region 101B.

[0030] The second doped region 114 may be disposed within the third well region 108. In some embodiments, the second doped region 114 may form a continuous region surrounding the cathode region 101B. In some embodiments, the second doped region 114 may be doped with a dopant type different from that in the first doped region 112 (i.e., n-type or p-type), and the doping concentration is substantially equal to or greater than that of the first doped region 112. In some embodiments, the second doped region 114 may be doped with a p-type dopant, such as boron, indium, aluminum, gallium, and other suitable p-type dopants, wherein the doping concentration is approximately 1 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 21 atoms / cm 3 Within the range. In some embodiments, the second doped region 114 can electrically couple the body region 101C to a body terminal (not shown). The doping concentration of the second doped region 114 can be used to control the electrical characteristics of the body region 101C.

[0031] refer to Figure 1AIn some embodiments, the metallization layer 116A may include (i) a metal silicide layer 136 disposed on the second well region 106 and the fourth well region 110, and (ii) a metal silicide nitride layer 138 disposed on the metal silicide layer 136. In some embodiments, both the metal silicide layer 136 and the metal silicide nitride layer 138 may be disposed within the substrate 102. In some embodiments, the top surface 138s of the metal silicide nitride layer 138 may be substantially coplanar with the top surface 102s of the substrate 102. In some embodiments, the interface 140 between the metal silicide layer 136 and the metal silicide nitride layer 138 may be disposed within the substrate 102 and located in a plane below the top surface 142 of the substrate 102.

[0032] refer to Figure 1B In some embodiments, the diode 100 may have a metallization layer 116B having a metal silicide layer 136 disposed within the substrate 102 and a metal silicide nitride layer 138 disposed on the top surface 102s of the substrate 102. The interface 140 between the metal silicide layer 136 and the metal silicide nitride layer 138 may be substantially coplanar with the top surface 102s of the substrate 102, or may be disposed at a plane above the top surface 102s of the substrate 102 (not shown). The relative positions of the metallization layers 116A and 116B with respect to the top surface 102s of the substrate 102 may depend on the manufacturing process of the diode 100, as described in detail below.

[0033] refer to Figure 1A and Figure 1B A Schottky junction can be formed at the interface between the metal silicide layer 136 and the second well region 106, and between the metal silicide layer 136 and the fourth well region 110. In some embodiments, the metal silicide layer 136 may include cobalt silicide (Co). x Si y ), titanium silicide (Ti x Si y Nickel silicide (Ni) x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y Platinum silicide (Pt) x Si y Zirconium silicide (Zr) x Si y ), Tungsten silicide (W) x Si y Scandium silicide (Sc) x Si y ), yttrium silicide (Y x Siy ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium silicide (Er x Si y ), Ytterbium silicide (Yb x Si y Europium silicide (Eu) x Si y ), Thorium silicide (Th) x Si y ), manganese silicide (Mn) x Si y ), iron silicide (Fe) x Si y ), Rhodium silicide (Rh x Si y ), Palladium silicide (Pd) x Si y ), Ruthenium silicide (Ru) x Si y ), Iridium silicide (Ir) x Si y ), Osmium silicide (Os) x Si y Other suitable metal silicide materials or combinations thereof. In some embodiments, the metal silicide layer 136 may include Co. x Si y Ti x Si y or Ni x Si y , where the value of x is equal to 1 and the value of y is equal to 1.

[0034] In some embodiments, the metal silicide nitride layer 138 may include cobalt silicide nitride (Co). x Si y N z ), titanium nitride (Ti x Si y N z Nickel nitride (Ni) x Si y N z ), tantalum silicon nitride (Ta x Si y N z ), molybdenum silicon nitride (Mo) x Si y N z Platinum silicon nitride (Pt) x Si y N z ), Zirconium silicon nitride (Zrx Si y N z ), silicon nitride tungsten (W) x Si y N z ), Scandium nitride (Sc) x Si y N z ), Yttrium silicon nitride (Y) x Si y N z ), terbium silicon nitride (Tb x Si y N z ), Lutetium silicon nitride (Lu) x Si y N z ), terbium silicon nitride (Er x Si y N z ), Ytterbium nitride (Yb x Si y N z Europium silicon nitride (Eu) x Si y N z ), Thorium silicon nitride (Th) x Si y N z ), manganese silicon nitride (Mn x Si y N z ), silicon nitride iron (Fe) x Si y N z europium silicon nitride (Rh) x Si y N z ), palladium nitride (Pd) x Si y N z ), Ruthenium silicon nitride (Ru x Si y N z ), iridium silicon nitride (Ir) x Si y N z ), Osmium nitride (Os) x Si y N z Other suitable metal silicide nitride materials or combinations thereof, wherein the value of z is in the range of about 1 to about 2. In some embodiments, the metal silicide nitride layer 138 may include Co. x Si y N z Ti x Siy N z or Ni x Si y N z , where the value of x is equal to 1, the value of y is equal to 1, and the value of z is in the range of approximately 1 to approximately 2.

[0035] Nitrogen atoms in the metal silicide nitride layer 138 prevent or mitigate the formation of surface traps on the top surface 138s of the metal silicide nitride layer 138 and at the interface 140 between the metal silicide layer 136 and the metal silicide nitride layer 138. Surface traps may be due to dangling surface bonds formed during the formation of the metallization layer 116A. Surface traps on the metallization layer 116A and / or at the interface 140 can trap charges and reduce the Schottky barrier between the metallization layer 116A and the semiconductor material (e.g., silicon) of the second well region 106 and the fourth well region 110. The reduction of the Schottky barrier can lead to current leakage during the off-state of the diode 100. By using the metal silicide nitride layer 138 on the metal silicide layer 136, the current leakage in the diode 100 can be reduced by about 10% to about 50% compared to a diode without the metal silicide nitride layer 136. Therefore, the device performance of diode 100 can be improved by using metal silicide nitride layer 138 in metallization layers 116A and 116B.

[0036] Figure 1C The following are shown according to some embodiments. Figure 1A and Figure 1B Line AA crosses the nitrogen, metal, and silicon concentration distributions 142, 144, and 146 of ESL126, metal silicide nitride layer 138, metal silicide layer 136, and second well region 106. (As shown) Figure 1C As shown, the peak concentration of nitrogen atoms (distribution 142) is close to the top surface 138s of the metal silicide nitride layer 138. In some embodiments, to sufficiently reduce current leakage in the diode 100, the peak concentration of nitrogen atoms is positioned at a distance D1 from the top surface 138s of the metal silicide nitride layer 138. In some embodiments, the distance D1 can be in the range of about 0.05 nm to about 1 nm. If the distance D1 is greater than 1 nm, the resistivity and / or current leakage of the diode 100 increase, thus degrading device performance.

[0037] refer to Figure 1A-Figure 1BIn some embodiments, for sufficient device performance and minimal current leakage of diode 100, metal silicide layer 136 may have a thickness T1 ranging from about 20 nm to about 40 nm, and metal silicide nitride layer 138 may have a thickness T2 of less than 9 nm (e.g., from about 0.1 nm to about 8.9 nm). In some embodiments, the ratio between thickness T2 and thickness T1 (i.e., T2:T1) may be in the range of about 1:3 to about 1:20.

[0038] The discussion of metallization layers 116A and 116B applies to (i) metallization layers 118A and 118B disposed on the first doped region 112, and (ii) metallization layers 120A and 120B disposed on the second doped region 114, unless otherwise stated.

[0039] STI region 122 can be configured to electrically isolate anode region 101A from cathode region 101B, and to electrically isolate cathode region 101B from body region 101C. In some embodiments, STI region 122 may include an insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), other suitable insulating materials, and combinations thereof. In some embodiments, the STI region 122 may be disposed within the substrate 102, and the top surface of the STI region 122 may be substantially coplanar with the top surface 102s of the substrate 102. In some embodiments, the top surface of the STI region 122 may be substantially coplanar with the top surface 138s of the metal silicide nitride layer 138, such as... Figure 1A As shown, or it can be substantially coplanar with interface 140, such as Figure 1B As shown. In some embodiments, interface 140 may be located at a plane (not shown) above the top surface of STI region 122. In some embodiments, the dimension (e.g., height) of STI region 122 along the Z-axis may be smaller than the dimension (e.g., height) of fourth well region 110 along the Z-axis. In some embodiments, the dimension (e.g., height) of STI region 122 along the Z-axis may be larger than the dimension (e.g., height) of first doped region 112 and second doped region 114 along the Z-axis.

[0040] In some embodiments, dielectric layer 124 may include an oxide layer and may be configured to control the resistivity of diode 100. The resistivity can be controlled by adjusting the dimension (e.g., length) of dielectric layer 124 along the X-axis. Extending the dimension (e.g., length) of dielectric layer 124 along the X-axis to reduce the distance D2 between dielectric layers 124 can increase the resistivity of diode 100. Additionally, adjusting the distance D2 between dielectric layers 124 can control the dimension of metallization layers 116A and 116B along the X-axis, and thus control the resistivity of diode 100.

[0041] In some embodiments, ESL 126 may include an insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), other suitable insulating materials, and combinations thereof. ESL 126 protects the underlying layer from subsequent processing of the ILD layer 128 and / or the contact structures 130, 132, and 134 of the diode 100 and / or other structures (e.g., interconnect structures) on the diode 100 and / or the substrate 102. In some embodiments, ESL 126 may have a thickness T3 in the range of about 5 nm to about 10 nm to adequately protect the underlying layer without affecting device size and manufacturing cost. In some embodiments, the ratio (i.e., T2:T3) between the thickness T2 of the metal silicide nitride layer 138 and the thickness T3 of ESL 126 may be in the range of about 1:20 to about 1:40.

[0042] In some embodiments, the ILD layer 128 may include an insulating material, such as silicon oxide (SiO2). x The contact structures 130, 132, and 134 may be disposed on the metal silicide nitride layer 138 through the ILD layer 128 and ESL 126. Each of the contact structures 130, 132, and 134 may include a conductive material having a low resistivity (e.g., about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), other suitable low-resistivity conductive materials, and combinations thereof. In some embodiments, the dimension (e.g., width) of contact structure 130 along the X-axis may be greater than the dimension (e.g., width) of contact structures 132 and 134 along the X-axis.

[0043] Figure 2It is according to some embodiments for manufacturing having Figure 1A and Figure 1B The flowchart of an example method 200 for manufacturing a diode 100, shown in the cross-sectional view, is provided. For illustrative purposes, reference will be made to methods for manufacturing such diodes. Figures 3-21 The example manufacturing process of diode 100 is described below. Figure 2 The operation shown. Figures 3-19 This is a cross-sectional view of diode 100 at various manufacturing stages according to some embodiments. Figures 20-21 The crystal structure of the cap layer used in the fabrication of diode 100 according to some embodiments is shown. Operations may be performed in different orders or not at all, depending on the specific application. It should be noted that method 200 may not produce a complete diode 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and some other processes may only be briefly described herein. Figures 3-21 It has with Figures 1A-1B The elements in the same label are those described above.

[0044] In operation 205, an isolation region is formed in the substrate. For example, as... Figure 3 As shown, an STI region 122 is formed in substrate 102. Forming the STI region 122 may include the following sequential operations: (i) forming a trench (not shown) in substrate 102, (ii) depositing an insulating material layer within the trench to fill the trench (not shown), and (iii) performing a chemical mechanical polishing (CMP) process on the insulating material layer to form... Figure 3 The structure.

[0045] refer to Figure 2 In operation 210, a well region is formed in the substrate. For example, as shown in reference... Figures 4-6 As described, a first well region 104, a second well region 106, a third well region 108, and a fourth well region 110 are formed in substrate 102. Forming the well regions may include the following sequential operations: (i) forming a patterned masking layer 447 on STI region 122, such as... Figure 4 As shown, (ii) an n-type dopant is implanted into the substrate 102 to form a first well region 104, as... Figure 4 As shown, (iii) an n-type dopant is implanted into the substrate region above the first well region 104 to form Figure 4 (iv) implanting p-type dopant into the substrate region adjacent to the second well region 106 to form the structure. Figure 5 The structure, (v) from Figure 5 The structure is removed by patterned masking layer 447 (not shown), (vi) forming patterned masking layer 647, as shown Figure 6 As shown, (vii) p-type dopant is implanted through opening 649 to form Figure 6 The structure, and (viii) removal of the patterned masking layer 647.

[0046] refer to Figure 2 In operation 215, doped regions are formed between the isolation regions. For example, as... Figure 7 As shown, a first doped region 112 and a second doped region 114 are formed between STI regions 122. The first doped region 112 can be formed by implanting an n-type dopant into the second well region between the STI regions 122, as shown. Figure 7 As shown. The second doped region 114 can be formed by implanting a p-type dopant into the third well region 108, as shown. Figure 7 As shown. After forming the second doped region 114, it is possible to... Figure 7 The dielectric layer 124 is patterned in structure to form Figure 8 The structure.

[0047] refer to Figure 2 In operation 220, a metallization layer is formed on the well region and the doped region. For example, as referenced... Figures 9-17 As described, metallization layers 116A and 116B are formed on the second well region 106 and the fourth well region 110, metallization layers 118A and 118B are formed on the first doped region 112, and metallization layers 120A and 120B are formed on the second doped region 114. Metallization layers 116A, 118A, and 120A can be formed simultaneously, and metallization layers 116B, 118B, and 120B can be formed simultaneously, as described below.

[0048] Forming metallization layers 116A, 118A, and 120A may include the following sequential operations: (i) in Figure 8 Depositing a metal layer 948 on the structure to form Figure 9 The structure, (ii) in Figure 9 The structure is deposited with a cap layer 1050 to form Figure 10 The structure, (iii) for Figure 10 The structure simultaneously undergoes thermal annealing and surface treatment processes, such as Figure 11 As shown, to form Figure 12 The structure, and (iv) removing the cap layer 1050 and the unreacted metal layer 1248 to form Figure 14 The structure.

[0049] Similarly, forming metallization layers 116B, 118B, and 120B may include the following sequential operations: (i) in Figure 8 Depositing a metal layer 948 on the structure to form Figure 9 The structure, (ii) in Figure 9 The structure is deposited with a cap layer 1050 to form Figure 10 The structure, (iii) for Figure 10 The structure undergoes thermal annealing and surface treatment processes, such as Figure 11 As shown, forming Figure 13 The structure, and (iv) removing the cap layer 1050 and the unreacted metal layer 1248 to form Figure 15 The structure. The unreacted metal layer 1248 is the portion of metal layer 948 that has not been converted into silicide.

[0050] In some embodiments, the thermal annealing process may include applying a rapid thermal annealing process to the sample at a temperature of about 550°C to about 850°C. Figure 10 The structure is annealed. The thermal annealing process can initiate a silicide reaction between the metal layer 948 and the semiconductor material (e.g., silicon) of the second well region 106, the third well region 108, and the fourth well region 110 to form a metal silicide layer 136, such as... Figure 12 or Figure 13 As shown. The top surface of the metal silicide layer 136 may have dangling bonds, which can create surface traps, as explained above. A surface treatment process performed concurrently with the thermal annealing process can repair the top surface of the metal silicide layer 136 during the silicide reaction.

[0051] In some embodiments, the surface treatment process may include the flow of nitrogen-based gas 1152 during a thermal annealing process, such as Figure 11 As shown. In some embodiments, the nitrogen-based gas may include nitrogen, ammonia (NH3), nitrous oxide (N2O), or other suitable nitrogen-based gas 1152. Nitrogen atoms may react with the top of the metal silicide layer 136 to form a metal silicide nitride layer 138, such as Figure 12 or Figure 13 As shown. Figure 12 The relative positions of metal silicide layer 136 and metal silicide nitride layer 138 with respect to the top surface 102s of substrate 102 are shown when the unreacted metal layer 1248 remains on metal silicide nitride layer 138. Figure 13 The diagram shows the relative positions of the metal silicide layer 136 and the metal silicide nitride layer 138 with respect to the top surface 102s of the substrate 102 when there is no unreacted metal layer 1248 on the metal silicide nitride layer 138. The presence or absence of an unreacted metal layer 1248 on the metal silicide nitride layer 138 depends on the annealing temperature and duration.

[0052] The capping layer 1050 prevents oxidation of the metallization layers 116A and 116B during the thermal annealing process. In some embodiments, the deposition of the capping layer 1050 may include depositing a metal nitride layer, such as titanium nitride (TiN), tantalum nitride (TaN), and other suitable metal nitride materials. To allow sufficient diffusion of nitrogen atoms through the capping layer 1050 during the surface treatment process, the metal nitride material of the capping layer 1050 is formed with a cubic crystal structure, such as... Figure 20 As shown. Figure 21 As shown, the cubic packing arrangement of metal and nitrogen atoms in the capping layer 1050 allows nitrogen gas to flow through the capping layer 1050 during the surface treatment process. The (100), (200), or (220) crystal planes (not shown) of the top surface 1050s of the capping layer 1050 exposed to the nitrogen gas flow 1152 promote nitrogen atom diffusion through the capping layer 1050. If the capping layer 1050 is formed with other crystal structures, such as a hexagonal close-packed (HCP) structure, the HCP packing arrangement of metal and nitrogen atoms can prevent nitrogen atom diffusion during the surface treatment process.

[0053] In some embodiments, forming a capping layer 1050 having a cubic crystal structure may include forming a metal nitride layer in which the metal to nitrogen concentration ratio is in the range of about 1:3 to about 1:4. If the metal to nitrogen concentration ratio is less than about 1:3, the metal nitride material may have an HCP crystal structure. In some embodiments, the capping layer 1050 may be formed using a physical vapor deposition process using a gas mixture of argon and a nitrogen-based gas, such as nitrogen, ammonia (NH3), nitrous oxide (N2O), or other suitable nitrogen-based gas. In some embodiments, the nitrogen to argon ratio in the gas mixture is in the range of about 2 to about 4 to form a metal nitride material having a cubic crystal structure and a metal to nitrogen concentration ratio of about 1:3 to about 1:4 for the capping layer 1050. If the nitrogen to argon ratio in the gas mixture is outside the range of about 2 to about 4, the metal concentration may increase, and the metal nitride material may have a non-cubic crystal structure, such as an HCP crystal structure.

[0054] refer to Figure 2 In operation 225, a contact structure is formed on the metallization layer. For example, as... Figure 18 and Figure 19 As shown, contact structures 130, 132, and 134 can be formed on the metal silicide nitride layer 138 through the ESL 126 and the ILD layer 128. Before forming contact structures 130, 132, and 134, the ESL 126 can be formed on... Figure 14 or Figure 15 Structurally, to form separately Figure 16 or Figure 17The structure is as follows. Following the formation of ESL 126, the formation of ILD layer 128 may occur. Forming contact structures 130, 132, and 134 may include the following sequential operations: (i) forming contact openings (not shown) within ILD layer 128 and ESL 126, (ii) depositing conductive material within the contact openings, and (iii) performing a CMP process on the conductive material to form... Figure 18 or Figure 19 The structure.

[0055] This disclosure provides an example diode (e.g., diode 100) and an example method of forming the same (e.g., method 200). The diode may include a metallization layer (e.g., metallization layers 116A-116B) disposed on a semiconductor substrate. In some embodiments, the metallization layer may include a stack of metal silicide nitride layers (e.g., metal silicide nitride layer 138) and metal silicide layers (e.g., metal silicide layer 136).

[0056] In some embodiments, the metal silicide layer can be formed via a silicide process between a metal layer (e.g., metal layer 948) and a semiconductor material of the substrate. In some embodiments, during a surface treatment process of the metallization layer performed concurrently with the silicide process, the top of the metal silicide layer can be converted into a metal silicide nitride layer. This surface treatment process may include introducing nitrogen atoms into the metallization layer through a capping layer (e.g., capping layer 1050) disposed on the metallization layer. The capping layer may comprise a metal nitride material (e.g., TiN) and may prevent oxidation of the metallization layer during the silicide process.

[0057] In some embodiments, to allow sufficient diffusion of nitrogen atoms through the capping layer during the surface treatment process, the metal nitride material of the capping layer is formed with a cubic crystal structure. The cubic packing arrangement of the metal and nitrogen atoms in the capping layer allows nitrogen gas to flow through the capping layer during the surface treatment process. In some embodiments, forming the capping layer with the cubic crystal structure may include using a gas mixture of argon and nitrogen-based gases to form a metal nitride layer in which the concentration ratio of metal to nitrogen is in the range of about 1:3 to about 1:4.

[0058] In some embodiments, surface current leakage in a diode having a stack of metal silicide nitride layers and metal silicide layers can be reduced by about 10% to about 50% compared to a diode without a metal silicide nitride layer in the metallization layer.

[0059] In some embodiments, a semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopant, the second well region includes a second type of dopant different from the first type of dopant, and the array of well regions includes the second type of dopant. The semiconductor device also includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

[0060] In some embodiments, a semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The semiconductor device further includes a silicide layer disposed on the array of well regions and within the substrate, a silicide nitride layer disposed on the substrate, and a contact structure disposed on the silicide nitride layer.

[0061] In some embodiments, a method includes forming a first well region having a first type of dopant within a substrate, and forming an array of well regions having a second type of dopant within the first well region. The second type of dopant is different from the first type of dopant. The method also includes forming a metal silicide layer on the well region array and within the substrate, forming a metal silicide nitride layer on the metal silicide layer and within the substrate, and forming a contact structure on the metal silicide nitride layer.

[0062] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to perform the formation of contact structures on a metal silicide nitride layer to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0063] Example 1 is a semiconductor device comprising: a substrate; a first well region disposed within the substrate, wherein the first well region includes a first type of dopant; a second well region disposed adjacent to the first well region and within the substrate, wherein the second well region includes a second type of dopant different from the first type of dopant; a well region array disposed within the first well region, wherein the well region array includes the second type of dopant; a metal silicide layer disposed on the well region array and within the substrate; a metal silicide nitride layer disposed on the metal silicide layer and within the substrate; and a contact structure disposed on the metal silicide nitride layer.

[0064] Example 2 is the semiconductor device described in Example 1, wherein a first portion of the metal silicide layer is disposed on the well region array, and a second portion of the metal silicide layer is disposed on the first well region.

[0065] Example 3 is the semiconductor device described in Example 1, and further includes an etch stop layer disposed on the metal silicide nitride layer.

[0066] Example 4 is the semiconductor device described in Example 1, wherein the peak concentration of nitrogen atoms in the metal silicide nitride layer is separated from the top surface of the metal silicide nitride layer by a distance of about 0.05 nm to about 1 nm.

[0067] Example 5 is the semiconductor device described in Example 1, wherein the top surface of the metal silicide nitride layer is substantially coplanar with the top surface of the substrate.

[0068] Example 6 is the semiconductor device described in Example 1, wherein the interface between the metal silicide layer and the metal silicide nitride layer is located in a plane below the top surface of the substrate.

[0069] Example 7 is the semiconductor device described in Example 1, wherein the ratio between the thickness of the metal silicide nitride layer and the thickness of the metal silicide layer is about 1:3 to about 1:20.

[0070] Example 8 is the semiconductor device described in Example 1, further comprising a doped region disposed on the first well region and within the substrate, wherein the doped region comprises a dopant of the first type.

[0071] Example 9 is the semiconductor device described in Example 8, further comprising: another metal silicide layer disposed on the doped region and within the substrate; and another metal silicide nitride layer disposed on the other metal silicide layer and within the substrate.

[0072] Example 10 is the semiconductor device described in Example 1, wherein the metal silicide layer comprises cobalt silicide, and the metal silicide nitride layer comprises cobalt silicide nitride.

[0073] Example 11 is a semiconductor device comprising: a substrate; a first well region disposed within the substrate; a second well region disposed adjacent to the first well region and within the substrate; a well region array disposed within the first well region; a silicide layer disposed on the well region array and within the substrate; a silicide nitride layer disposed on the substrate; and a contact structure disposed on the silicide nitride layer.

[0074] Example 12 is the semiconductor device described in Example 11, wherein the top surface of the silicide layer is substantially coplanar with the top surface of the substrate.

[0075] Example 13 is the semiconductor device described in Example 11, wherein the interface between the silicide layer and the silicide nitride layer is substantially coplanar with the top surface of the substrate.

[0076] Example 14 is the semiconductor device described in Example 11, and further includes an etch stop layer disposed on the silicide nitride layer.

[0077] Example 15 is the semiconductor device described in Example 11, wherein the ratio between the thickness of the silicide nitride layer and the thickness of the silicide layer is about 1:3 to about 1:20.

[0078] Example 16 is the semiconductor device described in Example 11, wherein the peak concentration of nitrogen atoms in the silicide nitride layer is separated from the top surface of the silicide nitride layer by a distance of about 0.05 nm to about 1 nm.

[0079] Example 17 is a method of manufacturing a semiconductor device, comprising: forming a first well region having a first type of dopant in a substrate; forming an array of well regions having a second type of dopant in the first well region, wherein the second type of dopant is different from the first type of dopant; forming a metal silicide layer on the well region array and in the substrate; forming a metal silicide nitride layer on the metal silicide layer and in the substrate; and forming a contact structure on the metal silicide nitride layer.

[0080] Example 18 is the method of Example 17, wherein forming the metal silicide layer includes depositing a metal layer on the well region array.

[0081] Example 19 is the method described in Example 18, wherein forming the metal silicide layer includes forming a capping layer.

[0082] Example 20 is the method described in Example 19, wherein forming the cap layer includes depositing a nitride layer having a cubic crystal structure.

Claims

1. A semiconductor device, comprising: Substrate; A first well region is disposed within the substrate, wherein the first well region includes a first type of dopant; A second well region is configured to be adjacent to the first well region and within the substrate, wherein the second well region includes a second type of dopant that is different from the first type of dopant; A well region array is disposed within the first well region, wherein the well region array includes the second type of dopant; A metal silicide layer is disposed on the well region array and within the substrate; A metal silicide nitride layer is disposed on the metal silicide layer and within the substrate; and The contact structure is disposed on the metal silicide nitride layer.

2. The semiconductor device according to claim 1, wherein, A first portion of the metal silicide layer is disposed on the well region array, and a second portion of the metal silicide layer is disposed on the first well region.

3. The semiconductor device according to claim 1 further includes an etch stop layer disposed on the metal silicide nitride layer.

4. The semiconductor device according to claim 1, wherein, The peak concentration of nitrogen atoms in the metal silicide nitride layer is separated from the top surface of the metal silicide nitride layer by a distance of 0.05 nm to 1 nm.

5. The semiconductor device according to claim 1, wherein, The top surface of the metal silicide nitride layer is substantially coplanar with the top surface of the substrate.

6. The semiconductor device according to claim 1, wherein, The interface between the metal silicide layer and the metal silicide nitride layer is located in a plane below the top surface of the substrate.

7. The semiconductor device according to claim 1, wherein, The ratio between the thickness of the metal silicide nitride layer and the thickness of the metal silicide layer is 1:3 to 1:

20.

8. The semiconductor device of claim 1, further comprising a doped region disposed on the first well region and within the substrate, wherein, The doped region includes the first type of dopant.

9. The semiconductor device according to claim 8, further comprising: Another metal silicide layer is disposed on the doped region and within the substrate; as well as Another metal silicide nitride layer is disposed on the other metal silicide layer and within the substrate.

10. The semiconductor device according to claim 1, wherein, The metal silicide layer includes cobalt silicide, and the metal silicide nitride layer includes cobalt silicide nitride.

11. A semiconductor device, comprising: Substrate; A first well region is disposed within the substrate, wherein the first well region includes a first type of dopant; A second well region is configured to be adjacent to the first well region and within the substrate, wherein the second well region includes a second type of dopant that is different from the first type of dopant; A well region array is disposed within the first well region, wherein the well region array includes the second type of dopant; A silicide layer is disposed on the well region array and within the substrate; A silicide nitride layer is disposed on the substrate; and The contact structure is disposed on the silicide nitride layer.

12. The semiconductor device according to claim 11, wherein, The top surface of the silicide layer is substantially coplanar with the top surface of the substrate.

13. The semiconductor device according to claim 11, wherein, The interface between the silicide layer and the silicide nitride layer is substantially coplanar with the top surface of the substrate.

14. The semiconductor device of claim 11, further comprising an etch stop layer disposed on the silicide nitride layer.

15. The semiconductor device according to claim 11, wherein, The ratio between the thickness of the silicide nitride layer and the thickness of the silicide layer is 1:3 to 1:

20.

16. The semiconductor device according to claim 11, wherein, The peak concentration of nitrogen atoms in the silicide nitride layer is separated from the top surface of the silicide nitride layer by a distance of 0.05 nm to 1 nm.

17. A method for manufacturing a semiconductor device, comprising: A first well region with a first type of dopant is formed within the substrate; An array of well regions with a second type of dopant is formed within the first well region, wherein the second type of dopant is different from the first type of dopant; A metal silicide layer is formed on the well region array and within the substrate; A metal silicide nitride layer is formed on the metal silicide layer and within the substrate; and A contact structure is formed on the metal silicide nitride layer.

18. The method according to claim 17, wherein, Forming the metal silicide layer involves depositing a metal layer on the array of well regions.

19. The method according to claim 18, wherein, Forming the metal silicide layer includes forming a capping layer.

20. The method according to claim 19, wherein, Forming the cap layer includes depositing a nitride layer having a cubic crystal structure.

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