Method, apparatus and storage medium for outputting a frequency-multiplied signal with high harmonic rejection

Abstract

Embodiments of the present application provide a method and device for outputting a frequency multiplication signal with high harmonic suppression and a storage medium. The method comprises: obtaining an initial signal; inputting the initial signal into a target circuit, wherein the target circuit comprises a parallel circuit, a frequency multiplier is arranged on a first circuit of the parallel circuit, a phase adjustment module is arranged on a second circuit of the parallel circuit, the first circuit is connected with an input end and an output end of the target circuit, the second circuit is kept disconnected with the input end and the output end, the phase adjustment module is used to adjust the phase of the second circuit to a target phase, and the phase difference between the target phase and a first phase of the first circuit is greater than 90 degrees; and taking a target signal output by the target circuit as a frequency multiplication signal of the initial signal. Through the present application, the problem of high harmonic of the output frequency multiplication signal is solved, and the spectral purity of the output frequency multiplication signal is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and more specifically, to a method, apparatus, and storage medium for outputting high harmonic suppression harmonic signals. Background Technology

[0002] In existing technologies, during the output of frequency-multiplied signals, such as when a second harmonic signal is needed, the initial signal is directly input into the frequency seconder, which then outputs the second harmonic signal. However, during this process, the frequency seconder also outputs the initial signal, third harmonic signal, fourth harmonic signal, and so on. This results in a low harmonic rejection ratio for the output frequency-multiplied signal. Summary of the Invention

[0003] This invention provides a method, apparatus, and storage medium for outputting a harmonic suppression frequency signal, so as to at least solve the problem of low harmonic suppression ratio of the output harmonic signal in the related art.

[0004] According to an embodiment of the present invention, a method for outputting a frequency-multiplied signal is provided, comprising: acquiring an initial signal; inputting the initial signal into a target circuit, wherein the target circuit includes a parallel circuit, a frequency multiplier is disposed on a first circuit of the parallel circuit, a phase adjustment module is disposed on a second circuit of the parallel circuit, the first circuit is connected to the input and output terminals of the target circuit, the second circuit is kept disconnected from the input and output terminals, the phase adjustment module is used to adjust the phase of the second circuit to a target phase, the phase difference between the target phase and the first phase of the first circuit is greater than 90 degrees; and using the target signal output by the target circuit as the frequency-multiplied signal of the initial signal.

[0005] According to another embodiment of the present invention, an apparatus for outputting a frequency multiplier signal is provided, comprising: a target circuit, the target circuit including a parallel circuit, a frequency multiplier disposed on a first circuit of the parallel circuit, a phase adjustment module disposed on a second circuit of the parallel circuit, the first circuit being connected to the input and output terminals of the target circuit, the second circuit being disconnected from the input and output terminals, the phase adjustment module being used to adjust the phase of the second circuit to a target phase, the phase difference between the target phase and the first phase of the first circuit being greater than 90 degrees, and the target circuit being used to multiply an input initial signal to a frequency multiplier signal of the initial signal.

[0006] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0007] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0008] This invention, by incorporating a phase adjustment module, adjusts the phase of the second circuit to a phase difference greater than 90 degrees from the phase of the first circuit. Furthermore, by disconnecting the phase adjustment module in the second circuit and connecting the frequency multiplier in the first circuit, the phase adjustment module can cancel out interference signals output by the frequency multiplier in the first circuit, resulting in a purer frequency multiplier signal. This solves the problem of low harmonic suppression ratio in the output frequency multiplier signal, thereby improving the spectral purity of the output frequency multiplier signal. Attached Figure Description

[0009] Figure 1 This is a hardware structure diagram of a method for outputting a frequency multiplication signal according to an embodiment of the present invention;

[0010] Figure 2 This is a flowchart of a method for outputting a frequency-doubled signal according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of the system structure of the method for outputting a frequency-doubled signal according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of the system structure of the method for outputting a frequency-doubled signal according to an embodiment of the present invention;

[0013] Figure 5 This is a circuit diagram of a frequency multiplier for a method of outputting a frequency multiplier signal according to an embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram of the gain and harmonic suppression ratio of a traditional balanced double frequency converter;

[0015] Figure 7 This is a schematic diagram of the frequency conversion gain and harmonic suppression ratio of the first and second frequency multipliers in the method of outputting frequency multiplier signals according to an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram of the fundamental harmonic suppression ratio comparison curve of the method for outputting a frequency-doubled signal according to an embodiment of the present invention;

[0017] Figure 9 This is a schematic diagram of the target circuit of the device for outputting a frequency multiplication signal according to an embodiment of the present invention. Detailed Implementation

[0018] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] The methods and embodiments provided in this application can be executed on a mobile terminal, a computer terminal, or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal for a method of outputting a frequency-multiplying signal according to an embodiment of the present invention. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0021] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the method for outputting a frequency multiplication signal in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0022] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0023] Optionally, such as Figure 2 As shown, the above method for outputting a frequency-multiplied signal includes:

[0024] S202, Obtain the initial signal;

[0025] S204, the initial signal is input into the target circuit, wherein the target circuit includes a parallel circuit, a frequency multiplier is provided on the first circuit of the parallel circuit, and a phase adjustment module is provided on the second circuit of the parallel circuit. The first circuit is connected to the input and output terminals of the target circuit, and the second circuit is kept disconnected from the input and output terminals. The phase adjustment module is used to adjust the phase of the second circuit to the target phase, and the phase difference between the target phase and the first phase of the first circuit is greater than 90 degrees.

[0026] S206, the target signal output by the target circuit is used as a frequency multiplier signal of the initial signal.

[0027] Optionally, the above-described method for outputting a frequency-multiplied signal can be applied, but is not limited to, to the process of multiplying the initial signal. The frequency multiplier is selected based on the desired frequency multiplication factor. For example, when obtaining a second-multiplication signal, the second frequency multiplier can be connected in parallel with a phase adjustment module. The phase adjustment module is kept disconnected from the circuit, while the phase adjustment module is connected to the circuit. The phase adjustment module adjusts the phase of the second circuit to the target phase, resulting in a phase difference of more than 90 degrees between the second and third circuits. Since the phase difference between the first and second circuits is more than 90 degrees, the second circuit can generate a signal opposite to the first circuit, canceling out interference signals generated by the frequency multiplier during the frequency multiplication process. This makes the frequency-multiplied signal purer and improves the spectral purity of the output frequency-multiplied signal.

[0028] Optionally, the phase adjustment module is further configured to set the harmonic amplitude of the second circuit to a harmonic amplitude whose difference from the harmonic amplitude of the first circuit is less than a first threshold.

[0029] If the difference in harmonic amplitudes between the two circuits is small, it ensures that the interference signal from the first circuit is canceled out by the signal from the second circuit as much as possible, thereby improving the harmonic suppression ratio of the output harmonic signal. It should be noted that setting the harmonic amplitude of the second circuit to be such that the difference between its amplitude and that of the first circuit is less than a first threshold actually means that, under the combined action of the phase adjustment module and the open switch, the difference between its harmonic amplitude and that of the first circuit is less than the first threshold.

[0030] Optionally, the phase difference between the target phase and the first phase is 180 degrees. If the second circuit and the first circuit are 180 degrees out of phase, it means that the phases are completely opposite, which can cancel out as much interference signal from the first circuit as possible.

[0031] Optionally, the phase adjustment module is a phase shifter, an inverter, or an amplifier. That is, the phase adjustment module in this embodiment can be any device, circuit, or module unit capable of adjusting the phase; this embodiment is not limited to any particular type.

[0032] The first circuit is connected to the input and output terminals via a single-pole double-throw (SPDT) switch. Optionally, if the SPDT switch is connected to the first circuit of the target circuit, the initial signal can be multiplied by the frequency multiplier of the first circuit. During this process, the second circuit is disconnected, and the phase adjustment module of the second circuit can cancel out some interference signals. If the SPDT switch is connected to the second circuit of the target circuit, the initial signal can be obtained by passing through the second circuit. During this process, the first circuit can cancel out some interference signals, achieving the effect of filtering the output initial signal.

[0033] Optionally, the frequency multiplier is a first second frequency multiplier, and a second second frequency multiplier is connected after the output terminal. The step of using the target signal output by the target circuit as the frequency multiplier signal of the initial signal includes:

[0034] With the first circuit connected to the input and output terminals of the target circuit, and the second circuit disconnected from the input and output terminals, the initial signal passes through the first and second frequency multipliers to output a quadruple frequency signal.

[0035] With the input and output terminals of the first circuit and the target circuit remaining disconnected, and the second circuit connected to the input and output terminals, the initial signal passes through the phase adjustment module and the second frequency multiplier to output a frequency-doubled signal.

[0036] This embodiment achieves the effect of improving the harmonic suppression ratio of the output harmonic signal during the process of acquiring the harmonic signal of the initial output signal.

[0037] The following example illustrates the method for outputting a frequency-multiplying signal.

[0038] This application's embodiments relate to harmonic suppression in the frequency multiplier of a local oscillator link. This application's embodiments propose a target circuit. For example... Figure 3 The system framework diagram of the circuit shows that the target circuit includes: a single-pole double-throw switch 304, a phase adjustment module 306, and a frequency multiplier 308. The single-pole double-throw switch is connected to the frequency multiplier 308, and the phase adjustment module 306 is disconnected. The fundamental harmonic (initial signal) is input at input terminal 302, passes through the frequency multiplier 308, and is output as a second harmonic at output terminal (the frequency multiplier 308 is a double frequency multiplier).

[0039] As an optional example, in the target circuit of this application embodiment, the parallel circuit is connected to a frequency doubler. For example... Figure 4 As shown. Figure 4 In the diagram, f0 represents the fundamental harmonic, the phase shifter is the phase adjustment module, RFin is the fundamental harmonic input segment, RFout is the fundamental harmonic output segment, and x2 doubler1 and x2 doubler2 are frequency doublers. The arrows indicate signal strength and direction.

[0040] when Figure 4 When the system is in x2 operating mode, the single-pole double-throw switch is on at the dashed line position and off at the solid line position. The signal passes through the phase shifter in the first-stage parallel branch and the cascaded frequency multiplier in the second stage. When the system is in x4 operating mode, the single-pole double-throw switch is on at the solid line position and off at the dashed line position. The signal passes through the cascaded frequency multiplier in the first stage and the cascaded frequency multiplier in the second stage. The x2 operating mode means that the input is the fundamental harmonic and the output is the second harmonic, while the x4 operating mode means that the input is the fundamental harmonic and the output is the fourth harmonic.

[0041] Compared with traditional frequency multiplexing systems, the improved scheme proposed in this application not only does not increase the hardware area occupied, but also improves the overall harmonic suppression ratio.

[0042] The novel x2 and x4 frequency multiplier multiplexing system includes two single-pole double-throw (SPD) switches, two-stage frequency multipliers, and a phase shifter. The two SPD switches control the selection of different paths in the first stage under different scenarios. Frequency multiplier x2doubler1 multiplies the input signal from f0 to 2f0, and frequency multiplier x2doubler2 multiplies the input signal from 2f0 to 4f0.

[0043] When the single-pole double-throw switch is switched to the solid line, x2 doubler1 in the first-stage circuit is turned on. The signal passes through two frequency multipliers to achieve a fourfold frequency multiplication, realizing a fourfold frequency multiplication of the input signal from f0 to 4f0. At this time, the phase shifter on the other path and the two open switches together generate a small signal that is superimposed in reverse with the output signal of the first-stage frequency multiplier, which can suppress harmonics and thus improve the overall harmonic rejection ratio of the fourfold frequency multiplier. In the design of the frequency multiplier, even-order harmonic components are easily suppressed by differential circuits, while fundamental harmonics, especially those close to the useful output spectrum and the third harmonic, are more difficult to suppress. In addition, the fundamental harmonic (f0) of the first-stage frequency multiplier will mix with the fundamental harmonic (2f0) and second harmonic (4f0) of the second-stage frequency multiplier to generate new spectral components. Therefore, improving the fundamental harmonic rejection ratio of the frequency multiplier can significantly improve the overall performance of the frequency multiplier.

[0044] When the single-pole double-throw switch is set to the dotted line, the phase shifter in the first-stage circuit is turned on, which has almost no side effects on the spectrum of the input signal. The signal is cascaded through the phase shifter and x2 doubler2 to achieve frequency doubling, and the gain brought by the phase shifter also improves the gain, flatness, and harmonic suppression of the frequency doubling.

[0045] Combining principles Figure 4 Let me continue explaining.

[0046] Input a pure sine signal Acos(ω0t) at the system input terminal, where ω0=2πf0. Consider the case where both single-pole double-throw switches are at the solid line position, i.e., the first-stage frequency multiplier is turned on.

[0047] Ignoring the losses introduced by the switching, the signal at node 2 is Acos(ω0t). After passing through the first-stage frequency multiplier, the signal at node 3 is:

[0048] a1cos(ω0t)+a2cos(2ω0t)+a3cos(3ω0t)+a4cos(4ω0t)+…

[0049] Where a2 is the amplitude of the output signal, a1 is the amplitude of the fundamental harmonic, a3 is the amplitude of the third harmonic, and a4 is the amplitude of the fourth harmonic. In actual operation, a2 is close to 1, while a1, a3, and a4 are close to zero. That is to say, the ideal result is an output of a2cos(2ω0t), but there will be other signal interference. The phase shifter reduces this interference.

[0050] Since both single-pole double-throw switches are turned on in the frequency multiplier path and turned off in the phase shifter path, the switches have a certain isolation IL from the input port to the open port. This causes the signal amplitude at node 4 to be attenuated by IL. Similarly, after passing through the second switch, the signal amplitude will be attenuated by another IL. Assuming the phase shifter gain is 1, then the signal at node 5 is b1cos(ω0t).

[0051] Figure 4 The phase shifter in the circuit is adjustable, ensuring that the phases at f0 are opposite at nodes 5 and 3. Therefore, the signal at node 6 is:

[0052] |a1-b1|cos(ω0t)+a2cos(2ω0t)+a3cos(3ω0t)+a4cos(4ω0t)+…

[0053] The fundamental harmonic suppression of the first-stage frequency multiplier from nodes 1 to 6 is significantly improved. For the quadruple frequency multiplier, the spectrum of the input signal becomes "clean," and the harmonic suppression of the output signal is also improved.

[0054] Consider the second scenario: both single-pole double-throw switches are located at the dashed lines, meaning the branch containing the first-stage frequency multiplier is not conducting. When the signal passes through the phase shifter cascaded with the second-stage frequency multiplier, ignoring the losses from the switches, assume the phase shifter gain is 1. Then the signal at node 6 is: Compared to traditional frequency multiplier architectures, the signal amplitude at this node is slightly larger, which increases the output power of the output signal after cascading with the second-stage frequency multiplier.

[0055] Considering that the chip area occupied by the phase shifter cannot be eliminated when the entire system is cascaded, the introduction of the phase shifter will not bring additional area.

[0056] For example, design doubler1 as a doubler with an input frequency of 3.5GHz-6.5GHz and doubler2 as a doubler with an input frequency of 7GHz-13GHz. When the system operates in quadruple mode, the two doublers are cascaded, with an input frequency of 3.5GHz-6.5GHz and an output frequency of 14GHz-26GHz. When the system operates in double mode, the phase shifter and the second doubler are cascaded, with an input frequency of 7GHz-13GHz and an output frequency of 14GHz-26GHz.

[0057] The advantages of the frequency multiplier architecture used in this invention are explained by adopting a balanced frequency multiplier architecture. The circuit diagram of the frequency multiplier is shown below. Figure 5 As shown, it consists of a single-stage balanced frequency multiplier and a single-stage buffer. Vcas is the gate voltage of the cascode transistor, Vgm is the gate voltage of the common-source transistor, and Vdd is the operating voltage of the circuit.

[0058] The frequency conversion gain and harmonic suppression of the first-stage frequency doubler are, for example... Figure 6 As shown. H2 is the second harmonic power, which is the required second harmonic signal. HR1 is the fundamental harmonic rejection ratio (CHR), HR3 is the third harmonic rejection ratio (CHR), and HR4 is the fourth harmonic rejection ratio (CHR). Within the frequency band of interest, the frequency multiplier's conversion gain is -1dB to 3dB; the fundamental harmonic rejection ratio (CHR) of the frequency multiplier, HR1, is above 26dBc, the third harmonic rejection ratio (CHR) of HR3 is above 32dBc, and the fourth harmonic rejection ratio (CHR) of HR4 is above 28dBc. After adding a phase shifter unit to the parallel branch of the first-stage frequency multiplier, its phase change parameter sweep optimization is performed. When the phase change of the phase shifter makes the phase difference between the two paths approximately 180°, the harmonic rejection ratio of the frequency multiplier is significantly improved, and its conversion gain and harmonic rejection ratio are significantly improved. Figure 7 As shown. Within the frequency band of interest, the frequency multiplier's conversion gain is -1dB to 3dB; the fundamental harmonic rejection ratio (HR1) of the frequency multiplier is above 31dBc, the third harmonic rejection ratio (HR3) is above 38dBc, and the fourth harmonic rejection ratio (HR4) is above 28dBc. Clearly, the conversion gain of the improved frequency multiplier remains almost unchanged, but the harmonic rejection ratio is greatly improved, especially in the fundamental harmonic rejection ratio.

[0059] For ease of comparison, the fundamental harmonics of the two are compared side-by-side, such as... Figure 8 As shown, within the frequency band of interest, the fundamental harmonic rejection ratio (WHR) is improved by at least 5 dB, and even at the center frequency of around 5.5 GHz, the WHR is improved by 15 dB.

[0060] The harmonic suppression ratio of the fourth harmonic obtained after cascading two frequency multipliers is affected by the harmonic suppression ratios of the two frequency multipliers. Therefore, the improvement of the harmonic suppression of the first frequency multiplier also indirectly improves the harmonic suppression ratio of the fourth frequency multiplier.

[0061] In this frequency multiplier system that uses frequency doubling and quadruple multiplication, even if the parallel branch of the first-stage frequency multiplier does not introduce phase shifting units such as phase shifters, it still needs to be connected by microstrip lines or coplanar waveguides. Therefore, the introduction of phase shifters does not occupy additional area.

[0062] This invention aims to reduce fundamental harmonic suppression by using the interaction of two circuit structures to synthesize signals in the frequency band of interest, representing a significant innovation in frequency multiplication circuits. This invention is applicable not only to second and fourth harmonic multiplexing systems but also to standalone second harmonic circuits. Furthermore, the harmonic suppression ratio of a second harmonic circuit can be improved by connecting parallel branches; the specific implementation can be found in the first-stage circuit.

[0063] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0064] This embodiment also provides a device for outputting a frequency-multiplying signal, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0065] Optionally, such as Figure 9 As shown, the device includes a target circuit 902. The target circuit includes parallel circuits; a frequency multiplier is installed on the first circuit of the parallel circuit, and a phase adjustment module is installed on the second circuit of the parallel circuit. The first circuit is connected to the input and output terminals of the target circuit, while the second circuit remains disconnected from both the input and output terminals. The phase adjustment module is used to adjust the phase of the second circuit to the target phase. The phase difference between the target phase and the first phase of the first circuit is greater than 90 degrees. The target circuit is used to multiply the input initial signal to a frequency-multiplied signal.

[0066] For other examples of this embodiment, please refer to the examples above, which will not be repeated here.

[0067] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0068] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0069] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0070] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0071] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0072] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for outputting a high harmonic suppression harmonic-frequency harmonic signal, characterized in that, include: Obtain the initial signal; The initial signal is input into the target circuit, wherein the target circuit includes a parallel circuit, a frequency multiplier is provided on the first circuit of the parallel circuit, and a phase adjustment module is provided on the second circuit of the parallel circuit. The phase adjustment module is used to adjust the phase of the second circuit to the target phase, and the phase difference between the target phase and the first phase of the first circuit is greater than 90 degrees. With the first circuit connected to the input and output terminals of the target circuit via two single-pole double-throw switches respectively, the second circuit remains disconnected from both the input and output terminals. The single-pole double-throw switches have a certain isolation IL from their input ports to their open-circuit ports. The signal amplitude attenuates by IL as it passes through the input port of the first single-pole double-throw switch to its open-circuit port; the signal amplitude attenuates again by IL as it passes through the open-circuit port of the second single-pole double-throw switch to its output port. The target signal output by the target circuit is used as a frequency multiplier of the initial signal.

2. The method according to claim 1, characterized in that, The phase adjustment module is further configured to set the harmonic amplitude of the second circuit to a harmonic amplitude whose difference from the harmonic amplitude of the first circuit is less than a first threshold.

3. The method according to claim 1, characterized in that, The phase difference between the target phase and the first phase is 180 degrees.

4. The method according to claim 1, characterized in that, The phase adjustment module is a phase shifter, an inverter, or an amplifier.

5. The method according to any one of claims 1 to 4, characterized in that, The frequency multiplier is a first second frequency multiplier, and a second second frequency multiplier is connected after the output terminal. The step of using the target signal output by the target circuit as the frequency multiplier signal of the initial signal includes: With the first circuit connected to the input and output terminals of the target circuit, and the second circuit disconnected from the input and output terminals, the initial signal passes through the first and second frequency multipliers to output a quadruple frequency signal. With the input and output terminals of the first circuit and the target circuit remaining disconnected, and the second circuit connected to the input and output terminals, the initial signal passes through the phase adjustment module and the second frequency multiplier to output a frequency-doubled signal.

6. A device for outputting a high harmonic suppression harmonic-frequency harmonic signal, characterized in that, include: The target circuit includes a parallel circuit. A frequency multiplier is provided on the first circuit of the parallel circuit, and a phase adjustment module is provided on the second circuit of the parallel circuit. The phase adjustment module is used to adjust the phase of the second circuit to the target phase. The phase difference between the target phase and the first phase of the first circuit is greater than 90 degrees. With the first circuit connected to the input and output terminals of the target circuit via two single-pole double-throw switches respectively, the second circuit remains disconnected from both the input and output terminals. The single-pole double-throw switches have a certain isolation IL from their input ports to their open-circuit ports. The signal amplitude attenuates by IL as it passes through the input port of the first single-pole double-throw switch to its open-circuit port; the signal amplitude attenuates again by IL as it passes through the open-circuit port of the second single-pole double-throw switch to its output port. The target circuit is used to multiply the input initial signal to a frequency-multiplied signal of the initial signal.

7. The apparatus according to claim 6, characterized in that, The frequency multiplier on the first circuit is a first and second frequency multiplier, and the device further includes: The second frequency multiplier is connected in series with the parallel circuit. With the first circuit connected to the input and output terminals of the target circuit, and the second circuit disconnected from the input and output terminals, the initial signal passes through the first and second frequency multipliers to output a quadruple frequency signal. With the input and output terminals of the first circuit and the target circuit remaining disconnected, and the second circuit connected to the input and output terminals, the initial signal passes through the phase adjustment module and the second frequency multiplier to output a frequency-doubled signal.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 5.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 5.

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