Integrated circuit with input multiplexer system

Abstract

An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjustment circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuits, and more specifically, to an integrated circuit having an input multiplexer system. Background Technology

[0002] In typical data acquisition systems, an input multiplexer (MUX) is followed by a programmable gain amplifier (PGA) for buffering and gain scaling of the signal before digitization using an analog-to-digital converter (ADC). However, the slew rate capability of amplifiers is typically limited. While the switching speed of an input MUX can be fast, the switching speed of a data acquisition system is generally limited by the slew rate of the input amplifier. That is, the input signal is typically slowed down significantly based on worst-case scenarios to allow the conversion amplifier to operate within its safe operating range and stabilize at the target accuracy of the ADC digitization. This limits the switching speed of the input MUX system. Therefore, there is a need for an input MUX system that can improve the switching speed for any given slew rate-limited amplifier while maintaining accuracy. Summary of the Invention

[0003] The following are various embodiments of the present invention.

[0004] In one embodiment, an integrated circuit includes: a multiplexer circuit configured to provide an output signal on a conductive line; a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer; a slew rate adjustment circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier; a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier; and a low-pass filter connected between the first terminal and the second terminal of the first switch. In one aspect, the slew rate adjustment circuit includes a current source including a first terminal coupled to a first supply voltage and a second terminal coupled to a first terminal of a second switch; the second switch includes a second terminal coupled to the first node. In another aspect, the integrated circuit further includes an overvoltage detection circuit coupled between the second terminal of the second switch and the first node, wherein an overvoltage signal output by the overvoltage detection circuit is provided to the multiplexer circuit. In another aspect, the overvoltage detection circuit includes: a first comparator having a non-inverting input coupled to a second supply voltage higher than the first supply voltage and an inverting input coupled to a second terminal of the second switch; a second comparator having a non-inverting input coupled to the second terminal of the second switch and an inverting input coupled to a third supply voltage lower than a fourth supply voltage; and a logic gate including a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator, wherein the output of the logic gate is the overvoltage signal. In another aspect, the low-pass filter includes: a resistive element including a first terminal coupled to the first node and a second terminal coupled to the second terminal of the first switch; and a capacitive element including a first terminal coupled to the second terminal of the resistive element and a second terminal coupled to ground. In another aspect, the slew rate adjustment circuit is a pull-up circuit, and the first supply voltage is a positive supply voltage. In another aspect, the slew rate adjustment circuit is a pull-down circuit, and the first supply voltage is a negative supply voltage. In yet another aspect, the integrated circuit further includes an anti-parallel diode coupled to the non-inverting and inverting inputs of the programmable gain amplifier. In another aspect, the integrated circuit further includes an analog-to-digital converter, which includes an input coupled to the output of the programmable gain amplifier.

[0005] In another embodiment, an integrated circuit includes: a multiplexer including a plurality of inputs, a first control input, and an output; a programmable gain amplifier coupled to the output of the multiplexer; a slew rate adjustment circuit coupled to the programmable gain amplifier, the slew rate adjustment circuit including: a current source including a first terminal coupled to a supply voltage and a second terminal coupled between the output of the multiplexer and the programmable gain amplifier; and an analog-to-digital converter coupled to the output of the programmable gain amplifier. In one aspect, the integrated circuit further includes: a clamping circuit coupled to the programmable gain amplifier; and a first switch including a first terminal connected to the output of the multiplexer and a second terminal connected to an input of the clamping circuit. In another aspect, the integrated circuit further includes a second switch including a first terminal coupled to a second terminal of the current source and a second terminal coupled to the first terminal of the first switch. In yet another aspect, the integrated circuit further includes an overvoltage detection circuit coupled between the second terminal of the second switch and the first terminal of the first switch, wherein an overvoltage signal output by the overvoltage detection circuit is provided as a control input to the multiplexer. In another aspect, the overvoltage detection circuit includes: a first comparator having a non-inverting input coupled to a second supply voltage higher than the first supply voltage and an inverting input coupled to a second terminal of the second switch; a second comparator having a non-inverting input coupled to the second terminal of the second switch and an inverting input coupled to a third supply voltage lower than a fourth supply voltage; and a logic gate including a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and the output of the logic gate being the overvoltage signal. In another embodiment, the slew rate adjustment circuit is one of the following: a pull-up circuit, where the first supply voltage is a positive supply voltage, and a pull-down circuit, where the first supply voltage is a negative supply voltage.

[0006] In yet another embodiment, an integrated circuit includes: a multiplexer including a plurality of inputs, outputs, and control inputs; a programmable gain amplifier including a first input, a second input, and an output; a first switch including a first terminal coupled to the output of the multiplexer and a second terminal coupled to the first and second inputs of the programmable gain amplifier; and a low-pass filter circuit including a resistive element and a capacitive element, the resistive element being coupled in parallel with the first switch, and the capacitive element including a second terminal coupled to the first switch and a first terminal coupled to ground. In one aspect, the integrated circuit further includes a control circuit system configured to place the first switch in an open position when a signal changes at the output of the multiplexer, and to place the first switch in a closed position after a predetermined time period. In another aspect, the predetermined time period is based on a previous output of the multiplexer and an output from the next channel of the multiplexer. In yet another aspect, the time constant of the low-pass filter has a time constant proportional to the slew rate of the programmable gain amplifier. In another aspect, the integrated circuit further includes: a clamping circuit coupled to the programmable gain amplifier; and an analog-to-digital converter including an input coupled to the output of the programmable gain amplifier. Attached Figure Description

[0007] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which the same reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0008] Figure 1 An input MUX system with an input MUX according to an embodiment of the present invention is shown in block diagram form.

[0009] Figure 2-4 This is an illustration of an embodiment of the present invention. Figure 1 Timing diagrams of various signals within the input MUX system.

[0010] Figure 5 An embodiment of the present invention is shown in the form of partial schematic diagrams and partial block diagrams. Figure 1 The implementation scheme for input MUX.

[0011] Figure 6 A timing diagram according to an embodiment of the present invention is shown, the timing diagram illustrating the use of Figure 5 Implementation of input MUX Figure 1 The input signals within the MUX system.

[0012] Figure 7Another embodiment of the present invention is shown in the form of partial schematic diagrams and partial block diagrams. Figure 1 The implementation scheme for input MUX.

[0013] Figure 8 A timing diagram according to another embodiment of the present invention is shown, the timing diagram illustrating the use of Figure 7 Implementation of input MUX Figure 1 The input signals within the MUX system. Detailed Implementation

[0014] In one aspect, to provide an improved input MUX system capable of high-speed switching, the output of the MUX is pulled up to a positive supply voltage or pulled down to ground or a negative supply voltage during the break-before-make time that occurs when the input MUX switches from one input channel to another. In another aspect, an additional switch connected in parallel with a resistor is inserted between the MUX output and the PGA input, such that when the switch is open, the resistor, together with a capacitor coupled to the PGA input, forms a resistor-capacitor (RC) filter between the MUX output and the PGA input; however, once the switch is closed, the resistor is short-circuited to charge the capacitor more quickly. Therefore, in one embodiment, when the input MUX switches to the next input channel, the switch is initially open, and then, after a predetermined amount of time, closes while still selecting the next input. These aspects can be used independently or in combination to provide an input MUX system with high-speed switching.

[0015] Figure 1An input MUX system 100 according to an embodiment of the present invention is shown. System 100 is coupled to a first power supply terminal configured to provide a first supply voltage (VDD) and a second power supply terminal configured to provide a second supply voltage (VEE). VDD is greater than VEE, where VEE can be a negative supply voltage or ground. VEE can also be referred to as VSS. It should be noted that the first power supply terminal can simply be referred to as VDD, and the second power supply terminal can simply be referred to as VEE. System 100 includes external pins 110a-d and 111a-b (also referred to as external terminals). Pin 111a corresponds to the first power supply terminal supplying VDD, and pin 111b corresponds to the second power supply terminal supplying VEE. System 100 includes a protection diode 112, an input MUX 114, a unity-gain amplifier 140, a gain unit 142, an analog-to-digital converter (ADC) 144, and control circuitry 130. The unity-gain amplifier 140, together with the gain unit 142, forms a programmable gain amplifier (PGA), where the input of amplifier 140 corresponds to the input of the PGA, and the output of the gain unit corresponds to the output of the PGA. In one embodiment, everything from external pins 110 and 111 to the right side of system 100 can be implemented on a single integrated circuit (IC).

[0016] System 100 includes four input channels, each receiving a corresponding analog input signal AIN1-AIN4 via a corresponding pin 110. System 100 receives each of the signals AIN1-AIN4 through a corresponding input RC filter, which includes corresponding resistors 106a-106d and corresponding capacitors 108a-108d. These input RC filters are typically located off-chip and may therefore not be included as part of system 100. Input MUX 114 has four inputs, each coupled to a corresponding input channel to receive one of AIN1-AIN4, and coupled to an output on a conductor that provides a selected one of AIN1-AIN4 as MUXOUT to circuit node 130. MUX 114 includes four switches, each coupled between an input channel and an output. For example, switch 1 (SW1) provides AIN1 as MUXOUT when closed, switch 2 (SW2) provides AIN2 as MUXOUT when closed, switch 3 (SW3) provides AIN3 as MUXOUT when closed, and switch 4 (SW) provides AIN4 as MUXOUT when closed. In operation, one of SW1-SW4 can be closed to provide a selected one of AIN1-4 as MUXOUT, wherein the switch control signals SC1-SC4 can be provided to each of SW1-SW4 respectively through the control circuit 150.

[0017] Although System 100 and MUX 114 are in Figure 1 The MUX 114 is shown as having four input channels and four MUX inputs, but system 100 may include any number of N input channels (and therefore N pins 110), where MUX 114 will have N MUX inputs coupled to the output of MUX 114 via N corresponding switches. The value N can be any integer greater than or equal to two. It should be noted that during operation, only one switch of MUX 114 can be closed (i.e., turned on) at a given time, so that input signals do not collide on MUXOUT.

[0018] for Figure 1 Any switch (e.g., switches SW1-SW4, SS, SD, and SE) will close or turn on when the corresponding switch control signal is asserted, making the switch in a conducting state; and will turn off or turn off when the switch control signal is negated (or deasserted), making the switch in a non-conducting state. Therefore, the use of turning on or off the switches is interchangeable, as is the use of turning off or turning off the switches.

[0019] Still referencing Figure 1 System 100, protection diode 112 (also known as an ESD clamping diode) includes a diode coupled between each input channel and VDD (where the diode cathode is coupled to VDD) and a diode coupled between each input channel and VEE (where the diode anode is coupled to VEE). In one embodiment, Zener diode 102 is coupled between pin 111a and ground, and Zener diode 104 is coupled between pin 111b and ground. The cathode of diode 102 is coupled to pin 111a and the anode is coupled to ground, and the anode of diode 104 is coupled to pin 111b and the cathode is coupled to ground. Diodes 102 and 104 may be located off-chip, and therefore outside system 100. Protection diode 112 is an on-chip clamping diode that shunts current to VDD and VEE during a surge event (or during an electrostatic discharge (ESD) event), and diodes 102 and 104 provide additional off-chip protection by shunting current to ground.

[0020] In the illustrated embodiment, system 100 includes pull-up circuit 152 and pull-down circuit 153. However, an integrated circuit designed using system 100 will only include one of pull-up circuit 152 or pull-down circuit 153. Alternatively, the integrated circuit may have both pull-up circuit 152 and pull-down circuit 153, but one of the pull-up or pull-down circuits is disabled, such that only one of the pull-up or pull-down circuits can operate within system 100.

[0021] Pull-up circuit 152 includes current source IDD 118 and switch SD 126. A first terminal of IDD 118 is coupled to VDD, and a second terminal of IDD 118 is coupled to a first terminal of SD 126. The second terminal of SD 126 is coupled to circuit node 130. SD 126 is controlled by a control signal SCSD provided by control circuit 150. Pull-down circuit 153 includes current source IEE 124 and switch SE 128. A first terminal of SE 128 is coupled to circuit node 130, and a second terminal of SE 128 is coupled to a first terminal of IEE 124. The second terminal of IEE 124 is coupled to VEE. SE 128 is controlled by a control signal SCSE provided by control circuit 150. It should be noted that, depending on whether there is a pull-up circuit 152 or a pull-down circuit 153 in system 100, control circuit 150 provides only one of SCSD or SCSE. Therefore, the control signal provided by control circuit 150 is labeled "SCSD / SCSE" to indicate that one or the other control signal is provided.

[0022] System 100 includes amplifier 140, which receives an analog amplifier input signal AMPIN at a non-inverting input and provides an output signal AMPOUT at an output. The output of amplifier 140 is coupled to the inverting input of amplifier 140. A pair of anti-parallel diodes 138 are coupled between the non-inverting and inverting inputs of amplifier 140. The analog amplifier output signal AMPOUT is provided to gain unit 142. Gain unit 142 has a programmable gain, and the amplified analog output of gain unit 142 is provided to ADC 144. Thus, amplifier 140 and gain unit 142 together form a PGA, where AMPIN is provided to the input of the PGA, and the output of the PGA is provided to ADC 144. ADC 144 converts the analog signal from gain unit 142 into an M-bit digital output ADCOUNT, where M corresponds to the conversion accuracy. That is, the larger the value of M, the higher the conversion accuracy.

[0023] System 100 includes a switch SS 132, a resistor RS 134, and a capacitor CS 136. SS 132 has a first terminal coupled to circuit node 130 and a second terminal coupled to the non-inverting input of amplifier 140. SS 132 is controlled by a switch control signal SCSS provided by control circuit 150. RS 134 is coupled in parallel with SS 132, with a first terminal coupled to circuit node 130 and a second terminal coupled to the non-inverting input of amplifier 140. CS 136 has a first terminal coupled to the non-inverting input of amplifier 140 and a second terminal coupled to ground.

[0024] System 100 also includes an overvoltage detection circuit 148, which includes comparators 154 and 156, and an OR gate 158. Comparator 154 receives a low voltage threshold voltage VTL at a first input (e.g., a non-inverting input) and a second input (e.g., an inverting input) coupled to circuit node 130. Comparator 156 receives a high voltage threshold voltage VTH at a first input (e.g., an inverting input) and a second input (e.g., a non-inverting input) coupled to circuit node 130. The output of comparator 154 provides an overvoltage indicator OVL based on VTL, and the output of comparator 156 provides an overvoltage indicator OVH based on VHL. In the illustrated embodiment, comparators 154 and 156 are implemented with hysteresis. The first input of OR gate 158 is coupled to the output of comparator 154, and the second input of OR gate 158 is coupled to the output of comparator 156. The output of OR gate 158 provides an overvoltage indicator OV. The OV is provided to MUX 114.

[0025] In operation, system 100 receives an analog input signal from an input source from one of its channels, and control circuit 150 asserts the corresponding switch control signal to close the corresponding switch. In this way, the received analog signal is provided as MUXOUT of circuit node 130. For example, if analog input signal AIN1 is received, SC1 is asserted to close SW1, such that AIN1 is provided as MUXOUT. When the next analog input signal (e.g., AIN2) is received, SC1 is negated to open SW1, and the switch corresponding to the next analog input signal (e.g., SW2) closes, such that the next analog input signal (e.g., AIN2) is provided as MUXOUT. MUXOUT is provided as AMPIN of amplifier 140 (when SS 132 is closed) or via an RC filter formed by RS 134 and CS 136 as AMPIN of amplifier 140 (when SS 132 is open). The PGA, formed by amplifier 140 and gain unit 142, buffers and amplifies the received input analog signal and provides the amplified signal to ADC 144, which converts the amplified signal into a digital signal ADCOUT.

[0026] When MUX 114 switches from one input source to another, there are no pull-up circuits 152 and 153, nor are SS 132 and RS 134 (where node 130 is connected to the non-inverting input of amplifier 140, so that MUXOUT is directly provided as AMPIN). Due to the change in voltage level in the input analog signal, a step function pulse is generated on AMPIN at the non-inverting input of amplifier 140. Amplifier 140 has limited slew rate capability and cannot handle fast switching at its input. Anti-parallel diodes 138 clamp the input of amplifier 140 for device protection, ensuring that all devices operate within safe voltage limits during this switching condition; however, when these anti-parallel diodes are triggered, a large current is drawn from the input source. This interferes with the voltage level of the input voltage, thus requiring a longer time for the PGA to re-stabilize. Therefore, the various components of system 100 help to address the problems caused by MUX 114 switching between input sources (and therefore input channels).

[0027] The following will combine Figure 2-4 The timing diagram describes the operation of system 100 in more detail, including the operation of pull-up circuit 152 or pull-down circuit 153 and SS 132 and RS 134. To address the slew rate limitation of amplifier 140, in a first aspect, pull-up circuit 152 or pull-down circuit 153 is used during the break-before-make time of MUX 114. For the asymmetric slew rate of amplifier 140, MUXOUT is pulled up or pulled down during the make-before-break time. In the case of a positive slew rate that is faster than a negative slew rate, pull-down circuit 153 is used in system 100. In this case, pull-up circuit 152 is not required in system 100. In the case of a negative slew rate that is faster than a positive slew rate, pull-up circuit 152 is used in system 100 (and pull-down circuit 153 is not required in system 100). A positive slew rate corresponds to a ramp-up slew rate from a lower voltage level to a higher voltage level, and a negative slew rate corresponds to a ramp-down slew rate from a higher voltage level to a lower voltage level. Therefore, pull-up circuit 152 and pull-down circuit 153 can also be referred to as slew rate adjustment circuits.

[0028] Figure 2The diagram illustrates a pull-up or pull-down signal occurring during the connect-then-disconnect time in system 100 according to the first aspect, wherein waveform 206 corresponds to MUXOUT when pull-up circuit 152 is present in system 100, and waveform 208 corresponds to MUXOUT when pull-down circuit 153 is present in system 100. As mentioned above, one of pull-up circuit 152 or pull-down circuit 153 can be selected at design time to be included in system 100, and this decision can be made based on the worst-case positive and negative slew rates of amplifier 140 within a particular die group (e.g., wafer or batch). It should be noted that in this embodiment, SCSS is asserted to keep SS 132 always on (e.g., closed).

[0029] refer to Figure 2 At time t1, SC1 is asserted to turn on (e.g., close) SW1 of MUX 114 so that AIN1 is provided as MUXOUT. Therefore, as seen in waveforms 206 and 208, MUXOUT increases to the voltage level of AIN1 after SW1 is closed. With SS132 on and thus in its on state, MUXOUT is directly provided as AMPIN of the PGA. ADCOUT is generated based on AIN1. After switching from the input source of AIN1 to the input source of AIN2 in MUX 114, SC1 is first negated at time t2 to turn off (e.g., disconnect) SW1. Note that the parallel interrupt line indicates that SW1 can be turned on for any time length (and therefore MUXOUT remains at the AIN1 level for the same time length). Turning off SW1 at time t2 begins from the turn-on-off time 202. The turn-on-off time 202 can be set to a predetermined duration and is controlled by control logic 150. It should be noted that the turn-on / off time 202 is typically shorter than the on-time of any switch (e.g., SW1) in MUX 114. During the turn-on / off time 202, MUXOUT is pulled to VDD or VEE. In the case of waveform 206, at time t2, SCSD is asserted to turn on (e.g., close) SD 121, thereby enabling IDD 118 to pull MUXOUT at node 130 up to VDD. In the case of waveform 208, at time t2, SCSE is asserted to turn on (e.g., close) SE 128, thereby enabling IEE 124 to pull MUXOUT at node 130 down to VEE.

[0030] After the turn-on / turn-off time, control logic 150 asserts SC2 at time t3, thus turning on SW2 of MUX 114 so that AIN2 is now provided as MUXOUT. Therefore, in waveform 206, MUXOUT drops from VDD to the voltage level of AIN2, and in waveform 208, MAXOUT rises from VEE to the voltage level of AIN2. Because MUXOUT is pulled up or down before SW2 is turned on, amplifier 140 is able to operate at its highest slew rate. An external input RC low-pass filter (corresponding to resistor 106 and capacitor 108) can also be sized to loosely match the slower slew edges of amplifier 140 to low-pass filter fast steps of the signal at the active input channel (e.g., the channel for AIN2).

[0031] When switching from the input source of AIN2 to the input source of AIN3 in MUX 114, a turn-on / turn-off time 204 is used between turning off SW2 and turning on SW3, starting at time t4. Similarly, parallel interrupt lines indicate that SW2 and SS 132 can remain on for any length of time (and therefore MUXOUT remains at the AIN2 level for the same length of time). During the turn-on / turn-off time 204 (which can be the same predetermined duration as turn-on / turn-off time 202), MUXOUT is pulled up to VDD again (as shown in waveform 206) or pulled down to VEE (as shown in waveform 208). After the turn-on / turn-off time 204, at time t5, SW3 turns on and SS 132 turns on.

[0032] By using a pull-up-before-drop time between changes in the input channels of MUX 114 to pull up or pull down MUXOUT, system 100 can avoid triggering the anti-parallel diode 138. This prevents large current draw and the resulting increase in the settling time of the PGA. An additional pull-up-before time occurs between each switch turn-off in MUX 114 and the turn-on of another switch in MUX 114, but its duration is less than the increase in settling time required to trigger the anti-parallel diode 138. Therefore, pulling up or pulling down MUXOUT between switches in the input channels of MUX 114 can produce faster switching without sacrificing accuracy in ADCOUT. It should be noted that in one embodiment where pull-up circuit 152 or pull-down circuit 153 is present, SS 132 and RS 134 may be absent, such that node 130 is connected to the non-inverting input of amplifier 140. The duration of the pull-up-before time can be determined during design time and programmed into control circuitry 150 so that timing of the switch control signal can be provided accordingly. Alternatively, the duration of the connection-then-disconnect time can be determined and programmed by the control circuit 150 during the operation of system 100.

[0033] Figure 3 The signal in system 100 according to the second aspect is shown, where neither pull-up circuit 152 nor pull-up circuit 154 exists, but SS 132 and RS 134 exist between node 130 and the non-inverting input of amplifier 140. Figure 3 In the process, there is only a minimum turn-on / off time between switching channels using MUX 144. At time t1, SC1 is asserted to turn on SW1, but SS 132 remains off (disconnected). Therefore, starting from time t1, MUXOUT begins to rise toward AIN1. When SS 132 is off, the RC filter formed by RS and CS forms a low-pass filter, where the time constant (corresponding to RS*CS) is matched (or proportional to) the slew rate of amplifier 140. For a short duration after t1, but while SW1 is still selected (i.e., on), SS 132 closes to accelerate the charging of CS by shorting RS. The short duration for which SS 132 is closed after t1 is determined based on the voltage difference between MUXOUT and AMPIN at t1. This can be a predetermined amount of time determined during the design time of system 100 and controlled by control logic 150. Therefore, as in Figure 3 As can be seen, at time t1, MUXOUT rises to AIN1 according to the time constant corresponding to RS*CS.

[0034] When MUX 114 makes its next switch at time t2, SW1 is turned off and SW2 is turned on. When SW1 is turned off, SS132 is also turned off. Since there is no pull-up or pull-down for MUXOUT, at time t2, MUXOUT switches from AIN1 to AIN2 according to the time constant corresponding to RS*CS. After a predetermined short duration starting from time t2 (when SW2 is still selected), SS 132 closes to quickly charge CS. Similarly, at time t3, SW2 and SS 132 are turned off (disconnected) and SW3 is turned on. MUXOUT switches from AIN2 to AIN3 according to the time constant corresponding to RS*CS, and after a predetermined short duration starting from time t3 (when SW3 is still selected), SS 132 closes again. By using SS 132 to short RS 134 at some point after switching to the next input channel from MUX 114, CS 136 charges faster, thus allowing amplifier 140 to stabilize faster compared to not shorting RS 134. It should be noted that while MUX 114 is selecting a channel, the corresponding switch (and SS 132) can remain on for any length of time (and therefore MUXOUT remains at the input level for the same length of time).

[0035] Figure 4The signal in system 100 is shown, which combines, according to a first aspect, the use of pull-up or pull-down circuitry during the connect-then-disconnect time with, according to a second aspect, the use of SS 132 to short-circuit RS 134 shortly after the switch within MUX 114 is turned on, to achieve the advantages of both. This could potentially further improve switching speed without sacrificing ADC accuracy. Figure 4 In the system 100, when pull-up circuit 152 is present, waveform 404 corresponds to MUXOUT, and when pull-down circuit 153 is present in the system 100, waveform 206 corresponds to MUXOUT.

[0036] refer to Figure 4 At time t1, SC1 is asserted to turn on (e.g., close) SW1 of MUX 114 to provide AIN1 as MUXOUT. However, at time t1, SS 132 remains off. Therefore, as seen in waveforms 404 and 406, after SW1 is closed at time t1, MUXOUT begins to transition to the voltage level of AIN1 according to a time constant corresponding to RS*RC (because RS 134 is not short-circuited). At time t2, a predetermined shorter time amount after t1 but while SW1 is still on, SS 132 turns on (e.g., closes), thus allowing MUXOUT to no longer rapidly complete the transition to AIN1 according to the time constant (because RS 134 is short-circuited). Figure 3 As shown, the predetermined shorter time for closing SS 132 after t1 can be determined based on the voltage difference between MUXOUT and AMPIN at t1. It should be noted that, as Figure 2 As shown, the parallel interrupt lines indicate that SW1 and SS 132 can be turned on for any length of time (and therefore MUXOUT remains at the AIN1 level for the same length of time).

[0037] When switching from the input source of AIN1 to the input source of AIN2 in MUX 114, SC2 is first negated at time t3 to turn off (e.g., disconnect) SW1. SS 132 is also turned off at time t3. Turning off SW1 at time t3 begins from the connect-then-disconnect time 402. Like the connect-then-disconnect time 202, the connect-then-disconnect time 402 can be set to a predetermined duration and is controlled by control logic 150. During the connect-then-disconnect time 402, MUXOUT is pulled to VDD or VEE. In the case of waveform 404, at time t3, SD 121 is turned on (closed), allowing IDD 118 to pull MUXOUT at node 130 up to VDD. MUXOUT increases to VDD, where the slope of dV / dt is determined by IDD / CS. In the case of waveform 406, at time t3, SE 128 is turned on (closed), allowing IEE 124 to pull MUXOUT at node 130 down to VEE. MUXOUT decreases to VEE, where the slope dV / dt is determined by IEE / CS.

[0038] After the turn-on / turn-off time, at time t4, SW2 of MUX 114 is turned on so that AIN2 is now provided as MUXOUT. However, at time t4, SS 132 remains off. Therefore, as seen in waveforms 404 and 406, after SW2 is closed at time t4, MUXOUT begins to transition to the voltage level of AIN2 according to the time constant corresponding to RS*RC (because RS 134 is not short-circuited). At time t5, a predetermined shorter time amount after t4 but while SW2 is still on, SS 132 is turned on (e.g., closed), thus allowing MUXOUT to no longer rapidly complete the transition to AIN2 according to the time constant (because RS 134 is short-circuited). It should be noted that, again, the parallel break lines indicate that SW2 and SS 132 can be turned on for any time length (and therefore MUXOUT remains at the AIN2 level for the same time length).

[0039] When switching from the input source of AIN2 to the input source of AIN3 in MUX 114, a turn-on / turn-off time is used starting at time t6, between turning off SW2 and turning on SW3. During this turn-on / turn-off time, MUXOUT is pulled up to VDD again (as shown in waveform 206) or pulled down to VEE (as shown in waveform 208). After the turn-on / turn-off time, SW3 is turned on at time t7, and then SS 132 is turned on at time t8. In this way, the benefits of pull-up to VDD or pull-down to VEE and selective shorting of RS 134 and SS 132 can be obtained.

[0040] Return to reference Figure 1To prevent surge events (which are relatively slow and longer-lasting compared to ESD events), ESD clamping diode 112 shunts the surge current to VDD and VEE, and diodes 102 and 104 clamp VDD and VEE, respectively. Surge tolerance can be improved by using larger ESD devices to clamp the diodes, but this increases the circuit size. Therefore, to further improve the surge tolerance level, overvoltage protection circuit 148 includes a fast-acting comparator that triggers during a surge or fault event and, in response, disconnects all MUX switches connected to MUX 114 at pin 110. For example, if the voltage at node 130 is below VTL, OVL is asserted, and if the voltage at node 130 is above VTH, OVH is asserted. If either comparator is triggered (i.e., if OVL or OVH is asserted), OV is asserted, corresponding to the output of OR gate 158. If OV is asserted, all switches (SW1-SW4) within MUX 114 are turned off (disconnected). In this way, all core circuitry within the IC (e.g., coupled to ADC 144) is protected by isolation. This is similar to having a dedicated circuit breaker where the switches within MUX 114 operate as a circuit breaker if node 130 approaches or exceeds VDD or VEE. Therefore, in one embodiment, VTH is set slightly below VDD, and VTL is set slightly above VEE. While all switches are open in response to the OV assertion to isolate the circuitry within the IC, diodes 112, 102, and 104 continue to operate to handle surge or ESD events. Additionally, it should be noted that overvoltage protection circuitry 148 is disabled during channel switching (e.g., when pull-up circuitry 118 / pull-down circuitry 153 pulls up / pull down MUXOUT). In this way, overvoltage protection circuitry 148 is in active mode while MUX 114 is connected to the active input channel.

[0041] Figure 5 and 7 Each is shown as a portion of the system 100 according to the first aspect, which implements the switches (SW1-SW4) in the MUX 114 as N-type metal-oxide-semiconductor (NMOS) transistors. Figure 5 or P-type metal-oxide-semiconductor (PMOS) transistor ( Figure 7 By using NMOS or PMOS transistors as switches in the MUX 114, the slew rate of the MUXOUT can be further controlled to match the positive slew rate of the amplifier 140 (using an NMOS transistor) or the negative slew rate of the amplifier 140 (using a PMOS transistor). Figure 5 and 7 In the example, the operation of SS 132 and RS 134 can be as described above with reference to the first aspect (e.g., using...). Figure 2 and4 (Timing diagram). Alternatively, SS 132 and RS 134 may be absent, where node 130 is coupled to the non-inverting input of amplifier 140, so that MUXOUT is directly provided as AMPIN. Figure 6 Show and use Figure 5 The timing diagrams corresponding to several signals used in the system 100 embodiment of the MUX114 NMOS implementation are shown, and Figure 8 Show and use Figure 7 The timing diagrams corresponding to several signals used in the implementation of the PMOS scheme of the MUX 114 in system 100 are shown. Figure 6 and 8 In the two timing diagrams, it is assumed that SS 132 and RS 134 exist in system 100.

[0042] refer to Figure 5 , Figure 5 A portion of system 100 is shown, which implements MUX 114 using MUX 114a and includes pull-down circuitry 153 (instead of pull-up circuitry 152). MUX 114a uses NMOS transistors for switching SW1-SW4. Figure 5 As shown, MUX 114a includes MUX 115 with slew rate control circuitry, and each of SW1-SW4 is implemented using an NMOS transistor. Each input signal of AIN1-AIN4 is received via a resistor in MUX 114a to the first current electrode of the corresponding switch of SW1-SW4. The second current electrodes of SW1-SW4 are all connected to circuit node 130 and provide MUXOUT. MUX 115 with slew rate control circuitry receives SC1-SC4 and provides slew rate control voltages SLC[4:1] to the control electrodes of SW1-SW4. The control electrode of each switch receives the corresponding SLC voltage (e.g., SW1 receives SLC1, SW2 receives SLC2, SW3 receives SLC3, and SW4 receives SLC4). (Refer to...) Figure 6 The timing diagram describes the operation.

[0043] exist Figure 6 In this circuit, AIN1 is provided as the input signal for MUX 114a; therefore, SC1 can be asserted to indicate that SW1 should be turned on (closed). MUX 115, with its slew rate control circuitry, provides a voltage as SLC1 to the control electrode of SW1 to turn on SW1. Therefore, as... Figure 6As seen in the second waveform, SLC1 increases from VEE to the voltage level of AIN1 + the NMOS gate-to-source voltage (VGSN) of SW1. The voltage value of SLC1 controls the ramp-up of SLC1 (608) and is set by MUX115 with slew rate control circuitry, such that the ramp-up matches the positive slew rate of amplifier 140. As a result, the voltage level of MUXOUT from VEE ramp-up (602) to AIN1 is limited by the gate voltage level SLC1. It should be noted that when SW1 is controlled to provide AIN1 as MUXOUT, SS 132 is closed, thereby shorting RS 134.

[0044] When the channel switches to AIN2, SLC1 is negated (e.g., set to 0 V to turn off SW1). SE 128 closes to enable pull-down circuit 153, which pulls MUXOUT down to VEE. When SLC1 is negated, SS 132 is also negated. Therefore, the ramp-down (604) of MUXOUT is controlled by IEE 124 and RS 134. During the turn-on-off time (with SE 128 closed), MUXOUT remains at VEE. Subsequently, SC2 is asserted to indicate that SW2 should now be turned on (closed), and MUX 115 with slew rate control circuitry provides the voltage as SLC2. Figure 6 As shown, SLC2 increases from VEE to the voltage level of AIN2 + VGSN of SW2. As previously mentioned, the value of SLC2 controls the ramp-up of SLC2 (610) and is set by MUX 115 with slew rate control circuitry such that the ramp-up matches the positive slew rate of amplifier 140. Therefore, the ramp-up of the voltage level of MUXOUT from VEE to AIN2 (606) is limited by the gate voltage level SLC2. It should also be noted that in this embodiment, SLC1 and SLC2 are at VEE to turn off the corresponding switches, and the rising edges 602 and 606 follow the slopes of the rising edges 608 and 610 of SLC1 and SLC2, respectively.

[0045] Figure 7 They operate in a very similar way, however, Figure 7 System 100 uses pull-up circuit 152 instead of pull-down circuit 153, and implements MUX 114 using MUX 114b, where PMOS transistors instead of NMOS transistors are used to switch SW1-SW4. Figure 7 In this configuration, the SLC voltage is set such that the downslope of the SLC (e.g., 808, 810) is controlled to match the negative slew rate of the amplifier 140. For example, the MUX 115, which has a slew rate control circuit, provides voltage SLC1 to the control electrode of SW1 to turn on SW1, and as... Figure 8As shown, the voltage level of SLC1 (from VDD) decreases to AIN1 – the PMOS gate-to-source voltage (VGSP) of SW1. SLC1 is controlled so that this ramp (808) matches the negative slew rate of amplifier 140. Therefore, the ramp (802) of the MUXOUT voltage level from VDD to AIN1 is limited by the gate voltage level SLC2. It should be noted that, as Figure 6 As shown, when SW1 is controlled to provide AIN1 as MUXOUT, SS 132 closes, thereby short-circuiting RS 134.

[0046] When switching from AIN1 to AIN2, during the connect-before-disconnect time after SW1 is turned off, SD 121 is turned on to pull MUXOUT to VDD. During the connect-before-disconnect time, the ramp-up to VDD (e.g., 804) is controlled by IDD 118 or RS 134. After the connect-before-disconnect time, gate voltage SLC2 is provided to turn on SW2. Figure 8 As shown, SLC2 decreases from VDD to the voltage level of AIN2 – VGSP of SW2. As previously mentioned, the value of SLC2 controls the ramp of SLC2 (810) and is set by MUX 115 with slew rate control circuitry such that the ramp matches the negative slew rate of amplifier 140. Therefore, the ramp (806) of the voltage level of MUXOUT from VDD to AIN2 is limited by the gate voltage level SLC2. It should also be noted that in this embodiment, SLC1 and SLC2 are at VDD to turn off the corresponding switches, and the falling edges 802 and 806 follow the slopes of the falling edges 808 and 810 of SLC1 and SLC2, respectively.

[0047] Therefore, it is now understood how the improved input MUX system can provide high-speed switching regardless of the PGA's conversion rate limitations and without adversely affecting the accuracy of the resulting digital signal. In one embodiment, a pull-up-then-drop time is inserted between changes in the selected input channel by the input MUX, so that the output of the input MUX is pulled up or down after the current input channel is deselected and before the next input channel is selected. This allows for improved settling times for the PGA and ADC of the input MUX system. In another embodiment, a switch connected in parallel with a resistor is added between the output of the input MUX and the input of the PGA, such that the switch can bypass the resistor shortly after the input MUX selects a new input channel (and before deselecting a new input channel) to rapidly charge the capacitor coupled at the input of the PGA. This also achieves improved settling time. Furthermore, as discussed above, both embodiments can be used together within the input MUX system.

[0048] In this document, the terms "assert" or "set" and "negate" (or "cancel assertion" or "clear") are used to refer to a signal, status bit, or similar device to its logical true or logical false state. If the logical true state is logic level one, then the logical false state is logic level zero. And if the logical true state is logic level zero, then the logical false state is logic level one.

[0049] Each signal described herein can be designed as either positive or negative logic, where negative logic is indicated by a hyphen above the signal name or by an asterisk (*) after the name. In the case of a negative logic signal, the signal is active low, where a true logic state corresponds to logic level zero. In the case of a positive logic signal, the signal is active high, where a true logic state corresponds to logic level one. It should be noted that any signal described herein can be designed as either a negative or positive logic signal. Therefore, in alternative embodiments, those signals described as positive logic signals can be implemented as negative logic signals, and those signals described as negative logic signals can be implemented as positive logic signals.

[0050] In this document, brackets are used to indicate the position of conductors or bits of a bus value. For example, “bus 60 [7:0]” or “conductors of bus 60 [7:0]” indicates the eight low-order conductors of bus 60, and “address bits [7:0]” or “address [7:0]” indicates the eight low-order bits of an address value. The symbol “$” preceding a number indicates that the number is represented in hexadecimal or alphanumeric form. The symbol “%” preceding a number indicates that the number is represented in binary or alphanumeric form.

[0051] Since the devices implementing this invention consist mostly of electronic components and circuits known to those skilled in the art, circuit details will not be described to any greater extent than deemed necessary above in order to understand and comprehend the basic concepts of this invention and to avoid obscuring or departing from its teachings.

[0052] Although the invention has been described with respect to the polarity of a particular type of conductivity or potential, those skilled in the art will understand that the polarity of the type of conductivity or potential can be reversed.

[0053] For example, in one embodiment, the elements of the illustrated system 100, except for the input RC filter, are circuit systems located on a single integrated circuit or within the same device. Alternatively, system 100 may include any number of separate integrated circuits or separate devices interconnected with each other.

[0054] Furthermore, those skilled in the art will recognize that the boundaries between the functionalities of the above-described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed across other operations. Additionally, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be modified in various other embodiments.

[0055] While the invention has been described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the invention as set forth in the appended claims. For example, pull-up and pull-down circuits can be implemented using different circuit topologies, and switches can be implemented in various different ways. Furthermore, comparators and logic gates can be implemented in different ways using any number of circuit elements or circuit elements different from those shown. Therefore, this specification and drawings should be viewed in an illustrative rather than restrictive sense, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to a problem described herein with reference to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0056] As used in this article, the term “coupling” is not intended to be limited to direct coupling or mechanical coupling.

[0057] Furthermore, as used herein, the terms “a” or “an” are defined as one or more. Moreover, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed as implying that another claim element introduced by the indefinite article “a” or “an” limits any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrase “one or more” or “at least one” and indefinite articles such as “a” or “an”. The same applies to the use of definite articles.

[0058] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority of these elements.

Claims

1. An integrated circuit, characterized in that, include: A multiplexer circuit configured to provide an output signal on a conductive line; A programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer; A conversion rate adjustment circuit is connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier. A first switch includes a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier; as well as A low-pass filter is connected between the first terminal and the second terminal of the first switch.

2. The integrated circuit according to claim 1, characterized in that, The conversion rate adjustment circuit includes: A current source, comprising a first terminal coupled to a first supply voltage and a second terminal coupled to a first terminal of a second switch; The second switch includes a second end coupled to the first node.

3. The integrated circuit according to claim 2, characterized in that, In addition, including: An overvoltage detection circuit is coupled between the second terminal of the second switch and the first node, wherein the overvoltage signal output by the overvoltage detection circuit is provided to the multiplexer circuit.

4. The integrated circuit according to claim 3, characterized in that, The overvoltage detection circuit includes: A first comparator has a non-inverting input coupled to a second supply voltage higher than the first supply voltage and an inverting input coupled to the second terminal of the second switch; A second comparator has a non-inverting input coupled to the second terminal of the second switch and an inverting input coupled to a third supply voltage lower than the fourth supply voltage; and A logic gate comprising a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and the output of the logic gate being the overvoltage signal.

5. The integrated circuit according to claim 2, characterized in that, The low-pass filter includes: A resistive element comprising a first end coupled to the first node and a second end coupled to the second end of the first switch; and A capacitor element comprising a first end coupled to the second end of the resistive element and a second end coupled to ground.

6. The integrated circuit according to claim 2, characterized in that, The conversion rate adjustment circuit is a pull-up circuit, and the first supply voltage is a positive supply voltage.

7. The integrated circuit according to claim 2, characterized in that, The conversion rate adjustment circuit is a pull-down circuit, and the first supply voltage is a negative supply voltage.

8. The integrated circuit according to claim 1, characterized in that, In addition, including: An anti-parallel diode is coupled to both the non-inverting and inverting inputs of the programmable gain amplifier.

9. An integrated circuit, characterized in that, include: A multiplexer that includes multiple inputs, a first control input, and an output; A programmable gain amplifier coupled to the output of the multiplexer; A slew rate adjustment circuit, coupled to the programmable gain amplifier, includes: A current source, comprising a first terminal coupled to a supply voltage and a second terminal coupled between the output of the multiplexer and the programmable gain amplifier; as well as An analog-to-digital converter coupled to the output of the programmable gain amplifier; The conversion rate adjustment circuit is one of the following: a pull-up circuit, wherein the supply voltage is a positive supply voltage; or a pull-down circuit, wherein the supply voltage is a negative supply voltage.

10. An integrated circuit, characterized in that, include: A multiplexer, which includes multiple inputs, outputs and control inputs; A programmable gain amplifier, comprising a first input, a second input, and an output; A first switch includes a first terminal coupled to the output of the multiplexer and a second terminal coupled to the first input and the second input of the programmable gain amplifier; as well as A low-pass filter circuit includes a resistive element and a capacitive element, the resistive element being coupled in parallel with a first switch, and the capacitive element including a second terminal coupled to the first switch, a first terminal of the resistive element, and a second terminal coupled to ground.

Images