Method and universal flash storage system for performing state switching using selective pass

Abstract

A method and a universal flash storage system for performing state switching using selective path are provided. Embodiments herein provide a method and a UFS system (6000) for performing state switching using a selective path between a first electronic device (100) and a second electronic device (200) in the UFS system (6000). In the proposed method, the first electronic device (100) determines whether a data request is received from an application layer of the first electronic device (100). If the data request is not received from the application layer of the electronic device (100), the first electronic device (100) configures a first path from a plurality of paths between the first electronic device (100) and the second electronic device (200) in an active state, and configures remaining paths from the plurality of paths in a power saving mode to regulate power of the first electronic device (100).

Description

[0001] This application is based on and claims priority to Indian Application No. 202041050543, filed on November 20, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a universal flash storage (UFS) system, and more specifically, to a method and a UFS system for performing state switching using a selective path between a first electronic device and a second electronic device in the UFS system. Background Technology

[0003] Typically, JEDEC Universal Flash Memory (UFS) is specifically tailored for mobile applications and computing systems requiring high performance and low power consumption. JEDEC UFS utilizes technologies from... The Alliance's industry-leading standard MIPI v4.1 Physical Layer Specification and MIPI The v1.8 transport layer specification is used to form the interconnect layer in the UFS system.

[0004] In a UFS system, commands (e.g., read commands, write commands, etc.) are initiated by one end of a link (e.g., DP-DN differential signaling) (referred to as the initiating device), while the other end (referred to as the target device) acts as a slave and processes the commands. To achieve a balance between power consumption and throughput, the UFS system provides multiple speed and power settings with an adjustable number of paths. For example, speed modes adjust the rate of data frames at the initiating device (100) and the target device (200). Speed ​​modes can be, for example, but not limited to, fast mode, fast automatic mode, PWM G1 mode, HSG1 mode, HSG2 mode, HSG3 mode, and HSG4 mode. In one example, in HSG1 mode, the data frame transmission rate is 1248 Mbps. In another example, in HSG2 mode, the data frame transmission rate is 2496 Mbps. Furthermore, the configuration for multiple speed or power settings is primarily determined by the initiating device. During different read operations and write requests that anticipate most data transfer in a single direction, there are provisions in the UFS system to conserve power on opposite sides of the path without compromising the overall throughput of the UFS system.

[0005] In the case of a read operation, the target device receives a data request and waits for the application layer to provide the data needed to send back to the initiating device. This waiting time is called the initiating device's latency and is unknown to the initiating device. During the waiting time, both the initiating and target devices remain in idle mode, wasting power at both ends. Once data is available to be sent from the target device, the initiating device only needs a small amount of bandwidth to send an acknowledgment of the received data; therefore, most of the bandwidth and power is wasted at both the initiating and target devices.

[0006] In the event of a data write request, the target device sends a back UFS specific ready message to transmit a UFS Protocol Information Unit (UPIU). After receiving the round-turn-around time (RTT) UPIU, the initiating device begins and transmits the write data, and again, sending an acknowledgment of the transmitted data from the target device requires only a small bandwidth.

[0007] Figure 1 is a signal timing diagram (S100) illustrating the performance impact in fast mode according to the prior art. Referring to Figure 1, the UFS system provides many speed modes to handle the speed-power trade-off. In fast mode, all paths are always active regardless of data transmission requirements. There is no delay whenever any data is to be transmitted because all paths are always active; however, fast mode does not offer much optimization in terms of power and consumes more power. In Figure 1, the data to be transmitted may include filler characters (FLR).

[0008] Figure 2 is a signal timing diagram (S200) illustrating the performance impact in fast automatic mode according to the prior art. Referring to Figure 2, in fast automatic mode, when there is no data to be transmitted, all paths can enter a power-saving state. There are significant delays in preparation and synchronization lengths during the transition between the power-saving and active states. If the initiating or target device operates in automatic mode and closes all active paths when they are idle, acknowledgments and flow control (AFC) arrive at the initiating device late, affecting the overall throughput of the UFS system. Therefore, fast automatic mode is more power-optimized, but throughput is compromised.

[0009] Figures 3 and 4 are signal timing diagrams illustrating a typical scenario of the initiator TX block according to the prior art.

[0010] According to the standard specification, a device can send 16 incomplete frames without receiving an AFC from the host. After sending the 16 incomplete frames, the host will be blocked from transmitting data. As shown in Figure 3, in this example, since the group ACK is 9, device RX first receives 9 frames, and then only device RX begins sending AFCs for the received data. After receiving the 9 frames, device TX initiates a burst to send AFCs for the first 9 frames. However, since device TX is currently in a save state (auto mode), there is a delay of the prepare plussync length when sending the AFCs for the first 9 frames. This time is greater than the time required for the host to send the remaining 7 frames (16-9). After sending all 16 frames, since the host has not yet received any AFCs, the host will be blocked from transmitting data.

[0011] Now, because the host is blocked from transmitting data, it moves to a save state. After some time, an AFC (Automatic Forwarding Decision) arrives at the host, so the host must again move to a burst state, and the latency for preparing to add synchronization is increased.

[0012] On the device side, after sending an AFC for 9 frames, the device receives the next 7 frames, and then does not receive anything for a period of time because the host is blocked during this period. Therefore, the device TX also switches to a save state.

[0013] The above process is repeated, and the throughput for data transmission is reduced due to the continuous save-burst state switching.

[0014] Referring now to Figure 4, in this example, the group ACK is 7, so the device starts sending an AFC after receiving 7 frames. Because the time to send the remaining 9 frames (16-7) is greater than the save-to-burst transition delay (preparation plus synchronization), the host always receives the AFC before sending all 16 incomplete frames, and therefore is never blocked from transmitting data. Thus, as observed in the above case, there is no additional delay for the redundant save-to-burst transition. However, because of this, the burst is always open in all paths on both the host and device sides. Therefore, there is no power saving.

[0015] Furthermore, referring to Figures 3 and 4, consider conventional methods and systems where data transmission may be blocked because L2 flow control credits / AFCs are not sent back quickly enough. The following are use cases.

[0016] Case 1: If group ACK > 7, then as shown above, the device will switch to stop after sending credit / ACK, and the host will be repeatedly blocked from data transmission, which will affect performance.

[0017] Case 2: The optimal value for group ACK is <= 7, but in this case, if the host is continuously sending data, the device burst will remain on.

[0018] The L2 buffer is calculated as follows.

[0019] Configuration:

[0020] Gear-HSG4 Series-A

[0021] Number of active pathways – 2

[0022] Synchronization length – 1024 bytes

[0023]

[0024]

[0025] Figure 5 is a graph showing the power in burst mode and the power in save mode according to the prior art.

[0026] Figure 5 illustrates the power and delay tradeoff between burst mode and power-saving mode. The horizontal axis represents time, while the vertical axis represents power consumption. Burst mode consumes more power to save power when no data is to be transmitted, and the M-PHY switches to power-saving mode, but there is equal delay when switching back from power-saving mode to burst mode.

[0027] Therefore, a method and a UFS system are needed for performing state switching using a selective path between an initiating device and a target device in a UFS system. Summary of the Invention

[0028] The primary objective of the embodiments herein is to provide a method and a UFS system for performing power-saving state switching using selective paths between a first electronic device and a second electronic device in a UFS system. When no data is available from the local application layer of the first electronic device, all paths except path-0 are switched to the power-saving state. This is independent of the data received by the peer device. For example, when no data is available from the local application layer, all paths except path-0 are switched to the power-saving state. This is independent of the data received by the peer device. Therefore, the UFS system is more power-efficient.

[0029] In the proposed method, when data from the local application layer of the electronic device (initiating device or target device) is available, the electronic device configures multiple paths between the first and second electronic devices to be active to achieve maximum throughput from the first electronic device. Therefore, the UFS system is more optimized in terms of throughput.

[0030] Therefore, this embodiment provides a method for performing power-saving state switching using selective paths between a first electronic device and a second electronic device in a UFS system. The method includes: detecting whether a data request is received from the application layer of the first electronic device. In response to determining that no data request is received from the application layer of the first electronic device, the method includes: configuring a first path from a plurality of paths between the first and second electronic devices in an active state, and configuring the remaining paths from the plurality of paths in a power-saving mode to regulate the power of the first electronic device; and using a first link to send one of an acknowledgment and flow control (AFC) frame and credit information corresponding to the data to the second electronic device. In response to determining that a data request is received from the application layer of the first electronic device, the method includes: configuring the plurality of paths between the first and second electronic devices in an active state to achieve maximum throughput from the first electronic device; and using at least one path from the plurality of links to send the data from the first electronic device to the second electronic device.

[0031] In one embodiment, a data request received from the application layer of the first electronic device indicates one of a data read request and a data write request at the first electronic device.

[0032] In one embodiment, the first electronic device is the initiating device, and the second electronic device is the target device.

[0033] In one embodiment, the first electronic device is the target device, and the second electronic device is the initiating device.

[0034] Therefore, this embodiment provides a UFS system for performing state switching using selective links. The UFS system includes: a first electronic device; and a second electronic device communicatively coupled to the first electronic device using multiple links. The first electronic device includes: a UFS memory configured to support one or more power-saving modes. A path controller is configured to detect whether a data request is received from the application layer of the first electronic device. In response to determining that no data request is received from the application layer of the first electronic device, the path controller configures a first path from the multiple paths between the first and second electronic devices to an active state, and configures the remaining paths from the multiple paths to a power-saving mode to regulate the power of the first electronic device, and uses the first link to send one of the AFC and credit information corresponding to the data to the second electronic device. In response to determining that a data request is received from the application layer of the first electronic device, the path controller configures the multiple paths between the first and second electronic devices to an active state to achieve maximum throughput from the first electronic device, and uses at least one path from the multiple links to send the data from the first electronic device to the second electronic device.

[0035] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and accompanying drawings. However, it should be understood that while the following description indicates preferred embodiments and many specific details thereof, it is given by way of illustration rather than limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the scope of the embodiments herein, and all such modifications are included in the embodiments herein. Attached Figure Description

[0036] The method and UFS system are illustrated in the accompanying drawings, and the same reference numerals indicate corresponding parts in the various drawings. The embodiments herein will be better understood from the following description with reference to the accompanying drawings, in which:

[0037] Figure 1 is a signal timing diagram illustrating the performance impact in fast mode according to the prior art;

[0038] Figure 2 is a signal timing diagram illustrating the performance impact in fast automatic mode according to the prior art;

[0039] Figures 3 and 4 are signal timing diagrams illustrating a typical scenario of the initiator TX block according to the prior art;

[0040] Figure 5 is a graph showing the power in burst mode and the power in power saving mode according to the prior art;

[0041] Figure 6 A proposed UFS system according to embodiments disclosed herein is shown;

[0042] Figure 7a Various hardware components of the initiator device according to embodiments disclosed herein are shown;

[0043] Figure 7b Various hardware components of a target device according to embodiments disclosed herein are shown;

[0044] Figure 8 This illustrates a data flow in a UFS system with state switching in a selective path when the target device is in idle mode, according to an embodiment disclosed herein;

[0045] Figure 9 This illustrates a data flow in a UFS system with state switching in a selective path when the initiating device is in idle mode, according to an embodiment disclosed herein.

[0046] Figure 10 This is a flowchart illustrating a method for performing a state transition in a UFS system using a selective path between a first electronic device and a second electronic device, according to embodiments disclosed herein.

[0047] Figure 11a and Figure 11b This is an example flowchart illustrating various operations for performing state switching using a selective path between a first electronic device and a second electronic device in a UFS system, according to embodiments disclosed herein.

[0048] Figure 12 The differences in energy consumption for fast mode, fast auto mode and proposed schemes for write conditions are shown according to the embodiments disclosed herein;

[0049] Figure 13 The diagram illustrates the energy consumption differences between the fast mode, fast automatic mode, and the proposed scheme for reading scenarios, according to embodiments disclosed herein; and

[0050] Figure 14 This illustrates the calculation of multiple read / write requests for a UFS system based on embodiments disclosed herein. Detailed Implementation

[0051] The embodiments herein, along with their various features and advantageous details, are explained more fully with reference to the non-limiting embodiments illustrated in the accompanying drawings and described in detail below. Descriptions of well-known components and processing techniques have been omitted to avoid unnecessarily obscuring the embodiments herein. Furthermore, since some embodiments can be combined with one or more other embodiments to form new embodiments, the embodiments described herein are not necessarily mutually exclusive. Unless otherwise indicated, the term "or" as used herein means non-exclusive or. The examples used herein are intended only to facilitate understanding of how the embodiments herein can be practiced and to further enable those skilled in the art to practice the embodiments herein. Therefore, the examples should not be construed as limiting the scope of the embodiments herein.

[0052] As is conventional in the art, embodiments can be described and illustrated in terms of blocks that perform one or more functions. These blocks (which may herein be referred to as managers, units, modules, hardware components, etc.) may be physically implemented by analog and / or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and may optionally be driven by firmware and software. For example, the circuitry may be implemented in one or more semiconductor chips or on a substrate support (such as a printed circuit board, etc.). The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Without departing from the scope of disclosure, each block of an embodiment may be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of disclosure, the blocks of an embodiment may be physically combined into more complex blocks.

[0053] Therefore, the embodiments herein will provide a method and a UFS system for performing save state switching using selective paths between a first electronic device and a second electronic device in a UFS system. The method includes the first electronic device detecting whether a data request has been received from the application layer of the first electronic device. In response to determining that no data request has been received from the application layer of the first electronic device, the method includes: configuring a first path from a plurality of paths between the first and second electronic devices in an active state, configuring the remaining paths from the plurality of paths in a power-saving mode to regulate the power of the first electronic device, and transmitting at least one of an AFC frame corresponding to the data and credit information to the second electronic device using a first link (hereinafter, the term "link" may be used interchangeably with the term "path"). In response to determining that a data request has been received from the application layer of the first electronic device, the method includes configuring a plurality of paths between the first and second electronic devices in an active state to achieve maximum throughput from the first electronic device, and transmitting data from the first electronic device to the second electronic device using at least one path from the plurality of links.

[0054] In the proposed method, the first electronic device determines whether it has received a data request from its application layer. If no data request is received from the application layer, the first electronic device configures a first path from multiple channels between the first and second electronic devices to be active, and configures the remaining paths from multiple channels to a power-saving mode to regulate the power consumption of the first electronic device. Therefore, the UFS system is more power-efficient.

[0055] In the proposed method, if a data request is received from the application layer of the first electronic device, the first electronic device configures multiple pathways between itself and the second electronic device to be active, thereby maximizing the throughput from the first electronic device. Therefore, the UFS system is more optimized in terms of throughput.

[0056] Now referring to the accompanying drawings, and more specifically to Figures 5 to 6, in which similar reference numerals throughout the drawings denote the corresponding features. Figure 14 A preferred embodiment is shown.

[0057] Figure 6A proposed UFS system (6000) according to an embodiment disclosed herein is illustrated. The UFS system (6000) includes a first electronic device (100) and a second electronic device (200). The UFS system (6000) may be a flash memory system defined by the Joint Electron Device Engineering Committee (JEDEC) standard, which is designed for high data transfer speeds and low power consumption. In one embodiment, the first electronic device (100) is an initiating device and the second electronic device (200) is a target device. In another embodiment, the first electronic device (100) is a target device and the second electronic device (200) is an initiating device.

[0058] The initiating device and the target device can be flash memory devices. Examples of initiating devices and target devices can be, but are not limited to, smartphones, laptops, tablets, flexible devices, Internet of Things (IoT) devices, etc. The initiating device and the target device can be embedded devices within electronic devices, or can be integrated on a removable card for flexible use with different electronic devices.

[0059] The first electronic device (100) detects whether a data request has been received from the local application layer of the first electronic device (100). In one embodiment, the data request received from the application layer of the first electronic device (100) indicates one of a data read request and a data write request at the first electronic device (100).

[0060] If no data request is received from the local application layer of the first electronic device (100), the first electronic device (100) configures "a first active path from multiple paths between the first electronic device (100) and the second electronic device (200)" and "the remaining paths from multiple paths in power-saving mode to regulate the power of the first electronic device (100)". Paths can be, for example, but not limited to, wireless communication links, serial point-to-point links, transmission lines, copper wires, optical lines, and infrared communication links. A link / path represents a connection between an initiating device and a target device. A path can support one path. Each path represents a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, multiple paths can be aggregated by xN, where N is any supported path width (e.g., 1, 2, 3, 4). Furthermore, the first electronic device (100) uses the first link to transmit at least one of the AFC and credit information corresponding to the data to the second electronic device (200).

[0061] In one embodiment, credit information is used to determine the buffer space available at the peer. For example, if a host wants to send data to a device, the host will use the credit information to check how much buffer space is available at the device and send the data accordingly.

[0062] If a data request is received from the application layer of the first electronic device (100), the first electronic device (100) configures multiple paths between the first electronic device (100) and the second electronic device (200) to be active to achieve maximum throughput from the first electronic device (100). The first electronic device (100) uses at least one path from multiple links to send data from the first electronic device (100) to the second electronic device (200).

[0063] In current UFS systems, despite defining different speed and power-saving states, power is still unnecessarily wasted across multiple paths when application-layer traffic is unavailable and the target device only needs to send AFC (Automatic Facing) data for reception (which requires very little bandwidth). Furthermore, current UFS systems are inflexible in burst-opening / closing dynamically required paths and keeping other paths in power-saving states. Consider the example, see [reference]. Figure 6 The proposed UFS system (6000) operates as follows:

[0064] 1. When the target device only has traffic from the initiating device, the target device's link layer keeps path 0 active to send AFC / credit information to the initiating device, and dynamically shuts down all other active paths in power-saving or energy-saving mode.

[0065] 2. When the target device has traffic from its own application layer, the target device's link layer will dynamically switch all available paths to an active state to achieve the required throughput.

[0066] 3. When the initiating device only has traffic from the target device, the link layer of the initiating device keeps path 0 active to send AFC / credit information to the target device, and dynamically switches the remaining available paths (except path 0) to power-saving mode to save power.

[0067] 4. When the initiating device has traffic from its own application layer, the initiating device's link layer will dynamically switch all available paths to an active state to achieve throughput.

[0068] 5. The initiating and target devices will keep the selective path in a power-saving state based on data traffic, regardless of whether it is a fast mode or a fast automatic dynamic mode.

[0069] Figure 7aVarious hardware components of a first electronic device (100) according to an embodiment disclosed herein are shown. The first electronic device 100 includes a transmitter (110), a receiver (120), a processor (130), a UFS memory (140), and a path controller (150). The processor (130) is combined with the transmitter (110), receiver (120), UFS memory (140), and path controller (150).

[0070] The path controller (150) is configured to detect whether a data request has been received from the application layer of the first electronic device (100). If no data request has been received from the application layer of the first electronic device (100), the path controller (150) configures the first path from the plurality of paths between the first electronic device (100) and the second electronic device (200) to be active, and configures the remaining paths from the plurality of paths to be in power-saving mode to regulate the power of the first electronic device (100). In addition, the path controller (150) uses the first link to send at least one of the AFC and credit information corresponding to the data to the second electronic device (200).

[0071] In one embodiment, the credit information is used to determine the available buffer space at the second electronic device (200). For example, if the host wants to send data to the device, the host will use the credit information to check how much buffer space is available at the device end and send the data accordingly.

[0072] If a data request is received from the application layer of the first electronic device (100), the path controller (150) configures multiple paths between the first electronic device (100) and the second electronic device (200) to be active to achieve maximum throughput from the first electronic device (100). The path controller (150) uses at least one path from multiple links to send data from the first electronic device (100) to the second electronic device (200).

[0073] The access controller (150) is physically implemented by analog or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and may optionally be driven by firmware. The access controller (150) may, for example, be implemented in one or more semiconductor chips or on a substrate support (such as a printed circuit board). The circuitry constituting the block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmable microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block.

[0074] The processor (130) is configured to execute instructions stored in the UFS memory (140) and perform various processes. The processor (130) may include one or more processors. The one or more processors may be general-purpose processors (such as central processing unit (CPU), application processor (AP), etc.), graphics-only processors (such as graphics processing unit (GPU), vision processor (VPU)) and / or AI-specific processors (such as neural processor (NPU)). The processor (130) may include multiple cores and is configured to execute instructions stored in the UFS memory (140).

[0075] One or more processors control the processing of input data based on predefined operating rules or artificial intelligence (AI) models stored in non-volatile and volatile memory. These predefined operating rules or AI models are provided through training or learning.

[0076] The UFS memory (140) also stores instructions to be executed by the processor (130). The UFS memory (140) stores the state of the link. The UFS memory (140) may include non-volatile storage elements. Additionally, in some examples, the UFS memory (140) may be considered a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not implemented with a carrier or propagating signal. However, the term "non-transitory" should not be interpreted as the memory (140) being immovable. In some examples, the memory (140) may be configured to store a larger amount of information. In certain instances, a non-transitory storage medium may (e.g., in random access memory (RAM) or a cache) store data that may change over time.

[0077] The transmitter (110) is configured to communicate internally between internal hardware components and with external devices via one or more networks. The transmitter (110) may be, for example, but not limited to, a Bluetooth transmitter, a Wi-Fi module, and a Li-Fi module. The receiver (120) is configured to communicate internally between internal hardware components and with external devices via one or more networks. The receiver (120) may be, for example, but not limited to, a Bluetooth receiver, a Wi-Fi receiver, and a Li-Fi receiver.

[0078] In addition, the initiator device (100) also includes a memory core, which may include one or more memory banks, arrays and / or other organizations of memory cells designed using flash memory technology (such as NAND flash memory cells).

[0079] although Figure 7aVarious hardware components of the initiating device (100) are shown, but it should be understood that other embodiments are not limited thereto. In other embodiments, the initiating device (100) may include fewer or more components. Furthermore, the labels or names of the components are for illustrative purposes only and do not limit the scope of the invention. One or more components may be combined to perform the same or substantially similar functions for autonomously detecting the status of a pathway between the initiating device (100) and the target device (200) in a UFS system.

[0080] Figure 7b Various hardware components of a second electronic device (200) according to an embodiment disclosed herein are shown. The operation and function of the second electronic device (200) are similar to those of the first electronic device (100). For the sake of brevity, the operation and function of the second electronic device (200) are not repeated.

[0081] Figure 8 This illustrates a hierarchical data flow (S800) in a UFS system (6000) with state switching in a selective path when the target device is in idle mode, according to an embodiment disclosed herein. In S802, when the first electronic device (100) is in a path-1 power-saving state, the physical interface layer of the first electronic device (100) receives a data frame from the second electronic device (200). The physical interface layer of the first electronic device (100) sends the received data frame to a receiver buffer. The receiver buffer stores the received data frame. In S804, the receiver buffer sends the received data to the UFS transport protocol layer of the first electronic device (100). For example, the first electronic device (100) may also include a UFS unified protocol layer for data transmission. In S806, when traffic is arriving at the unipro transmitter buffer from the application layer, unipro activates the physical layer (MPHY) path and sends data. In S808, the UIC layer receives the read data and shares the read data with the UFS transport protocol layer. The UFS transport protocol layer writes the data frame sent from the first electronic device (100). The UFS transport protocol layer passes data frames to the application layer, where the data frames are stored in a receiver buffer. A similar operation is performed in the second electronic device (200) (S810 to S814). For example, the second electronic device (200) may also include a UFS unified protocol layer for data transmission. Data is received at the target device's physical layer and passed to the target device's unipro receiver buffer (S810). Data is then passed from the receiver buffer to the target device's application layer (here, the arrow from the receiver buffer to the target device's application layer is lost). Similarly, data transmission also occurs in the opposite direction.

[0082] like Figure 8The diagram illustrates an example of data transmission between the initiating device and the target device in the proposed concept (in this example, the left side is considered the initiating device, and the right side is considered the target device). Initially, only the initiating device has traffic from its application layer, while the target device has no traffic from its application layer. Therefore, in the direction from the initiating device to the target device, all paths are kept active for maximum throughput, while in the opposite direction only AFC is required, so for maximum power saving, only the path -0 in the target-to-initiating direction is active.

[0083] After some time, the target device also receives traffic from its application layer, so again for maximum throughput, all paths are activated in the direction from the target device to the initiating device.

[0084] In this way, power is saved without compromising throughput.

[0085] Figure 9 This illustrates a hierarchical data flow (S900) in a UFS system (6000) with state switching in a selective path when the initiating device is in idle mode, according to an embodiment disclosed herein. This example is similar to... Figure 8 Here, initially both the target device and the initiating device have traffic from their respective application layers, so all paths are active in both directions. After a certain period of time, traffic stops from the initiating side's application layer, so all lines from the initiating device to the target device, except line -0, switch to a power-saving state. All other functions are similar. Figure 8 .

[0086] In S902, the physical interface layer of the first electronic device (100) receives a data frame from the second electronic device (200). The physical interface layer of the first electronic device (100) sends the received data frame to the receiver buffer (810). The receiver buffer stores the received data frame. In S904, the receiver buffer sends the received data to the UFS transport protocol layer of the first electronic device (100). In S906, when traffic is arriving at the unipro transmitter buffer from the application layer, unipro activates the physical layer (MPHY) and sends data. In S908, the UIC layer receives the read data and shares the read data with the UFS transport protocol layer. The UFS transport protocol layer writes the data frame sent from the first electronic device (100). The UFS transport protocol layer passes the data frame to the application layer, where the data frame is stored in the receiver buffer. Similar operations are performed in the second electronic device (200) (S910 to S914).

[0087] Figure 10This is a flowchart (S1000) illustrating a method for performing a state switching in a UFS system (6000) using a selective path between a first electronic device (100) and a second electronic device (200) according to an embodiment disclosed herein. Operations (S1002 to S1010) are performed by a path controller (150) or a path controller (250).

[0088] In S1002, the method includes determining whether a data request has been received from the application layer of the first electronic device (100). If no data request has been received from the application layer of the first electronic device (100), then in S1004, the method includes configuring a first path from a plurality of paths between the first electronic device (100) and the second electronic device (200) to an active state, and configuring the remaining paths from the plurality of paths to a power-saving mode to regulate the power of the first electronic device (100). In S1006, the method includes using the first link to send one of an AFC frame corresponding to the data and credit information to the second electronic device (200).

[0089] If a data request is received from the application layer of the first electronic device (100), then in S1008, the method includes configuring multiple paths between the first electronic device (100) and the second electronic device (200) to be active to achieve maximum throughput from the first electronic device (100). In S1010, the method includes sending data from the first electronic device (100) to the second electronic device (200) using paths from the multiple links.

[0090] The various actions, movements, blocks, steps, etc. in the flowchart (S1000) can be executed in the presented order, in different orders, or simultaneously. Furthermore, in some embodiments, some actions, movements, blocks, steps, etc., may be omitted, added, modified, or skipped without departing from the scope of the invention.

[0091] Figure 11a and Figure 11bThis is an example flowchart (S1100) illustrating various operations for performing state switching using a selective path between a first electronic device (100) and a second electronic device (200) in a UFS system (6000) according to embodiments disclosed herein. Operations (S1102 to S1126) are performed by a path controller (150) or a path controller (250). In S1102, the method includes activating a path between the first electronic device (100) and the second electronic device (200). In S1104, the method includes changing a power mode. In S1106, the method includes detecting a burst occurrence. In S1108, the method includes determining whether a control request or a data read request has been received. If a control request is received, in S1110, the method includes disabling the burst SFR or shutting down all incoming bursts. If a data read request is received, in S1112, the method includes determining whether all path activations are active. If all path activations are active, in S1120, the method includes processing the data read request. If not all activated channels are active, then in S1114, the method includes activating all channels. If a control request is received, then in S1116, the method includes determining whether channel-0 is active. If channel-0 is active, then in S1120, the method includes processing the control request. If channel-0 is not active, then in S1118, the method includes activating channel-0. In S1122, the method includes determining whether a data read request is pending. If a data read request is pending, then in S1108, the method includes determining whether a control request or a data read request has been received. If a data read request is not pending, then in S1124, the method includes determining whether channel-1 is active. If channel-1 is active, then in S1126, the method includes closing channel-1. If channel-1 is not active, then in S1108, the method includes determining whether a control request or a data read request has been received.

[0092] The various actions, movements, blocks, steps, etc. in the flowchart (S1100) can be executed in the presented order, in different orders, or simultaneously. Furthermore, in some embodiments, some of the actions, movements, blocks, steps, etc., can be omitted, added, modified, or skipped without departing from the scope of the invention.

[0093] Figure 12 The energy consumption differences for fast mode, fast auto mode, and the proposed scheme for write scenarios are shown according to the embodiments disclosed herein. During a single data write request, the initiating device operates in HSG4 Series-A mode, the data frame size of the initiating device is 256KB, and the total path of the initiating device is 2. Furthermore, the following are the energy saving levels:

[0094] 1. Regarding Fast Mode – 21.16%

[0095] 2. Regarding the Quick Auto Mode – 21.10%

[0096] A comparison of energy consumption for the fast mode, fast automatic mode, and the proposed concept for a single write operation.

[0097] i. For all three modes, the write operation takes almost the same amount of time (slightly higher in Fast Auto mode due to the Saver-Burst transition latency).

[0098] ii. The power consumption of Fast Mode and Fast Auto Mode is almost the same (because in Fast Auto Mode, all channels will be active for data transmission, considering groups <= 7).

[0099] iii. Since all paths are active only in the data transmission direction, the proposed concept has the lowest energy consumption. For AFC, only path -0 is active, while all other paths are in a power-saving state.

[0100] Figure 13 The energy consumption differences for fast mode, fast auto mode, and the proposed scheme for read scenarios are shown according to the embodiments disclosed herein. During a single read operation, the initiating device operates in Gear-HSG4 Series-A mode, the data size of the initiating device is 256KB, the total path of the initiating device is 2, and the read latency is 50µs. Furthermore, the following are the energy saving levels:

[0101] 1. Regarding Fast Mode – 27.33%

[0102] 2. Regarding the Quick Auto Mode – 5.09%

[0103] Figure 14 The calculation of multiple read / write requests for a UFS system according to an embodiment disclosed herein is illustrated. The proposed calculation of multiple read / write requests has the following details (i.e., Gear – HSG4 series-A, data size – 256KB, incomplete commands – 72, and number of paths – 2).

[0104] A comparison of energy consumption for fast mode, fast auto mode, and the proposed concept for a single read operation. Fast mode consumes the most energy because all paths are always active. In fast auto mode, all paths switch to a power-saving state during the read latency, while in the proposed model, selective paths remain active based on available throughput. Overall, the proposed model exhibits the lowest energy consumption.

[0105] The foregoing description of specific embodiments will so fully reveal the general nature of the embodiments herein that others can readily modify and / or adapt such specific embodiments for various applications by applying present knowledge without departing from the general concept. Therefore, such modifications and alterations should and are intended to be understood within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation. Thus, although embodiments have been described herein according to preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modifications within the scope of the embodiments described herein.

Claims

1. A method for performing a state switch in a selective path between a first electronic device (100) and a second electronic device (200) in a general-purpose flash memory storage system (6000), wherein, The method includes: The first electronic device (100) detects whether a data request has been received from the application layer of the first electronic device (100); and One of the following is performed by the first electronic device (100): In response to determining that no data request has been received from the application layer of the first electronic device (100), the first path of the plurality of paths between the first electronic device (100) and the second electronic device (200) is configured to be active, and the remaining paths of the plurality of paths are configured to be in power-saving mode to adjust the power of the first electronic device (100), and credit information corresponding to the data is sent to the second electronic device (200) using the first path. In response to determining that a data request has been received from the application layer of the first electronic device (100), the plurality of paths between the first electronic device (100) and the second electronic device (200) are configured to be active to achieve maximum throughput from the first electronic device (100), and the data is transmitted from the first electronic device (100) to the second electronic device (200) using at least one of the plurality of paths.

2. The method according to claim 1, wherein, Credit information is used to determine the available buffer space at the second electronic device (200).

3. The method according to claim 1, wherein, The data request received from the application layer of the first electronic device (100) indicates one of the data read request and data write request at the first electronic device (100).

4. The method according to claim 1, wherein, The first electronic device (100) is the initiating device, and the second electronic device (200) is the target device.

5. The method according to claim 1, wherein, The first electronic device (100) is the target device, and the second electronic device (200) is the initiator device.

6. A general-purpose flash memory storage system (6000) for performing state switching using selective paths, wherein, The general-purpose flash memory storage system (6000) includes: First electronic device (100); and The second electronic device (200) is communicatively integrated with the first electronic device (100) using multiple channels. The first electronic device (100) includes: The general-purpose flash memory (140) is configured to support one or more power-saving modes, and The access controller (150) is configured as follows: Detect whether a data request has been received from the application layer of the first electronic device (100), and Perform one of the following: In response to determining that no data request has been received from the application layer of the first electronic device (100), the first path of the plurality of paths between the first electronic device (100) and the second electronic device (200) is configured to be active, and the remaining paths of the plurality of paths are configured to be in power-saving mode to adjust the power of the first electronic device (100), and credit information corresponding to the data is sent to the second electronic device (200) using the first path. In response to determining that a data request has been received from the application layer of the first electronic device (100), the plurality of paths between the first electronic device (100) and the second electronic device (200) are configured to be active to achieve maximum throughput from the first electronic device (100), and the data is transmitted from the first electronic device (100) to the second electronic device (200) using at least one of the plurality of paths.

7. The general-purpose flash memory storage system (6000) according to claim 6, wherein, Credit information is used to determine the available buffer space at the second electronic device (200).

8. The general-purpose flash memory storage system (6000) according to claim 6, wherein, The data request received from the application layer of the first electronic device (100) indicates one of the data read request and data write request at the first electronic device (100).

9. The general-purpose flash memory storage system (6000) according to claim 6, wherein, The first electronic device (100) is the initiating device, and the second electronic device (200) is the target device.

10. The general-purpose flash memory storage system (6000) according to claim 6, wherein, The first electronic device (100) is the target device, and the second electronic device (200) is the initiator device.

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