Dynamically reconfigurable networking using programmable integrated circuits

Abstract

An integrated circuit (IC) can include a platform (218) implemented at least partially in a static region (202) of programmable circuitry and a dynamic region (204) of programmable circuitry, where the platform includes a network interface card controller (NIC) coupled to a host interface (212) and a network interface (206), and the dynamic region (204) of programmable circuitry is configured to implement user-specified circuitry (216) in communication with the platform, where the user-specified circuitry implements one or more packet processing functions. The NIC includes a plurality of communication interfaces connected to the dynamic region. The platform can establish and maintain a first communication link with a host data processing system using the host interface and a second communication link with a network using the network interface. The platform can continue to transfer data between the network and the host data processing system while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured to implement different user-specified circuitry therein.

Description

Technical Field

[0001] This disclosure relates to integrated circuits (ICs), and more specifically, to dynamically reconfigurable networking using programmable ICs. Background Technology

[0002] A programmable integrated circuit (IC) is a device that includes programmable logic. An example of a programmable IC is a field-programmable gate array (FPGA). FPGAs are characterized by including programmable circuit blocks. Examples of programmable circuit blocks include, but are not limited to, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), digital signal processing blocks (DSPs), processors, clock managers, and delay-locked loops (DLLs).

[0003] Each programmable module typically comprises a programmable interconnect circuit system and a programmable logic circuit system. The programmable interconnect circuit system typically consists of a large number of interconnects of varying lengths connected by programmable interconnect points (PIPs). The programmable logic circuit system uses programmable elements to implement user-designed logic, which can include, for example, function generators, registers, arithmetic logic, and so on.

[0004] Programmable interconnects and programmable logic circuit systems are typically programmed by loading configuration data streams into internal configuration memory cells that define how programmable elements are configured. Configuration data can be read from memory (e.g., from an external PROM) or written to the FPGA by an external device. The collective state of the individual memory cells then determines the functionality of the FPGA.

[0005] Modern programmable ICs have evolved to include programmable logic combined with one or more other subsystems. For example, some programmable ICs have evolved into systems-on-a-chip (SoCs), which include programmable logic and a hard-wired processor. Other types of programmable ICs include additional and / or different subsystems. The phrase "programmable IC" refers to a device that includes at least part and is partially or fully programmable, including programmable logic.

[0006] Typically, the functionality of a programmable IC is controlled by data bits provided to the device for this purpose. Data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some other programmable ICs, such as complex programmable logic devices (CPLDs)), in non-volatile memory (e.g., flash memory, as in some CPLDs), or in any other type of memory cell. Summary of the Invention

[0007] The integrated circuit (IC) may include a platform implemented at least partially in the static region of a programmable circuit system. This platform may include a network interface card controller coupled to a host interface and a network interface. The IC may include a dynamic region of the programmable circuit system configured to implement user-defined circuits that communicate with the platform. The user-defined circuits are capable of implementing one or more packet processing functions. The network interface card controller may include multiple communication interfaces connected to the dynamic region. The platform may be configured to establish and maintain a first communication link with a host data processing system using the host interface and a second communication link with a network using the network interface. The platform may be configured to continue transmitting data between the network and the host data processing system while at least a portion of the dynamic region of the programmable circuit system is dynamically reconfigured to implement different user-defined circuits therein.

[0008] The content of this invention is provided only to illustrate certain concepts and not to identify any key or essential features of the claimed subject matter. Other features of the invention will become apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0009] The arrangement of the invention is illustrated by way of example in the accompanying drawings. However, the drawings should not be construed as limiting the arrangement of the invention to the specific embodiments shown. Various aspects and advantages will become apparent from the following detailed description and with reference to the accompanying drawings.

[0010] Figure 1 The illustration shows an example of a host data processing system and a hardware acceleration card.

[0011] Figure 2A The illustration shows an example platform implemented in a programmable integrated circuit (IC).

[0012] Figure 2B The illustration shows another example platform implemented in a programmable IC.

[0013] Figure 3 The illustration shows another example platform implemented in a programmable IC.

[0014] Figure 4 The illustration shows another example platform implemented in a programmable IC.

[0015] Figure 5 The illustration shows another example platform implemented in a programmable IC.

[0016] Figure 6 The illustration shows another example platform implemented in a programmable IC.

[0017] Figure 7 The illustration shows another example platform implemented in a programmable IC.

[0018] Figure 8 The illustration shows another example platform implemented in a programmable IC.

[0019] Figure 9 The diagram illustrates an example implementation of a network interface card (NIC) controller within the platform.

[0020] Figure 10 The illustration shows another example platform implemented in a programmable IC.

[0021] Figure 11 The illustration shows another example platform implemented in a programmable IC.

[0022] Figure 12 The illustration shows another example platform implemented in a programmable IC.

[0023] Figure 13 The illustration shows an example method of operating a programmable IC that implements the functionality of a smart NIC as described in this article.

[0024] Figure 14 The illustration shows an example method for implementing a platform on a programmable IC.

[0025] Figure 15 The illustration shows an example architecture used for ICs. Detailed Implementation

[0026] Although this disclosure concludes with claims defining novel features, it is believed that the various features described herein will be better understood by considering the specification in conjunction with the accompanying drawings. The processes(s), machines(s), manufacture(s), and any variations thereof described herein are provided for illustrative purposes. The specific structural and functional details described herein should not be construed as limiting, but only as the basis for the claims and as a representative basis for teaching those skilled in the art to employ the features described in virtually any suitable detailed structure in different ways. Furthermore, the terminology and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the described features.

[0027] This disclosure relates to integrated circuits (ICs), and more specifically, to dynamically reconfigurable networking using programmable ICs. According to the inventive arrangements described herein, programmable ICs are used to implement and deploy dynamically reconfigurable network attachment acceleration functions. The described functionality can be provided within a single device. For example, as described herein, a platform implemented in a programmable IC can provide compute, storage, and networking acceleration functions within a single programmable IC. This platform supports the implementation and deployment of user-specified circuitry for performing one or more network attachment acceleration functions. These user-specified circuits can be dynamically inserted and / or removed from the platform in flight without affecting network traffic processed by the programmable IC platform. Thus, during operation of the programmable IC, the platform can be functionally extended over time by including, removing, and / or swapping user-specified circuitry.

[0028] Network attachment acceleration refers to processing typically performed on a network interface card (NIC), which is plugged into a data processing system such as a server (e.g., a host system) via a communication bus. The NIC may include a field-programmable gate array (FPGA) connected to an application-specific integrated circuit (ASIC). The ASIC typically receives data through a network port and performs basic packet processing functions, while the FPGA performs additional enhanced network acceleration functions on the data (known as "smart NIC" functions). The ASIC can then transmit the processed data to the host system.

[0029] According to the inventive arrangements described herein, a single device (e.g., a single programmable IC, such as an FPGA) can be used to provide ASIC functionality and enhanced or smart NIC functionality. The platforms described herein (such as those implemented in a programmable IC) support the described data processing and the ability to implement different custom or user-specified circuits over time without affecting the programmable IC's ability to continue performing basic NIC functions. Therefore, portions of the programmable IC can be dynamically reconfigured (e.g., partially reconfigured) to perform packet processing operations related to computing, storage, and / or networking acceleration functions, while other areas on the programmable IC can continue to operate uninterruptedly without data loss or communication links with the network. The programmable IC can also maintain communication links with the host system. Thus, while one or more different user-specified circuits are dynamically inserted, removed, and / or replaced during operation to process network data, the programmable IC can continue to transfer data between the network and the host system without data loss.

[0030] The arrangement of this invention provides a platform in which additional functionality can be added to the basic NIC functions provided by a NIC controller. This additional functionality may involve networking, computing, and / or storage acceleration. Developers are able to create specific functions without recreating the entire NIC infrastructure provided by the platform. The use of this platform offers various benefits. These benefits may include reduced compile time when developing hardware for implementation in a programmable IC, because the platform does not need to be reimplemented for each different user-specified circuit being developed. These benefits may also include reduced time spent downloading configuration data to the programmable IC to implement the user-specified circuit system at runtime, because the platform does not need to be reimplemented in the programmable IC each time a different user-specified circuit is added, removed, and / or modified.

[0031] Other aspects and / or benefits of the invention's arrangement are described in more detail below with reference to the accompanying drawings. For simplicity and clarity, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, reference numerals in the drawings are repeated where deemed appropriate to indicate corresponding, similar, or analogous features.

[0032] Figure 1 An example of a host data processing system (host system) 100 and a hardware acceleration card (card) 104 is illustrated. Components of the host system 100 may include, but are not limited to, one or more processors 106 (e.g., a central processing unit), memory 108, and a bus 110 that couples various system components, including memory 108, to the processor(s) 106. The processor(s) 106 may include any of a variety of processors capable of executing program code. Example processor types include, but are not limited to, processors with x86-type architectures (IA-32, IA-64, etc.), power architectures, ARM processors, etc.

[0033] Bus 110 represents one or more of several types of communication bus architectures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of the various available bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA (EISA) buses, Video Electronics Standards Association (VESA) local buses, Peripheral Component Interconnect (PCI) buses, and PCI Express (PCIe) buses.

[0034] The host system 100 typically includes a variety of computer-readable media. Such media can be any available media accessible to the host system 100, and can include any combination of volatile media, non-volatile media, removable media, and / or non-removable media.

[0035] Memory 108 may include computer-readable media in the form of volatile memory, such as random access memory (RAM) 112 and / or cache memory 114. Host system 100 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example, storage system 116 may be provided for reading from and writing to non-removable non-volatile magnetic media (not shown and generally referred to as a "hard disk drive"). Although not shown, a disk drive for reading from and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM, or other optical media) may be provided. In this case, each may be connected to bus 110 via one or more data media interfaces. As will be further described and illustrated below, memory 108 may include at least one computer program product having a set (e.g., at least one) of program modules (e.g., program code) configured to perform the functions and / or operations described in this disclosure.

[0036] For example, program / utility 118 (having a set (at least one) of program modules 120, which may include, but is not limited to, an operating system, one or more applications, other program modules, and / or program data) is stored in memory 108. Program modules 120 typically perform the functions and / or methods described herein with respect to at least the operations performed by host system 100. For example, program module 120 may include one or more applications and drivers or background processes for communicating with hardware accelerator card 104 and / or programmable IC 132.

[0037] Program / utility 118 may be executed by processor(s) 106. Program / utility 118 and any data items used, generated, and / or manipulated by processor(s) 106 are functional data structures that are given functionality when adopted by processor(s) 106. As defined in this disclosure, a "data structure" is a physical implementation of the data organization of a data model within physical memory. Thus, a data structure is formed by specific electrical or magnetic structural elements in memory. The data structure imposes a physical organization on the data stored in memory used by applications executed using the processor.

[0038] Host system 100 may include one or more input / output (I / O) interfaces 128 communicatively linked to bus 110. The I / O interfaces 128 allow host system 100 to communicate with external devices, allow host system 100 to be coupled to external devices (allowing (multiple) users to interact with host system 100), allow host system 100 to be coupled to external devices that allow host system 100 to communicate with other computing devices, and so on. For example, host system 100 may be communicatively linked to hardware accelerator card 104 via the I / O interfaces 128. Host system 100 may be coupled to other external devices (such as a keyboard and / or display) (not shown) via the I / O interfaces 128. Examples of I / O interfaces 128 may include, but are not limited to, network interface cards, modems, network adapters, hardware controllers, etc.

[0039] In the example implementation, the host system 100 communicates with the hardware accelerator card 104 via an I / O interface 128, which is a PCIe adapter. The hardware accelerator card 104 can be implemented as a board coupled to the host system 100. The hardware accelerator card 104 can be inserted into a card slot in the host system 100, for example, an available bus and / or PCIe slot.

[0040] Hardware accelerator card 104 includes a programmable IC 132. Hardware accelerator card 104 also includes volatile memory 134 coupled to programmable IC 132 and non-volatile memory 136 also coupled to programmable IC 132. Volatile memory 134 may be implemented as RAM and is considered "local memory" of programmable IC 132, while memory 108 within host system 100 is not considered local to programmable IC 132. For example, memory 108 is local to host system 100. In some implementations, volatile memory 134 may include multiple gigabytes of RAM, such as 64GB of RAM. Non-volatile memory 136 may be implemented as flash memory. Non-volatile memory 136 is considered local to programmable IC 132.

[0041] exist Figure 1In the example, programmable IC 132 is connected to network 138. In one example, network 138 is an Ethernet-type network. Network 138 can operate at any of a variety of different speeds. For example, network 138 can be a 10G, 25G, 50G, 100G, 200G, 400G, or other speed network. In a particular implementation, network 138 may be, include, or be coupled to a 5G network. Programmable IC 132 includes an Ethernet interface (not shown) for connecting (e.g., a communication link) programmable IC 132 to network 138. For example, programmable IC 132 can be connected to an Ethernet switch or one or more other networking devices via network 138. For illustrative purposes, the term "network" herein refers to network 138, such as an Ethernet network.

[0042] Figure 1 This is not intended to imply any limitation on the scope or functionality of the examples described herein. Host system 100 is an example of computer hardware (e.g., a system) capable of performing the various operations described herein in relation to hardware accelerator card 104 and / or programmable IC 132.

[0043] Host system 100 is merely one example implementation of a computer that can be used with a hardware accelerator card. Host system 100 is shown in the form of a computing device (e.g., a computer or server). Host system 100 can be practiced as a standalone device or a bare-metal server in a cluster or distributed cloud computing environment. In a distributed cloud computing environment, tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules can reside on local and remote computer system storage media (including memory storage devices).

[0044] As used herein, the term "cloud computing" refers to a computing model that facilitates convenient, on-demand network access to a shared pool of configurable computing resources, such as networks, servers, storage, applications, ICs (e.g., programmable ICs), and / or services. These computing resources can be rapidly provisioned and released with minimal management effort or service provider interaction. Cloud computing promotes availability and is characterized by on-demand self-service, widespread network access, resource pooling, rapid elasticity, and measured service.

[0045] Some computing environments (such as cloud computing and / or edge computing environments using host systems 100 or other suitable data processing systems) typically support the FPGA-as-a-Service (FaaS) model, where user functions are hardware-accelerated for user-specified or custom circuit designs and implemented within programmable ICs running under the control of a host computer system. The National Institute of Standards and Technology (NIST) (more specifically, NIST's Information Technology Laboratory) describes other examples of cloud computing models.

[0046] Host system 100 can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of computing systems, environments, and / or configurations that may be suitable for use with host system 100 include, but are not limited to, personal computer systems, server computer systems, thin clients, fat clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the aforementioned systems or devices.

[0047] Figure 2A The illustration shows that in Figure 1 Example platform 218 is implemented in the programmable IC 132. The programmable IC 132 includes a static region 202 and a dynamic region 204 of a programmable circuit system. Although both static region 202 and dynamic region 204 are implemented using a programmable circuit system, it should be understood that one or both regions may include one or more hardwired circuit blocks as described in more detail herein in conjunction with the remaining figures.

[0048] Static region 202 represents a region of the programmable circuitry of programmable IC 132 that, once configured using the circuit design, does not change over time. While static region 202 can be reconfigured, such an operation would take programmable IC 132 offline (e.g., offline from host system 100 and / or network 138). For illustrative purposes, static region 202 is shown using shading and is used to implement platform 218, which provides networking operation. Platform 218 is specified by the circuit design loaded into programmable IC 132 (e.g., as a configuration bitstream). Figure 2A In the example, platform 218 includes various circuit blocks included in the shaded area. Once implemented in programmable IC 132, platform 218 provides functional networking, host system interface, and optional memory interface during operation. Platform 218 is capable of passing network data from Ethernet interface to host system 100 (e.g., via a communication bus with basic network interface controller (NIC) functionality to processor 106).

[0049] Dynamic region 204 represents a region of the programmable circuitry system of programmable IC 132 that can be dynamically reconfigured over time to implement different user-specified (e.g., custom) circuits. The user-specified circuits implemented in dynamic region 204 are designed to connect to multiple circuit blocks implemented in platform 218 in static region 202. Typically, the user-specified circuits implemented in dynamic region 204 are used to extend the functionality and / or operability of platform 218.

[0050] Within static region 202, the circuit design has been loaded to create platform 218. For example, all or part of the configuration bitstream of platform 218 is loaded into programmable IC 132. Figure 2A In the example, platform 218 includes an Ethernet interface 206, a NIC controller 208, a direct memory access (DMA) circuit 210, and a peripheral component interconnect fast (PCIe) controller 212. Therefore, the Ethernet interface 206, NIC controller 208, DMA circuit 210, and PCIe controller 212 are implemented in a static area 202. The Ethernet interface 206 is connected to the NIC controller 208. The NIC controller 208 is connected to the DMA circuit 210. The DMA circuit 210 is connected to the PCIe controller 212. The Ethernet interface 206 is capable of establishing a communication link to network 138 (e.g., nodes or switches within it). The PCIe controller 212 is capable of establishing a communication link to host system 100.

[0051] In other examples, platform 218 may use other types of interfaces to connect to network 138. Furthermore, platform 218 may use other types of interfaces to connect to host system 100. The specific examples described in this disclosure are provided for illustrative purposes and not for limitation. Other alternative types of interfaces may be used.

[0052] exist Figure 2A In the example, each of Ethernet interface 206, NIC controller 208, DMA circuit 210, and PCIe controller 212 is implemented using a programmable circuit system. In one or more other example implementations, one or all (e.g., any combination) of Ethernet interface 206, DMA circuit 210, and / or PCIe controller 212 are implemented as hardwired circuit blocks.

[0053] The NIC controller 208 is implemented using one or more communication interfaces 214 connected to the dynamic region 204. In a particular implementation, the communication interface 214 and / or other communication interfaces between the NIC controller 208 and the dynamic region 204 may be implemented as flow interfaces. An example of a flow interface is a conformal interface. The interface is a 4AXI 4-Stream protocol (e.g., "AXI"). It should be understood that other types of streaming interfaces can be used to connect the NIC controller 208 to the dynamic region 204, and AXI is provided only as a non-limiting example. Another example of a streaming interface could be an on-chip network.

[0054] On one hand, the communication interface 214 is software-controllable. For example, the configuration bitstream used to implement the user-specified circuit system can be stored along with associated metadata. The metadata can specify the state of the communication interface 214, such as whether it is on or off. In the case of multiple such interfaces, the metadata can specify which communication interfaces 214 are enabled and will be used. In this respect, the metadata describes the connectivity between the platform 218 and the dynamic region 204 and / or the user-specified circuit 216.

[0055] As an example, communication interface 214 can be implemented using one or more multiplexers that can be supplied with control signals (e.g., selection signals) from a control interface. The selection signals can be specified by metadata. Once the configuration bitstream is loaded into programmable IC 132 to implement user-specified circuitry 216, host system 100 is able to obtain the metadata corresponding to the configuration bitstream and write the metadata to programmable IC 132. The metadata can be provided to the control interface, which generates appropriate selection signals to the multiplexers of communication interface 214 to activate and / or deactivate communication interface 214 to communicate with user-specified circuitry 216 as needed.

[0056] Data can be moved from platform 218 to dynamic zone 204 via communication interface 214, enter and be processed by user-designated circuitry system 216 in dynamic zone 204, and return to platform 218. NIC controller 208 may have multiple communication interfaces, which may be software-controllable as described. For example, on the ingress side, NIC controller 208 may receive data from network 138 via Ethernet interface 206. NIC controller 208 may or may not operate on the data before providing it to user-designated circuitry system 216 via communication interface 214. User-designated circuitry system 216 may operate on the received data and provide the processed data back to NIC controller 208 via communication interface 214. For example, user-designated circuitry system 216 may perform one or more packet processing or smart NIC functions. NIC controller 208 may or may not perform further processing on the data and provide it to host system 100 via DMA circuitry 210 and PCIe controller 212. In another example, NIC controller 208 can be configured to route data received from Ethernet interface 206 back to Ethernet interface 206 of network 138 after processing is performed by NIC controller 208 and / or user-specified circuit system 216 or without any such processing.

[0057] On the export side, NIC controller 208 can receive data from host system 100 via PCIe controller 212 and DMA circuitry 210. NIC controller 208 may or may not operate on the data before providing it to user-designated circuitry 216 via communication interface 214. User-designated circuitry 216 may operate on the received data and provide the processed data back to NIC controller 208 via communication interface 214. NIC controller 208 may or may not perform further processing on the data before providing it to network 138 via Ethernet interface 206. In another example, NIC controller 208 may be configured to route data received from host system 100 back to host system 100 after processing performed by NIC controller 208 and / or user-designated circuitry 216, or without any such processing.

[0058] Dynamic region 204 is implemented to include one or more partially reconfigurable (PR) regions. The PR region of programmable IC 132 refers to a region reserved for dynamically implementing one or more different user-specified (e.g., custom) circuit designs over time in a programmable circuit system. Dynamic region 204 may include more than one PR region. Generally, each different PR region implemented in dynamic region 204 is independently reconfigurable. Figure 2AIn the example, dynamic region 204 implements a single PR region.

[0059] exist Figure 2A In the example, static region 202 refers to the portion of programmable IC 132 located outside dynamic region 204. The platform 218 implemented in static region 202 remains unchanged, for example, remaining static, while the circuitry in dynamic region 204 can be modified over time to implement other different user-specified circuit designs. Figure 2A In the example, the user-specified circuit design is implemented in dynamic region 204 and is shown as user-specified circuit system 216. Dynamic region 204 can be reconfigured over time to implement different user-specified circuit systems (e.g., circuits other than user-specified circuit system 216), while platform 218 in static region 202 continues to operate uninterruptedly.

[0060] For example, the user-specified circuit system 216 can perform any of a variety of network acceleration functions. In this respect, the functionality of the platform 218 and, for example, the NIC controller 208 (although it is static in itself) can be enhanced by adding the user-specified circuit system 216. In one aspect, the user-specified circuit system 216 can perform any of a variety of incremental network acceleration functions because the NIC controller 208 can pass metadata, so that the user-specified circuit system 216 does not need to repeat operations that have already been performed (e.g., operations performed by the NIC controller 208).

[0061] User-specified circuitry system 216 can dynamically insert, remove, and / or replace data flowing through the static region 202 between network 138 and host system 100 during operation of programmable IC 132, such as data from network 138 (referred to as "network" or "entry" data) and / or data from host system 100 (referred to as "host" or "exit" data) (without interruption or loss of such data). On the other hand, in the case of virtual machines executing in host system 100, the terms "exit" and "entry" can be used relative to the virtual machine. For example, exit data of a virtual machine executing in host system 100 can be directed to network 138 or the entry of another virtual machine also executing in host system 100. In any case, platform 218 is able to maintain communication links with network 138 via Ethernet interface 206 and with host system 100 via PCIe controller 212 while dynamically reconfiguring dynamic region 204. Therefore, while the dynamic region 204 is being reconfigured, the programmable IC 132 appears to be "online" or operational to the host system 100 and other devices connected to the programmable IC 132 via the network 138.

[0062] Although in the example of Figure 2, NIC controller 208 is shown as including a single communication interface 214, NIC controller 208 may include multiple different communication interfaces. These communication interfaces may be included in one or more different stages of NIC controller 208. This allows NIC controller 208 to exchange data with user-specified circuitry 216 at any of these various processing stages.

[0063] Figure 2B The illustration shows that in Figure 1 Another example of platform 218 implemented in programmable IC 132. Figure 2B Platform 218 is basically similar to Figure 2A Examples. However, in Figure 2B In the example, platform 218 is partially implemented in static region 202. For example, PCIe controller 212 is implemented in static region 202. Ethernet interface 206, NIC controller 208, and DMA circuitry 210 are each implemented in different PR regions (e.g., PR regions 220, 222, and 224, respectively). Figure 2B In the example, dynamic region 204 can be implemented as another PR region that is separate from and independent of PR regions 220, 222 and 224.

[0064] Figure 2B The example allows different components of platform 218 to be updated over time. In fact, platform 218 is configurable. Updates to the circuitry in static region 202 typically require recompiling the user circuitry. Figure 2B The implementation minimizes the portion of platform 218 implemented in static region 202. By minimizing the amount of platform 218 implemented in static region 202, the likelihood of having to recompile the user-specified circuitry is reduced. For example, DMA circuitry 210, NIC controller 208, and Ethernet interface 206 can be changed (the PR region can be reconfigured using different implementations of these components) without requiring a recompilation of user-specified circuitry 216. Changes to PCIe controller 212 will require a recompilation of user-specified circuitry 216. Recompiling user circuitry (e.g., user-specified circuitry 216) is undesirable and can be particularly undesirable time-consuming effort in FaaS applications. Figure 2B In the example, most of platform 218 can be updated over time without recompiling the user-specified circuit system. This reduces the likelihood that the circuit system in static region 202 must be updated, and thus reduces the likelihood that the user circuit design needs to be recompiled.

[0065] Figure 2BProvided for illustrative purposes. Other example implementations may use a different number of PR regions to implement platform 218. For example, platform 218 may implement PCIe controller 212 in static region 202 and Ethernet interface 206, NIC controller 208, and DMA circuitry 210 in a single PR region. In another example, two PR regions may be used, with any two of Ethernet interface 206, NIC controller 208, and DMA circuitry 210 implemented in the first PR region, and the other component implemented in the second PR region. It should be understood that although not specifically illustrated in the various example platforms 218 shown in the remaining figures, in combination with... Figure 2B Each of the rendering examples described can use one or more PR regions to implement platform 218.

[0066] Figure 3 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 3 In the example, Ethernet interface 206 is shown in more detail. Ethernet interface 206 includes physical layer (PHY) 302 connected to media access control (MAC) 304. PHY 302 is connected to network 138. MAC 304 is connected to NIC controller 208. For example, MAC 304 may be connected to an Ethernet interface (not shown) included in NIC controller 208.

[0067] Figure 4 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 4 In one example, one or more memory controllers 402 are implemented as part of platform 218 in static region 202. The memory controllers 402 are connected to volatile memory (e.g., RAM) 134. The memory controllers 402 can be implemented using a programmable circuit system. However, in another example, one or more memory controllers 402 can be implemented as hardwired circuit blocks.

[0068] Memory controller 402 can be connected to user-defined circuitry 216 implemented in dynamic region 204. Furthermore, the memory controller(s) 402 can be coupled to DMA circuitry 210. Thus, user-defined circuitry 216 can access volatile memory 134 during operation. Additionally, host system 100 can read and / or write to volatile memory 134 via the memory controller(s) 402. This allows host system 100 to share data with user-defined circuitry 216.

[0069] In this disclosure, the various example platforms shown, whether or not a memory controller is shown, can be implemented to include one or more memory controllers. A memory controller may be optionally included. Furthermore, in implementations of platform 218 using one or more PR regions, the memory controllers may be implemented in their own PR region or included in another PR region having one or more other components of platform 218.

[0070] Figure 5 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 5 In this example, platform 218 includes a software-defined networking (SDN) data plane 502 implemented in NIC controller 208. The SDN data plane 502 enables decoupling of the data and control planes by implementing the data plane as part of platform 218. In this example, instead of implementing the data plane in software executing in host system 100, the data plane software is hardware-accelerated and implemented as the SDN data plane 502 within NIC controller 208.

[0071] In some example implementations, the SDN data plane 502 can be customized using a user-specified circuitry system 504 (and / or other user-specified circuitries in the dynamic region 204 connected to the SDN data plane 502 via communication interface 506). For example, using the port connecting the SDN data plane 502 to the dynamic region 204, the user-specified circuitry system 504 can be configured to add custom GRE headers to the data and / or implement custom parsers. For example, using a custom parser, metadata can be transmitted and associated with the new parser data. Furthermore, the GRE can be modified using network overlays(s) via the user-specified circuitry system 504. In any case, the availability of one or more communication interfaces 506 allows the SDN data plane 502 to be customized using programmable circuitries in the dynamic region 204.

[0072] SDN data plane 502 enables programmatic access for greater flexibility in network management. For example, custom flow tables can be implemented as user-specified circuit systems 216 and / or 504 within dynamic region 204, utilizing a large flow table searched on the lookup interface, in relation to NIC controller 208 and / or SDN data plane 502. SDN data plane 502 reduces the processing burden that would otherwise be placed on host system 100 to execute data plane software.

[0073] exist Figure 5In the example, the SDN data plane 502 can be connected to the dynamic region 204 via communication interface 506. The SDN data plane 502 may have more than one communication interface connected to the dynamic region 204. In other examples, the SDN data plane 502 may not include a communication interface to the dynamic region 204. Although multiple memory controllers 402 are shown, they are optional and can be omitted. When included, memory controllers 402 allow user-specified circuitry systems 504 and 214 to read from and write to volatile memory 134. Furthermore, multiple memory controllers 402 allow host system 100 to read from and write to volatile memory 134.

[0074] For illustrative purposes, dynamic region 204 includes an additional user-specified circuitry system 504. In one example, user-specified circuitry system 504 is connected to NIC controller 208 and / or SDN data plane 502 via communication interface 506. User-specified circuitry system 504 can implement custom flow tables that allow NIC controller 208 to redirect data flows.

[0075] In another example, user-specified circuitry system 216 can implement video decoder and scaling circuitry. User-specified circuitry system 504 can implement machine learning object detection circuitry. Using this configuration, dynamic region 204 is capable of performing real-time video processing and machine learning. This example illustrates how platform 218 can be used to implement network-attached real-time video decoding (followed by object detection and / or classification).

[0076] For example, the video decoder and scaling circuitry can operate on multiple different video streams received via network 138. The video streams may originate from a security system and / or a camera connected to network 138. The video decoder and scaling circuitry can decode the received video streams. The video decoder and scaling circuitry can extract one or more individual frames from the different video streams and scale the extracted frames for use by machine learning object detection circuitry.

[0077] exist Figure 5In the example, NIC controller 208 is capable of performing basic NIC functions. Video decoding and scaling functions for object detection and / or image classification, as well as machine learning inference, are implemented as a hardware-accelerated kernel within dynamic region 204. By implementing the functions as a kernel within dynamic region 204, the kernel is able to operate on the video stream in real time. Real-time operation reduces latency because processing can be performed on the video stream without it passing through the network stack of host system 100 (e.g., user-specified circuit systems 504 and 216 operate on the video before the data reaches host system 100). This accelerates the processing performed by programmable IC 132. Additionally, platform 218 reduces storage requirements because images without any labeled objects can be discarded, while images with labeled objects (e.g., frames) can be saved for further analysis. Furthermore, the workload placed on host system 100 is significantly reduced because the cycles of processor (multiple) 106 can be used for other operations.

[0078] In another example, Figure 5 Platform 218 can be used to perform inline malware detection on encrypted data traffic. In this example, platform 218 is able to operate based on certain information extracted from the data stream. This information may include the duration of the data stream, the number of packets sent by the client, the number of packets sent by the server, the number of bytes sent by the client, and the number of bytes sent by the server. For example, user-specified circuit system 216 can implement classification and feature extraction circuitry. The extracted information can be used with metadata from the unencrypted portion of the packet headers, also extracted by user-specified circuit system 216, to train a random forest classifier implemented by user-specified circuit system 504. The trained classifier can then be used to detect malware.

[0079] On one hand, the classifier can run in real time on packets entering the programmable IC 132 from network 138. User-specified circuitry 216 is able to extract features and classify packets into data streams. User-specified circuitry 216 can feed the determined information to user-specified circuitry 504. User-specified circuitry 504 can be pre-loaded with a trained model for malware of interest. In response to user-specified circuitry 504 detecting malware, user-specified circuitry 504 can send a message to set a filter within SDN data plane 502 to prevent any further network data sent from the attacker from reaching host system 100. In this example, NIC controller 208 and SDN data plane 502 operate as part of platform 218, while the feature extraction and classification functions for malware detection operate as a kernel loaded into dynamic region 204.

[0080] By performing classification, extraction, and malware detection in real time, malware can be blocked before it physically crosses the PCIe bus from the programmable IC 132 to the host system 100. This provides stronger protection for the host system 100. Random forest classification technology allows malware detection on encrypted traffic without complex decryption and proxy techniques. Furthermore, performing this function on the programmable IC 132 rather than on the device provides better scalability through workload distribution and prevents attacks originating from within the data center.

[0081] The specific user-specified circuits described herein are provided for illustrative purposes and not for limitation. The examples illustrate that any user-specified circuit system can be implemented in dynamic region 204 to extend the capabilities of platform 218. Furthermore, while different user-specified circuit system blocks may be included to communicate with NIC controller 208, these different user-specified circuit system blocks may or may not communicate with each other.

[0082] exist Figure 5 In the example, dynamic region 204 is implemented as a single PR region. In one or more other examples, each user-specified circuit block (e.g., 504 and 216) can be implemented in its own independently reconfigurable PR region. In such a configuration, the specific user-specified circuit system implemented in each PR region will be dynamically modifiable (e.g., reconfigurable) without modifying other user-specified circuit systems implemented in dynamic region 204. For example, if user-specified circuit system 504 is in the first PR region and user-specified circuit system 216 is in the second PR region, user-specified circuit system 504 can be removed and a different user-specified circuit system can be added to the first PR region without affecting the operation of user-specified circuit system 216. Similarly, user-specified circuit system 216 can be removed and a different user-specified circuit system can be added to the second PR region without affecting the operation of user-specified circuit system 504. In each case, platform 218 continues to operate uninterruptedly. Figure 5 Platform 218 can also be implemented using one or more PR regions as described in this article.

[0083] Figure 6 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 6 The example is basically similar to Figure 5 Examples. However, in Figure 6In the example, SDN data plane 502 is replaced by Open Virtual Switch (OVS) data plane 602. OVS data plane 602 is capable of connecting to the virtualization server. OVS data plane 602 implements a hardware-accelerated version of the virtual switch. Instead of implementing the virtual switch in software running on host system 100, the virtual switch software is hardware-accelerated and implemented as OVS data plane 602 within platform 218. OVS data plane 602 alleviates the processing burden that would otherwise be placed on host system 100. Figure 6 In the example, the OVS data plane 602 and / or the process table can be customized using user-specified circuitry 504 and / or user-specified circuitry 216 (e.g., using user-specified circuitry implemented in dynamic region 204 and connected to OVS data plane 602 and / or NIC controller 208 via one or more communication interfaces).

[0084] exist Figure 6 In the example, the OVS data plane 602 can be connected to the dynamic region 204 via the communication interface 604. The OVS data plane 602 may have more than one communication interface connected to the dynamic region 204. In another example, the OVS data plane 602 may not have a communication interface to the dynamic region 204. Although multiple memory controllers 402 are shown, they are optional. When included, the memory controllers 402 allow user-specified circuitry systems 504 and 214 to read and write to the volatile memory 134. Furthermore, the multiple memory controllers 402 allow the host system 100 to read and write to the volatile memory 134.

[0085] For illustrative purposes, dynamic region 204 includes an additional user-specified circuitry system 504. User-specified circuitry system 504 can be connected to NIC controller 208 and / or OVS data plane 602 via interface 604. In one example, user-specified circuitry system 216 may implement circuitry capable of performing one or more of storage compression, encryption, and / or deduplication operations.

[0086] exist Figure 6In the example, platform 218 can be used to implement a converged smart NIC for networking and storage. Platform 218 is capable of offloading and accelerating both networking and storage. Platform 218 provides a NIC controller 208 with an OVS data plane 602, an Ethernet interface 206, a PCIe controller 212, and (multiple) memory controllers 402. User-specified circuit systems 216 and 504, implemented in dynamic region 204, are capable of performing operations such as compression and / or encryption. As discussed, data flow between platform 218 and user-specified circuit systems 216 and 504 can be implemented using, for example, a streaming interface.

[0087] Control plane and slow path processing can be performed in the host system 100. However, in another example implementation, an embedded hard-wired processor and / or soft processor (see, for example) are used in the programmable IC 132. Figure 7 ) or an externally connected processor different from the processor in host system 100 (see, for example) Figure 8 It can perform storage offloading. The latter model, involving either an embedded processor or an external processor, can be used for a "bare metal" implementation, where the embedded or external processor manages network functions, storage, etc., in contrast to the host system processor(s) that performs such functions(s).

[0088] The specific user-specified circuits described herein are provided for illustrative purposes and not for limitation. The examples illustrate that any user-specified circuit system can be implemented in dynamic region 204 to extend the capabilities of platform 218. Furthermore, the illustrated user-specified circuit blocks may be included in the same or different PR regions, depending on the implementation. Similarly, Figure 6 Platform 218 can be implemented using one or more PR regions as described in this article.

[0089] Figure 7 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 7 In the example, static region 202 is implemented to include processor 702. Processor 702 is an embedded processor within programmable IC 132. In one aspect, processor 702 is a soft processor implemented using a programmable circuit system of programmable IC 132. In the example implementation, soft processor 702 is implemented as a MicroBlaze available from Xilinx Corporation of San Jose, California. TM Processor. Furthermore, processor 702 can be implemented as any of a variety of soft processors capable of executing program code. In another example, processor 702 is a hardwired processor. For example, processor 702 can be implemented as an ARM-type processor or an x86-type processor.

[0090] As shown in the figure, processor 702 is connected to on-chip interconnect 704. In one example, on-chip interconnect 704 is implemented as a memory-mapped interface. An example of a memory-mapped interface is a memory-mapped AXI interface. AXI is provided as an illustrative example of an interface and is not intended to be a limitation of the arrangement of the invention described in this disclosure. Other examples of on-chip interconnects include, but are not limited to, other types of buses, on-chip networks, cross-bar switches, or other types of switches.

[0091] Processor 702 is capable of performing any of a variety of different functions. Examples of functions that can be performed by processor 702 include, but are not limited to, OVS control plane, storage, and management. Figure 7 In the example, platform 218 is able to pass network data from Ethernet interface 206 to embedded processor 702 via the local interface shown (e.g., via NIC controller 208, DMA circuit 210 and memory-mapped interface 704).

[0092] exist Figure 7 In the example, platform 218 does not include a plurality of memory controllers. In one or more other examples, a plurality of memory controllers may be included in platform 218. The plurality of memory controllers may be connected to processor 702, user-specified circuitry systems 216 and / or 504 in dynamic region 204, and / or to host system 100. As discussed, platform 218 may be implemented using one or more PR regions.

[0093] Figure 8 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 8 In the example, platform 218 is implemented to include an additional (e.g., second) PCIe controller 802. PCIe controller 802 is implemented using a programmable circuit system. PCIe controller 802 is connected to an external processor 804. External processor 804 is capable of executing program code and can be located on hardware accelerator card 104 or on a different board or system coupled to hardware accelerator card 104.

[0094] The external processor 804 is capable of performing any of a variety of different functions. Examples of functions that can be performed by the processor 804 include, but are not limited to, OVS control plane, storage, and management.

[0095] exist Figure 8In the example, static region 202 does not include the memory controller(s). In one or more other examples, the memory controller(s) may be included in platform 218. The memory controller(s) may be connected to DMA circuitry 210, user-specified circuitry systems 216 and / or 504 in dynamic region 204, and / or to host system 100. As discussed, platform 218 may be implemented using one or more PR regions. In one aspect, PCIe controller 212 and PCIe controller 802 may be implemented in static region 202, while other components are included in one or more PR regions.

[0096] refer to Figure 7 and Figure 8 In this example implementation, the host system can implement one or more virtual machines. Each virtual machine has two independent virtual interfaces. One virtual interface is used for networking, and the other is used for storage. Network traffic is attached to the multi-queue DMA interface and passes through a processing pipeline that includes network offloading such as Receive-End Scaling (RSS), LSO / TSO (Large Send Offload / TCP Segmentation Offload), Virtual Scalable (VX) LAN / NVGRE (Network Virtualization with Generic Routing) tunneling offloading, and SDN matching / action processing (such as OVS). Storage traffic is offloaded via an embedded processor 702 or an external processor 804, which is optionally programmed to utilize RDMA capabilities. Storage traffic can then pass through a processing pipeline that includes NVMe and storage offloading operations such as compression and / or encryption performed in dynamic region 204. The processed data can then be merged with the data pipeline of NIC controller 208.

[0097] Figure 9 The illustration shows an example implementation of the NIC controller 208. Figure 9 In the example, NIC controller 208 includes an Ethernet interface 902, a bump-in-the-wire (BITW) arbitration circuit 904, a NIC core 906, an accelerator arbitration circuit 908, and a DMA interface 910. For illustrative and discussion purposes, NIC core 906 and accelerator arbitration circuit 908 may each be referred to as a “level” of NIC controller 208. In some example implementations, NIC core 906 itself may be formed by or include multiple different levels of circuitry.

[0098] exist Figure 9In the example, Ethernet interface 902 is connected to Ethernet interface 206 (e.g., MAC 304). DMA interface 910 is connected to DMA circuit 210. DMA interface 910, accelerator arbitration circuit 908, NIC core 906, BITW arbitration circuit 904, and Ethernet interface 902 each support ingress data flow (e.g., data flowing from Ethernet interface 206 into NIC controller 208) and egress data flow (e.g., data flowing from NIC controller 208 out to Ethernet interface 206).

[0099] As shown in the figure, each of the BITW arbitration circuit 904, NIC core 906, accelerator arbitration circuit 908, and DMA interface 910 includes an ingress communication interface to dynamic region 204 and an egress communication interface to dynamic region 204. In one aspect, the communication interface may include an ingress communication interface and an egress communication interface. For example, refer to... Figure 9 Each inlet / outlet pair can represent a communication interface. However, in other examples, the communication interface may include only inlet communication interfaces(s) or only outlet communication interfaces(s). Each circuit block described as having one or more communication interfaces to dynamic region 204 is capable of sending outlet data and / or inlet data via the appropriate inlet or outlet communication interface for further processing within any of the various user circuits 912, 914, 916, 918, 920 and / or 922 illustrated in dynamic region 204.

[0100] In another example implementation, the BITW arbitration circuit 904 can be implemented as one or more multiplexers (e.g., switches) that connect ingress and / or egress data paths to dynamic region 204. The BITW arbitration circuit 904 allows the NIC controller 208 to include one or more interfaces between Ethernet interface 902 and NIC core 906. The BITW arbitration circuit 904 can directly transmit data received from Ethernet interface 902 via the ingress communication interface to one or more user circuits, such as user circuit 914, for packet processing. User circuit 914 can perform packet processing on the received data and provide the processed data back to the BITW arbitration circuit 904 via the ingress communication interface. The BITW arbitration circuit 904 can then forward the processed data to NIC controller core 906.

[0101] In a particular implementation, the BITW arbitration circuit 904 can be configured to redirect data. For example, the BITW arbitration circuit 904 can receive data from Ethernet interface 902 and send data back to Ethernet interface 902 for output to Ethernet interface 206. The BITW arbitration circuit 904 may or may not provide data to the user circuitry in dynamic area 204 before redirecting the data. In any case, data received by NIC controller 208 from network 138 can be optionally processed, redirected, and sent back from NIC controller 208 to network 138 using the BITW arbitration circuit 904.

[0102] The BITW arbitration circuit 904 can also directly transmit data received from the NIC core 906 via the egress communication interface to one or more user circuits, such as user circuit 912, for packet processing. User circuit 912 can perform packet processing on the received data and provide the processed data back to the BITW arbitration circuit 904 via the egress communication interface. The BITW arbitration circuit 904 can then forward the processed data to the Ethernet interface 902. In another example, if sufficient data is exchanged between user circuits 912 and / or 914 via the BITW arbitration circuit 904, the NIC core 906 can perform operations such as parsing subsequent higher protocol layers.

[0103] In a particular implementation, the BITW arbitration circuit 904 can be configured to redirect data. For example, the BITW arbitration circuit 904 can receive data from the NIC controller 906 and send the data back to the NIC controller 906 for output to the DMA circuit 210. The BITW arbitration circuit 904 may or may not provide data to the user circuitry in the dynamic region 204 before redirecting the data. In any case, data received by the NIC controller 208 from the host system can be optionally processed, redirected, and sent back to the host system from the NIC controller 208 using the BITW arbitration circuit 904.

[0104] Thus, the BITW arbitration circuit 904 serves as a switch or interface in which ingress data can be provided to the user-specified circuitry system in the dynamic area 204 before entering the processing stage of the NIC controller 208. Similarly, the BITW arbitration circuit 904 serves as a switch or interface in which egress data can be directly provided to the user-specified circuitry system in the dynamic area 204 before leaving the NIC controller 208. As discussed, the BITW arbitration circuit 904 can also redirect ingress and / or egress data.

[0105] On one hand, the ingress and egress communication interfaces are implemented as stream interfaces. In one example implementation, user circuits 912 and 914 can implement Internet Protocol Security (IPSec) circuit blocks. For example, after being processed by user circuit 914, ingress packets destined for NIC core 906 can be fully decrypted, allowing for further processing of higher-level protocols such as Transmission Control Protocol (TCP). Unencrypted egress packets (e.g., plaintext) from NIC core 906 can be encrypted by user circuit 912.

[0106] On the other hand, user circuit 912 can perform operations such as adding Ethernet IP and TCP headers or GRE. User circuit 914 can be used to implement GRE header removal, also known as decapsulation. User circuit 912 can perform GRE header insertion (also known as encapsulation). Again, user circuits 912 and / or 914 can perform operations on data at points in the data path between Ethernet interface 206 and NIC core 906.

[0107] The NIC core 906 can directly transmit data received from the BITW arbitration circuit 904 via the ingress communication interface to one or more user circuits (such as user circuit 918) for packet processing. User circuit 918 can perform packet processing on the received data and provide the processed data back to the NIC core 906 via the ingress communication interface. The NIC core 906 can then forward the processed data to the acceleration arbitration circuit 908.

[0108] The NIC core 906 can directly transmit data received from the acceleration arbitration circuit 908 via its egress communication interface to one or more user circuits (such as user circuit 916) for packet processing. User circuit 916 can perform packet processing on the received data and provide the processed data back to the NIC core 906 via its egress communication interface. The NIC core 906 can then forward the processed data to the BITW arbitration circuit 904.

[0109] On one hand, the ingress and egress communication interfaces for the NIC core 906 are implemented as ternary content-addressable memory (TCAM) interfaces (e.g., at least one for ingress and at least one for egress). User circuits 916 and / or 918 can implement any of a variety of different circuits (including but not limited to access control lists / flow tables, algorithmic TCAMs, MAC filters, and / or algorithmic content-addressable memory (CAMs)).

[0110] In another example, in the case of video processing, operations such as UDP and checksum offloading can be performed by the NIC core 906. Multiple user circuits 918 and / or 916 can be used to perform flow lookups to identify where data should be directed. Data can be directed wherever indicated by the user circuits 918 and / or 916 implementing the flow table. For example, a user might want to use a larger table than can be implemented in the NIC core 906. Thus, the multiple user circuits 918 and / or 916 can use additional RAM in dynamic region 204 to expand the table included in the NIC core 906.

[0111] The accelerated arbitration circuit 908 can directly transmit data received from the NIC core 906 via the ingress communication interface to one or more user circuits (such as user circuit 922) for packet processing. User circuit 922 can perform packet processing on the received data and provide the processed data back to the accelerated arbitration circuit 908 via the ingress communication interface. The accelerated arbitration circuit 908 can then forward the processed data to the DMA interface 910.

[0112] The accelerated arbitration circuit 908 can directly transmit data received from the DMA interface 910 via the egress communication interface to one or more user circuits (such as user circuit 920) for packet processing. User circuit 920 can perform packet processing on the received data and provide the processed data back to the accelerated arbitration circuit 908 via the egress communication interface. The accelerated arbitration circuit 908 can then forward the processed data to the NIC core 906.

[0113] In the example implementation, the accelerator arbitration circuit 908 resides in the data path after TCP / IP, checksum offloading, and other advanced functionalities have been performed. Packets and associated metadata can be passed to dynamic region 204, where user circuits (e.g., user circuits 920 and / or 922) are capable of performing incremental acceleration. That is, if user circuits 920 and / or 922 are performing advanced operations, the circuit system does not need to re-execute previous operations performed elsewhere in the data pipeline of NIC controller 208.

[0114] On one hand, the ingress and egress communication interfaces are implemented as stream interfaces (e.g., at least one for ingress and at least one for egress). In the example implementation, user circuits 920 and 922 can implement circuitry for performing layer 4 and above deep packet inspection.

[0115] The DMA interface 910 can send data received from the acceleration arbitration circuit 908 to the DMA circuit 210. The DMA interface 910 can send data received from the DMA circuit 210 to the accelerator arbitration circuit 908.

[0116] exist Figure 9 In the example, the user circuitry is shown implemented in a single PR region. It should be understood that two or more PR regions can be implemented in dynamic region 204, which includes various combinations of user circuitry. In another example, user circuits 912 and 914 are implemented in one PR region; user circuits 916 and 918 are implemented in another PR region; and user circuits 920 and 922 are implemented in yet another PR region. Furthermore, the various examples of different user circuits and interfaces are intended for illustration and not limitation. In another example, each user circuit may be implemented in a different PR region.

[0117] like Figure 9 As illustrated in the example, platform 218 is capable of providing multiple different communication interfaces to dynamic region 204. These communication interfaces (e.g., connection points) allow data to move between platform 218 and dynamically loaded functions implemented in dynamic region 204 at any of the supported connection points. As mentioned, one or more of the communication interfaces (e.g., the communication interface of NIC controller 208) that connect platform 218 to dynamic region 204 are software-controllable. Thus, the embedded processor in programmable IC 132 (whether as...) Figure 7 (Whether the wiring shown is hardwired or softwired) or external devices or processors (e.g., such as...) Figure 8 The processor of the host system (as shown) and / or the host system can control each communication interface on an individual basis whether to enable it to exchange data between the static platform 218 and the dynamic region 204 or to disable it to prevent data exchange between the platform 218 and the dynamic region 204.

[0118] Figure 10 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 10 In the example, platform 218 includes a streaming service manager 1002. The streaming service manager 1002 is connected to accelerator arbitration circuit 908 and DMA circuit 210. Although in Figure 10 Not shown in the figure, but the streaming service manager 1002 may include one or more connections to the dynamic area 204.

[0119] The streaming service manager 1002 is capable of regulating the flow of data streams / packets between the host system 100 and the circuitry implemented in the dynamic region 204. Figure 10 In one example, the streaming service manager 1002 regulates the flow of data between the host system 100 and user circuits 1010 and / or 1012. In other examples, the dynamic region 204 may include additional user circuits, such as kernel circuits, which may be connected to the streaming service manager 1002 via interconnects (not shown).

[0120] exist Figure 10 In the example, dynamic region 204 is divided into PR regions 1006 and 1008. PR region 1006 includes user circuitry 1010. PR region 1008 includes user circuitry 1012. Each PR region in PR regions 1006 and 1008 can be dynamically reconfigured independently of each other. Therefore, since user circuitry 1010 is in PR region 1006 and user circuitry 1012 is in PR region 1008, user circuitry 1010 can be removed or replaced without affecting the operation of user circuitry 1012 or platform 218. Similarly, since user circuitry 1012 is implemented in PR region 1008, user circuitry 1012 can be removed or replaced without affecting the operation of user circuitry 1010 or platform 218. As discussed, one or both of PR regions 1006, 1008 (e.g., the entire dynamic region 204) can be reconfigured without interrupting the operation of platform 218. It should be understood that although dynamic region 204 is shown as including two PR regions, in another example, user circuit 1010 and user circuit 1012 can be implemented in a single PR region.

[0121] On one hand, user circuit 1012 implements the TCAM algorithm, which is capable of performing high-speed packet processing. User circuit 1010 implements an IPSec circuit capable of performing operations between two communication points across an IP network, including but not limited to data authentication, integrity, and / or confidentiality.

[0122] exist Figure 10 In the example, user circuit 1010 is able to receive data from NIC core 906, process the data, and provide the processed data back to NIC core 906. User circuit 1012 is illustrated as an example where user circuit 1012 (e.g., an IPSec circuit) can be programmed by host system 100. In this case, host system 100 (e.g., or another trusted processor, whether internal or external) is able to send post-configuration data to user circuit 1012 via PCIe controller 212 and a control interface to which user circuit 1012 is coupled. One example of a control interface is an AXI-Light compliant interface, but other control interfaces may also be used.

[0123] Figure 11 Another example of platform 218 implemented in programmable IC 132 is illustrated. Figure 11In the example, the streaming service manager 1002 is connected to interconnect 1102 and interconnect 1106 in dynamic region 204. Interconnect 1102 may be a memory-mapped interconnect, while interconnect 1106 may be a streaming interconnect. Interconnect 1102 is connected to one or more network cores 1104. Interconnect 1106 is connected to one or more compute cores 1108. The streaming service manager 1002 and / or accelerator arbitration circuit 908 are capable of managing the data flow (e.g., bootstrapping data flow) between host system 100 and network cores 1104 and compute cores 1108. Figure 11 In the example, the accelerator arbitration circuit 908 is able to communicate with the user circuit system implemented in the dynamic region 204 via the streaming service manager 1002.

[0124] Although dynamic region 204 is shown as comprising a single PR region, in another respect, dynamic region 204 may include multiple PR regions. For example, user circuit 1012 may be implemented in a first PR region, while user circuit 1010 may be implemented in a second PR region. Furthermore, interconnects 1102, 1106, network kernel 1104, and compute kernel 1108 may be implemented in a third PR region. In another respect, interconnect 1102 and (multiple) network kernels 1104 may be implemented in a third PR region, while interconnect 1106 and (multiple) compute kernels 1108 may be implemented in a fourth PR region. Figure 10 and Figure 11 In the example, the Streaming Service Manager 1002 can be implemented independently in a PR region or in a PR region containing one or more other components of platform 218. Alternatively, the Streaming Service Manager 1002 can be implemented in a static region 202.

[0125] Using the Flow Manager 1002 (which can operate at least partially as a switch), data from the host system can be routed via the accelerator arbitration circuit 908 to the interconnect 1102 and to one or more network cores 1104, to the interconnect 1106 and to one or more compute cores 1108, or to the NIC controller 208. For example, the Flow Manager 1002 can receive packets with a specified flow (e.g., route or destination). The Flow Manager 1002 is able to identify the flow of received packets and distribute the packets to the destination corresponding to the identified flow. This allows the Dynamic Area 204 to perform compute functions (e.g., hardware acceleration of tasks offloaded from the host system 100) and simultaneously perform network functions.

[0126] As another example, Figure 11The architecture illustrated allows data (e.g., packets) to flow from host system 100 to dynamic zone 204 for processing (e.g., via multiple compute cores and / or multiple network cores) and back to host system 100, or to flow from host system 100 to dynamic zone 204 for processing (e.g., via multiple compute cores and / or multiple network cores) and output to Ethernet via NIC controller 208, where NIC controller 208 may or may not use dynamic zone 204 (e.g., user circuits 1010 and / or 1012) for further data processing. Therefore, host system 100 can send data to dynamic zone 204 (e.g., compute core 1108) for processing. Flow traffic manager 1002 can determine whether to send the resulting data output from dynamic zone 204 back to host system 100 or NIC controller 208.

[0127] Although Figure 11 Not illustrated, but in another example, data can be exchanged directly between the computing kernel and the network kernel (or the user circuitry connected to the NIC controller 208).

[0128] Figure 12 Another example platform implemented in the programmable IC 132 is illustrated. Figure 12 In the example, a portion of static region 202 is shown as including NIC controller 208 and flow service manager 1002. Other components of static region 202 are not shown for clarity. Furthermore, instead of the separate ingress and egress communication interfaces illustrated, the communication interfaces between components of NIC controller 208 are shown more generally.

[0129] Figure 12 The architecture shown is intended for illustrative purposes to demonstrate more complex and powerful processing that can be used to extend the capabilities of platform 218 and NIC controller 208. In this example, dynamic region 204 is subdivided into multiple domains. Each domain is dedicated to a specific functionality. For example, dynamic region 204 includes NIC extension domain 1202, storage domain 1204, streaming domain 1206, and memory mapping domain 1208. In one aspect, each domain is implemented as a different PR region.

[0130] NIC extension domain 1202 may include a stream interface 1210 connected to acceleration arbitration circuitry 908. Stream interface 1210 is connected to RDMA circuitry 1212. Stream interface 1210 is further connected to stream interconnect 1230 in stream domain 1206 and to stream-to-memory-mapped interface 1228. Stream-to-memory-mapped interface 1228 bridges domains 1206 and 1208. For example, the stream-to-memory-mapped circuitry system of interface 1228 may be located in domain 1206, while the memory-mapped stream circuitry system of interface 1228 may be located in domain 1208. NIC extension domain 1202 also includes algorithm lookup circuitry 1214 connected to NIC core 906 and layer 4 processing and lookup circuitry 1216 connected to BITW interface 904.

[0131] Storage domain 1204 includes an NVMe EP 1218 connected to the streaming service manager 1002. The NVMe EP 1218 is also connected to an NVMe to NVMeoF 1220 and an NVMe / aggregation / encryption circuit 1222. The NVMe to NVMeoF 1220 is also connected to an RDMA 1212 in the NIC extension domain 1202. The NVMe / aggregation / encryption circuit 1222 is connected to PCIe RP 1224 and PCIe 1226, which are also included in storage domain 1204. PCIe RP 1224 and 1226 can connect to external non-volatile storage (e.g., non-volatile storage 136, such as an SSD).

[0132] Stream domain 1206 includes a stream interconnect 1230 connected to a stream service manager 1002. Stream domain 1206 also includes one or more stream cores 1232 connected to the stream interconnect 1230. Memory mapping domain 1208 includes a memory mapping interconnect 1234 connected to the stream service manager 1002. Memory mapping domain 1208 also includes one or more memory mapping cores 1236 connected to the memory mapping interconnect 1234. The memory mapping interconnect 1234 can be connected to one or more external DDR memories (e.g., volatile memory 134) via one or more memory controllers (not shown). Stream-to-memory mapping interface 1228 can also be connected to one or more external DDR memories (e.g., volatile memory 134) via one or more memory controllers (also not shown).

[0133] Figure 12This is provided for illustrative purposes and not for limitation. In other examples, one or more or any combination of domains can be implemented in dynamic region 204 at any given time. Furthermore, specific domains can be added and / or removed as needed during operation of programmable IC 132 using dynamic reconfiguration.

[0134] For example, once the platform is implemented in the programmable IC 132, a first portion of the configuration bitstream can be loaded into the programmable IC 132 to configure dynamic region 204 to include only flow domain 1206 and memory map domain 1208. At another time, a second portion of the configuration bitstream can be loaded into the programmable IC 132 to configure dynamic region 204 to implement memory domain 1204, flow domain 1206, and memory map domain 1208. At yet another time, a third portion of the configuration bitstream can be loaded into the programmable IC 132 to configure dynamic region 204 to implement NIC extension domain 1202, memory domain 1204, flow domain 1206, and memory map domain 1208.

[0135] On the other hand, each domain is implemented as a different PR region. Thus, the circuitry implemented in each corresponding domain can change over time without affecting the circuitry in other domains. In the case of inter-domain interfaces, data flow can be temporarily halted until the connecting PR regions have undergone partial reconfiguration.

[0136] Figure 13 The illustration depicts an example method 1300 for operating a programmable IC that implements the functionality of a smart NIC as described herein. In one aspect, combined with… Figure 13 The operations described related to the configuration of the programmable IC can be performed or initiated by the host system.

[0137] In block 1302, the programmable IC implements a platform within the device. This platform is implemented at least partially in the static circuitry of the programmable IC. For example, the host system is capable of writing a configuration bitstream (e.g., a complete or partial configuration bitstream) specifying the platform to non-volatile memory 136. The programmable IC is capable of bootstrapping at startup and loading the configuration bitstream for the platform. The configuration bitstream for the platform may reside within the programmable IC during operation. As discussed, the configuration bitstream at least partially defines a static region and physically implements the platform within that static region. Loading the configuration bitstream in block 1302 may also define a dynamic region of the device that is not used to implement the platform within the programmable IC.

[0138] In implementations that use one or more PR regions to implement a platform, the platform can be specified by loading multiple partial configuration bitstreams. For example, one partial configuration bitstream can be loaded to implement the portion of the platform in a static region. For each PR region used to implement the platform, another partial configuration bitstream is loaded for that PR region.

[0139] In block 1304, the programmable IC establishes communication links with the host system and the network. For example, the platform's PCIe controller establishes a communication link with the host system. The platform's Ethernet interface establishes a communication link with the network (e.g., nodes or switches in the network). It should be understood that once the platform is implemented in the programmable IC, the programmable IC can transmit data back and forth between the host system and the network.

[0140] In block 1306, the programmable IC implements a user-specified circuitry in a dynamic region of the device. For example, the host system can initiate partial reconfiguration of the programmable IC by loading a partial configuration bitstream therein. The partial configuration bitstream implements the user-specified circuitry in the dynamic region of the device. If the dynamic region comprises a single PR region, a single partial configuration bitstream can be loaded. If the dynamic region comprises multiple PR regions, the host system can initiate the loading of multiple partial configuration bitstreams into the programmable IC. For example, one partial configuration bitstream can be loaded for each PR region. In any case, one or more kernels can be implemented in each PR region of the dynamic region to implement the user-specified circuitry.

[0141] On one hand, as part of implementing a user-specified circuit system, the communication interface is selectively enabled and / or disabled based on metadata associated with the loaded partial configuration bitstream(s). In cases where the dynamic region comprises multiple PR regions, the partial configuration bitstream for a given PR region may include metadata necessary for programming the communication interface of the NIC controller coupled to that particular PR region.

[0142] In block 1308, the programmable IC is capable of using a user-specified circuitry to perform one or more operations as described in this disclosure. In block 1308, the user-specified circuitry is operable to process data for output and input data asymmetrically. That is, while input data is processed by one or more kernels in the dynamic region, or not processed by such kernels at all, output data may be processed independently of the processing performed on the input data by one or more different kernels in the dynamic region, or not processed by such kernels at all.

[0143] In block 1308, the left-hand block describes the processing of ingress data, while the right-hand block describes the processing of egress data. In block 1310, the programmable IC receives data from the network. The Ethernet interface receives the data and provides it to the NIC controller. In block 1312, the NIC controller in the platform can exchange data with user-specified circuitry in the dynamic area. Data is sent from one or more software-controlled communication interfaces, processed by the user-specified circuitry, and returned to the platform. In block 1314, the platform sends the processed data to the host system. For example, data is provided to DMA circuitry and the PCIe controller. The PCIe controller provides the processed data to the host system.

[0144] In block 1316, the programmable IC receives data from the host system. The PCIe controller receives data from the host system and provides it to the DMA circuitry. The DMA circuitry provides the data to one or more other circuits in the platform. In block 1318, the NIC controller is able to exchange data with user-specified circuitry in the dynamic area. Data is sent from one or more communication interfaces in the software-controlled communication interface, processed by the user-specified circuitry, and returned to the platform. In block 1320, the platform sends the processed data to the network. For example, the data is provided to the Ethernet interface. The Ethernet interface provides the processed data to the network.

[0145] On one hand, as part of block 1308 or at any time under the control of a processor as described herein, one or more of the platform's software-controlled communication interfaces can be turned on or off. For example, when implementing a dynamic region, each of the software-controlled communication interfaces can be placed in a specific state (on or off). As the programmable IC continues to operate, the software-controlled communication interfaces can be turned on or off independently of each other and reconfigured independently of the dynamic region.

[0146] For example, a given software-controlled communication interface can be enabled and then disabled without interrupting operation of the dynamic region. In some cases, a software-controlled communication interface can be disabled when a portion of the dynamic region connected to it (e.g., a specific PR region) is undergoing partial reconfiguration. The software-controlled communication interface can be re-enabled when the partial reconfiguration of the PR region is successful. In any case, dynamic control of the communication interface as described allows data flow through the dynamic region to be dynamically altered without initiating any partial reconfiguration within the dynamic region.

[0147] In block 1322, it is determined whether a trigger event has been detected. On one hand, the host system can receive requests for different types of user-specified circuitry to be implemented in the programmable IC, where such requests are considered trigger events for partial reconfiguration. On the other hand, the trigger event can be a signal or combination of signals detected by the programmable IC itself, which causes the programmable IC to notify the host system that partial reconfiguration is required. In either case, in response to the detection of a trigger event, method 1300 loops back to block 1306. In response to the absence of a trigger event, method 1300 continues to block 1324, where the programmable IC continues to operate with the current configuration of the platform and dynamic regions. Method 1300 can iterate between blocks 1322 and 1324 until a trigger event is detected.

[0148] In block 1306, the programmable IC is partially reconfigured. For example, the host system loads one or more additional partial configuration bitstreams into the programmable IC. The programmable IC may implement entirely new user-specified circuitry in the dynamic region (e.g., where the dynamic region comprises a single PR region) or implement new / different user-specified circuitry only in one or more selected or all PR regions of the dynamic region. Furthermore, the number of PR regions implemented in the dynamic region may change compared to the previous configuration of the dynamic region.

[0149] The arrangement of the invention described herein illustrates a platform implemented in a programmable IC that supports the dynamic (e.g., during runtime) insertion and / or replacement of functions consistent with network traffic. This platform enables the programmable IC to continue transmitting network traffic between the network and the host system without data loss. The inserted function can be inserted at any of a variety of insertion points within the data flow passing through the platform.

[0150] Figure 14 An example method 1400 for implementing a platform on a programmable IC is illustrated. In block 1402, a platform implemented at least partially in a static region of a programmable circuit system is provided on the device. In block 1404, a dynamic region of a programmable circuit system is provided on the device, configured to implement a user-specified circuit system communicating with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network, while at least a portion of the dynamic region of the programmable circuit system is dynamically reconfigured.

[0151] Figure 15The illustration depicts an example architecture 1500 for an IC. Architecture 1500 can be used to implement programmable ICs (such as programmable IC 132) as described herein. As an example, architecture 1500 can be used to implement a field-programmable gate array (FPGA). Architecture 1500 can also represent a System-on-Chip (SoC) type IC. An SoC is an IC that includes a processor that executes program code and one or more other circuits. The other circuits can be implemented as hardwired circuit systems, programmable circuit systems, and / or combinations thereof. These circuits can cooperate with each other and / or cooperate with the processor.

[0152] As shown, architecture 1500 includes several different types of programmable circuits, such as logic blocks. For example, architecture 1500 may include a large number of different programmable blocks, including a multi-gigabit transceiver (MGT) 1501, a configurable logic block (CLB) 1502, a random access memory block (BRAM) 1503, an input / output block (IOB) 1504, configuration and clock logic (CONFIG / CLOCKS) 1505, a digital signal processing block (DSP) 1506, dedicated I / O blocks 1507 (e.g., configuration ports and clock ports), and other programmable logic 1508 (such as a digital clock manager, an analog-to-digital converter, system monitoring logic, etc.).

[0153] In some ICs, each programmable block includes a programmable interconnect element (INT) 1511, which has standardized connections to and from corresponding INT 1511s in each adjacent block. Therefore, the INT 1511s together implement the programmable interconnect structure of the illustrated IC. Each INT 1511 also includes connections to and from programmable logic elements within the same block, such as in... Figure 15 The example included at the top is shown.

[0154] For example, CLB 1502 may include a configurable logic element (CLE) 1512 plus a single INT 1511, the configurable logic element (CLE) 1512 being programmable to implement user logic. In addition to one or more INT 1511s, BRAM 1503 may also include BRAM logic elements (BRL) 1513. Typically, the number of INT 1511s included in a block depends on the block height. As shown, the BRAM block has the same height as five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of INT 1511s, DSP block 1506 may also include DSP logic elements (DSPL) 1514. For example, in addition to one instance of INT 1511, IOB 1504 may also include two instances of I / O logic elements (IOL) 1515. The actual I / O pads connected to IOL 1515 may not be limited to the area of ​​IOL 1515.

[0155] exist Figure 15 In the example shown, a horizontal region near the center of the die (e.g., formed by regions 1505, 1507, and 1508) can be used for configuration, clocking, and other control logic. A vertical region 1509 extending from this horizontal region can be used for width-distributed clock and configuration signals across the programmable IC.

[0156] use Figure 15 Some of the ICs illustrated in the diagram include additional logic blocks that affect the conventional columnar structure that makes up the majority of the IC. These additional logic blocks can be programmable blocks and / or dedicated circuit systems. For example, a processor block described as PROC 1510 spans several columns of CLBs and BRAMs.

[0157] On one hand, the PROC 1510 can be implemented as a special-purpose circuit system, for example, as a hard-wired processor, which is manufactured as part of a programmable circuit system that implements an IC in a die. The PROC 1510 can represent any of a variety of different processor types and / or systems, ranging in complexity from an individual processor (e.g., a single core capable of executing program code) to an entire processor system with one or more cores, modules, coprocessors, interfaces, etc.

[0158] On the other hand, PROC 1510 can be omitted from architecture 1500 and replaced by one or more programmable blocks from other types of programmable blocks described. Furthermore, such blocks can be used to form a "soft processor" because various blocks of a programmable circuit system can be used to form a processor capable of executing program code (as with PROC 1510).

[0159] The phrase "programmable circuit system" refers to programmable circuit elements within an IC, such as the various programmable or configurable circuit blocks or sub-blocks described herein, and interconnecting circuit systems that selectively couple various circuit blocks, sub-blocks, and / or elements according to configuration data loaded into the IC. For example, Figure 15 The circuit blocks shown outside the PROC 1510 (such as CLB 1502 and BRAM 1503) are considered to be the programmable circuit system of the IC.

[0160] Typically, the functionality of a programmable circuit system is not established until configuration data is loaded into the IC. A set of configuration bits can be used to program a programmable circuit system of an IC such as an FPGA. These (multiple) configuration bits are often referred to as a "configuration bitstream." Generally, a programmable circuit system will not operate or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements a specific circuit design within the programmable circuit system. The circuit design specifies, for example, the functional aspects of the programmable circuit blocks and the physical connectivity between the various programmable circuit blocks.

[0161] Hard-wired or "hardened" (i.e., non-programmable) circuitry is manufactured as part of an IC. Unlike programmable circuitry, hard-wired circuitry, or circuit blocks, is not implemented after the IC is manufactured by loading a configuration bitstream. Hard-wired circuitry is typically considered to have dedicated circuit blocks and interconnects (e.g., it can operate without first loading a configuration bitstream into the IC), such as the PROC 1510.

[0162] In some instances, a hardwired circuit system can have one or more operating modes that can be set or selected based on register settings or values ​​stored in one or more memory elements within the IC. For example, the operating mode can be set by loading a configuration bitstream into the IC. Despite this capability, hardwired circuits are not considered programmable circuit systems because they are operable and have specific functions when manufactured as part of an IC.

[0163] In the case of a SoC, the configuration bitstream can specify the circuitry to be implemented within the programmable circuitry and the program code to be executed by the PROC 1510 or a soft processor. In some cases, Architecture 1500 includes a dedicated configuration processor that loads the configuration bitstream into the appropriate configuration memory and / or processor memory. The dedicated configuration processor does not execute the user-specified program code. In other cases, Architecture 1500 may utilize the PROC 1510 to receive the configuration bitstream, load the configuration bitstream into the appropriate configuration memory, and / or extract the program code for execution.

[0164] Figure 15This illustration aims to depict example architectures that can be used to implement ICs including programmable circuit systems (e.g., programmable structures). Examples include the number of logic blocks in a column, the relative width of the columns, the number and order of the columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the inclusion of... Figure 15 The interconnect / logic implementation at the top is purely illustrative. For example, in a real IC, more than one adjacent column of CLBs is typically included wherever a CLB appears to facilitate efficient implementation of the user's circuit design. However, the number of adjacent CLB columns can vary with the overall size of the IC. Furthermore, the size and / or positioning of blocks such as PROC 1510 within the IC are for illustrative purposes only and are not intended as limitations.

[0165] For illustrative purposes, specific nomenclature is explained to provide a thorough understanding of the various inventive concepts disclosed herein. However, the terminology used herein is for the purpose of describing specific aspects of the inventive arrangement only and is not intended to be limiting.

[0166] As defined herein, the singular forms “a,” “one,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0167] As defined herein, unless otherwise expressly stated, the terms “at least one,” “one or more,” and “and / or” are open-ended expressions that are both connected and separate in operation. For example, the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” and “A, B, and / or C” refer to A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0168] As defined in this article, the term “automatically” means without human intervention.

[0169] As defined herein, the term "computer-readable storage medium" means a storage medium that contains or stores program code used by or in conjunction with an instruction execution system, apparatus, or device. As defined herein, a "computer-readable storage medium" is not itself a transient, propagating signal. A computer-readable storage medium can be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. Various forms of memory described herein are examples of computer-readable storage media. A non-exhaustive list of more specific examples of computer-readable storage media may include: portable computer floppy disks, hard disks, RAM, read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electronically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, etc.

[0170] As defined herein, the term "if" means "when," "in," "in response to," or "in response to," depending on the context. Therefore, the phrase "if it is determined" or "if [the condition or event of the statement] is detected" can be interpreted as "when it is determined," "in response to determining," "when [the condition or event of the statement] is detected," "in response to detecting [the condition or event of the statement]," or "in response to detecting [the condition or event of the statement]," depending on the context.

[0171] As defined herein, the term "response" and similar language as described above, such as "if," "when," or "at," refers to a swift response or reaction to an action or event. A response or reaction is performed automatically. Therefore, if a second action is performed in response to a first action, a causal relationship exists between the occurrence of the first action and the occurrence of the second action. The term "response" implies a causal relationship.

[0172] As defined herein, the term "processor" refers to at least one hardware circuit. The hardware circuit can be configured to execute instructions contained in program code. The hardware circuit can be an integrated circuit. Examples of processors include, but are not limited to, central processing units (CPUs), array processors, vector processors, digital signal processors (DSPs), FPGAs, programmable logic arrays (PLAs), ASICs, programmable logic circuit systems, and controllers.

[0173] As defined herein, the term “real-time” refers to a level of responsiveness that a user or system senses for a particular process to be performed or determines is sufficiently immediate to enable the processor to keep up with certain external processing.

[0174] As defined herein, the term “substantially” means that it is not necessary to achieve the feature, parameter, or value precisely, but rather that deviations or variations (including, for example, tolerances, measurement errors, measurement accuracy limitations, and other factors known to those skilled in the art) may occur in a quantity that does not impede the effect that the feature is intended to provide.

[0175] The terms first, second, etc., may be used in this document to describe various elements. These elements should not be limited by these terms, as they are used only to distinguish one element from another unless otherwise specified or clearly indicated by the context.

[0176] A computer program product may include multiple computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of the invention arrangements described herein. In this disclosure, the terms "program code" and "computer-readable program instructions" are used interchangeably. The computer-readable program instructions described herein may be downloaded from the computer-readable storage media to a suitable computing / processing device, or downloaded via a network (e.g., the Internet, LAN, WAN, and / or wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge devices including edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0177] Computer-readable program instructions for performing the operations of the arrangements of the invention described herein may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​and / or procedural programming languages. Computer-readable program instructions may include state setting data. Computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including LAN or WAN) or (e.g., via the Internet through an Internet service provider). In some cases, electronic circuit systems, including, for example, programmable logic circuit systems, FPGAs, or PLAs, may execute computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuit system in order to perform aspects of the arrangements of the invention described herein.

[0178] This document describes certain aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions (e.g., program code).

[0179] These computer-readable program instructions may be provided to the processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create parts for implementing the functions / actions specified in the flowchart and / or block diagram(s). These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the operations specified in the flowchart and / or block diagram(s).

[0180] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operations to be performed on the computer, other programmable apparatus or other equipment to produce a computer-implemented process, such that the instructions, which are executed on the computer, other programmable apparatus or other equipment, implement the functions / actions specified in the flowchart and / or block diagram(s).

[0181] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products arranged according to various aspects of the present invention. In this regard, each block in a flowchart or block diagram may represent a portion of a module, segment, or instruction, which includes one or more executable instructions for implementing a specified operation.

[0182] In some alternative implementations, the operations mentioned in a block may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may be executed substantially simultaneously, or blocks may sometimes be executed in reverse order. In other examples, blocks may typically be executed in ascending numerical order, while in other examples, one or more blocks may be executed in a different order, with the results stored and utilized in subsequent or not immediately following blocks. It will also be noted that each block illustrated in the block diagrams and / or flowcharts, and combinations of blocks illustrated in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or action, or performs a combination of dedicated hardware and computer instructions.

[0183] The corresponding structures, materials, actions, and equivalents of all components or steps plus functional elements found in the following claims are intended to include any structures, materials, or actions used to perform functions in combination with other claimed elements as specifically required.

[0184] An apparatus includes a platform implemented at least partially in a static region of a programmable circuit system and a dynamic region of the programmable circuit system configured to implement a user-specified circuit system communicating with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network, while at least a portion of the dynamic region of the programmable circuit system is dynamically reconfigured.

[0185] The foregoing and other implementations may each optionally include one or more of the following features, individually or in combination. Some example implementations include all of the following features in combination.

[0186] On the other hand, the platform includes an Ethernet interface coupled to the NIC controller, a DMA circuit coupled to the network interface card controller, and a PCIe interface coupled to the DMA circuit.

[0187] On the other hand, at least one of the Ethernet interface, DMA circuitry, or network interface card controller is implemented in a partially reconfigurable area.

[0188] On the other hand, the user-specified circuit system is configured to perform grouping processing.

[0189] On the other hand, the platform includes a NIC controller with a communication interface that connects to dynamic regions.

[0190] On the other hand, the communication interface is located between the MAC and the first stage of the NIC controller.

[0191] On the other hand, the communication interface is software-activated.

[0192] On the other hand, the NIC controller includes multiple interconnect stages, and at least one of the multiple interconnect stages has a communication interface.

[0193] On the other hand, the first and second levels of the multiple interconnection levels each have independent communication interfaces configured to connect to dynamic regions.

[0194] On the other hand, each communication interface is connected to a different reconfiguration area in the dynamic area, and each reconfiguration area can be independently reconfigured to implement different user-specified circuits.

[0195] On the other hand, while the dynamic region is reconfigured to enable different user-specified circuitry systems to communicate with the platform, the platform continues to operate uninterruptedly.

[0196] A method includes: providing a platform on a device, at least partially implemented in a static region of a programmable circuit system, and providing a dynamic region of the programmable circuit system on the device, the dynamic region being configured to implement a user-specified circuit system communicating with the platform. The platform is configured to: establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of the programmable circuit system is dynamically reconfigured.

[0197] The foregoing and other implementations may each optionally include one or more of the following features, individually or in combination. Some example implementations include all of the following features in combination.

[0198] On the other hand, the platform includes an Ethernet interface coupled to the NIC controller, a DMA circuit coupled to the NIC controller, and a PCIe interface coupled to the DMA circuit.

[0199] On the other hand, at least one of the Ethernet interface, DMA circuitry, or network interface card controller is implemented in a partially reconfigurable area.

[0200] On the other hand, the user-specified circuit system is configured to perform grouping processing.

[0201] On the other hand, the method includes providing a NIC controller within the platform that has a communication interface connected to a dynamic region.

[0202] On the other hand, the communication interface is located between the MAC and the first stage of the NIC controller.

[0203] On the other hand, the method includes selectively activating the communication interface under software control.

[0204] In another aspect, the method includes providing multiple interconnect levels in a network interface card controller and providing a communication interface for at least one of the multiple interconnect levels.

[0205] On the other hand, the method includes providing a first level and a second level among a plurality of interconnection levels, wherein each of the first level and the second level has an independent communication interface configured to connect to a dynamic region.

[0206] On the other hand, each communication interface is connected to a different reconfiguration area in the dynamic area, and each reconfiguration area can be independently reconfigured to implement different user-specified circuits.

[0207] On the other hand, the method includes reconfiguring dynamic regions to enable different user-specified circuit systems to communicate with the platform while the platform continues to operate uninterruptedly.

[0208] The IC may include a platform implemented at least partially in the static region of the programmable circuit system, wherein the platform includes a network interface card controller coupled to a host interface and a network interface. The IC may also include a dynamic region of the programmable circuit system configured to implement user-specified circuit systems that communicate with the platform. The user-specified circuit systems may implement one or more packet processing functions. The network interface card controller includes multiple communication interfaces connected to the dynamic region. The platform may be configured to establish and maintain a first communication link with a host data processing system using the host interface and a second communication link with the network using the network interface. The platform may be configured to continue transmitting data between the network and the host data processing system while at least a portion of the dynamic region of the programmable circuit system is dynamically reconfigured to implement different user-specified circuit systems therein.

[0209] The foregoing and other implementations may each optionally include one or more of the following features, individually or in combination. Some example implementations include all of the following features in combination.

[0210] On the other hand, network interfaces include Ethernet interfaces.

[0211] On the other hand, the network interface is coupled to an arbitration circuit located in the static region between the network interface card controller's first stage and the network interface. The first of a plurality of communication interfaces connects the user-specified circuitry in the dynamic region to the arbitration circuit.

[0212] On the other hand, the arbitration circuit is configured to route data received from the network interface back to the network interface of the network, instead of providing the data to the network interface card controller.

[0213] On the other hand, the arbitration circuit routes the data back to the network interface after it has been processed by the user-specified circuit system.

[0214] On the other hand, the arbitration circuit is configured to route data received from the network interface card controller back to the network interface card controller, instead of providing data to the network interface.

[0215] On the other hand, the arbitration circuit routes the data back to the network interface card controller after it has been processed by the user-specified circuitry.

[0216] On the other hand, multiple communication interfaces are selectively enabled by the host data processing system.

[0217] On the other hand, the network interface card controller includes multiple levels, and each of the multiple communication interfaces is connected to a different level among the multiple levels.

[0218] On the other hand, the dynamic area comprises multiple partially reconfigurable areas, and each communication interface connects to different partially reconfigurable areas within these multiple partially reconfigurable areas. Each partially reconfigurable area can be independently reconfigured to implement different user-specified circuitry systems within it.

[0219] On the other hand, the host interface is a PCIe interface.

[0220] On the other hand, the IC may include DMA circuitry implemented in a static region, where the DMA circuitry is connected to the network interface card controller and the host interface. The memory controller may also be implemented in the static region. The memory controller may be coupled to the DMA circuitry and user-specified circuitry in the dynamic region.

[0221] On the other hand, the network interface card controller includes a network interface core connected to the network interface and an accelerator arbitration circuit connected to the DMA circuit. The accelerator arbitration circuit is coupled via a stream interface to one or more of the multiple partial reconfiguration regions within the dynamic region. Each partial reconfiguration region can implement different functionalities.

[0222] On the other hand, the flow interface is implemented in the first of the multiple partial reconfiguration areas and is connected to the accelerator arbitration circuitry of the network interface controller. User-specified circuitry can be implemented in one or more other partial reconfiguration areas.

[0223] On the other hand, one or more of the multiple partial reconfiguration regions include one or more kernel circuits configured to perform computational hardware acceleration tasks offloaded from the host data processing system.

[0224] The description of the invention arrangements provided herein is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed forms and examples. The terminology used herein is chosen to explain the principles, practical applications, or technical improvements to technologies found in the market, and / or to enable those skilled in the art to understand the invention arrangements disclosed herein. Modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described invention arrangements. Therefore, reference should be made to the following claims rather than the foregoing disclosure to indicate the scope of these features and implementations.

Claims

1. An integrated circuit, comprising: The platform is implemented, at least in part, in the static region of the programmable circuit system, wherein the platform includes a host interface, a network interface, and a network interface card controller, the network interface card controller being coupled to the host interface and the network interface; The dynamic region of the programmable circuit system is configured to implement a user-specified circuit system that communicates with the platform, wherein the user-specified circuit system implements one or more packet processing functions; The network interface card controller includes multiple communication interfaces connected to the dynamic area; The platform is configured to: establish and maintain a first communication link with a host data processing system outside the integrated circuit using the host interface, and establish and maintain a second communication link with a network outside the integrated circuit using the network interface; The platform is configured to continue transmitting data between the network and the host data processing system while at least a portion of the dynamic region of the programmable circuit system is dynamically reconfigured to implement different user-specified circuit systems therein; The plurality of communication interfaces includes one or more communication interfaces connected to the user-specified circuit system for communicating with the user-specified circuit system.

2. The integrated circuit according to claim 1, wherein the network interface includes an Ethernet interface.

3. The integrated circuit of claim 1, wherein the network interface is coupled to an arbitration circuit, the arbitration circuit being located in the network interface card controller between a first stage of the network interface card controller and the network interface; and The first of the plurality of communication interfaces connects the user-specified circuit system in the dynamic area to the arbitration circuit.

4. The integrated circuit of claim 3, wherein the arbitration circuit is configured to route data received from the network interface back to the network interface.

5. The integrated circuit of claim 4, wherein the arbitration circuit routes the data back to the network interface after processing by the user-specified circuit system.

6. The integrated circuit of claim 3, wherein the arbitration circuit is configured to route data received from the network interface card core in the network interface card controller back to the network interface card core, without providing the data to the network interface.

7. The integrated circuit of claim 5, wherein the arbitration circuit, after being processed by the user-specified circuit system, routes the data back to the network interface card core in the network interface card controller.

8. The integrated circuit of claim 1, wherein the plurality of communication interfaces are selectively enabled by the host data processing system.

9. The integrated circuit of claim 1, wherein the network interface card controller comprises multiple levels, and each of the multiple communication interfaces is connected to a different level among the multiple levels.

10. The integrated circuit according to claim 9, wherein: The dynamic region includes multiple partial reconfiguration regions, and each communication interface is connected to a different partial reconfiguration region within the multiple partial reconfiguration regions; as well as Each of the multiple partial reconfiguration areas can be reconfigured independently to implement different user-specified circuit systems.

11. The integrated circuit of claim 1, wherein the host interface is a peripheral component interconnect fast PCIe interface.

12. The integrated circuit according to claim 1, further comprising: A direct memory access circuit is implemented in the static region, wherein the direct memory access circuit is connected to the network interface card controller and the host interface; as well as A memory controller is implemented in the static region, wherein the memory controller is coupled to the direct memory access circuitry and the user-specified circuitry system in the dynamic region.

13. The integrated circuit of claim 12, wherein the network interface card controller includes a network interface card core and an accelerator arbitration circuit, the network interface core being coupled to the network interface, the accelerator arbitration circuit being coupled to the direct memory access circuit, wherein the accelerator arbitration circuit is coupled via a stream interface to one or more of a plurality of partial reconfiguration regions of a dynamic region, and wherein each partial reconfiguration region implements a different functionality.

14. The integrated circuit of claim 13, wherein the stream interface is implemented in a first partial reconfiguration region of the plurality of partial reconfiguration regions and connected to the accelerator arbitration circuitry of the network interface card controller and a user-specified circuitry implemented in one or more other partial reconfiguration regions of the plurality of partial reconfiguration regions.

15. The integrated circuit of claim 13, wherein one or more of the plurality of partial reconfiguration regions comprise one or more core circuits configured to perform computational hardware acceleration tasks offloaded from the host data processing system.

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