3D memory and control method thereof

Abstract

Disclosed is a 3D memory and a control method thereof. The control method comprises: performing a programming operation on a plurality of memory transistors when a first select transistor and a second select transistor are turned on; and performing a reading operation on the plurality of memory transistors when the first select transistor and the second select transistor are turned on, wherein, in an idle stage from the end of the programming operation on the plurality of memory transistors to the first reading operation, a channel pillar is biased at a negative potential to inhibit the escape of trapped electrons in a polysilicon channel trap of the plurality of memory transistors. The 3D memory and the control method thereof provided by the present application bias the channel pillar in the idle stage to reduce the transient reading error of the first reading, so that the result of the first reading does not need to be discarded. The control method can improve the reading speed of the 3D memory and reduce power consumption in the idle state and the reading operation.

Description

[0001] This application is a divisional application of the patent filed on April 15, 2021, with application number 202110405249.0, entitled "3D Memory and Control Method Thereof". Technical Field

[0002] This invention relates to the field of storage technology, and more specifically, to 3D memory and its control method. Background Technology

[0003] 3D memory comprises multiple memory cells stacked vertically, allowing for significantly increased integration density on a single wafer area and reduced costs. 3D memory is primarily used as non-volatile flash memory. The two main non-volatile flash memory technologies employ NAND and NOR structures, respectively. Compared to NOR memory, NAND memory has slightly slower read speeds but faster write speeds, simpler erase operations, and allows for smaller memory cells, resulting in higher storage density. Therefore, 3D memory using the NAND structure has gained widespread application.

[0004] In an example of a NAND structure 3D memory, multiple memory cell strings are arranged in a two-dimensional array. Each memory cell string is connected between a source line and a bit line and includes multiple memory transistors stacked vertically. Thus, the multiple memory cell strings together form multiple memory transistors arranged in a three-dimensional array. Each memory cell string includes multiple memory transistors sharing a common channel pillar. Each memory transistor includes a gate conductor, a channel region, and a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer sandwiched between them. Data is written to selected memory transistors using programming methods, for example, injecting charge into the charge storage layer to obtain logic 0, or clearing charge from the charge storage layer to obtain logic 1. During the programming operation, a programming voltage is applied not only to the gate conductor of the selected memory transistor to achieve data writing, but also a pass voltage is applied to the gate conductor of the unselected memory transistors to suppress programming.

[0005] During the idle phase between the end of the programming operation and the first read operation in the 3D memory, the gate conductor of the storage transistor is in a floating state. A certain number of grain boundary traps (GBTs) exist in the charge storage layer. Due to the charge trapping effect of these traps, a large number of transient read errors will occur during the first read operation, resulting in a First Read Issue (FRI). That is, the number of failure bit counts (FBC) during the first read is too high, and the FBC only returns to normal in subsequent read operations. In existing 3D memories and their control methods, the results of the first read must be discarded due to the FRI. The first read is also called a virtual read operation.

[0006] Further improvements are expected in 3D memory and its control methods to enhance the reliability of the first read and make the results of the first read available, thereby increasing read speed and reducing power consumption. Summary of the Invention

[0007] In view of the above problems, the present invention provides a 3D memory and a control method thereof, wherein, during the idle phase, the potential of the channel pillar is biased to a negative potential relative to the potential of the storage transistor to reduce transient read errors during the first read, so that the result of the first read can be used in the read operation.

[0008] According to one aspect of the present invention, a control method for a 3D memory is provided, the 3D memory comprising one or more memory cell strings, each memory cell string comprising a plurality of transistors sharing a common channel pillar, the plurality of transistors comprising a plurality of storage transistors, the control method comprising:

[0009] During the idle period between the end of the programming operation on the plurality of storage transistors and the execution of the first read operation on the plurality of storage transistors, the channel potential of the channel pillar is biased to a negative potential relative to the potential of the charge storage layer of the plurality of storage transistors.

[0010] Optionally, the plurality of transistors further includes at least one first virtual transistor and at least one second virtual transistor; wherein the plurality of memory transistors are located between the at least one first virtual transistor and the at least one second virtual transistor; the first virtual transistor closest to the plurality of memory transistors is the nearest neighbor first virtual transistor; and the second virtual transistor closest to the plurality of memory transistors is the nearest neighbor second virtual transistor.

[0011] During the idle phase, the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor are turned off before the plurality of storage transistors, so that the channel potential of the channel pillar is biased as negative relative to the potential of the charge storage layer of the plurality of storage transistors.

[0012] Optionally, when the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor are turned off before the plurality of storage transistors, the channel potential is biased to a negative potential as the gate voltage of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor decreases.

[0013] Optionally, the negative potential is equal to the threshold voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor.

[0014] Optionally, the control method further includes: performing one or more programming operations on the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor before the step of programming the plurality of storage transistors, such that the threshold voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor is greater than or equal to the threshold voltage of any one of the plurality of storage transistors, so that the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are turned off before the plurality of storage transistors.

[0015] Optionally, the threshold voltages of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are equal to each other.

[0016] Optionally, during the idle phase, the gate voltages of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor are less than their respective threshold voltages.

[0017] Optionally, the plurality of storage transistors, the at least one first virtual transistor, and the at least one second virtual transistor have the same structure.

[0018] Optionally, the plurality of transistors further includes a first selection transistor and a second selection transistor, wherein the at least one first virtual transistor, the plurality of storage transistors, and the at least one second virtual transistor are sequentially arranged between the first selection transistor and the second selection transistor, and the control method further includes:

[0019] When the first selection transistor and the second selection transistor are turned on, the plurality of storage transistors are programmed.

[0020] And when the first selection transistor and the second selection transistor are turned on, a read operation is performed on the plurality of storage transistors.

[0021] Optionally, during the programming operation, a programming voltage is applied to the gate conductor of the selected storage transistor of the plurality of storage transistors through a connected word line; a first pass voltage is applied to the gate conductors of the unselected storage transistor of the plurality of storage transistors, the at least one first virtual transistor, and the at least one second virtual transistor through their respective connected word lines.

[0022] Optionally, during a read operation, a read voltage is applied to the gate conductor of the selected storage transistor of the plurality of storage transistors via a connected word line; a second pass voltage is applied to the gate conductors of the unselected storage transistor of the plurality of storage transistors, the at least one first dummy transistor, and the at least one second dummy transistor via their respective connected word lines.

[0023] Optionally, during the idle phase, the gate voltages of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor recover from the first pass voltage to 0V.

[0024] Optionally, during the idle phase, the gate voltage of the plurality of storage transistors recovers from the programming voltage or the first pass voltage to 0V.

[0025] Optionally, during the idle phase, the first selection transistor and the second selection transistor are turned off, and the plurality of storage transistors are turned on or off.

[0026] According to another aspect of the present invention, a 3D memory is provided, comprising:

[0027] A memory array comprising: one or more strings of memory cells, each string of memory cells including a plurality of transistors sharing a common channel pillar, the plurality of transistors including a plurality of memory transistors;

[0028] and peripheral circuitry coupled to the memory array via one or more word lines for controlling the memory array; wherein,

[0029] The peripheral circuit is configured to: during the idle phase from the end of the programming operation on the plurality of storage transistors to the execution of the first read operation on the plurality of storage transistors, bias the channel potential of the channel pillar relative to the potential of the charge storage layer of the plurality of storage transistors to a negative potential.

[0030] Optionally, the plurality of transistors further includes at least one first virtual transistor and at least one second virtual transistor; wherein the plurality of memory transistors are located between the at least one first virtual transistor and the at least one second virtual transistor; the first virtual transistor closest to the plurality of memory transistors is the nearest neighbor first virtual transistor; and the second virtual transistor closest to the plurality of memory transistors is the nearest neighbor second virtual transistor.

[0031] The peripheral circuit is further configured to: during the idle phase, turn off the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor before the plurality of storage transistors, so that the channel potential of the channel pillar is biased to a negative potential relative to the potential of the charge storage layer of the plurality of storage transistors.

[0032] Optionally, the peripheral circuit is further configured to: perform one or more programming operations on the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor before the step of programming the plurality of storage transistors, such that the threshold voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor is greater than or equal to the threshold voltage of any one of the plurality of storage transistors.

[0033] Optionally, the plurality of transistors further includes a first selection transistor and a second selection transistor, wherein the first selection transistor and the second selection transistor are sequentially arranged as at least one first virtual transistor, the plurality of memory transistors, and at least one second virtual transistor;

[0034] The peripheral circuit is further configured to program the plurality of storage transistors when the first selection transistor and the second selection transistor are turned on.

[0035] And when the first selection transistor and the second selection transistor are turned on, a read operation is performed on the plurality of storage transistors.

[0036] Optionally, during the programming operation, the peripheral circuitry is configured to: apply a programming voltage to the word line connected to the selected memory transistor of the plurality of memory transistors; and apply a first pass voltage to the word line connected to the unselected memory transistor of the plurality of memory transistors, the at least one first virtual transistor, and the at least one second virtual transistor, respectively.

[0037] Optionally, during a read operation, the peripheral circuitry is configured to: apply a read voltage to the word line connected to the selected memory transistor of the plurality of memory transistors; and apply a second pass voltage to the word line connected to the unselected memory transistor of the plurality of memory transistors, the at least one first virtual transistor, and the at least one second virtual transistor, respectively.

[0038] Optionally, during the idle phase, the gate voltages of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor recover from the first pass voltage to 0V; the gate voltages of the plurality of storage transistors recover from the programming voltage or the first pass voltage to 0V.

[0039] Optionally, the memory array is a three-dimensional NAND array.

[0040] According to the 3D memory and its control method of the present invention, during the idle phase from the end of the programming operation to the first read operation, biasing the channel potential of the channel pillar relative to the potential of the plurality of storage transistors to a negative potential can suppress the escape of trapped electrons in the polysilicon channel traps corresponding to the plurality of storage transistors. The failure bit count (FBC) of the first read operation is significantly reduced. This control method can improve the reliability of the first read to make the result of the first read available, thereby increasing the read speed and reducing power consumption in the idle state and during read operations.

[0041] In a preferred embodiment, prior to the step of programming the plurality of storage transistors, the method further includes: performing multiple programming operations on the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor to adjust their threshold voltages so that their threshold voltages are greater than or equal to the threshold voltages of the plurality of storage transistors. After any one of the plurality of storage transistors has undergone a normal programming or reading operation, during the stage when the gate voltage returns to 0V, the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor located at the two ends of the plurality of storage transistors will turn off before the plurality of storage transistors, causing the channel between the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor to be in a floating state, and decreasing to a negative potential as the gate voltage decreases. This negative potential is equal to the threshold voltage of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor. This control method utilizes the down-coupling phenomenon (DCP) of the floating channel pillars to bias the channel at a negative potential, which can effectively suppress the escape of trapped electrons in the polysilicon channel traps corresponding to the plurality of storage transistors. Furthermore, this control method eliminates the need to turn on the selection transistor to provide bias voltage in the idle state, which not only avoids programming and reading interference between different memory cell strings, but also reduces the power consumption of the memory cell strings in the idle phase and simplifies the control circuit, thereby reducing system cost. Attached Figure Description

[0042] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0043] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D memory are shown respectively.

[0044] Figure 2 A perspective view of the 3D memory is shown.

[0045] Figure 3 A timing diagram of a control method for a 3D memory is shown.

[0046] Figure 4 and Figure 5 Show each Figure 3 The diagram illustrates the relationship between the number of failed bits and the number of reads in the 3D memory control method, as well as the principle of the first read problem.

[0047] Figure 6 This diagram illustrates the structure of a string of storage cells in a 3D memory.

[0048] Figure 7 This diagram illustrates the relationship between gate voltage and channel potential during the idle phase of a 3D memory control method.

[0049] Figure 8 A schematic diagram of the structure of a string of storage cells in a 3D memory according to an embodiment of the present invention is shown.

[0050] Figure 9 A schematic diagram showing the relationship between gate voltage and channel potential during the idle phase in a 3D memory control method according to an embodiment of the present invention is provided.

[0051] Figure 10 The relationship between the number of failure bits and the number of reads is shown in the 3D memory control method according to an embodiment of the present invention.

[0052] Figure 11 The relationship between the number of failure bits and the number of virtual memory transistors in the 3D memory control method according to an embodiment of the present invention is shown. Detailed Implementation

[0053] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0054] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0055] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0056] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0057] This invention can be presented in various forms, some of which will be described below.

[0058] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D memory are shown respectively. In this embodiment, the storage cell string shown includes four storage cells. It is understood that the invention is not limited to this; the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0059] like Figure 1a As shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first and second ends, including: a first selection transistor Q1, storage transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string select line SSL, and the gate of the second selection transistor Q2 is connected to the ground select line GSL. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines WL1 to WL4.

[0060] like Figure 1bAs shown, the first selection transistor Q1 and the second selection transistor Q2 of the memory cell string 100 each include gate conductors 122 and 123, and the memory transistors M1 to M4 each include a gate conductor 121. The gate conductors 121, 122, and 123 are arranged in the same stacking order as the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a barrier dielectric layer 114 are sandwiched between the gate conductor 121 and the channel region 111, thereby forming memory transistors M1 to M4. At both ends of the channel pillar 110, the gate conductors 122 and 123 are sandwiched between the gate conductors 122 and 123 and the channel region 111, thereby forming the first selection transistor Q1 and the second selection transistor Q2.

[0061] In this embodiment, the channel region 111 is composed, for example, of doped polysilicon; the tunneling dielectric layer 112 and the barrier dielectric layer 114 are each composed of oxides, such as silicon oxide; the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles; and the gate conductors 121, 122, and 123 are composed of metals, such as tungsten. The channel region 111 serves as the channel region for both the selection transistor and the storage transistor, and the doping type of the channel region 111 is the same as the type of the selection transistor and the storage transistor. For example, for an N-type selection transistor and a storage transistor, the channel region 111 can be N-type doped polysilicon.

[0062] In this embodiment, the core of the channel post 110 is a channel region 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the barrier dielectric layer 114 form a stacked structure surrounding the sidewall of the core. In an alternative embodiment, the core of the channel post 110 is an additional insulating layer, and the channel region 111, the tunneling dielectric layer 112, the charge storage layer 113, and the barrier dielectric layer 114 form a stacked structure surrounding the core.

[0063] In this embodiment, the first selection transistor Q1 and the second selection transistor Q2, and the storage transistors M1 to M4 use a common channel region 111 and a barrier dielectric layer 114. In the channel pillar 110, the channel region 111 provides the source / drain regions and channel regions for the plurality of transistors. In an alternative embodiment, the semiconductor layers and barrier dielectric layers of the first selection transistor Q1 and the second selection transistor Q2, as well as the semiconductor layers and barrier dielectric layers of the storage transistors M1 to M4, can be formed in separate steps.

[0064] Figure 2 A perspective view of the 3D memory is shown. For clarity, in... Figure 2The individual insulating layers in the 3D memory are not shown.

[0065] The 3D memory 200 shown in this embodiment includes 16 4x4 memory cell strings 100, each containing 4 memory cells, thus forming a 4x4x4 memory array with a total of 64 memory cells. It is understood that the invention is not limited thereto; the 3D memory can include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string can be any number, for example, 32 or 64.

[0066] In the 3D memory 200, each memory cell string includes its own channel pillar 110 and a common gate conductor 121, 122, and 123. The gate conductors 121, 122, and 123 are arranged in the same order as the transistors in the memory cell string 100. Adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

[0067] The internal structure of the channel column 110 is as follows Figure 1b As shown, no further details will be provided here. The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of multiple channel pillars 110 in the same column are connected to the same bit line (i.e., one of bit lines BL1 to BL4), and the second ends are connected to the substrate 101. The second ends form a common source connection through the substrate 100.

[0068] The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit 102. The gate lines of multiple channel pillars 110 in the same row are connected to the same series select line (i.e., one of the series select lines SSL1 to SSL4).

[0069] The gate conductors 121 of storage transistors M1 and M4 are respectively connected to the corresponding word lines. If the gate conductors 121 of storage transistors M1 and M4 are divided into different gate lines by gate line gaps 161, the gate lines on the same layer reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same word line (i.e., one of word lines WL1 to WL4) through conductive channels 133.

[0070] The gate conductors of the second selection transistor Q2 are connected as one. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line gap 161, the gate lines reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same ground selection line GSL through the conductive channel 133.

[0071] Figure 3 A timing diagram of a control method for a 3D memory is shown.

[0072] During the precharge phase, the gate conductors of the storage transistors receive a 0V voltage via their respective word lines. First selection transistor Q1 and second selection transistor Q2 are turned on, applying a precharge voltage to the bit line BL. This precharge voltage is applied to the channel pillars of the storage cell string 110, causing the channel regions within the channel pillars to reach the precharge voltage. Due to the precharge of the channel regions, the gate voltages of each storage transistor in the storage cell string 110 are all less than the tunneling voltage, thus suppressing programming.

[0073] During programming, the first selection transistor Q1 and the second selection transistor Q2 are turned on, and a 0V voltage is applied across the memory cell string 110 via the bit line BL and the source line SL. The gate conductor of the selected memory transistor Ms receives the programming voltage Vpgm via the corresponding word line WLs, while the gate conductor of the unselected memory transistor Ms receives the pass voltage Vpass (i.e., the first pass voltage) via the corresponding word line WLp. If a suitable programming voltage Vpgm and pass voltage Vpass are selected, the gate voltage of the selected memory transistor Ms exceeds the tunneling voltage, thus allowing programming. Since the gate voltage of the unselected memory transistor Ms is less than the tunneling voltage, programming of the unselected memory transistor can be suppressed.

[0074] After the programming operation, and after a period of idle time, the storage unit string 110 is read.

[0075] During the read operation, the first selection transistor Q1 and the second selection transistor Q2 are turned on, and a voltage difference is generated across the memory cell string 110 via the bit line BL and the source line SL. For example, the bit line BL and the source line SL are positive voltage and 0V voltage, respectively. The gate conductor of the selected memory transistor Ms receives the read voltage Vread via the corresponding word line WLs, and the gate conductor of the unselected memory transistor Ms receives the pass voltage Vpass (i.e., the second pass voltage) via the corresponding word line WLp. The threshold voltage of the memory transistor Ms varies with the amount of charge in the charge storage layer. If appropriate read voltage Vread and pass voltage Vpass are selected, the gate voltage of the selected memory transistor Ms is between the threshold voltage of the charged memory transistor Ms and the threshold voltage of the uncharged memory transistor Ms, and the gate voltage of the unselected memory transistor Ms is greater than both the threshold voltages of the charged and uncharged memory transistor Ms. Therefore, detecting the bit line voltage allows the logic value of the selected memory transistor to be read. Since the conduction state of the unselected storage transistor Ms is independent of the charge state in the charge storage layer, reading from the unselected storage transistor can be suppressed.

[0076] Figure 4 and Figure 5Show respectively according to Figure 3 The diagram illustrates the relationship between the number of failed bits and the number of reads in the 3D memory control method, as well as the principle of the first read problem.

[0077] The 3D memory's cell string remains idle for up to 24 hours after programming operations, followed by multiple read operations. In the cell string, word lines n to n+9 represent a total of 10 memory transistors stacked along the channel pillars. For example... Figure 4 As shown, for each memory transistor, the overall failure bit count (FBC) of the first read operation is higher than the failure bit count (FBC) of subsequent read operations, resulting in an unreliable first read result. This first read problem is particularly severe for the first layer of memory transistors being read.

[0078] In the storage cell string of a 3D memory, at 25°C and 85°C, the grain boundary trap (GBT) fill state of the charge storage layer (e.g., polysilicon floating gate) of the storage transistor changes with programming and reading operations. For example... Figure 5 As shown, during the programming operation (time period T1), the programming voltage Vpgm causes a large number of electrons to be trapped in the grain boundary traps. In the idle phase after the programming operation, the gate of the storage transistor is floating, and the gate voltage eventually decreases to 0V. The quasi-Fermi level (EFn) shifts downward, and the grain boundary traps in the charge storage layer release electrons, becoming empty traps. This causes a transient leftward shift in the threshold voltage of the storage transistor. In the first read operation after the programming operation (time period T2), the read voltage Vread performs the read operation according to the ideal storage transistor settings. However, the threshold voltage of the storage transistor has shifted. Therefore, the read voltage Vread in the first read operation is an incorrect read voltage relative to the threshold voltage of the storage transistor, and the overall failure bit count (FBC) of the first read operation is too high to provide a reliable value. After the first read operation, the read voltage Vread causes the grain boundary traps to recapture electrons, and the filling state of the grain boundary traps approaches the state at the end of the programming operation. The failure bit count (FBC) during the second read returns to the normal level.

[0079] Figure 6 A schematic diagram of the structure of a string of storage cells in a 3D memory is shown.

[0080] See Figure 2 and 3The memory cell string 100 includes a channel pillar 110. The channel pillar 110 extends through a gate stack structure. The gate stack structure includes multiple gate conductors. In the middle portion of the channel pillar, the channel pillar includes a channel region and a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer sandwiched between the gate conductors and the channel region, thereby forming multiple memory transistors Ms. At both ends of the channel pillar, the channel pillar includes a channel region and a barrier dielectric layer sandwiched between the gate conductors and the channel region, thereby forming a first selection transistor Q1 and a second selection transistor Q2, respectively.

[0081] See Figure 6 The gate conductor of the first selection transistor Q1 is connected to the serial select line SSL, and the gate conductor of the second selection transistor Q2 is connected to the ground select line GSL. The gate conductor of the storage transistor Ms is connected to the corresponding word line WL. The top end of the channel pillar 110 is connected to the bit line BL, and the bottom end is connected to the source line SL via the source region 11.

[0082] In a 3D memory, the threshold voltages of the first selection transistor Q1 and the second selection transistor Q2 of the storage cell string 100 are, for example, greater than 0V, and the threshold voltage of the storage transistor Ms is, for example, less than or equal to 0V.

[0083] Figure 7 This diagram illustrates the relationship between gate voltage and channel potential during the idle phase of a 3D memory control method.

[0084] During programming, the gate voltages of the first selection transistor Q1 and the second selection transistor Q2 are positive voltages greater than their respective threshold voltages. The gate voltage of the selected storage transistor Ms is the programming voltage Vpgm, and the gate voltage of the unselected storage transistor Ms is the pass voltage Vpass. Programming occurs when the gate voltage of the selected storage transistor Ms is greater than the tunneling voltage, and programming is suppressed when the gate voltage of the unselected storage transistor Ms is less than the tunneling voltage.

[0085] During the idle phase between the programming operation and the first read operation, the gate voltage of the first selection transistor Q1 and the gate voltage of the second selection transistor Q2 are both 0V, and the gate conductors of all storage transistors Ms are positive voltages greater than their respective threshold voltages.

[0086] In this 3D memory control method, the channel potential of the channel pillar 110 of the memory cell string 100 is, for example, 0V. Since the potential of the charge storage layer of the storage transistor Ms is negative relative to the channel potential, the grain boundary traps of the charge storage layer release electrons and become empty traps, that is, charge is lost from the charge storage layer, causing a transient shift in the threshold voltage of the storage transistor.

[0087] Figure 8 A schematic diagram of the structure of a string of storage cells in a 3D memory according to an embodiment of the present invention is shown.

[0088] See Figure 2 and 3 The memory cell string 200 includes a channel pillar 110. The channel pillar 110 extends through a gate stack structure. The gate stack structure includes multiple gate conductors. In the middle portion of the channel pillar, the channel pillar includes a channel region and a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer sandwiched between the gate conductors and the channel region, thereby forming multiple storage transistors Ms, at least one first dummy transistor Md1, and at least one second dummy transistor Md2. At both ends of the channel pillar, the channel pillar includes a channel region and a barrier dielectric layer sandwiched between the gate conductors and the channel region, thereby forming a first selection transistor Q1 and a second selection transistor Q2, respectively.

[0089] The at least one first virtual transistor Md1 is located between the first selection transistor Q1 and the plurality of storage transistors Ms, and includes the nearest neighbor first virtual transistor relative to the plurality of storage transistors Ms. The at least one second virtual transistor Md2 is located between the second selection transistor Q2 and the plurality of storage transistors Ms, and includes the nearest neighbor second virtual transistor relative to the plurality of storage transistors Ms.

[0090] See Figure 8 The gate conductor of the first selection transistor Q1 is connected to the serial select line SSL, and the gate conductor of the second selection transistor Q2 is connected to the ground select line GSL. The gate conductor of the storage transistor Ms is connected to the corresponding word line WL. The gate conductor of at least one first dummy transistor Md1 is connected to the corresponding word line WLd1, and the gate conductor of at least one second dummy transistor Md2 is connected to the corresponding word line WLd2. The top end of the channel pillar 110 is connected to the bit line BL, and the bottom end is connected to the source line SL via the source region 11.

[0091] In the 3D memory of this embodiment of the invention, the threshold voltages of the first selection transistor Q1 and the second selection transistor Q2 of the storage cell string 200 are, for example, greater than 0V; the threshold voltage of the nearest neighbor first virtual transistor in the at least one first virtual transistor Md1 is, for example, greater than 0V; the threshold voltages of the other first virtual transistors are, for example, less than or equal to 0V; the threshold voltage of the nearest neighbor second virtual transistor in the at least one second virtual transistor Md2 is, for example, greater than 0V; the threshold voltages of the other second virtual transistors are, for example, less than or equal to 0V; and the threshold voltage of the storage transistor Ms is, for example, less than or equal to 0V.

[0092] Figure 9 A schematic diagram showing the relationship between gate voltage and channel potential during the idle phase in a 3D memory control method according to an embodiment of the present invention is provided.

[0093] During programming, the gate voltages of the first selection transistor Q1 and the second selection transistor Q2 are positive voltages greater than their respective threshold voltages. The gate voltage of the selected storage transistor Ms is the programming voltage Vpgm, and the gate voltage of the unselected storage transistor Ms is the pass voltage Vpass. The gate voltages of the at least one first virtual transistor Md1 and the at least one second virtual transistor Md2 are also pass voltages Vpass. Programming occurs when the gate voltage of the selected storage transistor Ms is greater than the tunneling voltage, and programming is suppressed when the gate voltage of the unselected storage transistor Ms is less than the tunneling voltage.

[0094] During the idle phase between the programming operation and the first read operation, the gate voltage of the first selection transistor Q1 and the gate voltage of the second selection transistor Q2 are both 0V. The gate voltage of the nearest neighbor first virtual transistor in at least one first virtual transistor Md1 is 0V, and the gate voltages of the other first virtual transistors are positive voltages greater than their respective threshold voltages. The gate voltage of the nearest neighbor second virtual transistor in at least one second virtual transistor Md2 is 0V, and the gate voltages of the other second virtual transistors are positive voltages greater than their respective threshold voltages. The gate voltage of all storage transistors Ms is 0V, and the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor at both ends of all storage transistors Ms are in a turned-off state, making all storage transistors Ms a floating state (in the floating state, all storage transistors Ms are either turned on or turned off).

[0095] In this embodiment, the threshold voltage of the nearest-neighbor first virtual transistor in the at least one first virtual transistor Md1 and the nearest-neighbor second virtual transistor in the at least one second virtual transistor Md2 is greater than or equal to the threshold voltage of all storage transistors Ms. For example, before the step of programming all storage transistors Ms, the nearest-neighbor first virtual transistor in the at least one first virtual transistor Md1 and the nearest-neighbor second virtual transistor in the at least one second virtual transistor Md2 are programmed once or multiple times to adjust their threshold voltages.

[0096] After the programming operation of the storage transistor Ms is completed, the gate voltages of the nearest-neighbor first virtual transistor in at least one first virtual transistor Md1 and the nearest-neighbor second virtual transistor in at least one second virtual transistor Md2 recover from the pass voltage Vpass to 0V, and the gate voltages of all storage transistors Ms recover from the programming voltage Vpgm or the pass voltage Vpass to 0V. During the stage when the gate voltage recovers to 0V, due to the difference between the aforementioned nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor and the threshold voltage of the plurality of storage transistors, the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor located at the two ends of the plurality of storage transistors will turn off before the plurality of storage transistors, so that the channel between the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor is in a floating state, and drops to a negative potential as the gate voltage of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor decreases. This negative potential is equal to the threshold voltage of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor. The potential of all memory transistors Ms corresponding to the polysilicon channel is controlled by the threshold voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor at both ends and the gate voltage below the threshold voltage, which is a negative potential. This negative potential can suppress the escape of electrons trapped in the polysilicon channel traps corresponding to the multiple memory transistors.

[0097] In the 3D memory control method of this embodiment, the channel potential of the channel pillar 110 of the memory cell string 200 is, for example, a negative potential. Since the potential of the charge storage layer of the storage transistor Ms is a positive voltage relative to the channel potential, the grain boundary traps of the charge storage layer retain the trapped electrons under the effect of channel bias during the idle phase. Therefore, during the first read operation, the threshold voltage of the storage transistor remains unchanged, thus solving the first read problem.

[0098] Figure 10 The relationship between the number of failure bits and the number of reads is shown in the 3D memory control method according to an embodiment of the present invention.

[0099] The 3D memory's cell string remains idle for up to 24 hours after programming operations, followed by multiple read operations. In the cell string, word lines n to n+9 represent a total of 10 memory transistors stacked along the channel pillars.

[0100] The programming (PGM), read, and idle phase temperatures are all set to 25°C, with the idle phase lasting 12 hours. During the idle phase, the channel pillars of the memory cell string are floating. The gate voltages of the nearest-neighbor first and second-neighbor virtual transistors are 0V, and the channel is biased to a negative potential using the down-coupling phenomenon (DCP) of the floating channel pillars. In the first set of data, the gate voltage of the memory transistor is 2V, and the channel potential of the channel pillar is biased to a negative potential using the down-coupling phenomenon (DCP) of the floating channel pillar. In the other set of data, the gate voltage of the memory transistor is 0V, and the channel potential of the channel pillar is biased to 0V.

[0101] As shown in the figure, the failure bit count (FBC) of the first data set is significantly reduced compared to the second data set, and the failure bit count (FBC) of the storage transistors at different levels are all stable values. Therefore, this control method can improve the reliability of the first read, making the result of the first read usable, thereby increasing the read speed and reducing power consumption in idle states and read operations.

[0102] Figure 11 The relationship between the number of failure bits and the number of virtual memory transistors in the 3D memory control method according to an embodiment of the present invention is shown.

[0103] exist Figure 11 In the diagram, the horizontal axis represents the ratio of the number of failed bits during the first read to the number of failed bits during the second read, and the vertical axis represents the cumulative probability. A larger ratio indicates a more severe first-read problem. Curves "0", "x1", "x5", and "x10" represent the states where 0, 1, 5, and 10 virtual transistors are located at the two ends of the memory cell string, respectively. The threshold voltage of the virtual transistors at the two ends of the memory cell string is greater than or equal to the threshold voltage of the memory transistors in the middle of the string. During the idle phase, all virtual transistors are in the off state. As shown in the figure, the more virtual memory transistors there are, the better the optimization of the first-read problem.

[0104] In the above embodiments, it is described that in a 3D memory, the channel pillars of the memory cell string are floating and biased to a negative potential in an idle state, and the potential of the charge storage layer of the storage transistor is a positive voltage relative to the channel potential, thereby suppressing charge loss and improving the reliability of the first read.

[0105] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control method of a 3D memory, characterized by, The 3D memory includes one or more memory cell strings, each memory cell string including multiple transistors sharing a common channel pillar, the multiple transistors including multiple storage transistors; the multiple transistors also include at least one first virtual transistor and at least one second virtual transistor; wherein the multiple storage transistors are located between the at least one first virtual transistor and the at least one second virtual transistor; the first virtual transistor closest to the multiple storage transistors is the nearest neighbor first virtual transistor; the second virtual transistor closest to the multiple storage transistors is the nearest neighbor second virtual transistor; the threshold voltages of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are greater than or equal to the threshold voltage of any one of the multiple storage transistors; the control method includes: During the idle phase between the end of the programming operation on the plurality of storage transistors and the execution of the first read operation on the plurality of storage transistors, as the gate voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor decreases, the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are turned off before the plurality of storage transistors, so that the channel between the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor is in a floating state, so that the channel potential of the channel pillar is biased to a negative potential relative to the potential of the charge storage layer of the plurality of storage transistors.

2. The control method according to claim 1, characterized by, When the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are turned off before the plurality of memory transistors, the channel potential is biased to a negative potential as the gate voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor decreases.

3. The control method according to claim 1, characterized by, The control method further includes: Before the step of programming the plurality of storage transistors, the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are programmed once or multiple times to make the threshold voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor greater than or equal to the threshold voltage of any one of the plurality of storage transistors, so that the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are turned off before the plurality of storage transistors.

4. The control method according to claim 3, characterized by, The threshold voltages of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are equal to each other.

5. The control method according to claim 3, characterized by, During the idle phase, the gate voltages of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor are less than their respective threshold voltages.

6. The control method according to claim 1, characterized by, The plurality of transistors further includes a first selection transistor and a second selection transistor, wherein the first selection transistor and the second selection transistor are sequentially arranged as at least one first virtual transistor, the plurality of memory transistors, and at least one second virtual transistor, and the control method further includes: When the first selection transistor and the second selection transistor are turned on, the plurality of storage transistors are programmed. And when the first selection transistor and the second selection transistor are turned on, a read operation is performed on the plurality of storage transistors.

7. The control method according to claim 6, characterized by During programming, a programming voltage is applied to the gate conductor of the selected storage transistor of the plurality of storage transistors through the connected word line; The gate conductors of the unselected storage transistors of the plurality of storage transistors, the at least one first virtual transistor, and the at least one second virtual transistor are subjected to a first pass voltage through their respective connected word lines.

8. The control method according to claim 6, characterized by During a read operation, a read voltage is applied to the gate conductor of the selected memory transistor of the plurality of memory transistors through a connected word line; a second pass voltage is applied to the gate conductors of the unselected memory transistor of the plurality of memory transistors, the at least one first virtual transistor, and the at least one second virtual transistor through their respective connected word lines.

9. The control method according to claim 7, characterized by, During the idle phase, the gate voltages of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor recover from the first pass voltage to 0V.

10. The control method according to claim 7, characterized by, During the idle phase, the gate voltage of the plurality of storage transistors recovers from the programming voltage or the first pass voltage to 0V.

11. The control method according to claim 6, characterized by, During the idle phase, the first selection transistor and the second selection transistor are turned off, and the plurality of storage transistors are turned on or off.

12. A 3D memory, comprising: include: A memory array comprising: one or more memory cell strings, each memory cell string including a plurality of transistors sharing a common channel pillar, the plurality of transistors including a plurality of memory transistors; the plurality of transistors further including at least one first virtual transistor and at least one second virtual transistor; wherein the plurality of memory transistors are located between the at least one first virtual transistor and the at least one second virtual transistor; the first virtual transistor closest to the plurality of memory transistors is the nearest neighbor first virtual transistor; the second virtual transistor closest to the plurality of memory transistors is the nearest neighbor second virtual transistor; the threshold voltages of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor are greater than or equal to the threshold voltage of any one of the plurality of memory transistors; and peripheral circuitry coupled to the memory array via one or more word lines for controlling the memory array; wherein, The peripheral circuit is configured such that, during the idle phase from the end of the programming operation on the plurality of storage transistors to the execution of the first read operation on the plurality of storage transistors, as the gate voltage of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor decreases, the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor are turned off before the plurality of storage transistors, so that the channel between the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor is in a floating state, so that the channel potential of the channel pillar is biased to a negative potential relative to the potential of the charge storage layer of the plurality of storage transistors.

13. The 3D memory of claim 12, wherein, The peripheral circuit is further configured to: perform one or more programming operations on the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor before the step of programming the plurality of storage transistors, such that the threshold voltage of the nearest neighbor first virtual transistor and the nearest neighbor second virtual transistor is greater than or equal to the threshold voltage of any one of the plurality of storage transistors. 14.The 3D memory of claim 12, wherein, The plurality of transistors further includes a first selection transistor and a second selection transistor, wherein the first selection transistor and the second selection transistor are sequentially arranged as at least one first virtual transistor, the plurality of memory transistors, and at least one second virtual transistor; The peripheral circuit is further configured to perform programming operations on the plurality of storage transistors when the first selection transistor and the second selection transistor are turned on. And when the first selection transistor and the second selection transistor are turned on, a read operation is performed on the plurality of storage transistors. 15.The 3D memory of claim 14, wherein, During programming, the peripheral circuitry is configured to apply a programming voltage to the word lines connected to selected memory transistors of the plurality of memory transistors. A first pass voltage is applied to the word line to which the unselected memory transistor of the plurality of memory transistors, the at least one first virtual transistor, and the at least one second virtual transistor are respectively connected. 16.The 3D memory of claim 14, wherein, During a read operation, the peripheral circuitry is configured to apply a read voltage to the word line connected to the selected memory transistor of the plurality of memory transistors. A second pass voltage is applied to the word lines to which the unselected memory transistors of the plurality of memory transistors, the at least one first virtual transistor, and the at least one second virtual transistor are respectively connected. 17.The 3D memory of claim 15, wherein, During the idle phase, the gate voltages of the nearest-neighbor first virtual transistor and the nearest-neighbor second virtual transistor recover from the first pass voltage to 0V; the gate voltages of the plurality of storage transistors recover from the programming voltage or the first pass voltage to 0V.

18. The 3D memory of claim 12, wherein, The memory array is a three-dimensional NAND array.

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