Method of operating a host device and a memory device and a memory system

Abstract

A method of operating a host device and a memory device and a memory system are provided. The method of operating the host device includes transmitting a request command for performing an eye opening monitor (EOM) operation to the memory device, transmitting a parameter for performing the EOM operation to the memory device, transmitting mode data for performing the EOM operation to the memory device, and receiving a first response signal from the memory device, the first response signal including a result of the EOM operation performed based on the parameter and the mode data.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0157332, filed on November 23, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The disclosure relates to methods for operating host devices and memory devices, as well as memory systems. Background Technology

[0003] To detect the quality characteristics of signals transmitted and received through a channel, an eye-open monitor (EOM) is used. To measure the eye diagram of the signal received at the signal receiving end of a memory system (e.g., the receiver of the memory device), the memory device and an external device can be used to measure the eye of the signal received by the memory device.

[0004] However, in this case, the signal lines used to perform the measurement are different from the signal lines used by the memory device to actually receive the signal. Therefore, the measurement results may be inaccurate, and the measurement method is not simple. Summary of the Invention

[0005] The disclosed aspect provides a method of operating a host device for easily performing reliable eye diagram opening monitor (EOM) operation.

[0006] The disclosed aspect also provides an operating method for a memory device for easily performing reliable EOM operations.

[0007] The publicly available information also provides a memory system for easily performing reliable EOM operations.

[0008] It should be noted that the purpose of this disclosure is not limited to the purposes described above, and other purposes of the disclosure will be apparent to those skilled in the art from the following description.

[0009] According to some disclosed aspects, a method of operating a host device includes: the host device sending a request command for performing an EOM operation to a memory device; the host device sending parameters for performing the EOM operation to the memory device; the host device sending mode data for performing the EOM operation to the memory device; and the host device receiving a first response signal from the memory device, the first response signal including the result of the EOM operation performed based on the parameters and mode data.

[0010] According to some other disclosed aspects, a method of operating a memory device includes: receiving a request command from a host device for performing an EOM operation; receiving parameters from the host device for performing the EOM operation; receiving mode data from the host device for performing the EOM operation; performing the EOM operation based on the parameters and mode data; and sending a first response signal including the result of performing the EOM operation to the host device.

[0011] According to some other disclosed aspects, a memory system includes: a host device including a host controller; and a memory device including a device controller and an EOM (Entity Memory Operation). The host controller is configured to: send a request command for performing an EOM operation to the memory device, send parameters for performing the EOM operation to the memory device, send mode data for performing the EOM operation to the memory device, and receive a first response signal from the memory device, the first response signal including the result of the EOM operation performed based on the parameters and the mode data. Attached Figure Description

[0012] The above and other aspects and features disclosed will become clearer from the detailed description of the disclosed exemplary embodiments with reference to the accompanying drawings, wherein:

[0013] Figure 1 This is a block diagram of a memory system according to some example embodiments;

[0014] Figure 2 yes Figure 1 Block diagram of the Mobile Industry Processor Interface (MIPI) M-PHY;

[0015] Figure 3 and Figure 4 It is shown Figure 2 An illustration of the eye opening monitor (EOM);

[0016] Figure 5 It is shown Figure 1 A diagram illustrating the rearrangement of the Universal Flash Storage (UFS) device controller, storage interface, and non-volatile storage devices;

[0017] Figure 6 yes Figure 5 Example block diagram of a storage device;

[0018] Figure 7 This is a diagram illustrating a three-dimensional (3D) vertical (V)-NAND structure according to some example embodiments;

[0019] Figure 8 This is a sequence diagram illustrating the operation of a memory system according to some example embodiments;

[0020] Figures 9 to 14 This is a diagram illustrating the operation of a memory system according to some example embodiments;

[0021] Figure 15 This is a sequence diagram illustrating the operation of a memory system according to some example embodiments; and

[0022] Figure 16 This is a flowchart illustrating the operation of a memory system according to some example embodiments. Detailed Implementation

[0023] In the following description, exemplary embodiments based on the disclosed drawings will be described with reference to the accompanying drawings.

[0024] Figure 1 This is a block diagram of a memory system based on some publicly available example embodiments. Figure 2 yes Figure 1 Block diagram of the Mobile Industry Processor Interface (MIPI) M-PHY. Figure 3 and Figure 4 It is shown Figure 2 An illustration of the eye opening monitor (EOM).

[0025] The following description uses an example of a system conforming to the Universal Flash Storage (UFS) standard announced by the Joint Electron Device Engineering Council (JEDEC) to illustrate a memory system based on the disclosure. However, the disclosure is not limited thereto, and any aspect of the memory system may be modified within the scope of the disclosure.

[0026] Reference Figure 1 The UFS system 1 may include a host device (e.g., a UFS host) 100, a memory device (e.g., a UFS device) 200, and a UFS interface 300.

[0027] The host device 100 and the storage device 200 can be connected to each other via the UFS interface 300. In some example embodiments, the host device 100 may be implemented as part of an application processor.

[0028] The host device 100 may include a UFS host controller 110, an application 120, a UFS driver 130, a host memory 140, and a UFS interconnect (UIC) layer 150.

[0029] The memory device 200 may include a UFS device controller 210, a non-volatile storage device 220, a storage interface 230, a device memory 240, a UIC layer 250, and a regulator 260.

[0030] The non-volatile storage device 220 may include a plurality of storage cells 221. Storage cells 221 may include vertical (V)-NAND flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) structure, or may include other types of non-volatile memory (such as phase-change random access memory (PRAM) and / or resistive random access memory (RRAM)).

[0031] The UFS device controller 210 and the non-volatile storage device 220 can be connected to each other via a storage interface 230. The storage interface 230 can be implemented to conform to standard protocols (such as Toggle or Open NAND Flash Interface (ONFI)). The operation between the UFS device controller 210 and the non-volatile storage device 220 using Toggle will be described later.

[0032] Application 120 may include a program that needs to communicate with memory device 200 to use the functionality of memory device 200. Application 120 may send input-output requests (IORs) to UFS drive 130 for input and / or output to memory device 200. IORs may include, but are not limited to, data read requests, data write requests, and / or data erase requests.

[0033] UFS drive 130 can manage UFS host controller 110 via UFS-Host Controller Interface (HCI). UFS drive 130 can translate an IOR generated by application 120 into UFS commands defined in the UFS standard and send the translated UFS commands to UFS host controller 110. One IOR can be translated into multiple UFS commands. Essentially, UFS commands can be either commands specific to the UFS standard or commands defined in the Small Computer Small Interface (SCSI) standard.

[0034] The UFS host controller 110 can send UFS commands translated by the UFS driver 130 to the UIC layer 250 of the storage device 200 via the UIC layer 150 and the UFS interface 300. In this process, the UFS host register 111 of the UFS host controller 110 can be used as a command queue (CQ).

[0035] The UIC layer 150 of the host device 100 may include MIPI M-PHY 151 and MIPI UniPro 152, and the UIC layer 250 of the memory device 200 may include MIPI M-PHY 251 and MIPI UniPro 252.

[0036] Reference Figure 2The MIPI M-PHY 251 may include an EOM 251a and a Special Function Register (SFR) 251b.

[0037] The EOM 251a can be used with the SFR 251b to measure the quality of signals received from the host device 100 under specific offset conditions.

[0038] Specifically, refer to Figures 2 to 4 EOM 251a may be included in Figure 3 The main path is displayed as a solid line in the middle and in the middle. Figure 3 The EOM path is shown as a dashed line.

[0039] In the main path, the clock RCK can be recovered from the signal S using the clock recovery circuit CDR, and the data of the signal S is extracted using the recovered clock RCK to generate the main path signal MS. The signal S is received from the host device 100 and passes through the equalizer EQ. Then, the main path signal MS can be sent to the comparator COMP.

[0040] In the EOM path, clock dXRCK is generated by reflecting a specific offset value dX in clock RCK recovered from signal S, and data of signal S is extracted using clock dXRCK to reflect a specific offset value dY, thereby generating the EOM path signal ES. Signal S is received from host device 100 and passes through equalizer EQ. Then, the EOM path signal ES can be sent to comparator COMP.

[0041] For example, the main path signal MS can be in Figure 4 The data extracted under the reference conditions (XR, YR), the EOM path signal ES can be in Figure 4 Data extracted under the offset condition (dX, dY). Furthermore, in Figure 4 In this diagram, the X-axis can represent time, phase, etc., and the Y-axis can represent voltage, etc.

[0042] When the EOM path signal ES is identified as the same as the main path signal MS, the comparator COMP may not output the error count signal EC. Conversely, when the EOM path signal ES is identified as a different signal from the main path signal MS, the comparator COMP may output the error count signal EC. Furthermore, the comparator COMP may output the sample count signal SC each time a sample is taken.

[0043] In some example embodiments, the offset value dX may include a time offset value, a phase offset value, etc., and the offset value dY may include a voltage offset value, etc. However, the example embodiments are not limited thereto.

[0044] In some example embodiments, information such as the offset value dX, the offset value dY, the error count value of the error count signal EC, and the number of samples based on the sample count signal SC can be stored in the SFR 251b, but the example embodiments are not limited thereto. The detailed operation of the EOM 251a will be described later.

[0045] Return to reference Figure 1 The UFS interface 300 may include a line for transmitting a reference clock REF_CLK, a line for transmitting a hardware reset signal RESET_n for the memory device 200, a pair of lines for transmitting a pair of differential input signals DIN_T and DIN_C, and a pair of lines for transmitting a pair of differential output signals DOUT_T and DOUT_C.

[0046] The frequency value of the reference clock REF_CLK provided from the host device 100 to the memory device 200 may have one of four values: 19.2MHz, 26MHz, 38.4MHz, and 52MHz, but is not limited to these. Even during operation (i.e., when data is being sent and received between the host device 100 and the memory device 200), the host device 100 may change the frequency value of the reference clock REF_CLK.

[0047] The memory device 200 can use a phase-locked loop (PLL) or similar device to generate clocks with various frequencies based on a reference clock REF_CLK received from the host device 100. Furthermore, the host device 100 can set the data rate value between itself and the memory device 200 using the frequency value of the reference clock REF_CLK. In other words, the data rate value can be determined based on the frequency value of the reference clock REF_CLK.

[0048] The UFS interface 300 can support multiple lanes, and each lane can be implemented as a pair of differential lanes. For example, the UFS interface 300 may include one or more receive lanes and one or more transmit lanes. Figure 1 In this configuration, the pair of lines used to transmit a pair of differential input signals DIN_T and DIN_C can be a receiving path, and the pair of lines used to transmit a pair of differential output signals DOUT_T and DOUT_C ​​can be a transmitting path. Although Figure 1 A pair of transmit paths and a pair of receive paths are shown, but the number of transmit paths and the number of receive paths can be changed differently.

[0049] The receive and transmit paths can transmit data serially, and due to the separate structure of the receive and transmit paths, full-duplex communication is feasible between the host device 100 and the memory device 200. In other words, even when receiving data from the host device 100 via the receive path, the memory device 200 can still send data to the host device 100 via the transmit path. Furthermore, control data (such as commands from the host device 100 to the memory device 200) and user data can be transmitted through the same path; the user data will be stored in the non-volatile storage device 220 of the memory device 200 or read by the host device 100 from the non-volatile storage device 220. Therefore, in addition to a pair of receive paths and a pair of transmit paths, no additional paths are needed for transmitting data between the host device 100 and the memory device 200.

[0050] The UFS device controller 210 of the memory device 200 can control the overall operation of the memory device 200.

[0051] UFS device controller 210 can manage non-volatile storage device 220 through logical units (LUs) 211, which are logical data storage units. The number N of LUs 211 can be, for example, eight, but the example embodiment is not limited to this.

[0052] The UFS device controller 210 may include a flash translation layer (FTL) and uses address mapping information from the FTL to translate logical data addresses (e.g., logical block addresses (LBAs)) received from the host device 100 into physical data addresses (e.g., physical block addresses (PBAs) or physical page numbers (PPNs)). In the UFS system 1, logical blocks used to store user data may have sizes within a specific range. For example, the minimum size of a logical block may be set to 4K (kilobytes).

[0053] When a command from host device 100 is input to memory device 200 via UIC layer 250, UFS device controller 210 can execute an operation according to the input command. When the operation is completed, UFS device controller 210 can send a completion response to host device 100.

[0054] As an example, when host device 100 wants to store user data in storage device 200, host device 100 can send a data write command to storage device 200. When a "ready-to-transfer" response is received from storage device 200, host device 100 can send the user data to storage device 200. UFS device controller 210 can temporarily store the received user data in device memory 240 and store the user data temporarily stored in device memory 240 to a selected location in non-volatile storage device 220 based on FTL address mapping information.

[0055] As another example, when host device 100 needs to read user data stored in memory device 200, host device 100 can send a data read command to memory device 200. The UFS device controller 210, receiving the command, can read the user data from non-volatile storage device 220 based on the data read command and temporarily store the read user data in device memory 240. In this read process, UFS device controller 210 can use embedded error correction code (ECC) circuitry (not shown) to detect and correct errors in the read user data. Furthermore, UFS device controller 210 can send the user data temporarily stored in device memory 240 to host device 100.

[0056] Additionally, the UFS device controller 210 may include an Advanced Encryption Standard (AES) circuit (not shown). The AES circuit can use a symmetric key algorithm to encrypt or decrypt data input to the UFS device controller 210.

[0057] The host device 100 can sequentially store commands to be transmitted to the memory device 200 in the UFS host register 111, which can be used as a queue (CQ), and send the commands sequentially to the memory device 200. At this time, even if a previously sent command is still being processed by the memory device 200 (i.e., even before the host device 100 is notified that the previously sent command has been fully processed by the memory device 200), the host device 100 can still send subsequent commands waiting in the CQ to the memory device 200. Therefore, the memory device 200 can receive subsequent commands from the host device 100 while processing previously received commands. As an example, the maximum number of commands that can be stored in the CQ (i.e., the queue depth) can be 32. Furthermore, the CQ can be implemented in a loop type, where the start and end of the command string stored in the queue are indicated by a head pointer and a tail pointer, respectively.

[0058] Each of the plurality of memory cells 221 may include a memory cell array (not shown) and control circuitry (not shown), the control circuitry (not shown) controlling the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a single-level cell (SLC) storing one bit of information or a cell storing two or more bits of information (such as a multilevel cell (MLC), triple-level cell (TLC), or quadruple-level cell (QLC)). A 3D memory cell array may include vertically oriented vertical NAND strings, such that at least one memory cell can be placed on top of another memory cell. This will be described in further detail below.

[0059] As power supply voltages, VCC, VCCQ1, VCCQ2, etc., can be input to the memory device 200. VCC is the main power supply voltage for the memory device 200 and can have a value of 2.4V to 3.6V. VCCQ1 is a power supply voltage used to supply a low voltage range and is primarily intended for use with the UFS device controller 210. For example, VCCQ1 can have a value of 1.14V to 1.26V. VCCQ2 is a power supply voltage used to supply a voltage range lower than VCC but higher than VCCQ1 and is primarily intended for use with input / output interfaces (such as MIPI M-PHY 251). For example, VCCQ2 can have a value of 1.7V to 1.95V. The power supply voltage can be supplied to each element of the memory device 200 via a regulator 260. The regulator 260 can be implemented as a set of unit regulators, each unit regulator connected to the aforementioned power supply voltages.

[0060] Figure 5 It is shown Figure 1 A diagram illustrating the rearrangement of the UFS device controller, storage interface, and non-volatile storage devices.

[0061] Figure 1 The storage interface 230 may include a controller interface (e.g., controller interface circuitry) 230a and a memory interface (e.g., memory interface circuitry) 230b. In some example embodiments, Figure 5 The storage device (e.g., a non-volatile memory device) 224 shown may correspond to Figure 1 A storage unit 221. Furthermore, in some example embodiments, storage device 224 may correspond to... Figure 1 220. Non-volatile storage device.

[0062] Storage device 224 may include first pins P11 to eighth pins P18, memory interface circuitry 230b, control logic (e.g., control logic circuitry) 510, and memory cell array 520.

[0063] The memory interface circuit 230b can receive the chip enable signal nCE from the device controller 210 via the first pin P11. The memory interface circuit 230b can send signals to and receive signals from the device controller 210 via the second pin P12 to the eighth pin P18 based on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 230b can send signals to and receive signals from the device controller 210 via the second pin P12 to the eighth pin P18.

[0064] The memory interface circuit 230b can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the device controller 210 via pins P12 to P14, respectively. Through pin P17, the memory interface circuit 230b can receive or send the data signal DQ from the device controller 210. Command CMD, address ADDR, and data can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to multiple data signals.

[0065] The memory interface circuit 230b can acquire the command CMD from the data signal DQ received in the enable portion (e.g., high state) of the command latch enable signal CLE based on the toggle timing of the write enable signal nWE. The memory interface circuit 230b can also acquire the address ADDR from the data signal DQ received in the enable portion (e.g., high state) of the address latch enable signal ALE based on the toggle timing of the write enable signal nWE.

[0066] In some example embodiments, the write enable signal nWE can be held statically (e.g., high or low) and toggled between high and low levels. For example, the write enable signal nWE can be toggled during the portion where the command CMD or address ADDR is sent. Therefore, the memory interface circuit 230b can obtain the command CMD or address ADDR based on the toggling timing of the write enable signal nWE.

[0067] The memory interface circuit 230b can receive the read enable signal nRE from the device controller 210 via the fifth pin P15. The memory interface circuit 230b can receive the data strobe signal DQS from the device controller 210 or send the data strobe signal DQS to the device controller 210 via the sixth pin P16.

[0068] During the operation of the storage device 224 to output data, the memory interface circuit 230b may receive a toggling read enable signal nRE (i.e., the read enable signal nRE of the toggling state) via pin 5 P15 before outputting the data. The memory interface circuit 230b may generate a toggling data strobe signal DQS based on the toggling of the read enable signal nRE. For example, the memory interface circuit 230b may generate a data strobe signal DQS that begins to switch after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read enable signal nRE. The memory interface circuit 230b may transmit a data signal DQ including data DATA based on the switching timing of the data strobe signal DQS. Therefore, data DATA may be sent to the device controller 210 according to the switching timing of the data strobe signal DQS.

[0069] During the operation of the storage device 224 receiving data DATA, when the data signal DQ including the data DATA is received from the device controller 210, the memory interface circuit 230b can receive the switched data strobe signal DQS and the data DATA together from the device controller 210. The memory interface circuit 230b can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the memory interface circuit 230b can obtain the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0070] The memory interface circuit 230b can send a ready / busy output signal nR / B to the device controller 210 via pin 8 P18. The memory interface circuit 230b can also send status information of the storage device 224 to the device controller 210 via the ready / busy output signal nR / B. When the storage device 224 is in a busy state (e.g., when internal operations of the storage device 224 are being performed), the memory interface circuit 230b can send a ready / busy output signal nR / B indicating the busy state to the device controller 210. When the storage device 224 is in a ready state (e.g., when internal operations of the storage device 224 are not being performed or have been completed), the memory interface circuit 230b can send a ready / busy output signal mR / B indicating the ready state to the device controller 210. As an example, when storage device 224 is reading data DATA from memory cell array 520 in response to a page read command, memory interface circuit 230b may send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to device controller 210. As another example, when storage device 224 is programming data DATA into memory cell array 520 in response to a programming command, memory interface circuit 230b may send a ready / busy output signal nR / B indicating a busy state to device controller 210.

[0071] The control logic circuit 510 can generally control various operations of the storage device 224. The control logic circuit 510 can receive acquired commands (CMD) and addresses (ADDR) from the memory interface circuit 230b. The control logic circuit 510 can generate control signals for controlling other components of the storage device 224 based on the received commands (CMD) and addresses (ADDR). For example, the control logic circuit 510 can generate various control signals for programming data DATA into or reading data DATA from the memory cell array 520.

[0072] The memory cell array 520 can store data DATA obtained from the memory interface circuit 230b under the control of the control logic circuit 510. The memory cell array 520 can also output the stored data DATA to the memory interface circuit 230b under the control of the control logic circuit 510.

[0073] The memory cell array 520 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the disclosure is not limited thereto, and the memory cells may be RRAM cells, ferroelectric random access memory (FRAM) cells, PRAM cells, thyristor random access memory (TRAM) cells, or magnetic random access memory (MRAM) cells. Exemplary embodiments of the disclosure will now be described, wherein, for purposes of description, the memory cells are NAND flash memory cells.

[0074] The device controller 210 may include first pins P21 to eighth pins P28 and controller interface circuitry 230a. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the storage device 224, respectively.

[0075] The controller interface circuit 230a can send the chip enable signal nCE to the storage device 224 via the first pin P21. The controller interface circuit 230a can send signals to the storage device 224 selected by the chip enable signal nCE and receive signals from the storage device 224 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0076] The controller interface circuit 230a can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the storage device 224 via the second pin P22 to the fourth pin P24, respectively. The controller interface circuit 230a can send the data signal DQ to the storage device 224 or receive the data signal DQ from the storage device 224 via the seventh pin P27.

[0077] The controller interface circuit 230a can send a data signal DQ, including a command CMD or address ADDR, and a write enable signal nWE, to the storage device 224. When sending a command latch enable signal CLE with an enabled state, the controller interface circuit 230a can send the data signal DQ, including the command CMD, to the storage device 224. When sending an address latch enable signal ALE with an enabled state, the controller interface circuit 230a can send the data signal DQ, including the address ADDR, to the storage device 224.

[0078] The controller interface circuit 230a can send the read enable signal nRE to the storage device 224 via the fifth pin P25. The controller interface circuit 230a can receive the data strobe signal DQS from the storage device 224 or send the data strobe signal DQS to the storage device 224 via the sixth pin P26.

[0079] During the operation of the storage device 224 outputting data DATA, the controller interface circuit 230a can generate a switching read enable signal nRE and send the read enable signal to the storage device 224. For example, before the data DATA is output, the controller interface circuit 230a can generate a read enable signal nRE that transitions from a static state (e.g., high or low level) to a switching state. Therefore, a data strobe signal DQS that switches based on the read enable signal nRE can be generated by the storage device 224. The controller interface circuit 230a can receive a data signal DQ including the data DATA and the switching data strobe signal DQS from the storage device 224. The controller interface circuit 230a can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0080] During the operation of inputting data DATA into storage device 224, controller interface circuit 230a may generate a switching data strobe signal DQS. For example, before transmitting data DATA, controller interface circuit 230a may generate a data strobe signal DQS that transitions from a static state (e.g., high or low level) to a switching state. Controller interface circuit 230a may then send a data signal DQ, including data DATA, to storage device 224 based on the switching timing of the data strobe signal DQS.

[0081] The controller interface circuit 230a can receive the ready / busy output signal nR / B from the storage device 224 via pin 8 P28. The controller interface circuit 230a can determine the status information of the storage device 224 based on the ready / busy output signal nR / B.

[0082] Figure 6 yes Figure 5 Example block diagram of a storage device.

[0083] Reference Figure 6 The storage device 224 may include control logic circuitry 510, memory cell array 520, page buffer unit 550, voltage generator 530, and line decoder 540. Although Figure 6 Not shown, but storage device 224 may also include Figure 5 The memory interface circuit 230b shown in the figure also includes column logic, a pre-decoder, a temperature sensor, a command decoder, and an address decoder.

[0084] The control logic circuit 510 can generally control various operations within the storage device 224. The control logic circuit 510 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface circuit 230b. For example, the control logic circuit 510 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0085] The memory cell array 520 may include multiple memory blocks BLK1 to BLKz (z is a positive integer), and each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 520 can be connected to the page buffer unit 550 via bit line BL, and can be connected to the line decoder 540 via word line WL, serial select line SSL, and ground select line GSL.

[0086] In an example embodiment, memory cell array 520 may include a 3D memory cell array, which may include multiple NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. The entire contents of U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Application No. 2011 / 0233648 are incorporated herein by reference. In an example embodiment, memory cell array 520 may include a 2D memory cell array, which may include multiple NAND strings arranged in both row and column directions.

[0087] Page buffer unit 550 may include multiple page buffers PB1 to PBn (n is an integer greater than or equal to 3), and the multiple page buffers PB1 to PBn may be connected to one of the memory cells via multiple bit lines BL. Page buffer unit 550 may select at least one of the bit lines BL in response to column address Y-ADDR. Page buffer unit 550 may operate as a write driver or a sense amplifier depending on the operating mode. For example, in the case of a programming operation, page buffer unit 550 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. In the case of a read operation, page buffer unit 550 may detect the current or voltage of the selected bit line to read data stored in the memory cell.

[0088] Voltage generator 530 can generate various voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 530 can generate programming voltage, reading voltage, programming verification voltage, erasing voltage, etc. as word line voltage VWL.

[0089] In response to the row address X-ADDR, the row decoder 540 can select one of multiple word lines WL and one of multiple serial select lines SSL. For example, the row decoder 540 can apply a programming voltage and a programming verification voltage to the selected word line during a programming operation, and can apply a read voltage to the selected word line during a read operation.

[0090] Figure 7This is a diagram illustrating a 3D V-NAND structure according to some of the disclosed example embodiments.

[0091] When the storage module of a UFS device is implemented as 3D V-NAND flash memory, each of the multiple memory blocks constituting the storage module can be represented as follows: Figure 7 The equivalent circuit shown is shown in the figure.

[0092] Figure 7 The memory block BLKi shown represents a 3D memory block formed in a 3D structure on a substrate. For example, multiple NAND memory strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate (e.g., the X direction and / or the Y direction) (e.g., the Z direction).

[0093] Reference Figure 7 The memory block BLKi may include multiple NAND memory strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple NAND memory strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. Figure 7 The diagram shows that each of the multiple NAND memory strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., and MC8, but the number of memory cells included in each of the multiple NAND memory strings NS11 to NS33 is not limited thereto.

[0094] The string select transistor SST can be connected to the corresponding string select line SSL1, SSL2, or SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8, respectively. Gate lines GTL1, GTL2, ..., GTL8 can correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select line GSL1, GSL2, or GSL3. The string select transistor SST can be connected to the corresponding bit line BL1, BL2, or BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0095] Memory cells at the same height can be connected to a word line (e.g., GTL1), and ground select lines GSL1, GSL2, and GSL3 can be separated from serial select lines SSL1, SSL2, and SSL3. Although Figure 7 The memory block BLKi is shown connected to eight gate lines GTL1, GTL2, ..., and GTL8, and three bit lines BL1, BL2, and BL3, but the number and type of lines connected to the memory block BLKi are not limited to this.

[0096] Figure 8 This is a sequence diagram illustrating the operation of a memory system according to some of the disclosed example embodiments. Figures 9 to 14 This is a diagram illustrating the operation of a memory system according to some of the disclosed example embodiments.

[0097] Reference Figure 8 The host device (e.g., host) 100 sends a request command for performing EOM operation to the memory device (e.g., device) 200 (S110).

[0098] In some example embodiments, the request command can be in accordance with the JEDEC UFS standard. Figure 9 This is implemented in the form of a write buffer command. Figure 9 This is a diagram illustrating the command descriptor block (CDB) for a write buffer command. Figure 10 This is a diagram illustrating the description of the "Mode" field setting value for a write buffer command. In the diagram, MSB can represent the most significant bit, and LSB can represent the least significant bit.

[0099] Specifically, refer to Figure 1 , Figure 9 and Figure 10 The UFS host controller 110 of host device 100 can request the UFS device controller 210 of memory device 200 to perform an EOM operation by setting the "mode" field of the write buffer command to 1F (e.g., 1Fh, where h represents a hexadecimal number). The UFS device controller 210 that receives the write buffer command can prepare for the EOM operation.

[0100] In some example embodiments, the operation of the UFS host controller 110 and the operation of the UFS device controller 210 can be performed when the UFS host controller 110 and the UFS device controller 210 are controlled by specific firmware, but the example embodiments are not limited thereto.

[0101] Figure 10 The example shown is an embodiment requesting an EOM operation when the setting value of the “Mode” field in the write buffer command is 1F, but the example embodiment is not limited to the example shown. In one embodiment, the setting value of the “Mode” field used to request an EOM operation can be changed to other setting values ​​(such as 1D (e.g., 1Dh) and 1E (e.g., 1Eh)) that are set to “Reserved” in the standard specification.

[0102] Reference Figure 1 and Figure 9 The UFS host controller 110 can use the "parameter list length" field of the write buffer command to send the size of the EOM data to be described later to the UFS device controller 210.

[0103] Subsequently, referring to Figure 8 The memory device 200 sends a response to the write buffer command to the host device 100 (S120).

[0104] In some example embodiments, the response may include information about the amount of data that can be received by the memory device 200 in units. In other words, when the memory device 200 sends k (k is a natural number) bytes to the host device 100 in response, the host device 100 may subsequently send data (e.g., data to be used to perform EOM operations) to the memory device 200 in units of k bytes.

[0105] Subsequently, referring to Figure 8 The host device 100 sends the generated EOM data to the memory device 200 (S130), and the memory device 200 sends a response to the receipt of the EOM data to the host device 100 (S140).

[0106] In one example embodiment, host device 100 may generate EOM data that will be used for EOM operations to be performed in memory device 200.

[0107] EOM data may be generated before the host device 100 sends a request command for performing EOM operation to the memory device 200 (S110) or after the host device 100 receives a response to the write buffer command from the memory device 200 (S120).

[0108] Furthermore, in some example embodiments, the EOM data may be generated at a time point between when the host device 100 sends a request command for performing an EOM operation to the memory device 200 (S110) and when the host device 100 receives a response to a write buffer command from the memory device 200 (S120). The timing of the host device 100 generating the EOM data to be used in the EOM operation performed by the memory device 200 can be changed without limitation.

[0109] In some example embodiments, the EOM data generated by the host device 100 may include parameters for performing EOM operations and pattern data for performing EOM operations.

[0110] In some example embodiments, the parameters used to perform the EOM operation may include those used by the EOM 251a of the memory device 200 to perform the above-mentioned reference. Figure 3 and Figure 4The described operation includes offset values ​​dX and dY. For example, parameters used to perform an EOM operation may include at least one of a time offset value, a phase offset value, a voltage offset value, and phase resolution information.

[0111] The offset value dX may include time offset value, phase offset value, etc., and the offset value dY may include voltage offset value, etc., but the example embodiment is not limited to this.

[0112] Furthermore, the parameters used to perform EOM operations may include phase resolution information. The phase resolution information can be used by the memory device 200 to receive mode data from the host device 100.

[0113] In some example embodiments, the mode data used to perform the EOM operation may be used by the EOM 251a of the memory device 200 to perform the above-mentioned reference. Figure 3 and Figure 4 The operation described is provided by the host device 100 and the signal S.

[0114] In some example embodiments, the host device 100 may generate multiple pattern data. Multiple pattern data can be generated by using a combination of many bit sequences, and a consistent result of performing an EOM operation can be generated based on the data pattern.

[0115] Examples of such pattern data could be pseudo-random binary sequence (PRBS) data, compatible random test pattern (CRPAT) data, compatible jitter tolerance pattern (CJTPAT) data, etc., but the example implementation is not limited to these.

[0116] Figure 11 This is a diagram illustrating the structure of EOM data sent from host device 100 to memory device 200 according to some example embodiments.

[0117] Reference Figure 11 EOM data may include the EOM header EDH and the EOM data schema EDP.

[0118] The EOM header (EDH) may include parameters used to perform EOM operations. For example, the "Phase Selection" field may include an offset or phase offset value to be sent to the memory device 200, and the "Reference Voltage Control (VREF CONTROL)" field may include a voltage offset value to be sent to the memory device 200.

[0119] In other words, the time offset value or phase offset value can be provided from the host device 100 to the memory device 200 via the "phase selection" field, and the time offset value or phase offset value is used by the memory device 200 to perform the above reference. Figure 3 and Figure 4The EOM operation is described above. Furthermore, a voltage offset value can be provided from the host device 100 to the memory device 200 via the "VREF CONTROL" field, and the voltage offset value is used by the memory device 200 to perform the above-described EOM operation. Figure 3 and Figure 4 The EOM operation described.

[0120] The phase resolution information (or gear information) that the memory device 200 consults to receive mode data from the host device 100 can be provided to the memory device 200 from the host device 100 through the "phase resolution" field.

[0121] The number of samples performed by the memory device 200 during EOM operation can be provided to the memory device 200 from the host device 100 through the “Number of Samples” field.

[0122] In addition, the size of the pattern data received by the memory device 200 from the host device 100 can be provided to the memory device 200 from the host device 100 through the “EOM data length” field.

[0123] although Figure 11 An example with a 12-byte EOM header EDH is shown, but the example embodiment is not limited to this, and the size of the EOM header EDH can be changed without limitation.

[0124] The EOM data schema EDP can include schema data used to perform EOM operations. For example... Figure 11 As shown, the EOM data schema EDP may include multiple schema data. In some example embodiments, Figure 11 The N shown can be a natural number greater than 12.

[0125] Reference Figure 12 The EOM header (EDH) and EOM data pattern (EDP) can be sent from the host device 100 to the memory device 200 multiple times. In this case, when the host device 100 determines the method for sending the EOM header (EDH) and EOM data pattern (EDP) to the memory device 200, the amount of receivable data (or information about the amount of receivable data in units) can be considered, and the amount of receivable data can be included. Figure 8 The response sent from the memory device 200 to the host device 100 in operation S120.

[0126] For example, when included Figure 8 When the receiveable data quantity information in the response sent from the memory device 200 to the host device 100 in operation S120 is 12 bytes, the host device 100 can... Figure 12The method shown in the figure is to send the EOM data header EDH and the EOM data mode EDP to the memory device 200.

[0127] Specifically, the host device 100 first sends a 12-byte EOM header EDH to the memory device 200 (S130a). Then, the memory device 200 confirms to the host device 100 that the EOM header EDH has been received (S140a).

[0128] Subsequently, host device 100 sends one of the EOM data pattern EDPs (e.g., EOM data pattern EDP1) with a size of 12 bytes to memory device 200 (S130b). Then, memory device 200 acknowledges to host device 100 that EOM data pattern EDP1 has been received (S140b). Host device 100 then sends the next EOM data pattern EDP (e.g., EOM data pattern EDP2) with a size of 12 bytes to memory device 200 (S130c). Then, memory device 200 acknowledges to host device 100 that EOM data pattern EDP2 has been received (S140c). By repeating the above operations, Figure 11 All EOM data modes shown can be provided from host device 100 to memory device 200.

[0129] The structure of the EOM data sent from host device 100 to memory device 200 is not limited to... Figure 11 The example shown is shown in the image.

[0130] Figure 13 This is a diagram illustrating the structure of EOM data sent from host device 100 to memory device 200 according to some other example embodiments.

[0131] Reference Figure 13 EOM data may include the EOM header EDH and the EOM data schema EDP.

[0132] The EOM header (EDH) may include parameters used to perform EOM operations.

[0133] For example, the "Timing Offset" field and the "Timing Step" field may include a time offset value or a phase offset value that will be sent to the memory device 200, and the "Voltage Offset" field and the "Voltage Step" field may include a voltage offset value that will be sent to the memory device 200.

[0134] In other words, it is used by memory device 200 to execute the above-mentioned reference. Figure 3 and Figure 4The time offset and / or phase offset values ​​of the described EOM operation can be provided from the host device 100 to the memory device 200 via the "Timing Offset" field and / or "Timing Step" field. Furthermore, the memory device 200 uses these values ​​to perform the above-described EOM operation. Figure 3 and Figure 4 The voltage offset value of the described EOM operation can be provided from the host device 100 to the memory device 200 via the "Voltage Offset" field and / or the "Voltage Step" field.

[0135] In other words, in one example embodiment, Figure 3 and Figure 4 The offset values ​​dX and dY shown may not be displayed as shown in the image. Figure 11 The example embodiment shows one value, but it can instead be displayed in two fields: a reference value (e.g., a reference phase or a reference voltage) and an offset value relative to the reference value (e.g., an offset phase value or an offset voltage value).

[0136] The number of samples performed by the memory device 200 during EOM operation can be provided to the memory device 200 from the host device 100 through the “Number of Samples” field.

[0137] In addition, the size of the pattern data received by the memory device 200 from the host device 100 can be provided to the memory device 200 from the host device 100 through the "total data length" field.

[0138] Return to reference Figure 8 The memory device 200 that receives EOM data performs an EOM operation (S150).

[0139] In some example embodiments, when the EOM data mode (e.g., Figure 12 The EDP) in the EOM header (e.g., Figure 12 When the EDH (Electronic Data Name) is received, the EOM operation can be performed. However, the example embodiment is not limited to this, and the EOM operation can be performed in all EOM data modes (e.g., EOM, EOM, EOM). Figure 12 The EDP is executed after it is received.

[0140] Reference Figures 1 to 4 Whenever a pattern data is received from the host device 100, EOM 251a can perform the above-mentioned steps. Figure 3 and Figure 4 The described operation. In other words, the EOM 251a can output an error count signal EC and a sample count signal SC for each received pattern data.

[0141] The sample count signal SC can be used to determine whether the number of samples in the "Number of Samples" field provided from the host device 100 to the memory device 200 is equal to the number of samples performed by the memory device 200.

[0142] The error count signal EC can be used to calculate the error count value corresponding to the phase offset value provided by the "Phase Selection" field and the voltage offset value provided by the "VREF CONTROL" field regarding all mode data received from the host device 100.

[0143] For example, host device 100 may send 100 pattern data entries for memory device 200 to perform EOM operation, and EOM 251a may output 30 error count signals EC after the 100 pattern data entries are received. In this case, the error count value caused by the EOM operation can be 30. The error count value can be used to calculate the error rate (30% in this example).

[0144] Return to reference Figure 8 The memory device 200 that has performed the EOM operation sends a response signal, including the result of performing the EOM operation, to the host device 100 (S160).

[0145] In this case, the response signal may include information about whether the EOM operation has been successfully executed and at least one of the error count values ​​corresponding to the phase offset value and the voltage offset value.

[0146] For example, when the number of samples in the "number of samples" field provided from the host device 100 to the memory device 200 is equal to the value of the sample count signal SC output by the EOM 251a of the memory device 200, the memory device 200 can determine that the EOM operation has been fully performed and send completion information to the host device 100.

[0147] On the other hand, when the number of samples in the "number of samples" field provided from the host device 100 to the memory device 200 is different from the value of the sample count signal SC output by the EOM 251a of the memory device 200, the memory device 200 can determine that the EOM operation has not been fully executed and send fault information to the host device 100.

[0148] In some example embodiments, information about whether the EOM operation has been successfully executed can be obtained through, for example... Figure 14 The “Response” field shown (e.g., Response UFS Protocol Information Element (Response UPIU)) is provided to host device 100, but the example embodiment is not limited thereto. Furthermore, in Figure 14 In this context, LUN can represent a logical unit number, and E2ECRC can represent an end-to-end cyclic redundancy check.

[0149] Furthermore, in some example embodiments, the aforementioned error count value can be obtained through, for example... Figure 14 The four sense data fields Sense Data[0], Sense Data[1], Sense Data[2] and Sense Data[3] shown are provided to the host device 100, but the example embodiment is not limited thereto.

[0150] The results of the EOM operation generated in this way can be consulted and used to change the signal drive characteristics of the host device 100 or the signal reception characteristics of the memory device 200.

[0151] The memory system described in the example embodiment does not require an external device to detect the quality characteristics of signals transmitted and received between the host device 100 and the memory device 200. Furthermore, the signal lines through which the EOM operation is performed are the same as those through which the host device 100 and the memory device 200 actually transmit and receive signals. Therefore, reliable EOM operations can be easily performed.

[0152] Figure 15 This is a sequence diagram illustrating the operation of a memory system according to some other exemplary embodiments disclosed.

[0153] The following descriptions that overlap with the above embodiments will be omitted, and the differences will be described in detail.

[0154] Reference Figure 15 The host device 100 sends a request command to the memory device 200 to perform an EOM operation (S200). Then, the memory device 200 sends a response to the write buffer command to the host device 100 (S210).

[0155] Subsequently, the memory device 200 sends the mode data used to perform the EOM operation to the host device 100 (S220).

[0156] Reference Figure 1 In some example embodiments, the schema data used to perform EOM operations may be stored in the non-volatile storage device 220 of the memory device 200 and sent to the host device 100, but the example embodiments are not limited thereto.

[0157] In one example embodiment, different from the above reference Figure 8 In the described example embodiment, the host device 100 does not generate schema data for performing EOM operations, and the schema data stored in the memory device 200 is used to perform EOM operations.

[0158] Subsequently, the host device 100 sends EOM data, including parameters for performing the EOM operation and mode data received from the memory device 200, to the memory device 200 (S230). Then, the memory device 200 sends a response to the reception of the EOM data to the host device 100 (S240). The memory device 200 that received the EOM data performs the EOM operation (S250), and the memory device 200 that has performed the EOM operation sends a response signal including the result of performing the EOM operation to the host device 100 (S260).

[0159] Figure 16 This is a flowchart illustrating the operation of a memory system according to some other exemplary embodiments disclosed.

[0160] Reference Figure 16 Set the initial offset value (S300).

[0161] For example, refer to Figure 1 and Figure 11 The host device 100 can set the offset value to be included in the EOM data header EDH (e.g., the value to be included in the "Phase Selection" field and / or the value to be included in the "VREF CONTROL" field).

[0162] Then, an EOM operation is performed on the set offset value (e.g., performing EOM using the offset value) (S310). The EOM result is then identified (S320).

[0163] For example, the host device 100 and the memory device 200 can be referenced above. Figure 8 or Figure 15 The described operation performs an EOM operation and identifies the result.

[0164] If the EOM operation is not performed for all offset values ​​("No" in S330), the offset value is changed (S340). Then, the EOM operation is performed (S310), and the result is identified (S320). In other words, the EOM operation can be performed for a sufficient number of offset values ​​to detect the quality characteristics of the signals transmitted and received between the host device 100 and the memory device 200.

[0165] When the EOM operation has been performed for all offset values ​​("Yes" in S330), the parameters for the transmitting and receiving ends of the host device 100 and the memory device 200 are set based on the EOM result (S350).

[0166] For example, the host device 100 may set parameters related to signal driving or receiving based on the EOM result, and the memory device 200 may also set parameters related to signal driving or receiving. However, the example embodiment is not limited thereto.

[0167] Although the disclosure has been described with reference to the disclosed example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A method for operating a host device, the method comprising: The host device sends a request command to the memory device to perform the eye diagram opening monitor (EOM) operation. The host device sends at least one parameter for performing the EOM operation to the memory device; The host device sends the mode data used to perform EOM operations to the memory device; as well as The host device receives a first response signal from the memory device, the first response signal including the result of an EOM operation performed based on the at least one parameter and mode data. The EOM operation is performed based on a comparison between the main path signal and the EOM path signal. The main path signal corresponds to the signal received from the host device and recovered in the memory device, while the EOM path signal corresponds to the signal received from the host device and recovered in the memory device using an offset value. The at least one parameter used to perform the EOM operation includes a parameter that defines the offset value.

2. The method according to claim 1, wherein, The request commands used to perform EOM operations include write buffer commands.

3. The method according to claim 2, wherein, The "mode" field of the write buffer command is set to 1F.

4. The method according to claim 1, further comprising: The host device receives a second response signal from the memory device in response to a request command for performing an EOM operation. The second response signal includes information about the amount of data that can be received in units at the memory device, and The at least one parameter and mode data is sent to the memory device based on information about the amount of data that can be received in units at the memory device.

5. The method according to any one of claims 1 to 4, wherein, The at least one parameter includes at least one of time offset, phase offset, and voltage offset.

6. The method according to claim 5, wherein, The at least one parameter also includes phase resolution information.

7. The method according to claim 5, wherein, The first response signal includes at least one of information about whether the EOM operation has been successfully executed and an error count value obtained based on the EOM operation.

8. The method according to any one of claims 1 to 4, further comprising: The host device generates pattern data for performing EOM operations.

9. The method according to any one of claims 1 to 4, further comprising: Before sending pattern data, The host device receives mode data from the memory device for performing EOM operations.

10. A method of operating a memory device, the method comprising: The memory device receives a request command from the host device to perform the eye diagram opening monitor (EOM) operation; The memory device receives at least one parameter from the host device for performing EOM operations; The memory device receives mode data from the host device for performing EOM operations; as well as The memory device performs an EOM operation based on the at least one parameter and mode data, and sends a first response signal, including the result of the EOM operation, to the host device. The steps for performing an EOM operation include: performing the EOM operation based on a comparison between the master path signal and the EOM path signal, where the master path signal corresponds to the signal received from the host device and recovered at the memory device, and the EOM path signal corresponds to the signal received from the host device and recovered at the memory device using an offset value. The at least one parameter used to perform the EOM operation includes a parameter that defines the offset value.

11. The method according to claim 10, wherein, The request commands used to perform EOM operations include write buffer commands.

12. The method according to claim 11, wherein, The "mode" field of the write buffer command is set to 1F.

13. The method of claim 10, further comprising: The memory device sends a second response signal to the host device in response to a request command to perform an EOM operation. The second response signal includes information about the amount of data that the host device can receive in units, and The at least one parameter and mode data is received from the host device based on information about the amount of data that the host device can receive in units.

14. The method according to any one of claims 10 to 13, wherein, The at least one parameter includes at least one of time offset, phase offset, and voltage offset.

15. The method according to claim 14, wherein, The first response signal includes at least one of information about whether the EOM operation has been successfully executed and an error count value obtained based on the EOM operation.

16. The method according to any one of claims 10 to 13, wherein, Pattern data is generated in the host device and received by the memory device.

17. The method according to any one of claims 10 to 13, further comprising: Before receiving pattern data, The memory device sends the pattern data to the host device.

18. A memory system comprising: Host device, including host controller; as well as Memory device, including device controller and eye diagram opening monitor EOM, The host controller is configured to: send a request command for performing an EOM operation to a memory device; send at least one parameter for performing the EOM operation to the memory device; send mode data for performing the EOM operation to the memory device; and receive a first response signal from the memory device, the first response signal including the result of the EOM operation performed based on the at least one parameter and the mode data. The EOM operation is performed based on a comparison between the main path signal and the EOM path signal. The main path signal corresponds to the signal received from the host device and recovered in the memory device, while the EOM path signal corresponds to the signal received from the host device and recovered in the memory device using an offset value. The at least one parameter used to perform the EOM operation includes a parameter that defines the offset value.

19. The memory system according to claim 18, wherein, EOM is included in the general flash memory interconnect layer of memory devices.

20. The memory system according to claim 19, wherein, The general-purpose flash memory interconnect layer also includes special function registers (SFRs), and At least one parameter and pattern data are stored in the SFR.

21. The memory system according to any one of claims 18 to 20, wherein, The request commands used to perform EOM operations include a write buffer command, where the "mode" field of the write buffer command is set to 1F.

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