Semiconductor structure and method for providing cell array

Abstract

This invention provides a semiconductor structure and a method for providing a cell array, which can provide a cell array with mixed cell heights. One semiconductor structure includes: a cell array comprising: a first cell arranged in a first column, the first cell having a first cell height along a first direction and performing a first function; a second cell arranged in a second column, the second cell having a second cell height along the first direction and performing a second function; at least one third cell arranged in the first column, the third cell having a third cell height along the first direction and performing a third function; the second cell is coupled to and contacts the first cell and is configured to receive at least one signal from the first cell and provide an output signal based on the signal, the height of the second cell being greater than the height of the first cell, the number of the first cells being equal to the number of the second cells, and the height of the third cell being proportional to the height of the first cell.

Description

Technical Field

[0001] The present invention relates to a cell array, and more specifically, to a cell array formed by a plurality of cells having a mixed cell height. Background Technology

[0002] Integrated circuits (ICs) have become increasingly important. Applications using ICs are used by millions of people. These applications include mobile phones, smartphones, tablets, laptops, notebooks, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless network browsers. ICs increasingly incorporate powerful and efficient on-board data storage devices and logic circuits for signal control and processing.

[0003] As integrated circuits become smaller and more compact, their arrangement becomes increasingly complex when the height differences between the various cells frequently used in integrated circuits increase. Therefore, a cell array with mixed cell heights is needed. Summary of the Invention

[0004] The present invention provides a semiconductor structure and a method for providing a cell array, which can provide a cell array with a mixed cell height.

[0005] The present invention provides a semiconductor structure comprising: a cell array, the cell array comprising: a plurality of first cells arranged in a first column, each first cell having a first cell height along a first direction and configured to perform a first function; a plurality of second cells arranged in a second column adjacent to the first column, each second cell having a second cell height along the first direction and configured to perform a second function; and at least one third cell arranged in the first column, the third cell having a third cell height along the first direction and configured to perform a third function different from the first function and the second function; wherein each second cell is coupled to and in contact with a corresponding first cell, and is configured to receive at least one signal from the corresponding first cell and provide an output signal based on the received signal, wherein the height of the second cell is greater than the height of the first cell, and the number of the first cells is equal to the number of the second cells, wherein the height of the third cell is proportional to the height of the first cell.

[0006] Another semiconductor structure provided by the present invention includes: a cell array comprising: a plurality of first cells arranged in a first column, each first cell having a first cell height along a first direction and configured to perform a first function; a plurality of second cells arranged in a second column adjacent to the first column, each second cell having a second cell height along the first direction and configured to perform a second function; at least one third cell arranged in the first column, the third cell having a third cell height along the first direction and configured to perform a third function different from the first function; and at least one fourth cell arranged in the second column, the fourth cell having a height along the first direction that is half the height of the second cells and configured to perform a fourth function different from the second function, wherein each first cell is coupled to and contacts a corresponding second cell, and the first cell is configured to provide at least one signal to the corresponding second cell according to an input signal, wherein the height of the second cell is greater than the height of the first cell, and the number of the first cells is equal to the number of the second cells, wherein the height of the third cell is proportional to the height of the first cell.

[0007] The present invention provides a method for providing a cell array, comprising: obtaining a first cell height of a plurality of first cells and a second cell height of a plurality of second cells, wherein the second cell height is greater than the first cell height; obtaining an array height of the cell array based on the least common multiple of the first cell height and the second cell height; arranging the plurality of second cells in a first column of the cell array; arranging the plurality of first cells in a second column of the cell array, wherein the number of first cells arranged in the second column is equal to the number of second cells arranged in the first column, and each second cell is coupled to and contacts a corresponding first cell; and arranging at least one first additional cell having a third cell height in the second column of the cell array, wherein each first cell is configured to perform a first function and each second cell is configured to perform a second function different from the first function, wherein the third cell height is proportional to the first cell height, and wherein each first cell includes an interconnect structure configured to couple to and contact a corresponding second cell. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating the hierarchical design process of an integrated circuit (IC).

[0009] Figure 2 This is a simplified diagram illustrating the first and second units of an IC according to some embodiments of the present invention.

[0010] Figure 3This is a simplified diagram illustrating a cell array 100A with mixed cell height according to some embodiments of the present invention.

[0011] Figure 4A The illustrations are of some embodiments according to the present invention. Figure 3 A simplified diagram of the first and second cells of the cell array 100A.

[0012] Figure 4B Some embodiments of the present invention are shown Figure 4A Simplified diagrams of the device units in the first unit and the device units in the second unit.

[0013] Figure 5 This is a simplified diagram illustrating a cell array 100B with mixed cell height according to some embodiments of the present invention.

[0014] Figure 6 This is a simplified diagram illustrating a cell array 100C with mixed cell height according to some embodiments of the present invention.

[0015] Figure 7 This is a simplified diagram illustrating a cell array 100D with mixed cell height according to some embodiments of the present invention.

[0016] Figure 8 This is a simplified diagram illustrating a cell array 400A with a mixed cell height according to some embodiments of the present invention.

[0017] Figure 9 This is a flowchart of a method for providing a cell array with mixed cell height according to an embodiment of the present invention.

[0018] Figure 10 A calculator system 600 according to an embodiment of the present invention is shown. Detailed Implementation

[0019] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." "Substantially" means that, within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error. Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. The following description is a preferred mode for carrying out the invention and is intended to illustrate the spirit of the invention rather than to limit the scope of protection of the invention. The scope of protection of the invention shall be determined by the claims.

[0020] The following description represents the preferred embodiments of the present invention. These descriptions are intended to set forth the general principles of the invention and not to limit it. The scope of protection of the invention should be determined based on the claims.

[0021] In addition, for ease of description, spatial terms such as “below,” “under,” “lower side,” “below,” “above,” “above,” “upper side,” “above,” etc., may be used in this article to describe the relationship between an element or feature and another element or feature shown in the figure.

[0022] Figure 1This is a flowchart illustrating the hierarchical design process of an integrated circuit (IC). In step S110, Register-Transfer Level (RTL) code describing the functions performed by the IC is obtained. The RTL code can instruct a design to be executed by voice-described hardware, such as a Hardware Description Language (HDL). In step S120, the RTL code is synthesized to generate a netlist including the IC's gates (or cells). Generally, an IC comprises multiple blocks, each providing essential functionality, such as a specific processor (e.g., an application processor, video processor, audio processor, or controller), memory (e.g., an SRAM device), etc. Furthermore, each block has corresponding RTL code; therefore, the RTL code for each block is synthesized to generate a corresponding netlist including multiple gates for that block. Before synthesizing the RTL code, RTL simulation is performed to check the functional correctness of the RTL code. Additionally, after obtaining the gates of the blocks in the netlist, gate-level simulation is performed to check the functional correctness of the netlist. In step S130, placement and routing procedures are performed according to the gate level of the blocks in the netlist to generate the entire block layout within the IC chip area. Therefore, based on the placement points, chip placement and routing procedures are performed to obtain the final layout. In some embodiments, the layout is the entire chip layout. In some embodiments, the layout is a portion of the entire chip layout related to some digital or analog circuitry of the IC. In step S140, an analysis procedure is performed to verify the layout to check if it violates any of the various constraints or rules. After the layout is completed, a Design Rule Check (DRC) and layout-schematic analysis are performed. Figure 1 The process includes Layout Versus Schematic (LVS) and Electric Rule Check (ERC). DRC is the process of checking whether the layout is successfully completed using physical measurement space according to design rules. LVS is the process of checking whether the layout conforms to the corresponding circuit diagram. Additionally, ERC is the process of checking whether the devices and wires / nets are properly electrically connected. Furthermore, post-simulation is performed by extracting and simulating parasitic components (e.g., parasitic capacitance) to check the functional integrity of the layout. If the layout is free of violations, the IC is manufactured (or implemented) according to the layout (step S150). If the layout contains violations, the IC layout must be modified to resolve the violations until no violations exist.

[0023] Figure 2 is a simplified schematic diagram illustrating a first cell 10 and a second cell 20 of an IC according to some embodiments of the present invention, wherein the first cell 10 and the second cell 20 have different cell heights. The first cell 10 has a cell height H1 in the Y direction, the second cell 20 has a cell height H2 in the Y direction, and the cell height H2 is greater than the cell height H1, that is, H2>H1. Furthermore, each of the first cell 10 and the second cell 20 includes a plurality of transistors. In some embodiments, the transistors are selected from the group consisting of planar transistors, Fin Field Effect Transistors (FinFET), vertical Gate All Around (GAA), horizontal Gate All Around, nanowires, nanosheets, or combinations thereof.

[0024] As shown in Figure 2 , the transistors in the first cell 10 are formed by a plurality of fins 12 extending along the Y direction, and the transistors in the second cell 20 are formed by a plurality of fins 22 extending along the Y direction. In this embodiment, the fin width FW1 of the fins 12 in the first cell 10 is equal to the fin width FW2 of the fins 22 in the second cell 20, that is, FW1=FW2. Furthermore, the fin pitch FP1 of the fins 12 is different from the fin pitch FP2 of the fins 22. For example, the fin pitch FP2 is greater than the fin pitch FP1, that is, FP2>FP1.

[0025] In some embodiments, the fin width FW1 of the fins 12 in the first cell 10 is different from the fin width FW2 of the fins 22 in the second cell 20. For example, the width FW1 is less than the width FW2 (that is, FW1<FW2). In some embodiments, the fin pitch FP1 of the fins 12 is equal to the fin pitch FP2 of the fins 22. Furthermore, the number of the fins 12 in the first cell 10 may or may not be equal to the number of the fins 22 in the second cell 20.

[0026] Figure 3This is a simplified diagram illustrating a cell array 100A with mixed cell heights according to some embodiments of the present invention. The cell array 100A includes first cells 10_1 to 10_6 arranged in a first column COL1 and second cells 20_1 to 20_6 arranged in a second column COL2 adjacent to the first column COL1. As described above, the cell height H1 of the first cells 10_1 to 10_6 is smaller than the cell height H2 of the second cells 20_1 to 20_6. Furthermore, the fin spacing FP1 of the first cells 10_1 to 10_6 is different from the fin spacing FP2 of the second cells 20_1 to 20_6. Additionally, the first cells 10_1 to 10_6 and the second cells 20_1 to 20_6 can be digital cells or analog cells. In some embodiments, the cell height H1 is in the range of about 130 nm to about 410 nm, and the cell height H2 is in the range of about 280 nm to about 420 nm.

[0027] exist Figure 3 In this configuration, the cell array 100A has an array height H_LCM1 (e.g., 3.64 μm), and the array height H_LCM1 is determined based on the cell heights H1 and H2. In some embodiments, the array height H_LCM1 is the least common multiple (LCM) of the cell heights H1 and H2. For example, if the cell height H1 is 260 nm and the cell height H2 is 280 nm, then the array height H_LCM1 is the LCM of 260 nm and 280 nm, i.e., 3.64 μm. In some embodiments, the array height H_LCM1 is a multiple of the LCM of the cell heights H1 and H2.

[0028] In cell array 100A, each of the first cells 10_1 to 10_6 is a core device configured to perform a first function. Furthermore, the first cells 10_1 to 10_6 have the same circuit configuration. Similarly, each of the second cells 20_1 to 20_6 is an input / output (I / O) device configured to perform a second function. Furthermore, the second cells 20_1 to 20_6 have the same circuit configuration.

[0029] In the cell array 100A, each first cell 10 in the first column COL1 corresponds to a corresponding second cell 20 in the second column COL2, and each first cell 10 is coupled to the corresponding second cell 20 to perform a first function and a second function on the input signal to provide an output signal. For example, the first cell 10_1 is configured to perform a first function on the input signal IN1 to generate at least one intermediate signal to the second cell 20_1. In response to the intermediate signal, the second cell 20_1 is configured to perform a second function on the intermediate signal to provide an output signal OUT1. Therefore, the output signal OUT1 is obtained based on the input signal IN1 and through the signal path between the first cell 10_1 and the second cell 20_1. Similarly, the first cell 10_3 is configured to perform a first function on the input signal IN3 to generate at least one intermediate signal to the second cell 20_3. In response to the intermediate signal, the second cell 20_3 is configured to perform a second function on the intermediate signal to provide an output signal OUT3. Therefore, the output signal OUT3 is obtained based on the input signal IN3 and through the signal path between the first cell 10_3 and the second cell 20_3. Specifically, the output signals OUT1 to OUT6 are obtained based on the input signals IN1 to IN6 and through different signal paths in the unit array 100A.

[0030] In the cell array 100A, each of the second cells 20_1 to 20_6 is coupled to and in contact with the corresponding first cell 10. For example, the second cell 20_1 is coupled to and in contact with the first cell 10_1, the second cell 20_2 is coupled to and in contact with the first cell 10_2, the second cell 20_3 is coupled to and in contact with the first cell 10_3, and so on.

[0031] In cell array 100A, the array height H_LCM1 is only sufficient to accommodate six second cells 20, not seven. Therefore, a fourth cell (i.e., an additional cell) 40 with a cell height H4 is inserted into the second column COL2. In such an embodiment, the fourth cell 40 is adjacent to the second cell 20_1. Furthermore, the cell height H4 is half the cell height H2. The fourth cell 40 is configured to perform a function different from the first function of the first cell 10 and the second function of the second cell 20. In some embodiments, the fourth cell 40 is a dummy cell or a guardring cell. In some embodiments, the fourth cell 40 is configured to perform a specific function of a specific circuit that is different from the circuit including the first cells 10_1 to 10_6 and the second cells 20_1 to 20_6.

[0032] To accommodate the number of second units 20 that can be placed in the second column COL2, only six first units 10 are arranged in the first column COL1. Therefore, third units (i.e., additional units) 30_1 and 30_2, each with a unit height H3, are inserted into the first column COL1. Furthermore, the unit height H3 is half the unit height H1. In such an embodiment, the third unit 30_1 is adjacent to the first unit 10_1 (e.g., the top of column COL1), and the third unit 30_2 is adjacent to the first units 10_3 and 10_4 (e.g., the middle of column COL1). Each of the third units 30_1 and 30_2 is configured to perform a function different from the first function of the first unit 10 and the second function of the second unit 20. In some embodiments, each third unit 30 is a virtual unit or a guard ring unit. In some embodiments, the third unit 30 is configured to perform a specific function of a specific circuit that is different from the circuit comprising the first units 10_1 to 10_6 and the second units 20_1 to 20_6.

[0033] In cell array 100A, third cells 30_1 and 30_2 are used as filler cells in the first column COL1, and fourth cell 40 is used as a filler cell in the second column COL2. Therefore, there are no gaps (i.e., blank spaces) in the first column COL1 and the second column COL2, thus avoiding DRC violations caused by blank spaces.

[0034] Figure 4A The illustrations are of some embodiments according to the present invention. Figure 3 A simplified diagram of the first units 10_5 and 10_6 and the second units 20_5 and 20_6 of the unit array 100A. Each of the first units 10_5 and 10_6 includes multiple device units 15 and routing units 17. In each first unit 10, the device units 15 and routing units 17 have a unit height H1 and are arranged in the same row. Furthermore, the multiple device units 15 may have the same or different circuit configurations to perform various operations, and the device units 15 in the same row are configured to perform a first function of the first unit 10. Similarly, each of the second units 20_5 and 20_6 includes multiple device units 25. For each second unit 20, the device units 25 have a unit height H2 and are arranged in the same row. Furthermore, the multiple device units 25 may have the same or different circuit configurations to perform various operations, and the device units 25 in the same row are configured to perform a second function of the second unit 20.

[0035] exist Figure 4AIn each first unit 10, a device unit 15 is disposed in a device range 210, and a winding unit 17 is disposed in a winding range 220. Furthermore, a device unit 25 is disposed in a device range 230 in each second unit 20. Device range 210 and device range 230 are separated by the winding range 220. In other words, device unit 15 is separated from device unit 25 by the winding unit 17. In some embodiments, no transistors are arranged in the winding unit.

[0036] The winding unit 17 has a unit width W1 in the X direction. The device unit 15 has a unit width W2 in the X direction, and the unit width W2 is greater than the unit width W1, i.e., W2 > W1. The device unit 25 has a unit width W3 in the X direction, and the unit width W3 is also greater than the unit width W1, i.e., W3 > W1. In some embodiments, device units 15 in the same row but corresponding to different operations may have different unit widths, and device units 25 in the same row but corresponding to different operations may have different unit widths. In some embodiments, device units 15 in the same row and corresponding to the same operation may have the same unit width, and device units 25 in the same row and corresponding to the same operation may have the same unit width.

[0037] exist Figure 4A In this configuration, the first unit 10_5 is configured to perform a first function on the input signal IN5 to generate intermediate signals SA5 and SB5 for the second unit 20_5. Upon receiving the intermediate signals SA5 and SB5, the second unit 20_5 is configured to perform a second function on the intermediate signals SA5 and SB5 to provide an output signal OUT5. Therefore, the output signal OUT5 is obtained based on the input signal IN5 and through a signal path between the first unit 10_5 and the second unit 20_5, which is formed by the interconnect structure of device range 210, winding range 220, and device range 230. For example, the intermediate signal SA5 is provided to the second unit 20_5 through the interconnect structure 251 of the winding unit 17, while the intermediate signal SB5 is provided to the second unit 20_5 through the interconnect structure 252 of the winding unit 17.

[0038] In device cell 15 of the first unit 10_5, input signal IN5 is received via metal line 271, and intermediate signals SA5 and SB5 are provided to interconnect structures 251 and 252 via metal lines 272 and 273, respectively. Furthermore, output signal OUT5 is provided via metal line 274 in device cell 25 of the second unit 20_5. In such an embodiment, metal lines 271 to 274 are formed in a first metal layer. In some embodiments, metal lines 271 to 274 are formed in different metal layers. In some embodiments, the metal lines in the first unit 10_5 and the second unit 20_5 have different metal widths. For example, the metal width MW1 of metal line 271 in the first unit 10_5 is smaller than the metal width MW2 of metal line 274 in the second unit 20_5. Furthermore, interconnect structures 251 and 252 are formed by metal lines in the first metal layer, metal lines in the second metal layer above the first metal layer (e.g., 281), and corresponding vias (e.g., 291) in a via layer between the first and second metal layers. It should be noted that the configuration of interconnect structures 251 and 252 in this embodiment is only an example and is not intended to limit the present invention.

[0039] Similarly, the first unit 10_6 is configured to perform a first function on the input signal IN6 to generate intermediate signals SA6 and SB6 for the second unit 20_6. Upon receiving the intermediate signals SA6 and SB6, the second unit 20_6 is configured to perform a second function on the intermediate signals SA6 and SB6 to provide an output signal OUT6. Therefore, the output signal OUT6 is obtained based on the input signal IN6 and through a signal path between the first unit 10_6 and the second unit 20_6, which is formed by the interconnect structure of device range 210, winding range 220, and device range 230. For example, the intermediate signal SA6 is provided to the second unit 20_6 through the interconnect structure 253 of the winding unit 17, while the intermediate signal SB6 is provided to the second unit 20_6 through the interconnect structure 254 of the winding unit 17.

[0040] Because cell height H1 is different from cell height H2, the first cell 10_5 will not be aligned with the second cell 20_5, and the first cell 10_6 will not be aligned with the second cell 20_6. Therefore, the winding cells 17 of two adjacent first cells 10 in column COL1 have different interconnection structures. For example, as... Figure 4A As shown, the interconnection structure of the winding units 17 in the first unit 10_5 (e.g., 251 and 252) is different from the interconnection structure of the winding units 17 in the first unit 10_6 (e.g., 253 and 254).

[0041] Figure 4B Some embodiments of the present invention are shown Figure 4AA simplified diagram of device unit 15 in the first unit 10 and device unit 25 in the second unit 20.

[0042] In device range 210 of the first units 10_5 and 10_6, power lines 310 and 320 extend along the X direction and are arranged alternately. Power lines 310 and 320 are configured to connect various power signals. For example, when a power supply voltage (e.g., VDD) is applied to power line 310, power line 320 is grounded. Conversely, when a power supply voltage (e.g., VDD) is applied to power line 320, power line 310 is grounded.

[0043] In the first unit 10_6, power lines 310_1 and 310_2 are respectively disposed on the lower and upper sides of the first unit 10_6, and power line 320_1 is disposed between power lines 310_1 and 310_2. Furthermore, in the first unit 10_5, power lines 310_2 and 310_3 are respectively disposed on the lower and upper sides of the first unit 10_5, and power line 320_2 is disposed between power lines 310_2 and 310_3. In this embodiment, the spacing of the power lines 310 is equal to the spacing of the power lines 320. For example, the distance between power lines 310_1 and 310_2 is equal to the unit height H1, and the distance between power lines 320_1 and 320_2 is also equal to the unit height H1. Furthermore, in the first unit 10_6, the distance between power lines 310_1 and 320_1, and the distance between power lines 320_1 and 310_2, are equal to half the unit height H1, i.e., the unit height H3. Similarly, in the first unit 10_5, the distance between power lines 310_2 and 320_2, and the distance between power lines 320_2 and 310_3, are equal to half the unit height H1.

[0044] In the device range 230 of the second units 20_5 and 20_6, power lines 315 and 325 extend along the X direction and are arranged alternately. Power lines 315 and 325 are used to connect various power signals. For example, when a power supply voltage (e.g., VDD) is applied to power line 315, power line 325 is grounded. Conversely, when a power supply voltage (e.g., VDD) is applied to power line 325, power line 315 is grounded.

[0045] In the second unit 20_6, power lines 315_1 and 315_2 are respectively disposed on the lower and upper sides of the second unit 20_6, and power line 325_1 is disposed between power lines 315_1 and 315_2. Furthermore, in the second unit 20_5, power lines 315_2 and 315_3 are respectively disposed on the lower and upper sides of the second unit 20_6, and power line 325_2 is disposed between power lines 315_2 and 315_3. In this embodiment, the spacing of the power lines 315 is equal to the spacing of the power lines 325. For example, the distance between power lines 315_1 and 315_2 is equal to the unit height H2, and the distance between power lines 325_1 and 325_2 is also equal to the unit height H2. Furthermore, in the second unit 20_6, the distance between power lines 315_1 and 325_1, and the distance between power lines 325_1 and 315_2, are equal to half the unit height H2, i.e., the unit height H4. Similarly, in the second unit 20_5, the distance between power lines 315_2 and 325_2, and the distance between power lines 325_2 and 315_3, are equal to half the unit height H2.

[0046] exist Figure 4B In this configuration, power lines 310 and 320, as well as power lines 315 and 325, are formed in the same metal layer. Furthermore, power lines 310 and 320, as well as power lines 315 and 325, have the same width in the Y direction. In some embodiments, the widths of power lines 310 and 320 differ from the widths of power lines 315 and 325.

[0047] It should be noted that the configuration and arrangement of power lines 310 and 320, as well as power lines 315 and 325, are merely examples and are not intended to limit the present invention. Taking the first units 10_5 and 10_6 as examples, in some embodiments, multiple power lines 320 are arranged between two adjacent power lines 310, or multiple power lines 310 are arranged between two adjacent power lines 320. In some embodiments, the distance between the power line 310 and the two adjacent power lines 320 is unequal. In some embodiments, the power lines 310 and 320 are formed in different layers. For example, the power line 310 is formed in a first metal layer, and the power line 320 is formed in a second metal layer above or below the first metal layer. Furthermore, the power line 310 in the first metal layer may or may not cover the power line 320 in the second metal layer.

[0048] In each device cell 15, a plurality of transistors are formed in an active region 350 between a bottom power line (e.g., 310_1) and an intermediate power line (e.g., 320_1), and a plurality of transistors are formed in an active region 355 between an intermediate power line (e.g., 320_1) and a top power line (e.g., 310_2). In each device cell 25, a plurality of transistors are formed in an active region 360 between a bottom power line (e.g., 315_1) and an intermediate power line (e.g., 325_1), and a plurality of transistors are formed in an active region 365 between an intermediate power line (e.g., 325_1) and a top power line (e.g., 315_2). In some embodiments, the transistors are FinFETs, and the fin width of the transistors in device extent 230 is greater than the fin width of the transistors in device extent 210.

[0049] In each of the first units 10_5 and 10_6, a plurality of metal lines 330 extending in the X direction are formed above the transistor of device unit 15. Furthermore, in each of the second units 20_5 and 20_6, a plurality of metal lines 340 extending in the X direction are formed above the transistor of device unit 25. Figure 4B In this configuration, metal lines 330 and 340 are formed in the same metal layer. Furthermore, metal line 330 in device region 210 has a different metal width than metal line 340 in device region 230. For example, the metal width MW3 of metal line 330 in the first unit 10_5 is smaller than the metal width MW4 of metal line 340 in the second unit 20_5. Additionally, the line pitch MP1 of metal line 330 is different from the line pitch MP2 of metal line 340. For example, line pitch MP1 is smaller than line pitch MP2, i.e., MP1 < MP2.

[0050] Figure 5 This is a simplified diagram illustrating a cell array 100B with mixed cell heights according to some embodiments of the present invention. The cell array 100B includes first cells 10_1 to 10_6 arranged in a first column COL1 and second cells 20_1 to 20_6 arranged in a second column COL2 adjacent to the first column COL1. As described above, the cell height H1 of the first cells 10_1 to 10_6 is smaller than the cell height H2 of the second cells 20_1 to 20_6.

[0051] The array height H_LCM1 of cell array 100B is equal to Figure 3 The array height H_LCM1 of cell array 100A in the diagram. Figure 3 Comparison of cell array 100A in the middle, in Figure 5In the cell array 100B, third cells 30_1 and 30_2, with cell height H3, are arranged in the middle of the first column COL1, and a fourth cell 40, with cell height H4, is arranged in the middle of the second column COL2. Therefore, the layout of the cell array 100B is symmetrically configured along line A-AA. In other words, the winding units 17 and device units 15 of the first cells 10_1 and 10_6 are mirror images along line A-AA, the winding units 17 and device units 15 of the first cells 10_2 and 10_5 are mirror images along line A-AA, and the winding units 17 and device units 15 of the first cells 10_3 and 10_4 are mirror images along line A-AA. Similarly, the device units 25 of the second cells 20_1 and 20_6 are mirror images along line A-AA, the device units 25 of the second cells 20_2 and 20_5 are mirror images along line A-AA, and the device units 25 of the second cells 20_3 and 20_4 are mirror images along line A-AA.

[0052] In some embodiments, single power lines 310 and 320 are respectively disposed on the lower and upper sides of each of the third units 30_1 and 30_2. Furthermore, the distance between power lines 310 and 320 is equal to the unit height H3, which is half the unit height H1. Similarly, single power lines 330 and 340 are respectively disposed on the lower and upper sides of the fourth unit 40. Furthermore, the distance between power lines 330 and 340 is equal to the unit height H4, which is half the unit height H2.

[0053] exist Figure 3 In the cell array 100A, due to the asymmetrical arrangement of the first cell 10 and the second cell 20, the winding cells 17 in each of the first cells 10_1 to 10_6 have their own layout configuration. Figure 3 Compared to the 100A cell array, Figure 5 The cell array 100B has a first cell 10 and a second cell 20 arranged symmetrically along line A-AA, thus reducing layout cost and process complexity.

[0054] Figure 6 This is a simplified diagram illustrating a cell array 100C with mixed cell heights according to some embodiments of the present invention. The cell array 100C includes first cells 10_1 to 10_6 arranged in a first column COL1 and second cells 20_1 to 20_6 arranged in a second column COL2 adjacent to the first column COL1. As described above, the cell height H1 of the first cells 10_1 to 10_6 is smaller than the cell height H2 of the second cells 20_1 to 20_6.

[0055] exist Figure 6 In the configuration of the cell array 100C, it is similar to Figure 5 The configuration of cell array 100B in the middle. Figure 6 The cell array 100C and Figure 5 The difference between the cell arrays 100B in the middle is Figure 5 The third units 30_1 and 30_2, which have a unit height H3, are... Figure 6 The fifth cell 50, with a cell height H1, is replaced. Furthermore, the cell array 100C has a symmetrical arrangement along line B-BB. In other words, the first cells 10_1 and 10_6 are mirror images along line B-BB, the first cells 10_2 and 10_5 are mirror images along line B-BB, and the first cells 10_3 and 10_4 are mirror images along line B-BB. Similarly, the second cells 20_1 and 20_6 are mirror images along line B-BB, the second cells 20_2 and 20_5 are mirror images along line B-BB, and the second cells 20_3 and 20_4 are mirror images along line B-BB.

[0056] The fifth unit 50 is configured to perform a function different from the first function of the first unit 10 and the second function of the second unit 20. In some embodiments, the fifth unit 50 is a virtual unit or a guard ring unit. In some embodiments, the fifth unit 50 is configured to perform a specific function of a specific circuit that is different from the circuit including the first units 10_1 to 10_6 and the second units 20_1 to 20_6.

[0057] In some embodiments, dual power lines 310 are disposed on the lower and upper sides of the fifth unit 50, and a power line 320 is disposed between the dual power lines 310. Furthermore, the distance from each power line 310 to the power line 320 is equal to half the unit height H1.

[0058] Figure 7 This is a simplified diagram illustrating a cell array 100D with mixed cell heights according to some embodiments of the present invention. The cell array 100D includes first cells 10_1 to 10_6 arranged in a first column COL1 and second cells 20_1 to 20_6 arranged in a second column COL2 adjacent to the first column COL1. As described above, the cell height H1 of the first cells 10_1 to 10_6 is smaller than the cell height H2 of the second cells 20_1 to 20_6.

[0059] exist Figure 7 In the configuration of the 100D cell array, the configuration is similar to Figure 5 The configuration of cell array 100B in the middle. Figure 7 The cell array 100D and Figure 5 The difference between the cell arrays 100B in the middle is that Figure 7The third cells 30_1 and 30_2, with cell height H3, are not arranged in the middle of the first column COL1. In the first column COL1, the third cell 30_1 is inserted between the first cells 10_2 and 10_3, and the third cell 30_2 is inserted between the first cells 10_4 and 10_5. Similarly, the cell array 100D has a symmetrical configuration along line C-CC. In other words, the first cells 10_1 and 10_6 are mirror images along line C-CC, the first cells 10_2 and 10_5 are mirror images along line C-CC, and the first cells 10_3 and 10_4 are mirror images along line C-CC. Similarly, the second cells 20_1 and 20_6 are mirror images along line C-CC, the second cells 20_2 and 20_5 are mirror images along line C-CC, and the second cells 20_3 and 20_4 are mirror images along line C-CC.

[0060] In some embodiments, the third unit 30_1 is inserted between the first units 10_1 and 10_2 of the first column COL1, and the third unit 30_2 is inserted between the first units 10_5 and 10_6 of the first column COL1.

[0061] Figure 8 This is a simplified diagram illustrating a cell array 400A with mixed cell heights according to some embodiments of the present invention. The cell array 400A includes a sixth cell 60 arranged in a first column COL1 and a seventh cell 70 arranged in a second column COL2 adjacent to the first column COL1. In such an embodiment, the cell height H5 of the sixth cell 60 is less than the cell height H6 of the seventh cell 70. Furthermore, the fin spacing of the fins in the sixth cell 60 differs from the fin spacing of the fins in the seventh cell 70. For example, the fin spacing of the sixth cell 60 is less than the fin spacing of the seventh cell 70. In some embodiments, the cell height H5 is in the range of about 130 nm to about 410 nm, and the cell height H6 is in the range of about 280 nm to about 420 nm.

[0062] exist Figure 8 In this embodiment, the cell array 400A has an array height H_LCM2, and the array height H_LCM2 is determined based on the cell heights H5 and H6. In some embodiments, the array height H_LCM2 is the least common multiple (LCM) of the cell heights H5 and H6. In some embodiments, the array height H_LCM2 is a multiple of the LCM of the cell heights H5 and H6.

[0063] In the cell array 400A, the sixth cell 60 is the core device configured to perform the third function. Furthermore, multiple sixth cells 60 have the same circuit configuration. Similarly, the seventh cell 70 is an input / output (I / O) device configured to perform the fourth function. Furthermore, multiple seventh cells 70 have the same circuit configuration.

[0064] Each sixth cell 60 in the first column COL1 corresponds to a corresponding seventh cell 70 in the second column COL2, and each sixth cell 60 is coupled to and contacts the corresponding seventh cell 70 to perform third and fourth functions on the input signal to provide an output signal. Therefore, output signals OUT1 to OUT13 are obtained according to the input signals IN1 to IN13 and through different signal paths in the cell array 400A.

[0065] In cell array 400A, the array height H_LCM2 can accommodate 13 seventh cells 70, so no additional cells need to be inserted into the second column COL2. To accommodate the number of seventh cells 70 that can be placed in the second column COL2, only 13 sixth cells 60 are arranged in the first column COL1. Therefore, the eighth cell 80 with a cell height H5 is inserted into the first column COL1.

[0066] In cell array 400A, the eighth cell 80 is used as a fill cell in the first column COL1. Therefore, there are no gaps (i.e., blank spaces) in the first column COL1, thus avoiding DRC violations caused by blank spaces.

[0067] Figure 9 This is a flowchart of a method for providing a cell array with mixed cell height according to an embodiment of the present invention. Figure 9 It is performed by a calculator capable of operating Electronic Design Automation (EDA) tools.

[0068] First, in step S510, the different cell heights of the cells to be arranged in the cell array are obtained, such as the cell height H1 of the first cell 10, the cell height H2 of the second cell 20, the cell height H5 of the sixth cell 60, and the cell height H6 of the seventh cell 70.

[0069] In step S520, the array height of the cell array is obtained based on the cell height obtained in step S510. In some embodiments, the array height is the least common multiple (LCM) of different cell heights. In some embodiments, the array height H_LCM1 is a multiple of the LCM of different cell heights. In some embodiments, the array height H_LCM1 is an integer multiple of the LCM of different cell heights.

[0070] In step S530, cells with the largest cell height are arranged in the first column of the cell array. The cells arranged in the first column have the same circuit configuration, and these cells are identical devices configured to perform the same function. Therefore, the number of cells with the largest cell height to be arranged in the first column is determined. If the array height is not an integer multiple of the largest cell height, one or more additional cells are inserted in the first column to avoid DRC violations caused by blank space. As mentioned above, the additional cells can be dummy cells, guard ring cells, or cells of other circuitry.

[0071] In step S540, cells with other cell heights are arranged in other columns of the cell array. For example, cells with a first cell height are arranged in the second column of the cell array, and the first cell height is different from the maximum cell height. It should be noted that the number of cells with the first cell height in the second column is equal to the number of cells with the maximum cell height in the first column. In some embodiments, cells with a second cell height are arranged in the third column of the cell array, and the second cell height is different from both the maximum cell height and the first cell height. Furthermore, the number of cells with the second cell height in the second column is equal to the number of cells with the maximum cell height in the first column. As described above, if the array height of the cell array is not an integer multiple of the first cell height or the second cell height, one or more additional cells are inserted in the corresponding column to avoid DRC violations caused by blank space.

[0072] In step S550, an interconnection structure between cells in different columns is provided. In some embodiments, the interconnection structure is arranged in a specific cell whose cell height is less than the maximum cell height and is arranged in the same column. As described above, the interconnection structure is arranged in the winding cell 17 of the specific cell.

[0073] After the interconnect structure and cells with different cell heights are placed in the cell array, the layout of the cell array can have an asymmetric configuration (e.g., Figure 3 100A cell array and Figure 8 400A cell array) or symmetrical configuration (e.g., Figure 5 100B cell array Figure 6 100C cell array and Figure 7 (100D cell array).

[0074] Figure 10A calculator system 600 according to an embodiment of the present invention is illustrated. The calculator system 600 includes a calculator 610, a display device 620, and a user input interface 630, wherein the calculator 610 includes a processor 640, memory 650, and storage device 660. The calculator 610 is coupled to the display device 620 and the user input interface 630, wherein the calculator 610 is capable of operating electronic design automation (EDA) tools. Furthermore, the calculator 610 is capable of receiving input instructions or information (e.g., timing constraints, RTL code, or interface information of the memory device) from the user input interface 630 and displaying simulation results, the layout of ICs and blocks or circuits on the display device 620. In some embodiments, the display device 620 is a GUI for the calculator 610. Furthermore, the display device 620 and the user input interface 630 can be implemented within the calculator 610. The user input interface 630 may be a keyboard, mouse, etc. In calculator 610, storage device 660 can store operating system (OS), applications, information (e.g., circuit function information and power-related information), and input data required by the applications and / or output data generated by the applications. Processor 640 of calculator 610 can perform one or more operations of any method implied or explicitly described in this disclosure (automatically or using user input). For example, in one operation, processor 640 can load applications from storage device 660 into memory 650, which the user can then use to create, view, and / or edit the placement, planar diagrams, and physical layout of circuit designs (e.g., cell arrays with mixed cell heights).

[0075] The data structures and code described in this disclosure may be stored, in part or in whole, on a computer-readable storage medium and / or a hardware module and / or a hardware device. A computer-readable storage medium may be, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices, such as disk drives, magnetic tape, CDs (optical discs), DVDs (Digital Universal Discs or Digital Video Discs), or other media now known or hereafter developed capable of storing code and / or data. Examples of hardware modules or devices described in this disclosure include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and / or other known or hereafter developed hardware modules or devices.

[0076] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: The cell array includes: A plurality of first units arranged in a first column, each of the first units having a first unit height along a first direction and configured to perform a first function; A plurality of second units are arranged in a second column adjacent to the first column, each second unit having a second unit height along the first direction and configured to perform a second function; and At least one third unit is arranged in the first column, the third unit having a third unit height along the first direction and being configured to perform a third function different from the first function and the second function; Each of the second units is coupled to and in contact with the corresponding first unit, and is configured to receive at least one signal from the corresponding first unit and provide an output signal based on the received signal. The height of the second unit is greater than the height of the first unit, and the number of the first units is equal to the number of the second units. The height of the third unit is proportional to the height of the first unit.

2. The semiconductor structure as described in claim 1, characterized in that, Each of the first unit and the second unit includes: A power line extending in a second direction, wherein the second direction is perpendicular to the first direction; The ground wire extending along this second direction; A plurality of transistors are disposed between the power line and the ground line, wherein the plurality of transistors are configured to perform the first function or the second function; and Multiple metal lines extending along the second direction and located above the plurality of transistors.

3. The semiconductor structure as described in claim 2, characterized in that, The power and ground wires in the first and second units have the same width.

4. The semiconductor structure as described in claim 2, characterized in that, The metal wire in the first unit is narrower than the metal wire in the second unit.

5. The semiconductor structure as described in claim 1, characterized in that, The third unit is a virtual unit or a protection ring unit.

6. The semiconductor structure as described in claim 1, characterized in that, Each of the first units includes a plurality of device units arranged in the same row and a winding unit, wherein the device units are configured to perform the first function to generate the signal, and the winding unit includes at least one interconnect structure configured to transmit the signal to the second unit.

7. The semiconductor structure as described in claim 6, characterized in that, In this first column, the interconnection structures of the winding units of two adjacent first units are different.

8. The semiconductor structure as described in claim 6, characterized in that, The width of the device unit is greater than the width of the winding unit.

9. A semiconductor structure, characterized in that, include: The cell array includes: A plurality of first units arranged in a first column, each of the first units having a first unit height along a first direction and configured to perform a first function; A plurality of second units are arranged in a second column adjacent to the first column, each of the second units having a second unit height along the first direction and being configured to perform a second function; At least one third unit arranged in the first column, the third unit having a third unit height along a first direction and configured to perform a third function different from the first function; and At least one fourth unit is arranged in the second column, and the fourth unit has a height along the first direction that is half the height of the second unit, and is configured to perform a fourth function different from the second function. Each of the first units is coupled to and contacts the corresponding second unit, and the first unit is configured to provide at least one signal to the corresponding second unit according to the input signal. The height of the second unit is greater than the height of the first unit, and the number of the first units is equal to the number of the second units. The height of the third unit is proportional to the height of the first unit.

10. The semiconductor structure as described in claim 9, characterized in that, Each of the first unit and the second unit includes: A first power line extending along a second direction, wherein the second direction is perpendicular to the first direction; A second power line extending along the second direction; A third power line extends along the second direction and is disposed between the first power line and the second power line; Multiple transistors are disposed between the first power line and the third power line, and between the second power line and the third power line, and are configured to perform the first function or the second function; and Multiple metal lines extend along the second direction and are located above the multiple transistors. When the first power line and the second power line are supplied with a power supply voltage, the third power line is grounded; when the third power line is supplied with a power supply voltage, the first power line and the second power line are grounded.

11. The semiconductor structure as claimed in claim 10, characterized in that, The first power line, the second power line, and the third power line in the first unit and the second unit have the same width.

12. The semiconductor structure as claimed in claim 10, characterized in that, The metal wire in the first unit is narrower than the metal wire in the second unit.

13. The semiconductor structure as described in claim 9, characterized in that, Each of the third and fourth units is a virtual unit or a protection ring unit.

14. The semiconductor structure as claimed in claim 9, characterized in that, Each of the first units includes a plurality of device units arranged in the same row and a winding unit, wherein the device units are configured to perform the first function to generate the signal, and the winding unit includes at least one interconnect structure configured to transmit the signal to the second unit.

15. The semiconductor structure as described in claim 9, characterized in that, The third unit is located in the middle of the first column, and the fourth unit is located in the middle of the second column, wherein the third unit in the first column is adjacent to the fourth unit in the second column.

16. A method for providing a cell array, characterized in that, include: Obtain the height of a first unit of multiple first units and the height of a second unit of multiple second units, wherein the height of the second unit is greater than the height of the first unit; The array height of the cell array is obtained based on the least common multiple of the height of the first cell and the height of the second cell; Arrange the multiple second units in the first column of the unit array; The plurality of first units are arranged in a second column of the unit array, wherein the number of first units arranged in the second column is equal to the number of second units arranged in the first column, and each second unit is coupled to and contacts a corresponding first unit; and At least one first additional unit with a third unit height is arranged in the second column of the unit array. Each of the first units is configured to perform a first function, and each of the second units is configured to perform a second function different from the first function. The height of the third unit is proportional to the height of the first unit. Each of the first units includes an interconnect structure configured to couple to and contact the corresponding second unit.

17. The method for providing a cell array as described in claim 16, characterized in that, The first additional unit is a virtual unit or a guard ring unit.

18. The method for providing a cell array as described in claim 16, characterized in that, In this second column, the interconnection structures of two adjacent first units are different.

19. The method for providing a cell array as described in claim 16, characterized in that, Each of the first unit and the second unit includes: Power cord; A ground wire parallel to the power supply line; Multiple transistors are disposed between the power line and the ground line and configured to perform the first function or the second function; and Multiple metal lines are parallel to the power line and located above the multiple transistors.

20. The method for providing a cell array as described in claim 19, characterized in that, The power line and the ground line in the first unit and the second unit have the same width, and the metal wire in the first unit is narrower than the metal wire in the second unit.

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