Three-dimensional memory structures and methods of manufacturing and testing the same

Abstract

The present disclosure provides a method of manufacturing a three-dimensional memory structure, a three-dimensional memory structure manufactured according to the method, and a method of testing the three-dimensional memory structure. The method of manufacturing includes providing a substrate having a first conductivity type, forming an anti-doped region in the substrate, the anti-doped region having a second conductivity type opposite the first conductivity type, forming a stack structure including a plurality of gate layers on the substrate, and connecting at least one of the plurality of gate layers to the anti-doped region and at least one of the remaining gate layers to the substrate.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to three-dimensional memory structures and their manufacturing and testing methods. Background Technology

[0002] Three-dimensional memory sometimes suffers from leakage problems between gate layers or between the gate layer and the memory channel structure, which seriously affect the electrical performance of the three-dimensional memory structure. In order to detect leakage problems in the three-dimensional memory structure, related technologies usually use scanning VC (Voltage Contrast) to detect anomalies. However, it is difficult to achieve a stable test voltage when scanning VC. Summary of the Invention

[0003] This application provides methods and apparatus that can at least partially solve the aforementioned problems existing in the prior art.

[0004] According to one aspect, this application provides a method for manufacturing a three-dimensional memory structure, the method comprising: forming an anti-doped region in a substrate having a first conductivity type, the anti-doped region having a second conductivity type opposite to the first conductivity type; forming a stacked structure comprising a plurality of gate layers on the substrate; and connecting at least one of the plurality of gate layers to the anti-doped region, and connecting at least one of the remaining gate layers to the substrate.

[0005] In one embodiment, forming an anti-doped region in the substrate includes: forming at least two anti-doped regions in the substrate; and wherein connecting at least one of the plurality of gate layers to the anti-doped region includes: connecting at least two of the plurality of gate layers to at least two of the anti-doped regions.

[0006] According to another aspect, this application also provides a method for manufacturing a three-dimensional memory structure, the method comprising: forming an anti-doped region in a substrate having a first conductivity type, the anti-doped region having a second conductivity type opposite to the first conductivity type; forming a stacked structure including a plurality of gate layers on the substrate, and forming a plurality of memory channel structures in the stacked structure; and connecting at least one of the plurality of gate layers to the anti-doped region, and connecting at least one of the plurality of memory channel structures to the substrate.

[0007] In one embodiment, forming an anti-doped region in the substrate includes: forming at least two anti-doped regions in the substrate; and wherein connecting at least one of the plurality of gate layers to the anti-doped region includes: connecting at least two of the plurality of gate layers to at least two of the anti-doped regions, respectively.

[0008] According to another aspect, this application provides a three-dimensional memory structure, the three-dimensional memory structure comprising: a substrate having a first conductivity type; an anti-doped region located in the substrate having a second conductivity type opposite to the first conductivity type of the substrate; a stacked structure located on the substrate and including a plurality of gate layers; and a connection layer for connecting at least one of the plurality of gate layers to the anti-doped region and connecting at least one of the remaining gate layers to the substrate.

[0009] In one embodiment, the three-dimensional memory structure includes at least two anti-doped regions, and at least two of the plurality of gate layers are respectively connected to the at least two anti-doped regions.

[0010] In one embodiment, the three-dimensional memory structure further includes: a first contact connection structure located on the undoped region, wherein at least one of the plurality of gate layers is connected to the undoped region through the first contact connection structure.

[0011] In one embodiment, the three-dimensional memory structure further includes: a second contact connection structure located on the substrate, wherein at least one of the remaining gate layers is connected to the substrate through the second contact connection structure.

[0012] In one embodiment, the three-dimensional memory structure further includes: a plurality of gate contacts, wherein the connection layer is connected to a corresponding gate layer through one of the gate contacts.

[0013] According to another aspect, this application also provides a three-dimensional memory structure, the three-dimensional memory structure comprising: a substrate having a first conductivity type; an anti-doped region located in the substrate having a second conductivity type opposite to the first conductivity type of the substrate; a stacked structure located on the substrate, including a plurality of gate layers and a plurality of memory channel structures; and a connection layer for connecting at least one of the plurality of gate layers to the anti-doped region and connecting at least one of the plurality of memory channel structures to the substrate.

[0014] In one embodiment, the three-dimensional memory structure includes at least two anti-doped regions, and at least two of the plurality of gate layers are respectively connected to the at least two anti-doped regions.

[0015] In one embodiment, the three-dimensional memory structure further includes: a first contact connection structure located on the undoped region, wherein at least one of the plurality of gate layers is connected to the undoped region through the first contact connection structure.

[0016] In one embodiment, the three-dimensional memory structure further includes: a second contact connection structure located on the substrate, wherein at least one of the plurality of memory channel structures is connected to the substrate via the second contact connection structure.

[0017] In one embodiment, the three-dimensional memory structure further includes: a plurality of gate contacts, wherein the connection layer is connected to a corresponding gate layer through one of the gate contacts; and a plurality of channel structure contacts, wherein the connection layer is connected to a corresponding memory channel structure through one of the channel structure contacts.

[0018] In one embodiment, each of the channel structure contacts is connected to the channel layer of the corresponding storage channel structure.

[0019] According to another aspect, this application also provides a method for testing a three-dimensional memory structure as described above, comprising: alternately and repeatedly applying a first voltage and a second voltage to a substrate of the three-dimensional memory structure until a potential difference is maintained between a first gate layer and a second gate layer of the three-dimensional memory structure during a test time, wherein the first gate layer is a gate layer connected to the anti-doped region among the plurality of gate layers, and the second gate layer is a gate layer connected to the substrate; or alternately and repeatedly applying a first voltage and a second voltage to a substrate of the three-dimensional memory structure until a potential difference is maintained between a first gate layer and a memory channel structure of the three-dimensional memory structure during a test time, wherein the first gate layer is a gate layer connected to the anti-doped region, and the memory channel structure is a memory channel structure connected to the substrate; and performing a voltage contrast scan on the three-dimensional memory structure.

[0020] In one embodiment, the substrate is p-type doped and the anti-doped region is n-type doped, wherein the step of alternately applying a first voltage and a second voltage includes: alternately applying voltage to the substrate in the order of first providing a positive voltage and then providing a negative voltage.

[0021] In one embodiment, the substrate is N-type doped and the anti-doped region is P-type doped, wherein the step of alternately applying a first voltage and a second voltage includes: alternately applying voltage to the substrate in the order of first providing a negative voltage and then providing a positive voltage. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0023] Figure 1This is a flowchart of a method for manufacturing a three-dimensional memory structure according to an exemplary embodiment of this application;

[0024] Figure 2 and Figure 3 These are a cross-sectional view and a top view of an anti-doped region formed in a substrate according to an exemplary embodiment of this application;

[0025] Figure 4 and Figure 5 These are, respectively, a cross-sectional view and a top view of a three-dimensional memory structure to the CT layer formed according to an exemplary embodiment of this application;

[0026] Figure 6 and Figure 7 These are a cross-sectional view and a top view, respectively, illustrating an exemplary embodiment of this application in which a connection layer is formed on the CT layer of a three-dimensional memory structure to achieve connections between gate layers.

[0027] Figure 8 and Figure 9 These are a cross-sectional view and a top view, respectively, illustrating an exemplary embodiment of this application in which a connection layer is formed on the CT layer of a three-dimensional memory structure to achieve the connection between the gate layer and the memory channel structure.

[0028] Figure 10 This is a schematic diagram illustrating the charging of the gate layer and memory channel structure inside the three-dimensional memory by an external power source through a substrate according to an exemplary embodiment of this application.

[0029] Figure 11 This is a schematic diagram illustrating the charging of each gate layer to be tested through a substrate according to an exemplary embodiment of this application; and

[0030] Figure 12 This is a schematic diagram of charging the gate layer and the memory channel structure through a substrate according to an exemplary embodiment of this application. Detailed Implementation

[0031] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first side discussed herein may also be referred to as the second side, and the first window may also be referred to as the second window, and vice versa.

[0033] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0034] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0036] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0039] According to one aspect, this application provides a method for manufacturing a three-dimensional memory structure. Figure 1 The diagram shows a flowchart of a method for manufacturing a three-dimensional memory structure according to an exemplary embodiment of this application. The method 1000 for manufacturing a three-dimensional memory structure according to an exemplary embodiment of this application may include the following steps:

[0040] S1, providing a substrate 100 having a first conductivity type;

[0041] S2, an anti-doped region 110 is formed in the substrate 100, wherein the anti-doped region 110 has a second conductivity type opposite to the first conductivity type;

[0042] S3, a stacked structure 200 including multiple gate layers 201 is formed on the substrate 100, and multiple memory channel structures 210 are formed in the stacked structure 200; and

[0043] S4, at least one of the plurality of gate layers 201 is connected to the anti-doped region 110, and at least one of the remaining gate layers 201 is connected to the substrate 100 (i.e., the region of the substrate 100 having a first conductivity type, excluding the anti-doped region 110); or

[0044] At least one of the plurality of gate layers 201 is connected to the anti-doped region 110, and at least one of the plurality of memory channel structures 210 is connected to the substrate 100 (i.e., the region of the substrate 100 having a first conductivity type other than the anti-doped region 110).

[0045] The steps of the above method 1000 will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0046] According to step S1 in method 1000, a substrate 100 is set up, and an anti-doped region 110 is formed on the substrate 100. See [link to method 1000]. Figure 2The substrate 100 can be used to support the device structure thereon. The substrate 100 may include, for example, at least one of single-crystal silicon (Si), single-crystal germanium (Ge), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art. In one embodiment, the substrate 100 is, for example, a doped single-crystal silicon substrate. The substrate 100 may be a P-type substrate or an N-type substrate, and may further include N-wells and / or P-wells. However, this application is not limited thereto, and the substrate 100 may be configured and selected according to actual needs.

[0047] According to step S2 of method 1000, an anti-doped region 110 is formed in a specific region of the substrate 100. One or more anti-doped regions 110 can be provided as needed. The doping type of the anti-doped region 110 is opposite to the doping type of the substrate 100. In one embodiment, multiple anti-doped regions 110 are arranged in an array in a specific region of the substrate 100, such as... Figure 3 As shown. In one embodiment, the substrate 100 is a P-type doped substrate, and the anti-doped region 110 is N-type doped. In another embodiment, the substrate 100 is an N-type doped substrate, and the anti-doped region 110 is P-type doped. It should be understood that in other embodiments, the number and arrangement of the anti-doped regions 110 can be appropriately set according to design needs, and this application is not intended to limit them.

[0048] According to step S3 of method 1000, a stacked structure 200 including a plurality of gate layers 201 is formed on substrate 100. Specifically, substrate 100 may include a plurality of alternately stacked insulating layers 202 and a plurality of gate layers 201, such as... Figure 4 As shown, an insulating layer 202 is spaced between the gate layer 201 and the substrate 100, and between any two adjacent gate layers 201. In one embodiment, alternating insulating layers 202 and gate sacrificial layers (not shown) may be sequentially formed on the substrate 100 using thin film deposition processes including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the insulating layer 202 may include, for example, silicon oxide. The material of the gate sacrificial layer may include, for example, silicon nitride. In subsequent processes, the gate sacrificial layer may be replaced by a conductive material for the gate layer 201, such as tungsten metal.

[0049] In one embodiment, before replacing the gate sacrificial layer with the gate layer 201, a step region B may be formed, for example, at an edge region of a dielectric stack structure comprising alternating insulating layers 202 and gate sacrificial layers. In one embodiment, the step region B may be formed by performing multiple trim-etch cycles on the alternating insulating layers 202 and gate sacrificial layers.

[0050] Next, a memory channel structure 210 can be formed in a dielectric stack structure comprising alternating insulating layers 202 and gate sacrificial layers. The memory channel structure 210 can be formed, for example, in a core region A located in the central region of the dielectric stack structure. In one embodiment, a channel via extending through the dielectric stack structure and to the substrate 100 can be formed using, for example, an etching process. Then, a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer can be sequentially deposited on the inner wall of the formed channel via using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The materials of the charge blocking layer, charge trapping layer, and tunneling layer can, for example, sequentially include silicon oxide, silicon nitride, and silicon oxide to form an "ONO" (Oxide-Nitride-Oxide) structure. The material of the channel layer can include polysilicon. In one embodiment, the storage channel structure 210 may extend to a specific active region formed in the substrate 100. Specifically, the channel layer in the storage channel structure 210 may be connected to and led out from the active region; that is, it can be understood that the channel layer of the storage channel structure 210 is not connected to the substrate 100. In one embodiment, each storage channel structure 210 may be led out by a channel structure contact 211 formed on the top of the storage channel structure 210. The channel structure contact 211 may be formed of a conductive material (e.g., tungsten metal). The channel structure contact 211 may be connected to the channel layer in the storage channel structure 210.

[0051] Next, the gate sacrificial layer can be replaced with the gate layer 201. In one embodiment, a gate line gap extending through the dielectric stack structure and to the substrate 100 can be formed by, for example, dry etching or wet etching. Then, each gate sacrificial layer can be removed through the gate line gap to form a sacrificial gap. The formed sacrificial gap can then be filled with a conductive material (e.g., tungsten metal) through one or more deposition processes to form the gate layer 201.

[0052] Each gate layer 201 can be led out by a gate contact 220 formed in the step region B. Multiple gate contacts 220 can be formed in the step region B, each gate contact 220 being electrically connected to a gate layer 201. In one embodiment, a contact hole can be formed, for example, using an etching process, through a dielectric layer (not shown) located above the step region B and extending to, for example, the target gate layer 201, and then filled with a conductive material to form the gate contact 220. Exemplarily, the dielectric layer can cover portions including the step region B and the core region A, providing a flat upper surface for the entire stacked structure 200.

[0053] The above steps can be used to form the following: Figure 4 The illustrated stacked structure 200 includes alternating insulating layers 202 and gate layers 201. The core region A of the stacked structure 200 includes multiple memory channel structures 210, and the step region B includes multiple gate contacts 220 electrically connected to each gate layer 201. It is understood that... Figure 4 The diagram shown may be a partial view of a three-dimensional memory structure, and the number and thickness of the insulating layer 202 and the gate layer 201 can be selected and set according to actual conditions, which is not limited in this application. In addition, it should be noted that the above-described operation method and implementation steps are only examples and not limitations. In other embodiments, different process methods or process steps can also be used to complete the fabrication of the stacked structure 200 as described above.

[0054] According to an exemplary embodiment, a first contact connection structure 301 may be formed on the undoped region 110. In this step, to form the first contact connection structure 301 electrically connected to the undoped region 110, a connection hole may first be formed, for example, using an etching process, through a dielectric layer (not shown) located above the step region B and extending to the undoped region 110. Then, a conductive material may be filled into the formed connection hole using one or more deposition processes to form the first contact connection structure 301. As an example, a conductive material such as titanium nitride or tungsten alloy may be filled into the connection hole to form the first contact connection structure 301.

[0055] Figure 5 A top view of an exemplary three-dimensional memory structure at this stage, provided by Figure 5 As can be seen, in this exemplary embodiment, a first contact connection structure 301 is formed on each of the plurality of anti-doped regions 110 formed in step S1. Of course, in other embodiments, a first contact connection structure 301 may be formed on some of the plurality of anti-doped regions 110 formed in step S1, depending on design requirements (e.g., the number of gate layers to be connected to the anti-doped regions 110).

[0056] According to step S4 of method 1000, a connection layer 400 can be designed and formed to connect at least one of the plurality of gate layers 201 to the first contact connection structure 301, i.e., to the anti-doped region 110. At least one of the remaining gate layers 201 is then connected to the substrate 100 to form a testable connection between gate layers 201 (WL-WL). Alternatively, at least one of the plurality of memory channel structures 210 can be connected to the substrate 100 to form a testable connection between gate layers 201 and memory channel structures 210 (WL-CH). The connection layer 400 can be a metal layer that provides a conductive connection. The connection layer 400 can be designed for specific connection purposes, allowing a particular gate layer or memory channel structure to be connected to a contact connection structure that penetrates the stacked structure 200 and directly contacts the silicon substrate, such as the first contact connection structure 301 and the second contact connection structure 302 described below. In some embodiments, the connection layer 400 can be a single layer, such as a metal layer. In other embodiments, the connection layer 400 may also include multiple layers, such as metal layers, as required.

[0057] In this step, the designed interconnect layer 400 can connect at least one gate layer 201 to the first contact interconnect structure 301 formed on the anti-doped region 110. Figure 7 This is a top view schematic diagram of the connection layer 400 connecting each gate layer 201 to the contact connection structure in an exemplary embodiment. In this example connection method, for example, the gate contact 220-2 leading out of the gate layer 201-2 is connected to the first contact connection structure 301-1 formed on the anti-doped region 110-1 through 400-2 in the connection layer 400. As another example, the gate contact 220-4 leading out of the gate layer 201-4 is connected to the first contact connection structure 301-2 formed on the anti-doped region 110-2 through 400-3 in the connection layer 400. It can be seen that... Figure 7 In the exemplary embodiment shown, each first contact connection structure 301 is connected to at most one gate layer 201.

[0058] It is understood that this application is not intended to limit the formation method, number of layers, style, or specific material of the connection layer 400. The design form and function of the connection layer 400 will become clearer and more intuitive in conjunction with the detailed description of the exemplary embodiments below.

[0059] Furthermore, it should be noted that the basic structure of the three-dimensional memory before forming the interconnect layer 400 in step S4 can be formed stepwise according to the method described in steps S1 to S3, or it can be based on the already fabricated three-dimensional memory, by removing the portion located on top of its structure, including, for example, the interconnect layer, to expose the CT layer, and then performing the relevant operations in step S4. In this case, on the three-dimensional memory basic structure including the substrate 100, the stacked structure 200, and the memory channel structure 210 penetrating the stacked structure 200, in a specific area where the substrate 100 can be exposed, for example... Figure 4 The edge region of the step region B shown is formed into an anti-doped region 110 in a manner similar to that described above, and a first contact connection structure 301 is further formed on the anti-doped region 110.

[0060] According to an exemplary embodiment of this application, in conjunction with Figure 6 and Figure 7 Step S4 in the manufacturing method 1000 of the three-dimensional memory structure may further include the following steps:

[0061] S4-1, forming a second contact connection structure 302, the formed second contact connection structure 302 extending from the region of the substrate 100 excluding the anti-doped region 110; and

[0062] S4-2, A connection layer 400 is provided to connect at least one of the remaining plurality of gate layers 201 to the second contact connection structure 302.

[0063] According to step S4-1 above, a second contact connection structure 302 can be led out at an appropriate position in the non-reverse doped region of the substrate 100, such as... Figure 6 and Figure 7 As shown in the figure. In one embodiment, the second contact connection structure 302 can be formed in the same manner as the first contact connection structure 301. For example, a connection hole can first be formed by an etching process, penetrating the dielectric layer (not shown) located above the step region B and extending to the non-reverse doped region of the substrate 100. Then, a conductive material can be filled into the formed connection hole by one or more deposition processes to form the second contact connection structure 302. As an example, a conductive material such as titanium nitride or tungsten alloy can be filled into the connection hole to form the second contact connection structure 302. In this step, for example, a second contact connection structure 302 can be formed, such as... Figure 7As shown in the diagram, the second contact connection structure 302 can serve as a lead-out terminal of the substrate 100 (i.e., the region excluding the anti-doped region 110). During subsequent electrical performance testing of the three-dimensional memory structure (as described in the subsequent testing section), the anti-doped region 110 and the non-anti-doped region of the substrate 100 can respectively serve as the P-terminal and N-terminal of the PN junction formed during the test. That is, charging the substrate 100 during the test operation allows one or more gate layers 201 or one or more memory channel structures 210 connected to the second contact connection structure 302 to act as one end forming a potential difference, thus accumulating positive or negative charges. In one embodiment, the first contact connection structure 301 and the second contact connection structure 302 can be formed simultaneously.

[0064] According to step S4-2 above, at least one of the remaining multiple gate layers 201 is connected to the formed second contact connection structure 302 through the connection layer 400, that is, at least one of the remaining multiple gate layers 201 is connected to the substrate 100. As mentioned above, in the subsequent electrical performance testing of the three-dimensional memory structure (in conjunction with the relevant description in the test section below), the substrate 100 region can be used as one of the P-terminal and N-terminal in the PN junction formed during the test. Therefore, one or more gate layers 201 connected to the second contact connection structure 302 are also connected to one of the P-terminal and N-terminal in the PN junction.

[0065] See you again Figure 6 and Figure 7 In this embodiment, as described above, 400-2 in the connection layer 400 connects the gate layer 201-2 to the first contact connection structure 301-1 formed on the anti-doped region 110-1 via its gate contact 220-2, and 400-3 in the connection layer 400 connects the gate layer 201-4 to the first contact connection structure 301-2 formed on the anti-doped region 110-2 via its gate contact 220-4. In this step, the connection layer 400-1 is designed and formed to connect the gate layer 201-1 to the second contact connection structure 302 via its gate contact 220-1, and the gate layer 201-3 is also connected to the second contact connection structure 302 via its gate contact 220-3. It should be noted that in this exemplary embodiment, any two adjacent gate layers 201 (or their corresponding gate contacts 220) can be connected to either the first contact connection structure 301 or the second contact connection structure 302. For example... Figure 6The gate layers in this portion of the three-dimensional memory structure shown are, from top to bottom, 201-1, 201-2, 201-3, and 201-4. Gate layer 201-1 is connected to the second contact connection structure 302, gate layer 201-2 is connected to the first contact connection structure 301-1, gate layer 201-3 is connected to the second contact connection structure 302, and gate layer 201-4 is connected to the first contact connection structure 301-2. Figure 7 As shown. In conjunction with the foregoing, the doping type of the anti-doped region 110 connected to the first contact connection structure 301 is opposite to the doping type of the non-anti-doped region of the substrate 100 connected to the second contact connection structure 302. That is, in this exemplary embodiment, any two adjacent gate layers 201 (or their corresponding gate contacts 220) can be connected to either the P-type doped region or the N-type doped region in the substrate, respectively, to form a connection structure that can detect the electrical performance between adjacent gate layers 201 in subsequent testing operations. Specifically, this connection method can connect any two adjacent gate layers 201 to the two ends of the PN junction formed during the testing operation, charging the substrate 100. By detecting whether a corresponding potential difference is generated between any two adjacent gate layers 201, it is possible to test whether there are problems such as short circuits / leakage between adjacent gate layers 201. Furthermore, in this exemplary embodiment, multiple first contact connection structures 301 are arranged in an array, with each first contact connection structure 301 connected to only one gate layer 201; and a second contact connection structure 302 is provided, connecting both gate layers 201 to the second contact connection structure 302. It is understood that the connection configuration described in this step is merely an example and not a limitation. In other embodiments, different connection structures / methods may be used to achieve the detection based on the above implementation principle. For example, in one embodiment, the second contact connection structure 302 may be connected to more than two gate layers 201 simultaneously. As another example, in one embodiment, multiple second contact connection structures 302 may also be provided.

[0066] Figure 8 and Figure 9 Another exemplary embodiment according to this application is shown, in which step S4 of the three-dimensional memory structure manufacturing method 1000 may further include the following steps:

[0067] S4-1', forming a second contact connection structure 302, the formed second contact connection structure 302 extending from the region of the substrate 100 excluding the anti-doped region 110; and

[0068] S4-2', A connection layer 400 is provided to connect at least one of the plurality of memory channel structures 210 to a second contact connection structure 302, thereby forming a connection structure in which the electrical performance between the connected memory channel structure 210 and the corresponding gate layer 201 can be detected in subsequent test operations.

[0069] According to step S4-1' above, a second contact connection structure 302 can be led out at an appropriate position in the non-reverse doped region of the substrate 100, such as... Figure 8 and Figure 9 As shown in the figure. The specific formation method can be referred to the description in step S4-1 above, and will not be repeated here.

[0070] According to step S4-2' above, at least one of the plurality of memory channel structures 210 is connected to the formed second contact connection structure 302 via the connection layer 400. The stacked structure 200 includes a plurality of memory channel structures 210, and each memory channel structure 210 is led out by a channel structure contact 211, such as... Figure 8 and Figure 9 As shown, the method for forming the storage channel structure 210 and the channel structure contact 211 can be referred to the relevant description in step S3 above. Furthermore, according to the description in step S4 above: a connection layer 400 is formed to connect at least one of the plurality of gate layers 201 to the first contact connection structure 301. In this embodiment, 400-1' of the connection layer 400 connects the gate layer 201-1 to the first contact connection structure 301-1 formed on the anti-doped region 110-1 through its gate contact 220-1; 400-2' of the connection layer 400 connects the gate layer 201-2 to the first contact connection structure 301-2 formed on the anti-doped region 110-2 through its gate contact 220-2; and 400-4' of the connection layer 400 connects the gate layer 201-4 to the first contact connection structure 301-3 formed on the anti-doped region 110-3 through its gate contact 220-4. In step S4-2', the connecting layer 400-5 is designed and formed to... Figure 9 In the three-dimensional memory structure shown, all channel structure contacts 211 of this portion of the memory channel structure 210 are connected to the second contact connection structure 302. It is understood that... Figure 9 The connection method shown is merely an example and not a limitation. In other embodiments, for example, a portion of the channel structure contact 211 of the storage channel structure 210 may be connected to the second contact connection structure 302 as needed.

[0071] In this exemplary embodiment, a plurality of first contact connection structures 301 are arranged in an array. Each gate layer 201 connected to a first contact connection structure 301 is connected to a separate first contact connection structure 301. In other words, each first contact connection structure 301 is connected to at most one gate layer 201. In this exemplary embodiment, only one second contact connection structure 302 is provided, and all of the plurality of memory channel structures 210 are connected to this second contact connection structure 302. As mentioned above, the doping type of the anti-doped region 110 connected to the first contact connection structure 301 is opposite to the doping type of the non-anti-doped region of the substrate 100 connected to the second contact connection structure 302. That is, in this exemplary embodiment, according to design requirements, selected gate layers 201 (such as gate layers 201-1, 201-2, and 201-4 selected in this embodiment) and selected memory channel structures 210 (such as all channel structures in this embodiment) can be connected to one of the P-type doped region and the N-type doped region in the substrate, respectively. In subsequent testing, the substrate 100 is charged, and the potential difference between the storage channel structure 210 and the corresponding gate layers 201 is detected. This allows for the detection of issues such as short circuits or leakage between the storage channel structure 210 and the corresponding gate layers 201. It is understood that the connection configuration described in this step is merely an example and not a limitation. In other embodiments, the required connection configuration can be designed according to specific circumstances.

[0072] Furthermore, it should be noted that the second contact connection structure 302 described above can be formed according to the method described in step S4-1 or S4-1' above, or it can utilize, for example, through array contacts (TACs) already formed in the three-dimensional memory.

[0073] According to another aspect, this application provides a three-dimensional memory structure. This three-dimensional memory structure can be used for electrical performance testing. The three-dimensional memory structure may include: a substrate 100 having an anti-doped region 110, the doping type of the anti-doped region 110 being opposite to the doping type of the substrate 100; a stacked structure 200 comprising a plurality of gate layers 201 located on the substrate 100; a first contact connection structure 301 formed on the anti-doped region 110; a second contact connection structure formed on a region of the substrate 100 other than the anti-doped region 110; and a connection layer 400 connecting at least one of the plurality of gate layers 201 to the first contact connection structure 301.

[0074] In one embodiment, at least one of the remaining gate layers 201 is connected to the second contact connection structure 302 via a connection layer 400. In one embodiment, the three-dimensional memory structure includes a plurality of first contact connection structures 301, each first contact connection structure 301 being connected to at most one gate layer 201. In one embodiment, the second contact connection structure 302 is connected to the plurality of gate layers 201. In one embodiment, the three-dimensional memory structure further includes gate contacts 220 extending from each gate layer 201, and the connection layer 400 can connect each gate layer 201 to the first contact connection structure 301 or the second contact connection structure 302 via the gate contacts 220.

[0075] In another embodiment, the stacked structure 200 further includes a plurality of memory channel structures 210, wherein at least one memory channel structure 210 is connected to a second contact connection structure 302 via a connection layer 400. In one embodiment, all memory channel structures 210 are connected to the second contact connection structure 302. In one embodiment, the three-dimensional memory structure includes a plurality of first contact connection structures 301, each first contact connection structure 301 being connected to at most one gate layer 201. In one embodiment, the three-dimensional memory structure further includes gate contacts 220 led out from each gate layer 201 and channel structure contacts 211 led out from each memory channel structure 210, and the connection layer 400 can connect the gate layer 201 and the memory channel structure 210 to the first contact connection structure 301 or the second contact connection structure 302 via the gate contacts 220 and the channel structure contacts 211, respectively. In one embodiment, each memory channel structure 210 has a channel layer, and each channel structure contact 211 is connected to the channel layer.

[0076] According to yet another aspect, this application also provides a voltage testing method 2000 for the three-dimensional memory structure provided by this application as described above.

[0077] like Figure 10As shown, in one embodiment, the three-dimensional memory structure can be attached to a machine (not shown), and the substrate 100 can be connected to a power source. As described above, the gate layer 201 and the memory channel structure 210 can be connected to the anti-doped region 110 in the substrate 100 and / or the region of the substrate 100 excluding the anti-doped region 110, respectively. Therefore, the gate layer 201, the memory channel structure 210, etc., can be charged via the substrate 100 through an external power source. Specifically, depending on the connection method of the internal structure of the three-dimensional memory, for example, charging can be performed between the gate layers 201, or for example, between the gate layer 201 and the memory channel structure 210. As an example, the substrate 100 of the three-dimensional memory structure can be in direct contact with, for example, a metal stage 500 of the machine, and the stage 500 is connected to a power supply device 600 for charging the gate layer 201 or the memory channel structure 210. It should be noted that in other embodiments, the substrate 100 may be connected to the power supply in other different ways, and may also be charged, for example, the gate layer 201 and the memory channel structure 210 in other different ways. This application does not limit this.

[0078] In one embodiment, the substrate 100 may be p-type doped, and the second contact connection structure 302 directly led out from the substrate 100 is connected to the p-type terminal; the anti-doped region 110 formed on the substrate 100 may be n-type doped, and the first contact connection structure 301 led out from the anti-doped region 110 is connected to the n-type terminal. In this case, the voltage testing method 2000 may include the following steps:

[0079] Step a, a positive voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time; and

[0080] Step b: A negative voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time;

[0081] Step c, repeat steps a and b multiple times until a relatively stable voltage is maintained between the P-terminus of substrate 100 and the N-terminus of anti-doped region 110 during the test period; and

[0082] Step d: Perform a VC (Voltage Contrast) scan on the three-dimensional memory structure.

[0083] See Figure 11In one embodiment, in the three-dimensional memory structure, connection layer 400-1 connects gate layers 201-1 and 201-3 to the second contact connection structure 302 (P-terminal) via gate contacts 220-1 and 220-3; connection layer 400-2 connects gate layer 201-2 to the first contact connection structure 301-1 (N-terminal) via gate contact 220-2; and connection layer 400-3 connects gate layer 201-4 to the first contact connection structure 301-2 (N-terminal) via gate contact 220-4. According to step a, a positive voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time. This enables conduction between the P-terminal and the N-terminal (PN junction), causing positive charges to accumulate at the N-terminal, forming a high potential; that is, the gate layers 201-2 and 201-4 connected to the N-terminal have a high potential. According to step b, a negative voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time. Lowering the potential of the P-terminal, that is, making the gate layers 201-1 and 201-3 connected to the P-terminal have a low potential. This results in a larger potential difference between the P-terminal and the N-terminal, i.e., making... Figure 11 A large potential difference exists between any two adjacent gate layers shown, for example, between gate layers 201-1 and 201-2, between gate layers 201-2 and 201-3, and between gate layers 201-3 and 201-4. According to step c, steps a and b can be repeated multiple times depending on the specific charging conditions until a relatively stable voltage is maintained between the P-terminal of substrate 100 and the N-terminal of anti-doped region 110 during the test time. That is, the large potential difference between the P-terminal and N-terminal can be maintained relatively stably during the test time, and consequently, the large potential difference between adjacent gate layers can be maintained relatively stably during the test time. Finally, according to step d, a VC scan is performed on the three-dimensional memory structure to determine, for example, whether there is a short circuit or leakage between adjacent gate layers.

[0084] See Figure 12 In another embodiment, in the three-dimensional memory structure, connection layer 400-1' connects gate layer 201-1 to first contact connection structure 301-1 (N-terminal) via gate contact 220-1, connection layer 400-2' connects gate layer 201-2 to first contact connection structure 301-2 (N-terminal) via gate contact 220-2, connection layer 400-4' connects gate layer 201-4 to first contact connection structure 301-3 (N-terminal) via gate contact 220-4, and connection layer 400-5 connects... Figure 12 In the three-dimensional memory structure shown, all channel structure contacts 211 of the memory channel structure 210 included in this part are connected to the second contact connection structure 302 (P end).

[0085] According to step a, a positive voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time. This enables conduction between the P-terminal and the N-terminal (PN junction), causing positive charges to accumulate at the N-terminal, forming a high potential. That is, the gate layers 201-1, 201-2, and 201-4 connected to the N-terminal have a high potential. According to step b, a negative voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time. This lowers the potential of the P-terminal, that is, it causes the memory channel structure 210 connected to the P-terminal to have a low potential. This results in a larger potential difference between the P-terminal and the N-terminal, that is, it causes... Figure 12 Each of the memory channel structures 210 shown has a large potential difference with the gate layers 201-1, 201-2, and 201-4. That is, each memory channel structure 210 has a large potential difference with the gate layer 201-1, each memory channel structure 210 has a large potential difference with the gate layer 201-2, and each memory channel structure 210 has a large potential difference with the gate layer 201-4. According to step c, steps a and b can be repeated multiple times depending on the specific charging situation until a relatively stable voltage is maintained between the P-terminal of the substrate 100 and the N-terminal of the anti-doped region 110 during the test time. That is, the large potential difference between the P-terminal and the N-terminal can be maintained relatively stably during the test time, and the large potential difference between each memory channel structure 210 and the gate layers 201-1, 201-2, and 201-4 can be maintained relatively stably during the test time. Finally, according to step d, a VC scan is performed on the three-dimensional memory structure to determine, for example, whether there is a short circuit or leakage between the memory channel structure and each gate layer. It is understood that the above specific implementation is merely an example and not a limitation. In other implementations, different connection methods than those described for the three-dimensional memory structure can be used. A connection layer 400 can be designed according to testing needs to achieve appropriate connections between different structures under test, and the formed three-dimensional memory structure can be further tested using the test method 2000.

[0086] In related technologies, VC scanning is used to detect short circuits or leakage currents in three-dimensional memory structures, such as between gate layers or between the gate layer and the memory channel structure. Typically, electron beam injection is used to create a potential difference, but this method has low injection efficiency and makes it difficult to achieve a stable voltage. In contrast, the voltage testing method provided in this application performs a charging step on the three-dimensional memory structure as described in method 2000. This allows positive or negative charges to accumulate at the two ends (P-end and N-end) of the PN junction structure formed in the substrate, respectively. Similarly, positive or negative charges can accumulate at the two ends of the structure to be tested, which are connected to either the P-end or N-end of the PN junction. That is, positive or negative charges can accumulate at the two ends of the gate layer to be tested or between the gate layer and the memory channel structure, respectively. This changes the charge injection method, significantly improving charge injection efficiency and achieving a more stable potential difference between the gate layers to be tested or between the gate layer to be tested and the memory channel structure during the test. This, in turn, improves the speed and coverage of the VC scan. Furthermore, according to the voltage test method 2000 of this application, since the voltage value and duration achieved, for example, between the gate layers to be tested or between the gate layer to be tested and the memory channel structure can be better controlled, it is also beneficial to destroy the weak points existing between the aforementioned structures under test in advance under the action of the voltage, thereby exposing the problem in advance.

[0087] According to another embodiment of this application, the substrate 100 may be N-type doped, and the second contact connection structure 302 directly led out from the substrate 100 is connected to the N-type terminal; the anti-doped region 110 formed on the substrate 100 may be P-type doped, and the first contact connection structure 301 led out from the anti-doped region 110 is connected to the P-type terminal. In this case, the voltage testing method 2000' may include the following steps:

[0088] Step a, a negative voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time; and

[0089] Step b: A positive voltage is supplied to the substrate 100 by the power supply device 600 and maintained for a period of time;

[0090] Step c, repeat steps a and b multiple times until a relatively stable voltage is maintained between the P-terminus of substrate 100 and the N-terminus of anti-doped region 110 during the test period; and

[0091] Step d: Perform a VC (Voltage Contrast) scan on the three-dimensional memory structure.

[0092] For a detailed description of the voltage test method 2000, please refer to the above description of the voltage test method 2000. For the sake of brevity, the detailed description will not be repeated here.

[0093] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a three-dimensional memory structure, characterized in that, The method includes: An anti-doped region is formed in a substrate having a first conductivity type, the anti-doped region having a second conductivity type opposite to the first conductivity type; A stacked structure comprising multiple gate layers is formed on the substrate; and At least one of the plurality of gate layers is connected to the anti-doped region, and at least one of the remaining gate layers is connected to the substrate.

2. The manufacturing method according to claim 1, wherein, Forming the anti-doped regions in the substrate includes: forming at least two of the anti-doped regions in the substrate; and Connecting at least one of the plurality of gate layers to the anti-doped region includes: At least two of the plurality of gate layers are respectively connected to at least two of the anti-doped regions.

3. A method for manufacturing a three-dimensional memory structure, characterized in that, The method includes: An anti-doped region is formed in a substrate having a first conductivity type, the anti-doped region having a second conductivity type opposite to the first conductivity type; A stacked structure comprising multiple gate layers is formed on the substrate, and a multiple memory channel structure is formed in the stacked structure; and At least one of the plurality of gate layers is connected to the anti-doped region, and at least one of the plurality of memory channel structures is connected to the substrate.

4. The manufacturing method according to claim 3, wherein, Forming an anti-doped region in the substrate includes: At least two of the anti-doped regions are formed in the substrate; and Connecting at least one of the plurality of gate layers to the anti-doped region includes: At least two of the plurality of gate layers are respectively connected to at least two of the anti-doped regions.

5. A three-dimensional memory structure, characterized in that, include: The substrate has a first type of conductivity; An anti-doped region, located in the substrate, has a second conductivity type opposite to the first conductivity type of the substrate; A stacked structure is located on the substrate and includes multiple gate layers; as well as A connection layer for connecting at least one of the plurality of gate layers to the anti-doped region and connecting at least one of the remaining gate layers to the substrate.

6. The three-dimensional memory structure according to claim 5, wherein, The three-dimensional memory structure includes at least two anti-doped regions, and at least two of the plurality of gate layers are respectively connected to the at least two anti-doped regions.

7. The three-dimensional memory structure according to claim 5 further includes: A first contact connection structure is located on the anti-doped region, and at least one of the plurality of gate layers is connected to the anti-doped region through the first contact connection structure.

8. The three-dimensional memory structure according to claim 5, further comprising: A second contact connection structure is located on the substrate, and at least one of the remaining gate layers is connected to the substrate through the second contact connection structure.

9. The three-dimensional memory structure according to claim 5, further comprising: Multiple gate contacts, wherein the connection layer is connected to the corresponding gate layer through one of the gate contacts.

10. A three-dimensional memory structure, characterized in that, include: The substrate has a first type of conductivity; An anti-doped region, located in the substrate, has a second conductivity type opposite to the first conductivity type of the substrate; A stacked structure, located on the substrate, includes multiple gate layers and multiple memory channel structures; as well as A connection layer for connecting at least one of the plurality of gate layers to the anti-doped region and at least one of the plurality of memory channel structures to the substrate.

11. The three-dimensional memory structure according to claim 10, wherein, The three-dimensional memory structure includes at least two anti-doped regions, and at least two of the plurality of gate layers are respectively connected to the at least two anti-doped regions.

12. The three-dimensional memory structure according to claim 10, further comprising: A first contact connection structure is located on the anti-doped region, and at least one of the plurality of gate layers is connected to the anti-doped region through the first contact connection structure.

13. The three-dimensional memory structure according to claim 10, further comprising: A second contact connection structure is located on the substrate, and at least one of the plurality of memory channel structures is connected to the substrate through the second contact connection structure.

14. The three-dimensional memory structure according to claim 10, further comprising: Multiple gate contacts, wherein the connection layer is connected to a corresponding gate layer through one of the gate contacts; as well as Multiple channel structure contacts, wherein the connection layer is connected to a corresponding storage channel structure via one of the channel structure contacts.

15. The three-dimensional memory structure according to claim 14, wherein, Each of the channel structure contacts is connected to the channel layer of the corresponding storage channel structure.

16. A testing method for a three-dimensional memory structure, characterized in that, include: A first voltage and a second voltage are alternately and repeatedly applied to the substrate of the three-dimensional memory structure until a potential difference is maintained between the first gate layer and the second gate layer of the three-dimensional memory structure during the test time, wherein the three-dimensional memory structure is the three-dimensional memory structure as described in any one of claims 5 to 9, the first gate layer is the gate layer connected to the anti-doped region among the plurality of gate layers, and the second gate layer is the gate layer connected to the substrate; or A first voltage and a second voltage are alternately and repeatedly applied to the substrate of a three-dimensional memory structure until a potential difference is maintained between the first gate layer and the memory channel structure of the three-dimensional memory structure during a test time, wherein the three-dimensional memory structure is the three-dimensional memory structure as described in any one of claims 10 to 15, the first gate layer is a gate layer connected to the anti-doped region, and the memory channel structure is a memory channel structure connected to the substrate; and A voltage contrast scan was performed on the three-dimensional memory structure.

17. The test method according to claim 16, wherein, The substrate is p-type doped, and the anti-doped region is n-type doped. The step of alternately and repeatedly applying the first voltage and the second voltage includes: The voltage is applied to the substrate alternately and repeatedly in the order of first applying a positive voltage and then applying a negative voltage.

18. The test method according to claim 16, wherein, The substrate is N-type doped, and the anti-doped region is P-type doped. The step of alternately and repeatedly applying the first voltage and the second voltage includes: A voltage is applied to the substrate alternately and repeatedly, first applying a negative voltage and then a positive voltage.

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