Display panel and preparation method thereof
By setting a rough surface in the channel region of the oxide active layer to increase the contact area, and through roughening and annealing treatment, the problem of low crystallinity of the oxide active layer is solved, thereby improving the stability of the display panel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2022-02-11
- Publication Date
- 2026-06-16
AI Technical Summary
The existing oxide active layer has low crystallinity, which makes it easy to be damaged during the subsequent preparation of other film layers, affecting the stability of the display panel.
A rough surface is provided in the channel region of the oxide active layer. By increasing the contact area between the first active layer and the second active layer, the crystallinity is improved. The second active layer is formed by roughening and annealing treatment, which enhances its crystallinity performance.
The crystallinity of the oxide active layer was improved, which avoided damage to the channel area during the etching process and enhanced the stability of the display panel.
Smart Images
Figure CN114530461B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to a display panel and its manufacturing method. Background Technology
[0002] Display panels are typically composed of transistors and light-emitting layers. Transistors include oxide active layers. However, existing oxide active layers have low crystallinity, which means that when other layers are subsequently fabricated, etching can damage the oxide active layer, especially the channel region of the oxide active layer, thus reducing the stability of the device. Summary of the Invention
[0003] This application provides a display panel and its preparation method to improve the crystallinity of the channel region of the oxide active layer.
[0004] This application provides a display panel, including:
[0005] An oxide active layer, comprising a channel region and non-channel regions located on both sides of the channel region, the oxide active layer comprising a first active layer and a second active layer stacked sequentially, wherein the side of the first active layer closest to the second active layer is a rough surface, and the rough surface is located in the channel region, the rough surface having a roughness greater than or equal to 0.5 nm; and
[0006] The source and drain electrodes are disposed on the second active layer and located in the non-channel region.
[0007] Optionally, in some embodiments of this application, the roughness of the rough surface is greater than or equal to 0.8 nm.
[0008] Optionally, in some embodiments of this application, the rough surface is used to induce the second active layered crystallization.
[0009] Optionally, in some embodiments of this application, in the channel region, the crystallinity of the portion of the second active layer near the source / drain electrode is greater than the crystallinity of the portion of the second active layer away from the source / drain electrode.
[0010] Optionally, in some embodiments of this application, the materials of the first active layer and the second active layer include In-X-Zn, wherein X includes at least one of Ga, Al, Y and Sn; wherein, in the second active layer, the atomic percentage of Zn in the In-X-Zn is 10-60%.
[0011] Optionally, in some embodiments of this application, the rough surface is also located in the non-channel region.
[0012] Optionally, in some embodiments of this application, the display panel further includes a gate and a gate insulating layer, wherein the gate insulating layer and the oxide active layer are sequentially stacked on the gate, and the first active layer and the second active layer are sequentially stacked on the gate insulating layer.
[0013] Accordingly, this application also provides a display panel, including:
[0014] Provide a substrate;
[0015] The oxide active layer includes a channel region and non-channel regions located on both sides of the channel region. A first active layer of the oxide active layer is formed on the substrate and roughened. A rough surface is formed on the side of the first active layer away from the substrate, and the rough surface is located in the channel region. The roughness of the rough surface is greater than or equal to 0.5 nm.
[0016] A second active layer is formed on one side of the first active layer having the rough surface; and
[0017] Source and drain electrodes are formed on the second active layer, and the source and drain electrodes are located in the non-channel region.
[0018] Optionally, in some embodiments of this application, the step of forming a second active layer of the oxide active layer on the surface of the first active layer having the roughened surface includes:
[0019] A material with a second active layer is formed on one side of the first active layer having the rough surface, and then annealed to form the second active layer.
[0020] Optionally, in some embodiments of this application, the step of forming a second active layer on the surface of the first active layer having the roughened surface includes:
[0021] When the source and drain electrodes are formed on the second active layer, the loss of the second active layer is less than 0.2 angstroms / second.
[0022] This application discloses a display panel and its fabrication method. The display panel includes an oxide active layer and source / drain electrodes. The oxide active layer includes a channel region and non-channel regions located on both sides thereof. The oxide active layer includes a first active layer and a second active layer stacked sequentially. The side of the first active layer closest to the second active layer is a rough surface, and the rough surface is located in the channel region. The roughness of the rough surface is greater than or equal to 0.5 nm. The source / drain electrodes are disposed on the second active layer and located in the non-channel region. In this application, the side of the first active layer closest to the second active layer is made into a rough surface, and the rough surface is located in the channel region of the oxide active layer. This increases the contact area between the first and second active layers, thereby improving the crystallinity of the second active layer located in the channel region. This prevents the channel region from being damaged in subsequent etching processes, thereby improving the stability of the display panel. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of the first structure of the display panel provided in the embodiments of this application.
[0025] Figure 2 This is a schematic diagram of the first active layered atomic force microscope provided in the embodiments of this application.
[0026] Figure 3 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application.
[0027] Figure 4 This is a schematic diagram of the steps in the manufacturing method of the display panel provided in the embodiments of this application. Detailed Implementation
[0028] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. In this application, "reaction" can be a chemical reaction or a physical reaction.
[0029] This application discloses a display panel and its fabrication method. The display panel includes an oxide active layer and source / drain electrodes. The oxide active layer includes a channel region and non-channel regions located on both sides of the channel region. The oxide active layer includes a first active layer and a second active layer stacked sequentially. The side of the first active layer closest to the second active layer is a rough surface, and the rough surface is located in the channel region. The roughness of the rough surface is greater than or equal to 0.5 nm. The source / drain electrodes are disposed on the second active layer and are located in the non-channel region.
[0030] In this application, the side of the first active layer close to the second active layer is set as a rough surface, and the rough surface is located in the channel region, which increases the contact area between the first active layer and the second active layer, thereby improving the crystallinity of the second active layer located in the channel region, thereby avoiding damage to the channel region in subsequent etching processes, and thus improving the stability of the display panel.
[0031] The following is a detailed explanation:
[0032] Please see Figure 1 This application provides a display panel 10. The display panel 10 includes a gate 100, a gate insulating layer 200, an oxide active layer 300, and source / drain electrodes 400. Detailed description follows.
[0033] A gate insulating layer 200 is disposed on the gate 100.
[0034] Next, the oxide active layer 300 includes a channel region 301 and non-channel regions 302 located on both sides of the channel region 301. The oxide active layer 300 includes a first active layer 310 and a second active layer 320 stacked sequentially. The side of the first active layer 310 closest to the second active layer 320 is a rough surface 311, and the rough surface 311 is located at least in the channel region 301. The roughness Ra of the rough surface 311 is greater than or equal to 0.5 nm. Specifically, the first active layer 310 and the second active layer 320 are stacked sequentially on the gate insulating layer 200. The rough surface 311 is used to induce the crystallization of the second active layer 320. The roughness Ra of the rough surface 311 can be greater than or equal to 0.5 nm, 0.7 nm, 8 nm, 10 nm, or 11 nm, etc.
[0035] In this application, a rough surface 311 is provided on the side of the first active layer 310 close to the second active layer 320, and the rough surface 311 is located at least in the channel region 301. It is used to induce the crystallization of the second active layer 320. At the same time, the roughness Ra of the rough surface 311 is set to be greater than or equal to 0.5 nm. By increasing the roughness Ra of the rough surface 311, that is, increasing the contact area between the first active layer 310 and the second active layer 320, the crystallinity of the second active layer 320 located in the channel region 301 is improved, thereby avoiding damage or destruction to the channel region 301 in subsequent etching processes or other environments, thereby improving the stability of the display panel 10.
[0036] It should be noted that higher crystallinity means that the film layer is less likely to be damaged or destroyed.
[0037] It should be noted that roughness Ra represents the average roughness Ra.
[0038] In one embodiment, the roughness Ra of the rough surface 311 is greater than or equal to 0.8 nm. Specifically, the roughness Ra of the rough surface 311 can be greater than or equal to 0.8 nm, 0.9 nm, 1.1 nm, 1.5 nm, or 1.7 nm, etc.
[0039] In this application, the roughness Ra of the rough surface 311 is set to be greater than or equal to 0.8 nm, which further improves the roughness Ra of the rough surface 311, thereby further improving the crystallinity performance of the second active layer 320 induced by the first active layer 310, thereby further improving the crystallinity of the second active layer 320, thereby further preventing the second active layer 320 located in the channel region 301 from being damaged or destroyed by the etching solution, etching gas or environment during etching, thereby causing damage or destruction to the channel region 301 of the oxide active layer 300, thereby further improving the stability of the display panel 10.
[0040] Please see Figure 2 The roughness Ra of rough surface 311 is 0.9 nm.
[0041] In one embodiment, in the channel region 301, the crystallinity of the portion of the second active layer 320 near the source / drain electrode 400 is greater than the crystallinity of the portion of the second active layer 320 away from the source / drain electrode 400. Optionally, in the non-channel region 302, the crystallinity of the portion of the second active layer 320 near the source / drain electrode 400 is greater than the crystallinity of the portion of the second active layer 320 away from the source / drain electrode 400.
[0042] In this application, the crystallinity of the portion of the second active layer 320 near the source / drain electrode 400 is set to be greater than that of the portion of the second active layer 320 far from the source / drain electrode 400, so that the second active layer 320 located in the channel region 301 is less likely to be damaged in subsequent etching processes, thereby improving the stability of the display panel 10.
[0043] In one embodiment, the rough surface 311 is also located in the non-channel region 302. In this application, the rough surface 311 is also disposed on the first active layer 310 located in the non-channel region 302, so that it can be prepared together with the rough surface 311 of the first active layer 310 located in the channel region 301, simplifying the preparation process of the rough surface 311. At the same time, it can improve the crystallization effect of the second active layer 320 located in the non-channel region 302, thereby avoiding damage or destruction to the second active layer 320 located in the non-channel region 302, thereby improving the performance of the display panel 10.
[0044] In one embodiment, the materials of the first active layer 310 and the second active layer 320 include In-X-Zn, where X includes at least one of Ga, Al, Y, and Sn; wherein, in the second active layer 320, the atomic percentage of Zn in In-X-Zn is 10-60%. Specifically, the atomic percentage of Zn in In-X-Zn in the second active layer 320 can be 10%, 20%, 30%, 50%, or 60%, etc.
[0045] In this application, in the second active layer 320, the atomic percentage of Zn in In-X-Zn is set to the range of 10-60%, which makes the second active layer 320 easier to crystallize and ensures that the second active layer 320 crystallizes completely, thereby protecting the channel region 301 and improving the stability of the display panel 10.
[0046] In one embodiment, the In-X-Zn mass ratio in the first active layer 310 is 1:1:1. In this application, the In-X-Zn mass ratio in the first active layer 310 is set to 1:1:1, which improves the crystallization performance of the first active layer 310 inducing the second active layer 320.
[0047] In one embodiment, the In-X-Zn mass ratio in the second active layer 320 is 1:(1-2):(1-6). Specifically, the In-X-Zn mass ratio in the second active layer 320 can be 1:1:1, 1:1.2:1.8, 1:1.8:3, 1:2:5, or 1:2:6, etc. In this application, the In-X-Zn mass ratio in the second active layer 320 is set in the range of 1:(1-2):(1-6), which ensures that the second active layer 320 is easier to crystallize, thereby ensuring the stability of the display panel 10.
[0048] In one embodiment, during the process of forming the source / drain electrode 400 on the second active layer 320, the loss of the second active layer 320 is less than 0.2 angstroms / second. In this application, due to the increased crystallinity of the second active layer 320, the loss of the second active layer 320 during the process of forming the source / drain electrode 400 on the second active layer 320 is less than 0.2 angstroms / second. That is, the etching solution for etching the source / drain electrode 400 causes virtually no damage to the second active layer 320, thus protecting the channel region 301, and also protecting the oxide active layer 300, thereby improving the stability of the display panel 10 by at least 1V.
[0049] In one embodiment, the thickness H of the second active layer 320 is 3-10 nm. Specifically, the thickness H of the second active layer 320 can be 3 nm, 5 nm, 8 nm, or 10 nm, etc. In this application, setting the thickness H of the second active layer 320 in the range of 3-10 nm can further ensure that the second active layer 320 is easier to crystallize, thereby further ensuring the stability of the display panel 10.
[0050] Next, the source and drain electrodes 400 are disposed on the second active layer 320 and located in the non-channel region 302. Specifically, the source and drain electrodes 400 include a source electrode 410 and a drain electrode 420 disposed at a distance from each other in the second active layer 320. The source electrode 410 is located in one non-channel region 302, and the drain electrode 420 is located in another non-channel region 302.
[0051] The gate 100, the gate insulating layer 200, the oxide active layer 300 and the source drain 400 constitute a transistor, and the transistor is a bottom gate transistor.
[0052] It should be noted that the gate 100 and gate insulating layer 200 and other films can be removed as needed.
[0053] Please see Figure 3 It should be noted that the second structure differs from the first structure in that:
[0054] The transistor can also be a top-gate transistor. The transistor also includes an insulating layer 500. Specifically, the second active layer 320, the gate insulating layer 200, and the gate 100 are sequentially stacked on the first active layer 310, with the gate insulating layer 200 and the gate 100 located in the channel region 301. The insulating layer 500 is disposed on the second active layer 320, the gate insulating layer 200, and the gate 100. The insulating layer 500 has a first via and a second via. The first via penetrates the insulating layer 500 to expose one channel region 301. The second via penetrates the insulating layer 500 to expose another channel region 301. The source 410 and the drain 420 are spaced apart and disposed on the same layer of the insulating layer 500, with the source 410 filling the first via and connecting to the oxide active layer 300, and the drain 420 filling the second via and connecting to the oxide active layer 300. Other aspects are the same as the first structure and will not be described again here.
[0055] This application also provides a method for manufacturing a display panel, comprising:
[0056] B11: Provides a substrate.
[0057] B12: The oxide active layer includes a channel region and non-channel regions located on both sides of the channel region. The first active layer of the oxide active layer is formed on the substrate and roughened. A rough surface is formed on the side of the first active layer away from the substrate, and the rough surface is located in the channel region. The roughness of the rough surface is greater than or equal to 0.5 nm.
[0058] B13: A second active layer in which an oxide active layer is formed on the surface of the first active layer having a rough surface.
[0059] B14: Source and drain electrodes are formed on the second active layer, and the source and drain electrodes are located in the non-channel region.
[0060] In this application, the side of the first active layer close to the second active layer is set as a rough surface, and the rough surface is located in the channel region, which increases the contact area between the first active layer and the second active layer, thereby improving the crystallinity of the second active layer located in the channel region, thereby avoiding damage to the channel region in subsequent etching processes, and thus improving the stability of the display panel.
[0061] Please see Figure 4 This application also provides a method for manufacturing a display panel 10, comprising:
[0062] B11: Provides a substrate.
[0063] Please continue reading. Figure 1 Following step B11, the following is also included:
[0064] The material of the gate 100 is disposed on the substrate and patterned to form the gate 100. Then, a gate insulating layer 200 is formed on the substrate and the gate 100.
[0065] B12: The oxide active layer includes a channel region and non-channel regions located on both sides of the channel region. The first active layer of the oxide active layer is formed on the substrate and roughened. A rough surface is formed on the side of the first active layer away from the substrate, and the rough surface is located in the channel region. The roughness of the rough surface is greater than or equal to 0.5 nm.
[0066] The material of the first active layer 310 is disposed on the gate insulating layer 200. The material of the first active layer 310 is etched by dry etching to form the first active layer 310. A rough surface 311 is formed on the side of the first active layer 310 away from the gate 100, and the rough surface 311 is located in the channel region 301. The roughness Ra of the rough surface 311 is greater than or equal to 0.5 nm. Specifically, the material of the first active layer 310 is then disposed on the gate insulating layer 200 and placed in a dry etching apparatus. Then, etching gas is introduced into the dry etching apparatus, the pressure is set to 3-12 kW, the flow rate of the etching gas is set to 100 sccm-850 sccm, and the etching time is set to 5 s-30 s. The material of the first active layer 310 is roughened to form the first active layer 310. A rough surface 311 is formed on the side of the first active layer 310 away from the gate 100. The rough surface 311 is located in the channel region 301 and the non-channel region 302.
[0067] In one embodiment, the material of the first active layer 310 comprises In-X-Zn, where X includes at least one of Ga, Al, Y, or Sn. The mass ratio of In-X-Zn is 1:1:1. In this application, the mass ratio of In-X-Zn in the first active layer 310 is set to 1:1:1, which improves the crystallization performance of the first active layer 310 inducing the second active layer 320.
[0068] In one embodiment, the etching gas includes fluorine-containing gases, inert gases, or oxygen. Fluorine-containing gases include NF3. Inert gases include He, Ar, and Kr.
[0069] In one embodiment, the etching gas is NF3, which generates a large amount of F-containing plasma during dissociation. F has a stronger effect on roughening the first active layer 310.
[0070] In one embodiment, the pressure can be 3kW, 5kW, 8kW, 10kW, or 12kW, etc. In this application, the pressure is set to 3-12kW. Within this range, it can serve the purpose of surface treatment of the first active layer 310, that is, roughening treatment, while avoiding excessive damage to the surface of the first active layer 310 due to excessive treatment pressure, which would have the opposite effect.
[0071] In one embodiment, the flow rate of the etching gas can be 100 sccm, 200 sccm, 500 sccm, 600 sccm, or 850 sccm, etc. In this application, the flow rate of the etching gas is set to 100 sccm-850 sccm. Within this range, it can perform surface treatment on the first active layer 310, that is, roughen the surface, while avoiding excessive damage to the surface of the first active layer 310 due to excessive flow rate of etching gas, which would have the opposite effect.
[0072] In one embodiment, the etching time can be 5s, 10s, 20s or 30s, etc. Setting the etching time to 5s-30s can serve the purpose of surface treatment of the first active layer 310, that is, roughening treatment, while avoiding excessive damage to the surface of the first active layer 310 due to excessive etching time, which would have the opposite effect.
[0073] In this application, the surface morphology of the first active layer 310 is controlled by adjusting the etching gas pressure, the etching gas flow rate, and the etching time, so as to control the roughness Ra of the rough surface 311 of the first active layer.
[0074] In one embodiment, the roughness Ra of the rough surface 311 is greater than or equal to 0.8 nm. Specifically, the roughness Ra of the rough surface 311 can be greater than or equal to 0.8 nm, 0.9 nm, 1.1 nm, 1.5 nm, or 1.7 nm, etc.
[0075] In this application, the roughness Ra of the rough surface 311 is set to be greater than or equal to 0.8 nm, which further improves the roughness Ra of the rough surface 311, thereby further improving the crystallinity performance of the second active layer 320 induced by the first active layer 310, thereby further improving the crystallinity of the second active layer 320, thereby further preventing the second active layer 320 located in the channel region 301 from being affected by the etching solution, etching gas or environment during etching, which would cause damage or destruction to the second active layer 320, thereby causing damage or destruction to the channel region 301 of the oxide active layer 300, thereby further improving the stability of the display panel 10.
[0076] B13: A second active layer in which an oxide active layer is formed on the surface of the first active layer having a rough surface.
[0077] A material for a second active layer 320 is formed on one side of a first active layer 310 with a rough surface 311. Then, the material of the second active layer 320 is annealed to form the second active layer 320. Specifically, the annealing process includes first performing a first heat treatment on the material of the second active layer 320, and then performing a second heat treatment to form the second active layer 320. The temperature of the first heat treatment is higher than the temperature of the second heat treatment, and the time of the first heat treatment is shorter than the time of the second heat treatment. That is, the material of the second active layer 320 is first subjected to rapid high-temperature annealing, and then subjected to rapid low-temperature annealing.
[0078] In one embodiment, the material of the second active layer 320 includes In-X-Zn, where X includes at least one of Ga, Al, Y, or Sn; wherein, in the second active layer 320, the atomic percentage of Zn in In-X-Zn is 10-60%. Specifically, the atomic percentage of Zn in In-X-Zn in the second active layer 320 can be 10%, 20%, 30%, 50%, or 60%, etc.
[0079] In this application, in the second active layer 320, the atomic percentage of Zn in In-X-Zn is set to the range of 10-60%, which makes the second active layer 320 easy to crystallize, thereby protecting the channel region 301 and improving the stability of the display panel 10.
[0080] In one embodiment, the In-X-Zn mass ratio in the second active layer 320 is 1:(1-2):(1-6). Specifically, the In-X-Zn mass ratio in the second active layer 320 can be 1:1:1, 1:1.2:1.8, 1:1.8:3, 1:2:5, or 1:2:6, etc. In this application, the In-X-Zn mass ratio in the second active layer 320 is set in the range of 1:(1-2):(1-6), which ensures that the second active layer 320 is easier to crystallize, thereby ensuring the stability of the display panel 10.
[0081] In one embodiment, the temperature of the first heat treatment is 400-700 degrees Celsius. Specifically, the temperature of the first heat treatment can be 400 degrees Celsius, 500 degrees Celsius, 600 or 700 degrees Celsius, etc. In this application, setting the temperature of the first heat treatment to 400-700 degrees Celsius, i.e., high-temperature annealing, can strengthen the weak bonds in the metal and improve the crystallinity of the second active layer 320. This can prevent the second active layer 320 located in the channel region 301 from being damaged during subsequent etching or in other environments, thereby improving the stability of the display panel 10. At the same time, the combination of the temperature of the first heat treatment and the second active layer 320 can further prevent the second active layer 320 located in the channel region 301 from being damaged during subsequent etching or in other environments, thereby further improving the stability of the display panel 10.
[0082] In one embodiment, the first heat treatment time is 10-30 minutes. Specifically, the first heat treatment time can be 10 minutes, 20 minutes, 25 minutes, or 30 minutes, etc. In this application, setting the first heat treatment time to 10-30 minutes can strengthen the weak metal bonds and improve the crystallinity of the second active layer 320. This can prevent the second active layer 320 located in the channel region 301 from being damaged during subsequent etching or in other environments, thereby improving the stability of the display panel 10. At the same time, if the ratio of the first heat treatment to the second active layer 320 is matched, it can further prevent the second active layer 320 located in the channel region 301 from being damaged during subsequent etching or in other environments, thereby further improving the stability of the display panel 10.
[0083] In one embodiment, the temperature of the second heat treatment is less than 400 degrees Celsius. Specifically, the temperature of the second heat treatment is less than 400 degrees Celsius and greater than 100 degrees Celsius; the temperature of the second heat treatment can be 100 degrees Celsius, 200 degrees Celsius, 300 degrees Celsius, or 400 degrees Celsius, etc. In this application, the temperature of the second heat treatment is set to less than 400 degrees Celsius, i.e., rapid low-temperature annealing, so that the second active layer 320 cools down rapidly, ensuring complete crystallization of the second active layer 320. This avoids damage to the second active layer 320 located in the channel region 301 during subsequent etching or in other environments, thereby improving the stability of the display panel 10.
[0084] In one embodiment, the second heat treatment lasts for 2-5 hours. Specifically, the second heat treatment can last for 2 hours, 3 hours, 4 hours, or 5 hours, etc.
[0085] In this application, by combining the roughening treatment of the first active layer 310 with the use of materials with different Zn contents in the second active layer, the roughness Ra of the first active layer 310 is increased, thereby increasing the specific surface area and the contact area between the first active layer 310 and the second active layer. This can induce the second active layer 320 to crystallize more quickly. Combined with rapid high-temperature annealing, i.e., performing a first heat treatment at a temperature of 400-700 degrees Celsius for 10-30 minutes, followed by rapid low-temperature annealing, i.e., performing a second heat treatment for 2-5 hours at a temperature below 400 degrees Celsius, the second active layer 320 crystallizes completely. This results in the crystallinity of the portion of the second active layer 320 near the source / drain electrode 400 being greater than that of the portion of the second active layer 320 away from the source / drain electrode 400, thereby improving the stability of the display panel 10.
[0086] B14: Source and drain electrodes are formed on the second active layer, and the source and drain electrodes are located in the non-channel region.
[0087] Material for the source / drain electrode 400 is disposed on the second active layer 320, and the material for the source / drain electrode 400 is etched using an etching solution to form the source / drain electrode 400. The source / drain electrode 400 includes a source electrode 410 and a drain electrode 420 disposed at intervals. The source electrode 410 is located in one non-channel region 302, and the drain electrode 420 is located in another non-channel region 302. Then, the display panel 10 is tested, and the test results show that the stability of the display panel 10 is improved by 1V or more.
[0088] When the source and drain electrodes 400 are formed on the second active layer 320, the loss of the second active layer 320 is less than 0.2 angstroms / second.
[0089] In one embodiment, after step B14, the method further includes:
[0090] Remove the substrate.
[0091] For example, please refer to Figure 4A gate 100 is formed on a substrate; then, a gate insulating layer 200 is formed on the gate 100 and the substrate; then, IGZO (In-Ga-Zn mass ratio of 1:1:1) is disposed on the gate insulating layer 200; then, it is placed in a dry etching apparatus; then, NF3 is introduced into the dry etching apparatus, the pressure is set to 5kW, the flow rate of the etching gas is set to 120sccm, and the etching time is set to 20s. The material of the first active layer 310 is roughened to form the first active layer 310. A rough surface 311 is formed on the side of the first active layer 310 away from the gate 100, and the roughness Ra of the rough surface 311 is 0.9. Then, IGZO (In-Ga-Zn mass ratio of 1:2:3, wherein the atomic percentage of In in IGZO is 20%) is placed on the first active layer 310. Then, the IGZO is rapidly annealed at high temperature at 500 degrees Celsius for 20 minutes. Then, the IGZO is rapidly annealed at low temperature at 300 degrees Celsius for 2 hours, and the IGZO forms the second active layer 320. Then, the source and drain electrodes 400 are formed on the second active layer 320.
[0092] This application provides a method for preparing a display panel 10. In this application, a roughening treatment is performed on the first active layer 310, and the second active layer is made of a material with a different Zn content. By increasing the roughness Ra of the first active layer 310, the specific surface area is increased, thereby increasing the contact area between the first active layer 310 and the second active layer. This can induce the second active layer 320 to crystallize faster. This is combined with rapid high-temperature annealing, followed by rapid low-temperature annealing, so that the second active layer 320 crystallizes completely, thereby improving the stability of the display panel 10.
[0093] This application discloses a display panel 10 and its fabrication method. The display panel 10 includes an oxide active layer 300 and source / drain electrodes 400. The oxide active layer 300 includes a channel region 301 and non-channel regions 302 located on both sides thereof. The oxide active layer 300 includes a first active layer 310 and a second active layer 320 stacked sequentially. The side of the first active layer 310 closest to the second active layer 320 is a rough surface 311, and the rough surface 311 is located at least in the channel region 301. The roughness Ra of the rough surface 311 is greater than or equal to 0.5 nm. The source / drain electrodes 400 are disposed on the second active layer 320 and located in the non-channel region 302. In this application, the side of the first active layer 310 near the second active layer 320 is provided with a rough surface 311, and the rough surface 311 is located in the channel region 301. This increases the contact area between the first active layer 310 and the second active layer 320, thereby improving the crystallinity of the second active layer 320 located in the channel region 301. This prevents the channel region 301 from being damaged in subsequent etching processes, thereby improving the stability of the display panel 10.
[0094] The above provides a detailed description of a display panel and its preparation method according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A display panel, characterized by, include: An oxide active layer includes a channel region and non-channel regions located on both sides of the channel region. The oxide active layer includes a first active layer and a second active layer stacked sequentially. The side of the first active layer closest to the second active layer is a rough surface. The rough surface is used to induce the crystallization of the second active layer, and the rough surface is located in the channel region. The roughness of the rough surface is greater than or equal to 0.5 nm. and The source and drain electrodes are disposed on the second active layer and located in the non-channel region.
2. The display panel of claim 1, wherein, The roughness of the rough surface is greater than or equal to 0.8 nm.
3. The display panel according to claim 1, characterized in that, In the channel region, the crystallinity of the portion of the second active layer near the source / drain electrode is greater than the crystallinity of the portion of the second active layer away from the source / drain electrode.
4. The display panel according to claim 1, characterized in that, The materials of the first active layer and the second active layer include In-X-Zn, wherein X includes at least one of Ga, Al, Y and Sn; wherein, in the second active layer, the atomic percentage of Zn in the In-X-Zn is 10-60%.
5. The display panel according to claim 1, characterized in that, The rough surface is also located in the non-channel region.
6. The display panel according to claim 5, characterized in that, The display panel further includes a gate and a gate insulating layer, wherein the gate insulating layer and the oxide active layer are sequentially stacked on the gate, and the first active layer and the second active layer are sequentially stacked on the gate insulating layer.
7. A method for manufacturing a display panel, characterized in that, include: Provide a substrate; The oxide active layer includes a channel region and non-channel regions located on both sides of the channel region. A first active layer of the oxide active layer is formed on the substrate and roughened. A rough surface is formed on the side of the first active layer away from the substrate. The rough surface is used to induce the crystallization of the second active layer. The rough surface is located in the channel region. The roughness of the rough surface is greater than or equal to 0.5 nm. A second active layer of oxide active layer is formed on one side of the first active layer having the rough surface; as well as Source and drain electrodes are formed on the second active layer, and the source and drain electrodes are located in the non-channel region.
8. The method for manufacturing a display panel according to claim 7, characterized in that, The step of forming a second active layer of the oxide active layer on one side of the first active layer having the rough surface includes: A material with a second active layer is formed on one side of the first active layer having the rough surface, and then annealed to form the second active layer.
9. The method for manufacturing a display panel according to claim 7, characterized in that, The step of forming a second active layer on the surface of the first active layer having the roughened surface includes: When the source and drain electrodes are formed on the second active layer, the loss of the second active layer is less than 0.2 angstroms / second.