Display device and method of manufacturing the same

Abstract

The present application relates to display apparatuses and methods of manufacturing the same. A display apparatus is provided, which can include a substrate including a display area and a non-display area adjacent to the display area; a first thin film transistor disposed on the substrate and including a first semiconductor layer including an oxide semiconductor material; and a second thin film transistor disposed on the substrate and including a second semiconductor layer including a silicon semiconductor material, wherein a surface roughness of the first semiconductor layer is increased by a plasma treatment. A method of manufacturing a display apparatus is also provided.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0065185, filed on May 29, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device with improved device characteristics and a method of manufacturing the same. Background Technology

[0004] A display device may include a display element and a driving circuit for controlling electrical signals applied to the display element. The driving circuit may include thin-film transistors, storage capacitors, and lines.

[0005] To precisely control the light emission and intensity of display elements, the number of thin-film transistors electrically connected to a single display element has been increased. Accordingly, active research has been conducted to discover solutions for high integration and low power consumption in display devices. Summary of the Invention

[0006] Embodiments of this disclosure provide a display device driven by thin-film transistors including silicon semiconductors and thin-film transistors including oxide semiconductors, to reduce the power consumption of the display device and ensure high integration of the display device.

[0007] However, the scope of this disclosure is not limited thereto.

[0008] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of embodiments of this disclosure.

[0009] According to one aspect, the display device may include a substrate including a display area and a non-display area adjacent to the display area; a first thin-film transistor disposed on the substrate and including a first semiconductor layer comprising an oxide semiconductor material; and a second thin-film transistor disposed on the substrate and including a second semiconductor layer comprising a silicon semiconductor material, wherein the surface roughness of the first semiconductor layer may be increased by plasma treatment.

[0010] In an embodiment, the surface roughness of the first semiconductor layer can be in the range of about 2 nm to about 30 nm.

[0011] In an embodiment, the first semiconductor layer may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0012] In one embodiment, protrusions can be formed on the surface of the first semiconductor layer by plasma treatment, and the indium (In) content of the protrusions can be greater than the gallium (Ga) content or the zinc (Zn) content of the protrusions.

[0013] In an embodiment, the indium (In) content of the protruding portion may be greater than the indium (In) content of the main body portion of the first semiconductor layer.

[0014] In one embodiment, the first thin-film transistor may include a gate electrode that overlaps with a first semiconductor layer, and may include an insulating layer disposed between the first semiconductor layer and the gate electrode.

[0015] In one embodiment, the insulating layer may overlap with the first semiconductor layer.

[0016] In this implementation, the first semiconductor layer and the second semiconductor layer may be disposed on different layers.

[0017] In one embodiment, the display device may further include a lower metal layer disposed between the substrate and the first semiconductor layer to overlap with the first semiconductor layer.

[0018] According to another aspect, a method of manufacturing a display device may include forming a first semiconductor layer comprising an oxide semiconductor material on a substrate, increasing the surface roughness of the first semiconductor layer, forming an insulating layer on the first semiconductor layer, forming a metal layer on the insulating layer, and patterning the metal layer to form a gate electrode.

[0019] In an embodiment, the method may further include forming a second semiconductor layer comprising a silicon semiconductor material on the substrate before forming a first semiconductor layer comprising an oxide semiconductor material on the substrate.

[0020] In one embodiment, the method may further include forming a lower metal layer arranged to overlap with the first semiconductor layer before forming a first semiconductor layer comprising an oxide semiconductor material on the substrate.

[0021] In some embodiments, the first semiconductor layer and the second semiconductor layer may be formed on different layers.

[0022] In one embodiment, increasing the surface roughness of the first semiconductor layer may include performing plasma treatment on the surface of the first semiconductor layer to form protrusions on the surface of the first semiconductor layer.

[0023] In an embodiment, the surface roughness of the first semiconductor layer can be in the range of about 2 nm to about 30 nm.

[0024] In one embodiment, patterning the metal layer to form a gate electrode may include diffusing impurities into a first semiconductor layer to form a drain region and a source region.

[0025] In an embodiment, the first semiconductor layer may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0026] In an embodiment, the indium (In) content of the protruding portion may be greater than the gallium (Ga) content or the zinc (Zn) content of the protruding portion.

[0027] In an embodiment, the indium (In) content of the protruding portion may be greater than the indium (In) content of the main body portion of the first semiconductor layer.

[0028] In one embodiment, the insulating layer may overlap with the first semiconductor layer.

[0029] From the following detailed description, claims and drawings, aspects, features and advantages that differ from those described above will become apparent in order to implement the embodiments. Attached Figure Description

[0030] The above and other aspects, features and advantages of the embodiments of this disclosure will become more apparent from the following description, taken in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 A schematic perspective view illustrating a display device according to an embodiment;

[0032] Figure 2 A schematic plan view illustrating the display device according to the embodiment;

[0033] Figure 3 This is a schematic diagram of the equivalent circuitry that may be included in a pixel in a display device according to an embodiment;

[0034] Figure 4 A schematic cross-sectional view illustrating the display device according to an embodiment;

[0035] Figure 5A schematic cross-sectional view illustrating the display device according to an embodiment;

[0036] Figure 6 Images illustrating the results of transmission electron microscopy (TEM) analysis of the first semiconductor layer according to the embodiment;

[0037] Figure 7 A table illustrating the compositional proportions of each region of the first semiconductor layer according to the embodiment; and

[0038] Figures 8 to 13 A schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment. Detailed Implementation

[0039] This disclosure may have various modifications and examples, and specific embodiments will be illustrated and explained in detail in the accompanying drawings. The effects and features of this disclosure, as well as the methods for achieving these effects and features, can be more readily understood by referring to the following detailed description of the embodiments and the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be implemented in various forms.

[0040] In implementation, terms such as "first" and "second" are used to distinguish one component from other components, but components are not limited to these terms. These terms are only used to distinguish one element from another.

[0041] In implementation, unless otherwise clearly used, singular expressions include plural meanings.

[0042] In implementation, terms such as “comprises”, “comprising”, “includes”, “including”, “have”, “having”, “contains” and / or “containing” as used herein specify the presence of a described feature or element, but do not exclude the presence or addition of one or more other features or elements.

[0043] In implementations, when an element, such as a membrane, region, or component, is referred to as being "on" or "above" another element, it may be directly on or above the other element, or there may be an intermediate element present.

[0044] For ease of description, the dimensions of the components in the accompanying drawings may be enlarged or reduced. For example, for ease of description, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown, and therefore this disclosure is not limited to the dimensions and thicknesses illustrated in the drawings.

[0045] In this specification, the phrase “A and / or B” is understood to mean “A, B, or A and B”. The terms “and” and “or” can be used in a connecting or separating sense and are understood to be equivalent to “and / or”. Throughout this disclosure, the expression “at least one of A, B, and C” can indicate only A, only B, only C, both A and B, both A and C, both B and C, all A, B, and C, or variations thereof.

[0046] In the implementation, "the line extends in the first direction or the second direction" means not only that the line extends in a straight line shape, but also that the line extends in a zigzag or curved shape along the first direction or the second direction.

[0047] When different implementation methods are possible, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0048] In the embodiments, the phrase "in a plan view" means viewing the target portion from the top, and the phrase "in a cross-sectional view" means viewing the cross-section formed by vertically cutting the target portion from the side. In the embodiments described below, when an element "overlaps" with another element, the element "overlaps" with the other element "in a plan view" or "in a cross-sectional view".

[0049] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms “about” or “approximately” as used herein include stated values ​​and mean within an acceptable range of deviation from a particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±20%, ±10%, or ±5% of the stated value.

[0050] Unless otherwise specified or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0051] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be indicated by the same reference numerals.

[0052] Figure 1 A schematic perspective view illustrating a display device according to an embodiment.

[0053] refer to Figure 1The display device 1 may include a display area DA and a non-display area NDA adjacent to the display area DA. The non-display area NDA may surround the display area DA. The display device 1 may provide an image using light emitted from pixels P arranged in the display area DA, and the non-display area NDA may be an area on which no image is displayed.

[0054] The following description uses an organic light-emitting display as an example of a display device 1 according to an embodiment, but the display device disclosed herein is not limited thereto. In the embodiment, the display device 1 may be an inorganic light-emitting display, an inorganic electroluminescent display, or a display device such as a quantum dot light-emitting display. For example, the emitting layer provided for the display element in the display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0055] although Figure 1 A display device 1 having a flat display surface has been described, but this disclosure is not limited thereto. In embodiments, the display device 1 may include a three-dimensional display surface or a curved display surface.

[0056] If the display device 1 includes a three-dimensional display surface, then the display device 1 may include display areas indicating different directions, for example, a polygonal cylindrical display surface. In embodiments, if the display device 1 includes a curved display surface, then the display device 1 may be implemented in various forms, such as a flexible display device, a foldable display device, and a rollable display device.

[0057] Figure 1 A display device 1 suitable for mobile phone terminals is illustrated. Although not shown in the accompanying drawings, electronic modules, camera modules, and power modules mounted on the motherboard can be arranged together with the display device 1 in a bracket or housing to constitute a mobile phone terminal. In particular, the display device 1 according to this disclosure can be applied to large electronic devices, such as televisions and monitors, as well as small or medium-sized electronic devices, such as tablet computers, vehicle navigation systems, game consoles, and smartwatches.

[0058] although Figure 1 The display area DA of the display device 1 with a quadrilateral shape is explained, but the shape of the display area DA can be circular, elliptical or polygonal, such as triangular or pentagonal.

[0059] Display device 1 may include pixels P arranged in display area DA. Each pixel P may include an organic light-emitting diode (OLED) (see [reference needed]). Figure 3 Each pixel P can be represented by an organic light-emitting diode OLED (see...). Figure 3 ) emits, for example, red, green, blue, or white light. As mentioned above, pixel P in the specification can be understood as a pixel that emits any one of red, green, blue, or white light.

[0060] Figure 2 A schematic plan view illustrating a display device according to an embodiment.

[0061] refer to Figure 2 The display device 1 may include pixels P arranged in the display area DA. Each pixel P may include a display element, such as an organic light-emitting diode (OLED) (see [reference needed]). Figure 3 Each pixel P can be represented by an organic light-emitting diode OLED (see...). Figure 3 ) emits, for example, red, green, blue, or white light. As mentioned above, pixel P in the specification can be understood as a pixel that emits any one of red, green, blue, or white light.

[0062] Each pixel P can be electrically connected to peripheral circuitry arranged in the non-display area NDA. A first scan drive circuit 110, a first transmit drive circuit 115, a second scan drive circuit 120, a terminal 140, a data drive circuit 150, a first power line 160, and a second power line 170 can be arranged in the non-display area NDA.

[0063] The first scan driving circuit 110 supplies a scan signal to each pixel P via scan line SL. The first emission driving circuit 115 supplies an emission control signal to each pixel P via emission control line EL. The second scan driving circuit 120 can be arranged in parallel with the first scan driving circuit 110, and the display area DA is located between the second scan driving circuit 120 and the first scan driving circuit 110. Some pixels P arranged in the display area DA can be electrically connected to the first scan driving circuit 110, and the rest can be electrically connected to the second scan driving circuit 120. In an embodiment, the second scan driving circuit 120 can be omitted.

[0064] The first transmission drive circuit 115 may be spaced apart from the first scan drive circuit 110 in the x-direction and may be arranged in the non-display area NDA. The first transmission drive circuit 115 and the first scan drive circuit 110 may be arranged alternately in the y-direction.

[0065] Terminal 140 may be disposed on one side of substrate 100. Terminal 140 may be exposed and not covered by an insulating layer, and may be electrically connected to a printed circuit board (PCB). Port PCB-P of the PCB may be electrically connected to terminal 140 of display device 1. The PCB may transmit signals or power from the controller (not shown) to display device 1. Control signals generated in the controller may be transmitted via the PCB to the first scan drive circuit 110, the first transmit drive circuit 115, and the second scan drive circuit 120, respectively. The controller may supply a first power supply voltage ELVDD (see [link to relevant documentation]) to the first power line 160 and the second power line 170 via the first connection line 161 and the second connection line 171, respectively. Figure 3 ) and the second power supply voltage ELVSS (see Figure 3 First power supply voltage ELVDD (see...) Figure 3 The second power supply voltage (ELVSS) can be supplied to pixel P via the drive voltage line PL connected to the first power line 160, and the second power supply voltage (see...) Figure 3 It can be supplied to the opposite electrode of pixel P connected to the second power line 170.

[0066] The data driving circuit 150 can be electrically connected to the data line DL. The data signal of the data driving circuit 150 can be supplied to each pixel P through the connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151.

[0067] although Figure 2 The data driving circuit 150 arranged on a printed circuit board (PCB) is illustrated, but in some embodiments, the data driving circuit 150 may be arranged on the substrate 100. For example, the data driving circuit 150 may be arranged between the terminal 140 and the first power line 160.

[0068] The first power line 160 may include a first sub-line 162 and a second sub-line 163 extending parallel to each other in the x-direction, with the display area DA between the first sub-line 162 and the second sub-line 163. The second power line 170 may partially surround the display area DA in the form of a loop having an open side.

[0069] Figure 3 This is a schematic diagram of the equivalent circuitry of a pixel that may be included in a display device according to an embodiment.

[0070] refer to Figure 3 Each pixel P may include a pixel circuit PC and an organic light-emitting diode (OLED) electrically connected to the pixel circuit PC.

[0071] In one embodiment, the pixel circuit PC may include thin-film transistors T1 to T7 and a storage capacitor Cst. The thin-film transistors T1 to T7 and the storage capacitor Cst may be connected to signal lines SL1, SL2, SLp, SLn, EL, and DL, the initialization voltage line VIL, and the drive voltage line PL. In some embodiments, at least one of the signal lines SL1, SL2, SLp, SLn, EL, DL, the initialization voltage line VIL, and the drive voltage line PL, for example, the initialization voltage line VIL and / or the drive voltage line PL, may be shared by adjacent pixels P.

[0072] Thin-film transistors T1 to T7 may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0073] Some of the thin-film transistors T1 to T7 can be N-channel MOSFETs (NMOS), and the rest can be P-channel MOSFETs (PMOS).

[0074] For example, the compensation thin film transistor T3 and the first initialization thin film transistor T4 of thin film transistors T1 to T7 can be N-channel MOSFETs (NMOS), and the rest can be P-channel MOSFETs (PMOS).

[0075] In one embodiment, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, and the second initialization thin-film transistor T7 of thin-film transistors T1 to T7 can be N-channel MOSFETs (NMOS), and the rest can be P-channel MOSFETs (PMOS). In another embodiment, only one of the thin-film transistors T1 to T7 can be an NMOS, and the rest can be PMOS. In yet another embodiment, all of the thin-film transistors T1 to T7 can be NMOS.

[0076] Signal lines SL1, SL2, SLp, SLn, EL, and DL may include a first scan line SL1 for transmitting a first scan signal Sn', a second scan line SL2 for transmitting a second scan signal Sn", a previous scan line SLp for transmitting a previous scan signal Sn-1 to a first initialization thin-film transistor T4, an emit control line EL for transmitting an emit control signal En to an operation control thin-film transistor T5 and an emit control thin-film transistor T6, a next scan line SLn for transmitting a next scan signal Sn+1 to a second initialization thin-film transistor T7, and a data line DL that intersects with the first scan line SL1 and is used to transmit a data signal Dm.

[0077] The driving voltage line PL can transmit the first power supply voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VIL can transmit the initialization voltage Vint to initialize the driving thin film transistor T1 and the pixel electrode.

[0078] The driving gate electrode of the driving thin-film transistor T1 is connected to the first electrode CE1 of the storage capacitor Cst. The driving source region of the driving thin-film transistor T1 is connected to the driving voltage line PL via the operation control thin-film transistor T5, and the driving drain region of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. The driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin-film transistor T2, and can supply the driving current I to the OLED. OLED .

[0079] The switching gate electrode of the switching thin-film transistor T2 is connected to the first scan line SL1, the switching source region of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain region of the switching thin-film transistor T2 is connected to the driving source region of the driving thin-film transistor T1 and is connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on according to the first scan signal Sn' received through the first scan line SL1 and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the driving source region of the driving thin-film transistor T1.

[0080] The compensation gate electrode of the compensation thin-film transistor T3 is connected to the second scan line SL2. The compensation drain region of the compensation thin-film transistor T3 is connected to the driving drain region of the driving thin-film transistor T1, and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The compensation source region of the compensation thin-film transistor T3 is connected to the first electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin-film transistor T1. The compensation source region of the compensation thin-film transistor T3 is connected to the first initialization drain region of the first initialization thin-film transistor T4.

[0081] The compensation thin-film transistor T3 can be turned on according to the second scan signal Sn” received through the second scan line SL2 to electrically connect the driving gate electrode and the driving drain region of the driving thin-film transistor T1, thereby connecting the diode of the driving thin-film transistor T1.

[0082] The first initialization gate electrode of the first initialization thin-film transistor T4 is connected to the previous scan line SLp. The first initialization source region of the first initialization thin-film transistor T4 is connected to the second initialization source region of the second initialization thin-film transistor T7 and the initialization voltage line VIL. The first initialization drain region of the first initialization thin-film transistor T4 is connected to the first electrode CE1 of the storage capacitor Cst, the compensation source region of the compensation thin-film transistor T3, and the driving gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SLp to perform an initialization operation, thereby initializing the voltage of the driving gate electrode of the driving thin-film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode of the driving thin-film transistor T1.

[0083] The operation control gate electrode of the operation control thin film transistor T5 is connected to the emitter control line EL, the operation control source region of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the operation control drain region of the operation control thin film transistor T5 is connected to the drive source region of the drive thin film transistor T1 and the switch drain region of the switch thin film transistor T2.

[0084] The emission control gate electrode of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source region of the emission control thin film transistor T6 is connected to the driving drain region of the driving thin film transistor T1 and the compensation drain region of the compensation thin film transistor T3, and the emission control drain region of the emission control thin film transistor T6 is electrically connected to the second initialization drain region of the second initialization thin film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0085] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 can be simultaneously turned on according to the emission control signal En received through the emission control line EL. Therefore, the first power supply voltage ELVDD can be transmitted to the organic light-emitting diode OLED, and the driving current I... OLED It can flow in organic light-emitting diodes (OLEDs).

[0086] The second initialization gate electrode of the second initialization thin-film transistor T7 is connected to the next scan line SLn. The second initialization drain region of the second initialization thin-film transistor T7 is connected to the emission control drain region of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). Furthermore, the second initialization source region of the second initialization thin-film transistor T7 is connected to the first initialization source region of the first initialization thin-film transistor T4 and the initialization voltage line VIL. After receiving the next scan signal Sn+1 via the next scan line SLn, the second initialization thin-film transistor T7 can be turned on according to the next scan signal Sn+1 to initialize the pixel electrode of the OLED.

[0087] The second initialization thin-film transistor T7 can be connected to the next scan line SLn. In another embodiment, the second initialization thin-film transistor T7 can be connected to the emitter control line EL and can be driven according to the emitter control signal En. In another embodiment, the positions of the source and drain regions can be switched according to the type of transistor (P-type or N-type).

[0088] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst may be connected to the driving gate electrode of the driving thin-film transistor T1, and the second electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. The storage capacitor Cst may store the charge difference between the voltage corresponding to the driving gate electrode of the driving thin-film transistor T1 and the first power supply voltage ELVDD.

[0089] The detailed operation of each pixel P according to the implementation method can be as follows.

[0090] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin-film transistor T4 can be turned on in response to the previous scan signal Sn-1, and the driving thin-film transistor T1 can be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

[0091] During the data programming period, when the first scan signal Sn' and the second scan signal Sn” are supplied through the first scan line SL1 and the second scan line SL2 respectively, the switching thin-film transistor T2 and the compensation thin-film transistor T3 can be turned on in response to the first scan signal Sn' and the second scan signal Sn” respectively. The driving thin-film transistor T1 can be diode-connected through the turned-on compensation thin-film transistor T3 and can be forward biased.

[0092] The compensation voltage (Dm+Vth(not shown, where Vth(not shown) is negative) obtained by subtracting the threshold voltage Vth(not shown) of the driving thin-film transistor T1 from the data signal Dm supplied by the data line DL can be applied to the driving gate electrode of the driving thin-film transistor T1.

[0093] The first power supply voltage ELVDD and the compensation voltage Dm+Vth (not shown) can be applied to the two ends of the storage capacitor Cst, and the charge corresponding to the voltage difference between the two ends can be stored in the storage capacitor Cst.

[0094] During the emission period, the operation control thin-film transistor T5 and the emission control thin-film transistor T6 can be turned on by the emission control signal En supplied from the emission control line EL. A drive current I can be generated based on the difference between the voltage of the drive gate electrode of the drive thin-film transistor T1 and the first power supply voltage ELVDD.OLED And drive current I OLED The emission control thin-film transistor T6 can supply power to the organic light-emitting diode (OLED).

[0095] In an embodiment, at least one of the thin-film transistors T1 to T7 may include a semiconductor layer comprising an oxide, and the remainder may include a semiconductor layer comprising silicon.

[0096] The driving thin-film transistor T1, which directly affects the brightness of the display device, may include a semiconductor layer formed of polycrystalline silicon with high reliability, thereby enabling a high-resolution display device.

[0097] Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is minimal even with long drive times. Low-frequency driving is possible because the image color change due to voltage drop is minimal, even during low-frequency drive.

[0098] As mentioned above, since oxide semiconductors have low leakage current, at least one of the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 connected to the drive gate electrode of the drive thin film transistor T1 can be provided as oxide semiconductors to prevent leakage current that can flow to the drive gate electrode and at the same time reduce power consumption.

[0099] Figure 4 A schematic cross-sectional view is provided to illustrate a pixel P included in a display device 1 according to an embodiment. Figure 4 Showing along Figure 1 The cross-sectional view taken by line I-I' in the diagram.

[0100] refer to Figure 4 The display device 1 according to the embodiment may include a first thin-film transistor TFT1, a second thin-film transistor TFT2, and an organic light-emitting diode OLED. For example, the first thin-film transistor TFT1 may be at least one of the above-mentioned compensation thin-film transistor T3, first initialization thin-film transistor T4, and second initialization thin-film transistor T7, and the second thin-film transistor TFT2 may be the above-mentioned driving thin-film transistor T1.

[0101] The substrate 100 may comprise glass, ceramic, metallic, or other materials with flexible or bendable properties. When the substrate 100 possesses flexible or bendable properties, it may comprise a high molecular weight resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a single-layer or multi-layer structure comprising the above materials.

[0102] An isolation layer 101 may be disposed on a substrate 100. The isolation layer 101 may include inorganic materials, such as oxides or nitrides, organic materials, or organic / inorganic composite materials, and may have a single-layer structure or a multi-layer structure of inorganic and organic materials.

[0103] A buffer layer 103 may be disposed on the isolation layer 101. The buffer layer 103 may be disposed on the substrate 100 to prevent or reduce the penetration of impurities, moisture or external gases from below the substrate 100 and to provide a planarized surface on the substrate 100. The buffer layer 103 may comprise inorganic materials, such as oxides or nitrides, organic materials, or organic / inorganic composite materials, and may have a single-layer structure or a multi-layer structure of inorganic and organic materials.

[0104] The first thin-film transistor TFT1 and the second thin-film transistor TFT2 may be disposed on the substrate 100. The first thin-film transistor TFT1 may include a first semiconductor layer 134a, a first gate electrode 136a, a first source electrode 137a, and a first drain electrode 138a. The second thin-film transistor TFT2 may include a second semiconductor layer 134b, a second gate electrode 136b, a second source electrode 137b, and a second drain electrode 138b.

[0105] The second semiconductor layer 134b may be disposed on the buffer layer 103. The second semiconductor layer 134b may include a second channel region 131b, a second source region 132b, and a second drain region 133b. The second source region 132b and the second drain region 133b may be disposed on both sides of the second channel region 131b. The second source region 132b and the second drain region 133b may include impurities. The impurities may be N-type impurities or P-type impurities. The second source region 132b and the second drain region 133b may be electrically connected to the second source electrode 137b and the second drain electrode 138b, respectively.

[0106] The second semiconductor layer 134b may include a silicon semiconductor material. The second semiconductor layer 134b may include amorphous silicon (a-Si) or low-temperature polycrystalline silicon (LTPS) formed by crystallizing amorphous silicon (a-Si).

[0107] The first insulating layer 105 may be disposed on the second semiconductor layer 134b. The first insulating layer 105 may include at least one inorganic insulating material selected from the group consisting of: silicon oxide (SiO2). x ), silicon nitride (SiN) x The first insulating layer 105 may be a single layer or multiple layers comprising the above-mentioned inorganic insulating materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0108] The second gate electrode 136b may be disposed on the first insulating layer 105. The second gate electrode 136b may overlap with at least a portion of the second semiconductor layer 134b. For example, the second gate electrode 136b may overlap with the second channel region 131b of the second semiconductor layer 134b. The second gate electrode 136b may be formed as a single layer or multiple layers of at least one metal selected from the group consisting of: aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0109] The second insulating layer 107 may be disposed on the second gate electrode 136b. The second insulating layer 107 may include at least one inorganic insulating material selected from the group consisting of: silicon oxide (SiO2). x ), silicon nitride (SiN) x The inorganic insulating layer 107 may be a single layer or multiple layers comprising the above-mentioned inorganic insulating materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0110] A storage capacitor Cst may be disposed on a first insulating layer 105. The storage capacitor Cst may include a lower electrode 144 and an upper electrode 146 overlapping the lower electrode 144. The lower electrode 144 and the upper electrode 146 of the storage capacitor Cst may overlap each other, and a second insulating layer 107 is located between the lower electrode 144 and the upper electrode 146.

[0111] In one embodiment, the lower electrode 144 of the storage capacitor Cst may overlap with the second gate electrode 136b of the second thin-film transistor TFT2, and the lower electrode 144 of the storage capacitor Cst and the second gate electrode 136b of the second thin-film transistor TFT2 may be integral with each other. In another embodiment, the lower electrode 144 of the storage capacitor Cst may be disposed on the first insulating layer 105 as a separate component that does not overlap with the second gate electrode 136b of the second thin-film transistor TFT2.

[0112] The upper electrode 146 of the storage capacitor Cst may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multiple layers of the above materials.

[0113] The third insulating layer 109 may be disposed on the upper electrode 146 of the storage capacitor Cst. The third insulating layer 109 may include at least one inorganic insulating material selected from the group consisting of: silicon oxide (SiO2). x ), silicon nitride (SiN) x The third insulating layer 109 may be a single layer or multiple layers comprising the above-mentioned inorganic insulating materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). In an embodiment, when the third insulating layer 109 is provided as a multiple layer, the third insulating layer 109 may include silicon oxide (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). x The first layer 109a and containing silicon nitride (SiN) x The second insulating layer 109b. In another embodiment, the third insulating layer 109 may include silicon nitride (SiN). x The first layer 109a and containing silicon oxide (SiO) x The second layer 109b.

[0114] The first semiconductor layer 134a may be disposed on the third insulating layer 109. In one embodiment, the first semiconductor layer 134a and the second semiconductor layer 134b may be disposed on different layers. In another embodiment, the first semiconductor layer 134a and the second semiconductor layer 134b may be disposed on the same layer.

[0115] The first semiconductor layer 134a may include a first channel region 131a, a first source region 132a, and a first drain region 133a. The first source region 132a and the first drain region 133a may be located on opposite sides of the first channel region 131a. The first source region 132a and the first drain region 133a may include impurities. The impurities may be N-type impurities or P-type impurities. For example, the first source region 132a and the first drain region 133a may each include fluorine or hydrogen.

[0116] The first source region 132a and the first drain region 133a can be electrically connected to the first source electrode 137a and the first drain electrode 138a, respectively.

[0117] The first semiconductor layer 134a may include an oxide semiconductor material. For example, the first semiconductor layer 134a may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In embodiments, the first semiconductor layer 134a may be formed of ITZO (InSnZnO) or IGZO (InGaZnO), etc.

[0118] Because the first semiconductor layer 134a is formed of oxide semiconductor, it can have a wide bandgap (approximately 3.1 eV), high carrier mobility, and low leakage current. Therefore, since the voltage drop of the organic light-emitting diode OLED according to the embodiment is not significant even during long driving times, the brightness change due to the voltage drop is not large even during low-frequency driving.

[0119] Figure 5 A schematic cross-sectional view illustrating the display device according to an embodiment, Figure 6 To illustrate the images showing the results of TEM analysis of the first semiconductor layer according to the embodiment, and Figure 7 A table illustrating the composition of each region of the first semiconductor layer according to the embodiment. Figure 5 Explained Figure 4 An enlarged cross-sectional view of part A. Figure 6 The results of analysis using transmission electron microscopy after increasing the roughness of the IGZO layer are explained, and Figure 7 A table illustrating the composition of the first protruding portion 135a, the second protruding portion 135b, and the main body portion of the first semiconductor layer 134a.

[0120] refer to Figure 5 The first semiconductor layer 134a may include protrusions 135 formed on the surface of the first semiconductor layer 134a. As described below, the protrusions 135 can be formed on the surface of the first semiconductor layer 134a by performing a plasma treatment, such as N2O plasma treatment and H2 plasma treatment. For example, N2O plasma treatment or H2 plasma treatment can be performed on the entire area of ​​the first semiconductor layer 134a to form the protrusions 135 on the entire area of ​​the first semiconductor layer 134a, thereby increasing the roughness of the first semiconductor layer 134a.

[0121] refer to Figure 6 According to an embodiment, the first semiconductor layer 134a of the display device 1 may include upwardly projecting protrusions 135a and 135b. The first protrusion 135a may protrude from the surface (upper surface) of the first semiconductor layer 134a with a first thickness t1, and the second protrusion 135b may protrude from the surface (upper surface) of the first semiconductor layer 134a with a second thickness t2. For example, the first thickness t1 may be about 8.983 nm, and the second thickness t2 may be about 9.299 nm.

[0122] Because the first semiconductor layer 134a may include protrusions 135 disposed on the surface (upper surface) of the first semiconductor layer 134a, the surface roughness of the first semiconductor layer 134a can be increased. In embodiments, the surface roughness of the first semiconductor layer 134a can be in the range of about 5 nm to about 50 nm. For example, the surface roughness of the first semiconductor layer 134a can be in the range of about 10 nm to about 40 nm, or about 5 nm to about 35 nm. For example, the first semiconductor layer 134a may have a surface roughness in the range of about 2 nm to about 30 nm.

[0123] refer to Figure 7 The main body portion of the first semiconductor layer 134a has a composition of 56.24 atomic percent (at%) oxygen (O), 13.78 at% zinc (Zn), 19.29 at% gallium (Ga), and 10.67 at% indium (In). The first protruding portion 135a has a composition of 62.94 at% oxygen (O), 3.18 at% zinc (Zn), 4.74 at% gallium (Ga), and 29.12 at% indium (In). The second protruding portion 135b has a composition of 59.12 at% oxygen (O), 2.46 at% zinc (Zn), 3.86 at% gallium (Ga), and 34.56 at% indium (In). In this case, the main body portion of the first semiconductor layer 134a and the first protruding portion 135a may further include other elements.

[0124] As can be seen, compared with the indium (In) content and gallium (Ga) content or zinc (Zn) content of the main body of the first semiconductor layer 134a, the protruding portions 135a and 135b have an increased indium (In) content and a decreased gallium (Ga) content or zinc (Zn) content. It is also evident that the protruding portions 135a and 135b have a higher indium (In) content than the gallium (Ga) content or zinc (Zn) content.

[0125] Return to reference Figure 4 The lower metal layer BML can be disposed on the second insulating layer 107. The lower metal layer BML can be disposed below the first semiconductor layer 134a to overlap with the first semiconductor layer 134a. In one embodiment, the lower metal layer BML and the upper electrode 146 of the storage capacitor Cst can be disposed on the same layer. In another embodiment, the lower metal layer BML and the upper electrode 146 of the storage capacitor Cst can be disposed on different layers.

[0126] The lower metal layer (BML) may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a single layer or multiple layers comprising the aforementioned materials. For example, the lower metal layer (BML) may have a Ti / Al / Ti multilayer structure.

[0127] Because the first semiconductor layer 134a, which includes oxide semiconductor material, is susceptible to light, the lower metal layer BML can prevent the characteristics of the first thin-film transistor TFT1, which includes oxide semiconductor material, from being altered by photocurrents appearing on the first semiconductor layer 134a due to external light incident from the substrate 100.

[0128] A fourth insulating layer 111 may be disposed on the first semiconductor layer 134a. The fourth insulating layer 111 disposed on the first semiconductor layer 134a may be unetched and may overlap with the first semiconductor layer 134a. In an embodiment, the fourth insulating layer 111 may overlap the entire region of the first semiconductor layer 134a. Because the fourth insulating layer 111 is unetched, the distribution of the threshold voltage Vth (not shown) can be reduced. The fourth insulating layer 111 may include at least one inorganic insulating material selected from the group consisting of: silicon oxide (SiO2). x ), silicon nitride (SiN) x The fourth insulating layer 111 may be a single layer or multiple layers comprising the above-mentioned inorganic insulating materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0129] The first gate electrode 136a may be disposed on the fourth insulating layer 111. The first gate electrode 136a may overlap with at least a portion of the first semiconductor layer 134a. For example, the first gate electrode 136a may overlap with the first channel region 131a of the first semiconductor layer 134a. The first gate electrode 136a may be formed as a single layer or multiple layers of at least one metal selected from the group consisting of: aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one embodiment, the first gate electrode 136a and the second gate electrode 136b may be disposed on different layers. In another embodiment, the first gate electrode 136a and the second gate electrode 136b may be disposed on the same layer.

[0130] A fifth insulating layer 113 may be disposed on the first gate electrode 136a. The fifth insulating layer 113 may include at least one inorganic insulating material selected from the group consisting of: silicon oxide (SiO2). x ), silicon nitride (SiN) x The fifth insulating layer 113 may be a single layer or multiple layers comprising the above-mentioned inorganic insulating materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0131] The first source electrode 137a, the first drain electrode 138a, the second source electrode 137b, and the second drain electrode 138b may be disposed on the fifth insulating layer 113. The first source electrode 137a, the first drain electrode 138a, the second source electrode 137b, and the second drain electrode 138b may comprise a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a single layer or multiple layers comprising the aforementioned materials. The first source electrode 137a, the first drain electrode 138a, the second source electrode 137b, and the second drain electrode 138b may each have a Ti / Al / Ti multilayer structure.

[0132] The first source electrode 137a can be connected to the first source region 132a through the contact hole CNT, and the first drain electrode 138a can be connected to the first drain region 133a through the contact hole CNT. The second source electrode 137b can be connected to the second source region 132b through the contact hole CNT, and the second drain electrode 138b can be connected to the second drain region 133b through the contact hole CNT.

[0133] A planarization layer 117 may be disposed on the first source electrode 137a, the first drain electrode 138a, the second source electrode 137b, and the second drain electrode 138b. The planarization layer 117 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. The planarization layer 117 may comprise a first planarization layer 117a and a second planarization layer 117b. Accordingly, conductive patterns, such as lines, may be formed between the first planarization layer 117a and the second planarization layer 117b, thus enabling high integration. However, the second planarization layer 117b may be omitted.

[0134] In embodiments, planarization layer 117 may comprise a general polymer, such as benzocyclobutene (BCB), polyimide (PI), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof. Planarization layer 117 may comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). After the planarization layer 117 is formed, chemical mechanical polishing can be performed to provide a flat upper surface.

[0135] A contact metal layer CM may be disposed on the first planarization layer 117a. The contact metal layer CM may include aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a single layer or multiple layers. The contact metal layer CM may have a Ti / Al / Ti multilayer structure.

[0136] An organic light-emitting diode (OLED) comprising a pixel electrode 210, an intermediate layer 220, and a counter electrode 230 may be disposed on a planarization layer 117. The pixel electrode 210 may be electrically connected to a contact metal layer CM via a contact hole CNT penetrating the second planarization layer 117b, and the contact metal layer CM may be electrically connected to the second source electrode 137b or the second drain electrode 138b of the second thin-film transistor TFT2 via a contact hole CNT penetrating the first planarization layer 117a, thereby enabling the organic light-emitting diode (OLED) to be electrically connected to the second thin-film transistor TFT2.

[0137] Pixel electrode 210 may be disposed on the second planarization layer 117b. Pixel electrode 210 may be a (semi-)transparent electrode or a reflective electrode. Pixel electrode 210 may include a reflective film formed of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), or compounds thereof, and a transparent electrode layer or a semi-transparent electrode layer formed on the reflective film. The transparent electrode layer or the semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). Pixel electrode 210 may have an ITO / Ag / ITO stacked structure.

[0138] A pixel defining layer 180 may be disposed on the second planarization layer 117b, and the pixel defining layer 180 may have an opening that exposes at least a portion of the pixel electrode 210. The portion exposed by the opening of the pixel defining layer 180 may be defined as an emitting region. The periphery of the emitting region may be a non-emitting region, and the non-emitting region may surround the emitting region. For example, the display region DA may include an emitting region and a non-emitting region surrounding the emitting region. The pixel defining layer 180 may prevent arcing or the like at the edge of the pixel electrode 210 by increasing the distance between the upper part of the pixel electrode 210 and the opposing electrode 230. The pixel defining layer 180 may be formed from an organic insulating material, such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin, using a method such as spin coating.

[0139] Spacers 190 for preventing mask scratches may be disposed on pixel defining layer 180. Spacers 190 and pixel defining layer 180 may be integral with each other. For example, spacers 190 and pixel defining layer 180 may be formed simultaneously in the same process using a halftone mask.

[0140] Intermediate layer 220 may be disposed on at least a portion of pixel electrode 210 exposed by pixel defining layer 180. Intermediate layer 220 may include emitter layer 220b, and first functional layer 220a and second functional layer 220c may be selectively disposed below and on emitter layer 220b, respectively.

[0141] In one embodiment, the intermediate layer 220 may be disposed on at least a portion of the pixel electrode 210 exposed by the pixel defining layer 180. For example, the emitter layer 220b of the intermediate layer 220 may be disposed on at least a portion of the pixel electrode 210 exposed by the pixel defining layer 180.

[0142] The first functional layer 220a may be disposed below the emission layer 220b, and the second functional layer 220c may be disposed on the emission layer 220b. The first functional layer 220a and the second functional layer 220c disposed below the emission layer 220b and on the emission layer 220b, respectively, may be collectively referred to as organic functional layers.

[0143] The first functional layer 220a may include a hole injection layer (HIL) and / or a hole transport layer (HTL), and the second functional layer 220c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0144] The emitting layer 220b may include organic materials, including fluorescent or phosphorescent materials that emit red, green, blue, or white light. The emitting layer 220b may include low-molecular-weight or high-molecular-weight organic materials.

[0145] When the emitter layer 220b comprises a low molecular weight organic material, the intermediate layer 220 may have a structure in which the hole injection layer, hole transport layer, emitter layer, electron transport layer, or electron injection layer can be stacked in a single or composite structure, and the low molecular weight organic material can be various organic materials, such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), or tris(8-hydroxyquinoline)aluminum (Alq3), etc. These layers can be formed by vacuum deposition.

[0146] When the emitter layer 220b comprises a high molecular weight organic material, the intermediate layer 220 may have a structure including a hole transport layer and the emitter layer 220b. The hole transport layer may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the emitter layer 220b may comprise a high molecular weight material, such as polyphenylene acetylene (PPV) or polyfluorene. The emitter layer 220b may be formed by screen printing, inkjet printing, or laser-induced thermal imaging (LITI).

[0147] The opposing electrode 230 may be disposed on the intermediate layer 220. The opposing electrode 230 may be disposed on the intermediate layer 220 to cover the entire surface of the intermediate layer 220. The opposing electrode 230 may also be disposed on the display area DA to cover the entire surface of the display area DA. For example, the opposing electrode 230 may be integrally formed on the entire display area using an aperture mask to cover the pixel P disposed in the display area DA.

[0148] The counter electrode 230 may include a conductive material with a low work function. For example, in one embodiment, the counter electrode 230 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. In another embodiment, the counter electrode 230 may further include a layer of, for example, ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the above-described materials.

[0149] In one embodiment, the organic light-emitting diode (OLED) may be covered by a thin-film encapsulation layer. The thin-film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In another embodiment, the OLED may be covered by an encapsulation substrate.

[0150] Figures 8 to 13 A schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0151] The following text will refer to Figures 8 to 13 The method for manufacturing display devices is described sequentially.

[0152] refer to Figures 8 to 13 A method of manufacturing a display device according to an embodiment may include forming a first semiconductor layer 134a comprising an oxide semiconductor material on a substrate 100, increasing the surface roughness of the first semiconductor layer 134a, forming an insulating layer (e.g., a fourth insulating layer 111) on the first semiconductor layer 134a, forming a metal layer 136M on the insulating layer (e.g., the fourth insulating layer 111), and patterning the metal layer 136M to form a gate electrode (e.g., a first gate electrode 136a).

[0153] The method may further include forming a second semiconductor layer 134b comprising a silicon semiconductor material on the substrate 100 and forming a lower metal layer BML to overlap with the first semiconductor layer 134a before forming a first semiconductor layer 134a comprising an oxide semiconductor material on the substrate 100.

[0154] refer to Figure 8 The second semiconductor layer 134b, the second gate electrode 136b, the upper electrode 146, and the lower metal layer BML may be formed on the substrate 100. The second semiconductor layer 134b may include a silicon semiconductor material. The second semiconductor layer 134b may include amorphous silicon (a-Si) or low-temperature polycrystalline silicon (LTPS) formed by crystallizing amorphous silicon (a-Si).

[0155] An isolation layer 101 and a buffer layer 103 may be formed on a substrate 100, a first insulating layer 105 may be formed on a second semiconductor layer 134b, a second insulating layer 107 may be formed on a second gate electrode 136b, and a third insulating layer 109 may be formed on an upper electrode 146 and a lower metal layer BML.

[0156] The first semiconductor layer 134a may be formed on the third insulating layer 109. The first semiconductor layer 134a may include an oxide semiconductor material. For example, the first semiconductor layer 134a may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the first semiconductor layer 134a may be formed of ITZO (InSnZnO) or IGZO (InGaZnO).

[0157] In one embodiment, the first semiconductor layer 134a and the second semiconductor layer 134b may be disposed on different layers. In another embodiment, the first semiconductor layer 134a and the second semiconductor layer 134b may be disposed on the same layer.

[0158] refer to Figure 9 The method may further include increasing the surface roughness of the first semiconductor layer 134a after forming a first semiconductor layer 134a comprising an oxide semiconductor material on the substrate 100.

[0159] When increasing the surface roughness of the first semiconductor layer 134a, a protrusion 135 may be formed on the surface of the first semiconductor layer 134a. In an embodiment, a plasma treatment may be performed on the surface of the first semiconductor layer 134a to form the protrusion 135 on the surface of the first semiconductor layer 134a, thereby increasing the surface roughness of the first semiconductor layer 134a.

[0160] As a method to increase the surface roughness of the first semiconductor layer 134a, N2O plasma treatment, H2 plasma treatment, or plasma treatment by increasing the power of chemical vapor deposition (CVD) of silane (SiH4) or by increasing the power of the insulating layer (e.g., the fourth insulating layer 111) as described below can be used. The surface roughness of the entire surface of the first semiconductor layer 134a can be increased by N2O plasma treatment or H2 plasma treatment, etc. For example, the surface roughness of the first semiconductor layer 134a can be in the range of about 2 nm to about 30 nm.

[0161] Compared to the main body of the first semiconductor layer 134a, the upper portion of the first semiconductor layer 134a with increased surface roughness may have an increased indium (In) content and a decreased gallium (Ga) or zinc (Zn) content. The upper portion of the first semiconductor layer 134a with increased surface roughness may have a higher atomic percentage (at%) of indium (In) than that of gallium (Ga) or zinc (Zn).

[0162] refer to Figure 10 After increasing the surface roughness of the first semiconductor layer 134a, an insulating layer (e.g., a fourth insulating layer 111) may be formed on the first semiconductor layer 134a.

[0163] An insulating layer (e.g., a fourth insulating layer 111) formed on the first semiconductor layer 134a may be unetched and may overlap with the first semiconductor layer 134a. In an embodiment, the insulating layer (e.g., the fourth insulating layer 111) may overlap the entire area of ​​the first semiconductor layer 134a. Because the fourth insulating layer 111 may be unetched, the distribution of the threshold voltage Vth (not shown) can be reduced.

[0164] refer to Figure 11 After forming an insulating layer (e.g., a fourth insulating layer 111) on the first semiconductor layer 134a, a metal layer 136M may be formed on the insulating layer (e.g., the fourth insulating layer 111).

[0165] The metal layer 136M may be formed as a single layer or multiple layers of at least one metal selected from the group consisting of: aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0166] refer to Figure 12 After forming a metal layer 136M on an insulating layer (e.g., a fourth insulating layer 111), the metal layer 136M can be patterned to form a gate electrode (e.g., a first gate electrode 136a).

[0167] In an embodiment, the metal layer 136M formed on an insulating layer (e.g., a fourth insulating layer 111) can be patterned using a dry etching process. For example, by using dry etching gases such as NF6 and CF4, the metal layer 136M can be patterned into a gate electrode (e.g., a first gate electrode 136a). Further heat treatment can be performed on the patterned gate electrode (e.g., the first gate electrode 136a).

[0168] When the metal layer 136M is patterned into a gate electrode (e.g., the first gate electrode 136a) using dry etching gases such as NF6 and CF4 and heat-treated on the patterned gate electrode (e.g., the first gate electrode 136a), fluorine or hydrogen can diffuse into at least a portion of the first semiconductor layer 134a to form N+ conductive regions (e.g., the first source region 132a and the first drain region 133a).

[0169] As described above, because the surface roughness of the first semiconductor layer 134a can be increased, thereby increasing the contact area per unit length between the first semiconductor layer 134a and fluorine or hydrogen, and the proportion of indium (In) on the surface of the first semiconductor layer 134a can be increased, thereby improving the reactivity with fluorine or hydrogen, allowing fluorine and hydrogen to diffuse more into the N+ conductive regions (e.g., the first source region 132a and the first drain region 133a), and thus improving the conductivity of the N+ conductive regions (e.g., the first source region 132a and the first drain region 133a). For example, the carrier concentration per unit area of ​​the N+ conductive regions (e.g., the first source region 132a and the first drain region 133a) can be increased, thereby improving conductivity.

[0170] Because the reactivity between the N+ conductive region (e.g., the first source region 132a and the first drain region 133a) and fluorine or hydrogen can be increased (which can increase the proportion of oxygen vacancies), fluorine or hydrogen can be prevented from diffusing into the channel region (e.g., the first channel region 131a) of the first semiconductor layer 134a.

[0171] refer to Figure 13 After the metal layer 136M is patterned to form a gate electrode (e.g., a first gate electrode 136a), an organic light-emitting diode (OLED) can be formed on the gate electrode (e.g., the first gate electrode 136a).

[0172] The fifth insulating layer 113 may be formed on the gate electrode (e.g., the first gate electrode 136a), and the first source electrode 137a, the first drain electrode 138a, the second source electrode 137b, and the second drain electrode 138b may be formed on the fifth insulating layer 113.

[0173] A planarization layer 117 may be formed on the first source electrode 137a, the first drain electrode 138a, the second source electrode 137b, and the second drain electrode 138b. The planarization layer 117 may include a first planarization layer 117a and a second planarization layer 117b. An organic light-emitting diode (OLED) including a pixel electrode 210, an intermediate layer 220, and a counter electrode 230 may be formed on the planarization layer 117.

[0174] Because the insulating layer (e.g., the fourth insulating layer 111) disposed on the semiconductor layer including the oxide semiconductor material is not etched, the diffusion of hydrogen used as charge carriers is reduced, thereby reducing the conduction current.

[0175] To address the aforementioned issues, the conductivity of the N+ conductive regions (e.g., the first source region 132a and the first drain region 133a) can be improved by increasing the surface roughness of the semiconductor layer (e.g., the first semiconductor layer 134a), thereby simultaneously improving the conduction current and device characteristics.

[0176] In implementations, the surface roughness of the semiconductor layer (e.g., the first semiconductor layer 134a) can be increased by methods such as N2O plasma treatment, H2 plasma treatment, or plasma treatment by increasing the CVD power of silane (SiH4) or by increasing the power of the insulating layer (e.g., the fourth insulating layer 111). The upper part of the semiconductor layer (e.g., the first semiconductor layer 134a) with increased surface roughness may have an increased indium (In) content and a decreased gallium (Ga) content or zinc (Zn) content.

[0177] In this implementation, since the etching of the insulating layer (e.g., the fourth insulating layer 111) formed on the semiconductor layer (e.g., the first semiconductor layer 134a) can be omitted, the distribution of the threshold voltage Vth (not shown) can be reduced.

[0178] In this implementation, because the surface roughness of the semiconductor layer (e.g., the first semiconductor layer 134a) can be increased, thereby increasing the contact area per unit length between the semiconductor layer (e.g., the first semiconductor layer 134a) and fluorine or hydrogen, and the proportion of indium (In) in the upper part of the semiconductor layer (e.g., the first semiconductor layer 134a) can be increased, thereby improving reactivity, fluorine or hydrogen can diffuse more into the N+ conductive regions (e.g., the first source region 132a and the first drain region 133a), increasing the carrier concentration per unit area of ​​the N+ conductive regions (e.g., the first source region 132a and the first drain region 133a), and thus improving conductivity.

[0179] In this implementation, because the reactivity between fluorine or hydrogen in the N+ conductive region (e.g., the first source region 132a and the first drain region 133a) can be increased (which can increase the proportion of oxygen vacancies), fluorine or hydrogen can be prevented from diffusing into the channel region (e.g., the first channel region 131a) of the first semiconductor layer 134a.

[0180] According to the above embodiments, since the pixel circuit for driving the display device includes a first thin-film transistor containing an oxide semiconductor material and a second thin-film transistor containing a silicon semiconductor material, it is possible to provide a high-resolution display device with low power consumption.

[0181] This disclosure has been described with reference to the embodiments illustrated in the accompanying drawings; however, this is merely illustrative, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible from the embodiments. Therefore, the technical scope of this disclosure should be defined by the technical spirit of the appended claims.

Claims

1. A display device, the display device comprising: A substrate, the substrate including a display area and a non-display area adjacent to the display area; A first thin-film transistor, the first thin-film transistor being disposed on the substrate and including a first semiconductor layer comprising an oxide semiconductor material; and The second thin-film transistor is disposed on the substrate and includes a second semiconductor layer comprising a silicon semiconductor material. The surface roughness of the first semiconductor layer is increased by plasma treatment to form protrusions on the surface of the first semiconductor layer. The indium content of the protruding portion is greater than the gallium content or the zinc content of the protruding portion, and The indium content of the protruding portion is greater than the indium content of the main body portion of the first semiconductor layer.

2. The display device according to claim 1, wherein the surface roughness of the first semiconductor layer is in the range of 2 nm to 50 nm.

3. The display device according to claim 1, wherein the first semiconductor layer comprises an oxide of at least one material selected from the group consisting of: indium, gallium, tin, zirconium, vanadium, hafnium, cadmium, germanium, chromium, titanium, aluminum, cesium, cerium, and zinc.

4. The display device according to claim 1, wherein the first thin-film transistor comprises: A gate electrode, which overlaps with the first semiconductor layer; and An insulating layer is disposed between the first semiconductor layer and the gate electrode.

5. The display device according to claim 4, wherein the insulating layer overlaps with the first semiconductor layer.

6. The display device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are disposed on different layers.

7. The display device according to claim 1, further comprising: A lower metal layer is disposed between the substrate and the first semiconductor layer to overlap with the first semiconductor layer.

8. A method for manufacturing a display device according to any one of claims 1 to 7, the method comprising: A first semiconductor layer comprising an oxide semiconductor material is formed on a substrate; Increase the surface roughness of the first semiconductor layer; An insulating layer is formed on the first semiconductor layer; A metal layer is formed on the insulating layer; as well as The metal layer is patterned to form a gate electrode.

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