Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate having a gate structure on the substrate; a first spacer layer located on the sidewall of the gate structure, wherein the top surface of the first spacer layer is flush with the top surface of the gate structure; a second spacer layer located on the substrate at both sides of the gate structure, wherein the top surface of the second spacer layer is flush with the top surface of the gate structure, and a gap layer is provided between the second spacer layer and the first spacer layer. The semiconductor structure provided by the embodiment of the present invention is conducive to reducing the parasitic capacitance of the semiconductor device, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to the reduction in feature size, the channel length of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) is also continuously shortened accordingly.

[0003] As the length of the gate electrode continues to decrease, the most serious parasitic capacitance in MOS transistors exists between the gate electrode and the contact plug on the source and drain regions, and reducing the parasitic capacitance is the main method to improve the response speed and power consumption of small-size MOS transistors. However, in the current MOS transistor structure, the material of the sidewall (spacer) is generally silicon nitride, silicon oxide, etc. Since the dielectric constant of materials such as silicon nitride and silicon oxide is relatively large, the parasitic capacitance between the gate electrode and the contact plug on the source and drain regions is relatively large, which increases the delay and switching power consumption of the device. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce parasitic capacitance, and reduce the delay and switching power consumption of the device.

[0005] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, having a gate structure on the substrate; a first sidewall layer, located on the sidewall of the gate structure, and the top surface of the first sidewall layer is flush with the top surface of the gate structure; a second sidewall layer, located on the substrate on both sides of the gate structure, the top surface of the second sidewall layer is flush with the top surface of the gate structure, and a gap layer is provided between the second sidewall layer and the first sidewall layer.

[0006] Optionally, the method further comprises: a dielectric layer, wherein the dielectric layer is located on the substrate, and the top surface of the dielectric layer is flush with the top surface of the gate structure.

[0007] Optionally, it also includes: source-drain doping layers located in the substrate on both sides of the gate structure.

[0008] Optionally, it also includes: a first stop layer, located on the source / drain doping layer and on the sidewall of the second spacer layer.

[0009] Optionally, it also includes: a second stop layer, located on the dielectric layer, the second spacer layer, the first spacer layer and the surface of the gate structure.

[0010] Optionally, a material of the first spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride or silicon carbon boron nitride.

[0011] Optionally, a material of the second spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxide or silicon carbon boron nitride.

[0012] Correspondingly, an embodiment of the present invention also provides a method for forming the above-mentioned semiconductor structure, including: providing a substrate, on which a dummy gate structure is formed; forming a first sidewall layer, a sacrificial layer and a second sidewall layer on the sidewall of the dummy gate structure, the sacrificial layer being located between the first sidewall layer and the second sidewall layer, and the top surfaces of the first sidewall layer and the second sidewall layer are flush with the top surface of the dummy gate structure, and the top surface of the sacrificial layer is lower than the top surface of the dummy gate structure; removing the dummy gate structure to form a gate opening; forming an initial gate structure in the gate opening; flattening the initial gate structure, the first sidewall layer and the second sidewall layer until the top surface of the sacrificial layer is exposed to form a gate structure; removing the sacrificial layer to form a gap layer between the first sidewall layer and the second sidewall layer.

[0013] Optionally, the steps of forming a first sidewall layer, a sacrificial layer and a second sidewall layer on the sidewall of the pseudo gate structure include: forming a first sidewall material layer on the substrate, the top and the sidewall of the pseudo gate structure; forming a sacrificial material layer on the surface of the first sidewall material layer; etching the sacrificial material layer until the top surface of the sacrificial material layer is lower than the top surface of the pseudo gate structure, and forming a sacrificial layer on the sidewall surface of the first sidewall material layer; forming a second sidewall material layer on the substrate, the sacrificial layer and the first sidewall material layer; forming a dielectric layer on the substrate, the top surface of the dielectric layer is higher than the top surface of the second sidewall material layer; flattening the dielectric layer, the second sidewall material layer and the first sidewall material layer until the top surface of the pseudo gate structure is exposed, and forming a first sidewall layer and a second sidewall layer on the sidewall of the pseudo gate structure, the sacrificial layer being located between the first sidewall layer and the second sidewall layer.

[0014] Optionally, the process of etching the sacrificial material layer is a plasma dry etching process, and the process parameters of the plasma dry etching process include: the etching atmosphere includes NF3 and H2, and the bias voltage is 50-200V.

[0015] Optionally, after forming the second spacer material layer and before forming the dielectric layer, the method further includes: forming source-drain doping layers in the substrate on both sides of the dummy gate structure.

[0016] Optionally, after forming the source / drain doped layer and before forming the dielectric layer, the method further includes: forming a first stop layer on the source / drain doped layer, wherein the first stop layer also covers a surface of the second spacer material layer.

[0017] Optionally, after removing the sacrificial layer and forming a gap layer between the first spacer layer and the second spacer layer, the method further includes: forming a second stop layer on the dielectric layer, the first spacer layer, the second spacer layer and the surface of the gate structure.

[0018] Optionally, a method for forming the second stop layer includes chemical vapor deposition.

[0019] Optionally, a material of the first spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride or silicon carbon boron nitride.

[0020] Optionally, the material of the sacrificial layer includes amorphous silicon.

[0021] Optionally, a material of the second spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxide or silicon carbon boron nitride.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] The semiconductor structure provided by the embodiment of the present invention has a gap layer between the first sidewall layer and the second sidewall layer, and the gap layer is used to form an "air sidewall". The first sidewall layer, the "air sidewall" and the second sidewall layer play the role of gate structure sidewalls. Since the dielectric constant of air is very small, the existence of the "air sidewall" is beneficial to reducing the dielectric constant of the sidewall as a whole, which is beneficial to reducing the parasitic capacitance of the formed semiconductor device, reducing delay and switching power consumption, thereby improving the performance of the semiconductor structure.

[0024] In a method for forming a semiconductor structure provided by an embodiment of the present invention, a sacrificial layer is formed between a first sidewall layer and a second sidewall layer, the sacrificial layer occupies space for a void layer formed subsequently, and a void layer is formed after removing the sacrificial layer. The void layer is used to form an "air sidewall". Since the dielectric constant of air is very small, the presence of the "air sidewall" is beneficial to reducing the overall dielectric constant of the sidewall on the sidewall of the gate structure, which is beneficial to reducing the parasitic capacitance of the formed semiconductor device, reducing delay and switching power consumption, and thus improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 13 It is a schematic structural diagram corresponding to each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0026] As can be seen from the background technology, the materials of the sidewalls currently used in MOS transistors are generally silicon nitride, silicon oxide, etc., and the dielectric constants of materials such as silicon nitride and silicon oxide are relatively large, which makes the parasitic capacitance of the semiconductor device relatively large, thereby affecting the electrical performance of the semiconductor device.

[0027] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first sidewall layer, a sacrificial layer and a second sidewall layer are formed on the sidewall of a pseudo gate structure, the sacrificial layer is located between the first sidewall layer and the second sidewall layer, and the top surfaces of the first sidewall layer and the second sidewall layer are flush with the top surface of the pseudo gate structure, and the top surface of the sacrificial layer is lower than the top surface of the pseudo gate structure. After removing the pseudo gate structure to form an initial gate structure, the initial gate structure, the first sidewall layer and the second sidewall layer are planarized until the top surface of the sacrificial layer is exposed to form a gate structure, which is beneficial to controlling the height of the formed gate structure; after forming the gate structure, the sacrificial layer is removed to form a gap layer between the first sidewall layer and the second sidewall layer, thereby forming an "air sidewall". Since the dielectric constant of air is very small, the parasitic capacitance of the semiconductor device is significantly reduced, the delay of the device is reduced, and the response speed and switching power consumption of the switching state are improved.

[0028] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figures 1 to 13 It is a schematic structural diagram corresponding to each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0030] refer to Figure 1 , providing a substrate 100 , on which a dummy gate structure 110 is formed.

[0031] In this embodiment, the base 100 includes a substrate 101 and a fin 102 located on the substrate 101 .

[0032] In other embodiments, the fin 102 may not be formed on the substrate 101 .

[0033] In this embodiment, the material of the substrate 101 is silicon.

[0034] In other embodiments, the material of the substrate 101 may also be semiconductor materials such as germanium, silicon germanium, gallium arsenide, silicon on insulator (SOI), and germanium on insulator (GOI).

[0035] In this embodiment, the material of the fin 102 is silicon; in other embodiments, the material of the fin 102 may also be a semiconductor material such as germanium, silicon germanium, gallium arsenide, silicon on insulator (SOI), or germanium on insulator (GOI).

[0036] In this embodiment, the dummy gate structure 110 spans across the fin 102 , covering the top and a portion of the sidewall surface of the fin 102 .

[0037] In this embodiment, the dummy gate structure 110 includes: a dummy gate dielectric layer (not shown) located on the fin 102 and a dummy gate layer 111 located on the dummy gate dielectric layer.

[0038] In this embodiment, the steps of forming the dummy gate structure 110 include: forming a dummy gate dielectric layer, a dummy gate material layer covering the dummy gate dielectric layer, and a mask layer covering the dummy gate material layer on the surface of the substrate 100; forming a patterned photoresist layer on the mask layer; using the patterned photoresist layer as a mask, etching the mask layer, the dummy gate material layer and the dummy gate dielectric layer to form a dummy gate layer 111, a dummy gate dielectric layer (not shown) located between the substrate 100 and the dummy gate layer 111, and a mask layer 112 located on the dummy gate layer 111.

[0039] In this embodiment, after the dummy gate structure 110 is formed, the mask layer 112 is not removed first. The mask layer 112 can protect the dummy gate layer 111 from etching damage in the subsequent process, and the mask layer 112 is removed in the subsequent process, which simplifies the process steps.

[0040] In other embodiments, after the dummy gate structure 110 is formed, the mask layer 112 may also be removed.

[0041] In this embodiment, the material of the dummy gate dielectric layer is silicon oxide.

[0042] In this embodiment, the material of the dummy gate layer 111 is polysilicon; in other embodiments, the material of the dummy gate layer 111 may also be amorphous carbon.

[0043] In this embodiment, the mask layer 112 is multi-layered, including a first mask layer 1121 located on the pseudo gate layer 111 and a second mask layer 1122 located on the first mask layer 1121; in other embodiments, the mask layer 112 may also be a single layer, and the material of the single layer includes silicon nitride or silicon oxide or silicon carbide.

[0044] In this embodiment, the material of the first mask layer 1121 is silicon nitride; the material of the second mask layer 1122 is silicon oxide.

[0045] In other embodiments, the material of the first mask layer 1121 may also be silicon oxide or silicon carbide, and the material of the second mask layer 1122 may also be silicon nitride or silicon carbide.

[0046] After the dummy gate structure 110 is formed, a first sidewall layer, a sacrificial layer and a second sidewall layer are formed on the sidewalls of the dummy gate structure 110, the sacrificial layer is located between the first sidewall layer and the second sidewall layer, and the top surfaces of the first sidewall layer and the second sidewall layer are flush with the top surface of the dummy gate structure 110, and the top surface of the sacrificial layer is lower than the top surface of the dummy gate structure 110.

[0047] The steps of forming the first spacer layer, the sacrificial layer and the second spacer layer specifically include:

[0048] refer to Figure 2 , forming a first spacer material layer 120 on the substrate 100 and the top and sidewalls of the dummy gate structure 110 .

[0049] In this embodiment, the first spacer material layer 120 is used to subsequently form a first spacer layer, and is also used to protect the sidewall of the dummy gate structure 110 in subsequent processes and provide support when a gap layer is subsequently formed.

[0050] In this embodiment, the first spacer material layer 120 also covers the top and sidewall surfaces of the mask layer 112 .

[0051] In this embodiment, the material of the first side wall material layer 120 is silicon nitride; in other embodiments, the material of the first side wall material layer 120 can also be one or more combinations of materials such as silicon oxide (SiO2), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0052] In this embodiment, the first spacer material layer 120 is formed by chemical vapor deposition. In other embodiments, the first spacer material layer 120 may be formed by atomic layer deposition.

[0053] In this embodiment, the thickness of the first spacer material layer 120 is 2-10 nm. If the thickness of the first spacer material layer 120 is too thick, the thickness of the sidewall of the gate structure will be thicker, the dielectric constant will still be large, and the effect of reducing parasitic capacitance will be poor; if the thickness of the first spacer material layer 120 is too thin, the support effect will be poor when the sacrificial layer is removed later.

[0054] Continue to refer Figure 2 , a sacrificial material layer 130 is formed on the first spacer material layer 120 .

[0055] In this embodiment, the sacrificial material layer 130 covers the first spacer material layer 120 , and the sacrificial material layer 130 is used to subsequently form a sacrificial layer.

[0056] In this embodiment, the material of the sacrificial material layer 130 is amorphous silicon, which has a high etching selectivity ratio with the first sidewall material layer 120 and the second sidewall material layer 140, thereby avoiding etching damage to the first sidewall layer and the second sidewall layer when the sacrificial layer is subsequently removed.

[0057] In this embodiment, the sacrificial material layer 130 is formed by a chemical vapor deposition process; in other embodiments, the sacrificial material layer 130 may also be formed by an atomic layer deposition process.

[0058] In this embodiment, the thickness of the sacrificial material layer 130 is 2-10 nm. If the thickness of the sacrificial material layer 130 is too thick, the sacrificial layer formed subsequently is too thick, and the space of the gap layer formed after removing the sacrificial layer is large. When the second stop layer is formed subsequently, the second stop layer will be deposited in the gap, destroying the formed "air side wall"; if the thickness of the sacrificial material layer 130 is too thin, the thickness of the gap layer finally formed is too thin, resulting in a small effect of reducing the dielectric constant and reducing the parasitic capacitance.

[0059] refer to Figure 3 , the sacrificial material layer 130 is etched until the top surface of the sacrificial material layer 130 is lower than the top surface of the dummy gate structure 110 , and a sacrificial layer 131 is formed on the sidewall of the first spacer material layer 120 .

[0060] In this embodiment, the sacrificial material layer 130 on the substrate 100 and on the top and part of the sidewall of the dummy gate structure 110 is removed by etching.

[0061] In this embodiment, the process for etching the sacrificial material layer 130 is a plasma dry etching process, and the plasma dry etching process is to etch the sacrificial material layer 130 along a direction perpendicular to the substrate 100. Etching the sacrificial material layer using the directional plasma dry etching process can remove the pseudo gate structure 110 and the sacrificial material layer 130 on the substrate 100 while retaining the sacrificial material layer 130 on the side wall of the first sidewall material layer 120.

[0062] In this embodiment, the process parameters of the directional etching process include: the etching atmosphere includes NF3 and H2, and the bias voltage is 50-200V.

[0063] refer to Figure 4After the sacrificial layer 131 is formed, a second spacer material layer 140 is formed on the substrate 100 , the sacrificial layer 131 and the first spacer material layer 120 .

[0064] In this embodiment, specifically, the second spacer material layer 140 is formed on the substrate 100 , the sidewall and top surface of the sacrificial layer 131 , and the sidewall and top surface of the first spacer material layer 120 exposed by the sacrificial layer 131 .

[0065] In this embodiment, the second spacer material layer 140 is used to subsequently form a second spacer layer, and is also used to provide support for the final formation of a gap layer.

[0066] In this embodiment, the material of the second side wall material layer 140 is silicon nitride; in other embodiments, the material of the second side wall material layer 140 can also be one or more combinations of materials such as silicon oxide (SiO2), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0067] In this embodiment, the second spacer material layer 140 is formed by chemical vapor deposition. In other embodiments, the second spacer material layer 140 may be formed by atomic layer deposition.

[0068] In this embodiment, the thickness of the second spacer material layer 140 is 2-10 nm. If the thickness of the second spacer material layer 140 is too thick, the thickness of the sidewall of the gate structure will be thicker, the dielectric constant will still be large, and the effect of reducing parasitic capacitance will be poor; if the thickness of the second spacer material layer 140 is too thin, the support effect will be poor when the sacrificial layer is removed later.

[0069] refer to Figure 5 After forming the second spacer material layer 140 , the method further includes: forming a source-drain doping layer 103 in the substrate 100 on both sides of the dummy gate structure 110 .

[0070] In this embodiment, the first spacer material layer 120 , the sacrificial layer 131 and the second spacer material layer 140 are used together to position the source / drain doped layer 103 and protect the sidewall of the dummy gate layer 111 to prevent the dummy gate layer 111 from being damaged.

[0071] In this embodiment, the step of forming the source-drain doped layer 103 includes: using the dummy gate structure 110 and the second sidewall material layer 140 as masks, etching the fins 102 on both sides of the dummy gate structure 110, and forming grooves (not shown) in the fins 102 on both sides of the dummy gate structure 110 and the second sidewall material layer 140; and forming the source-drain doped layer 103 in the grooves.

[0072] The source-drain doping layer 103 contains source-drain ions.

[0073] In this embodiment, the process for forming the source-drain doped layer 103 includes an epitaxial growth process; and the process for doping source and drain ions in the source-drain doped layer 103 is a source-drain doping process.

[0074] In this embodiment, when the fins 102 on both sides of the dummy gate structure 110 are etched, the second spacer material layer 140 and the first spacer material layer 120 on the substrate 100 on both sides of the dummy gate structure 110 are removed by etching.

[0075] refer to Figure 6 , a first stop layer 104 is formed on the source / drain doped layer 103 , and the first stop layer 104 also covers the surface of the second spacer material layer 140 .

[0076] In the present embodiment, when the first stop layer 104 is formed to etch the conductive plug vias on the source-drain doped layer 103, on the one hand, the conductive plug vias of the source-drain doped layer are all stopped on the first stop layer 104, and the first stop layer 104 can protect the substrate 100 below and the side wall of the pseudo gate structure 110 from being damaged; on the other hand, the conductive plug vias are all stopped on the first stop layer 104, and the first stop layer 104 will not be over-etched, thereby forming conductive plug vias with the same depth.

[0077] In this embodiment, the material of the first stop layer 104 is silicon nitride; in other embodiments, the material of the first stop layer 104 may also be carbon-doped silicon nitride.

[0078] In this embodiment, the process of forming the first stop layer 104 is a chemical vapor deposition process; in other embodiments, the first stop layer 104 may also be formed by an atomic layer deposition process.

[0079] In this embodiment, the material of the first stop layer 104 is the same as the second spacer material layer 140 and the first spacer material layer 120 , and the portion of the first stop layer 104 located on the sidewall of the dummy gate structure 110 eventually also serves as a portion of the spacer on the sidewall of the gate structure.

[0080] The thickness of the first stop layer 104 is 2-10 nm. If the thickness of the first stop layer 104 is too large, the thickness of the sidewalls on the gate structure will eventually be too large, resulting in too large parasitic capacitance of the device; if the thickness of the first stop layer 104 is too small, it cannot play a good role in etching stop.

[0081] refer to Figure 7 , the dielectric layer 105 is formed on the substrate 100 , and the top surface of the dielectric layer 105 is higher than the top surface of the second spacer material layer 140 .

[0082] In this embodiment, specifically, the dielectric layer 105 is formed on the surface of the first stop layer 104 , and the top surface of the dielectric layer 105 is higher than the top surface of the first stop layer 104 .

[0083] In this embodiment, the material of the dielectric layer 105 is silicon oxide; in other embodiments, the material of the dielectric layer 105 includes one or more of silicon nitride, silicon oxynitride, silicon nitride carbon or silicon nitride carbon oxide.

[0084] In this embodiment, the process for forming the dielectric layer 105 is a chemical vapor deposition process.

[0085] refer to Figure 8 , the dielectric layer 105, the second spacer material layer 140 and the first spacer material layer 120 are planarized until the top surface of the dummy gate structure 110 is exposed, and a first spacer layer 121 and a second spacer layer 141 are formed on the sidewall of the dummy gate structure 110, and the sacrificial layer 131 is located between the first spacer layer 121 and the second spacer layer 141.

[0086] In this embodiment, the planarization process is a chemical mechanical polishing process.

[0087] In this embodiment, a chemical mechanical polishing process is also used to remove the first stop layer 104 and the mask layer 112 on the top of the dummy gate structure 110, so that the top surface of the dielectric layer 105 between the dummy gate structures 110 is flush with the top surface of the dummy gate structure 110.

[0088] In this embodiment, the top surfaces of the first sidewall layer 121 and the second sidewall layer 141 are flush with the top surface of the dummy gate structure 110, and the second sidewall layer 141 also covers the top surface of the sacrificial layer 131, which can protect the sacrificial layer 131 and prevent the sacrificial layer 131 from being damaged during the subsequent removal of the dummy gate structure 110.

[0089] refer to Fig. 9, the dummy gate structure 110 is removed to form a gate opening 150 , and the gate opening 150 is located in the dielectric layer 105 .

[0090] In this embodiment, the dummy gate layer 111 and the dummy gate dielectric layer are removed.

[0091] refer to Fig.10 , an initial gate structure 160 is formed in the gate opening 150 .

[0092] In this embodiment, the initial gate structure 160 includes: a gate dielectric layer (not shown) and a gate electrode layer 161 located on the surface of the gate dielectric layer.

[0093] In this embodiment, the gate dielectric layer is a high-k dielectric layer, and the material of the high-k dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0094] In this embodiment, the gate electrode layer 161 is metal, and the metal includes tungsten, copper, aluminum and other materials.

[0095] refer to Fig.11 , the initial gate structure 160 , the first spacer layer 121 , and the second spacer layer 141 are planarized until the top surface of the sacrificial layer 131 is exposed to form a gate structure 170 .

[0096] In this embodiment, the dielectric layer 105 and the first stop layer 104 are planarized.

[0097] In this embodiment, the planarization process is a chemical mechanical polishing process.

[0098] In this embodiment, the initial gate structure 160 is planarized to expose the top surface of the sacrificial layer 131. On the one hand, this provides conditions for the subsequent removal of the sacrificial layer 131. On the other hand, taking the height of the sacrificial layer 131 as the standard is beneficial to controlling the height of the finally formed gate structure 170, thereby enhancing the uniformity of the height of the gate structure 170.

[0099] refer to Fig.12 , the sacrificial layer 131 is removed, and a gap layer 180 is formed between the first spacer layer 121 and the second spacer layer 141 .

[0100] In this embodiment, the void layer 180 is used to form an "air side wall", and the side wall on the side wall of the gate structure 170 includes a first side wall layer 121, an "air side wall" formed by the void layer 180, a second side wall layer 141 and a first stop layer 104. A part of the side wall traditionally formed by materials such as silicon nitride or silicon oxide is replaced by air. Since the dielectric constant of air is very small, the dielectric constant of the side wall including the "air side wall" is also reduced, thereby reducing the parasitic capacitance of the semiconductor device, reducing the delay and switching state power consumption, which is beneficial to improving the performance of the semiconductor structure.

[0101] In this embodiment, the process of removing the sacrificial layer 131 is a dry etching process; in other embodiments, a wet etching process may be used to remove the sacrificial layer 131 .

[0102] refer to Fig.13 In this embodiment, after the gap layer 180 is formed, it also includes: forming a second stop layer 106 on the surface of the dielectric layer 105 , the first spacer layer 121 , the second spacer layer 131 and the gate structure 170 .

[0103] In this embodiment, when etching the conductive plug vias on the gate structure 170 , the second stop layer 106 makes the conductive plug vias on the gate structure stop on the second stop layer 106 , and the first stop layer 104 can protect the underlying dielectric layer 105 and the gate structure 170 from being damaged.

[0104] In this embodiment, the material of the second stop layer 106 is silicon nitride; in other embodiments, the material of the second stop layer 106 may also be carbon-doped silicon nitride.

[0105] In this embodiment, the process of forming the second stop layer 106 is a chemical vapor deposition process.

[0106] In this embodiment, the second stop layer 106 cannot be formed using a process with good filling performance such as an atomic layer deposition process, so as to prevent the second stop layer 106 from filling into the gap layer 180, destroying the "air side wall" and weakening the effect of reducing parasitic capacitance.

[0107] Correspondingly, an embodiment of the present invention further provides a semiconductor structure.

[0108] refer to Fig.13The semiconductor structure includes: a substrate 100, on which a gate structure 170 is provided; a first spacer layer 121, located on the sidewall of the gate structure 170, and the top surface of the first spacer layer 121 is flush with the top surface of the gate structure 170; a second spacer layer 141, located on the substrate 100 on both sides of the gate structure 170, and the top surface of the second spacer layer 141 is flush with the top surface of the gate structure 170, and a gap layer 180 is provided between the second spacer layer 141 and the first spacer layer 121.

[0109] In this embodiment, the side walls on both sides of the gate structure 170 include a first side wall layer 121, an "air side wall" formed by a gap layer 180, and a second side wall layer 141. The "air side wall" replaces a portion of the side walls formed by traditional silicon nitride, silicon oxide and other materials. Since the dielectric constant of air is very small, the dielectric constant of the side walls on both sides of the gate structure is effectively reduced, thereby reducing the parasitic capacitance of the semiconductor device, which is beneficial to improving the performance of the semiconductor structure.

[0110] In this embodiment, the base 100 includes a substrate 101 and a fin 102 located on the substrate 101 .

[0111] In this embodiment, the thickness of the first spacer layer 121 is 2-10 nm.

[0112] In this embodiment, the thickness of the second spacer layer 141 is 2-10 nm.

[0113] In this embodiment, the thickness of the gap layer 180 is 2-10 nm.

[0114] In this embodiment, the material of the first side wall layer 121 is silicon nitride; in other embodiments, the material of the first side wall layer 121 can also be one or more combinations of materials such as silicon oxide (SiO2), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0115] In this embodiment, the material of the second side wall layer 141 is silicon nitride; in other embodiments, the material of the second side wall layer 141 can also be one or more combinations of materials such as silicon oxide (SiO2), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0116] Continue to refer Fig.13In this embodiment, the semiconductor structure further includes: a dielectric layer 105 located on the substrate 100 , and a top surface of the dielectric layer 105 is flush with a top surface of the gate structure 170 .

[0117] In this embodiment, it further includes: a source-drain doping layer 103 located in the substrate 100 on both sides of the gate structure 170 .

[0118] In this embodiment, the structure further includes: a first stop layer 104 located on the source / drain doped layer 103 and on the sidewall of the second spacer layer 141 .

[0119] In this embodiment, the structure further includes: a second stop layer 106 located on the surfaces of the dielectric layer 105 , the first stop layer 104 , the second spacer layer 141 , the first spacer layer 121 and the gate structure 170 .

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein a gate structure is formed on the substrate, wherein the gate structure is obtained by removing the dummy gate structure, and a height of the gate structure is lower than a height of the dummy gate structure; A first spacer layer, located on the sidewall of the gate structure, wherein a top surface of the first spacer layer is flush with a top surface of the gate structure; A second sidewall layer is located on the substrate on both sides of the gate structure, the top surface of the second sidewall layer is flush with the top surface of the gate structure, and there is a gap layer between the second sidewall layer and the first sidewall layer, the gap layer is obtained by removing the sacrificial layer on the side wall of the first sidewall layer, and the top surface of the sacrificial layer is lower than the top surface of the dummy gate structure.

2. The semiconductor structure according to claim 1, wherein: Also includes: A dielectric layer is located on the substrate, and a top surface of the dielectric layer is flush with a top surface of the gate structure.

3. The semiconductor structure according to claim 1, wherein: Also includes: The source-drain doping layer is located in the substrate at both sides of the gate structure.

4. The semiconductor structure according to claim 3, characterized in that Also includes: The first stop layer is located on the source / drain doped layer and on the sidewall of the second spacer layer.

5. The semiconductor structure according to claim 2, wherein: Also includes: The second stop layer is located on the dielectric layer, the second spacer layer, the first spacer layer and the surface of the gate structure.

6. The semiconductor structure according to claim 1, wherein: The material of the first spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxide or silicon carbon boron nitride.

7. The semiconductor structure according to claim 1, wherein: The material of the second spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxide or silicon carbon boron nitride.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a dummy gate structure is formed; Forming a first spacer layer, a sacrificial layer, and a second spacer layer on the sidewall of the dummy gate structure, wherein the sacrificial layer is located between the first spacer layer and the second spacer layer, and the top surfaces of the first spacer layer and the second spacer layer are flush with the top surface of the dummy gate structure, and the top surface of the sacrificial layer is lower than the top surface of the dummy gate structure; removing the dummy gate structure to form a gate opening; forming an initial gate structure within the gate opening; performing a planarization process on the initial gate structure, the first spacer layer, and the second spacer layer until the top surface of the sacrificial layer is exposed to form a gate structure; The sacrificial layer is removed to form a gap layer between the first spacer layer and the second spacer layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming a first spacer layer, a sacrificial layer and a second spacer layer on the sidewall of the dummy gate structure comprises: Forming a first spacer material layer on the substrate, the top and the sidewall of the dummy gate structure; forming a sacrificial material layer on the surface of the first spacer material layer; Etching the sacrificial material layer until the top surface of the sacrificial material layer is lower than the top surface of the dummy gate structure, and forming a sacrificial layer on the sidewall surface of the first spacer material layer; forming a second spacer material layer on the substrate, the sacrificial layer and the first spacer material layer; forming a dielectric layer on the substrate, wherein a top surface of the dielectric layer is higher than a top surface of the second spacer material layer; The dielectric layer, the second spacer material layer and the first spacer material layer are planarized until the top surface of the dummy gate structure is exposed, and a first spacer layer and a second spacer layer are formed on the sidewall of the dummy gate structure, and the sacrificial layer is located between the first spacer layer and the second spacer layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of etching the sacrificial material layer is a plasma dry etching process, and the process parameters of the plasma dry etching process include: the etching atmosphere includes NF3 and H2, and the bias voltage is 50~200V.

11. The method for forming a semiconductor structure according to claim 9, wherein: After forming the second spacer material layer and before forming the dielectric layer, the method further includes: forming source-drain doping layers in the substrate at both sides of the dummy gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the source-drain doped layer and before forming the dielectric layer, the method further includes: forming a first stop layer on the source-drain doped layer, wherein the first stop layer also covers the surface of the second spacer material layer.

13. The method for forming a semiconductor structure according to claim 9, wherein: After removing the sacrificial layer and forming a gap layer between the first spacer layer and the second spacer layer, the method further includes: forming a second stop layer on the dielectric layer, the first spacer layer, the second spacer layer and the surface of the gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method of forming the second stop layer includes a chemical vapor deposition method.

15. The method for forming a semiconductor structure according to claim 8, wherein: The material of the first spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxide or silicon carbon boron nitride.

16. The method for forming a semiconductor structure according to claim 8, wherein: The material of the sacrificial layer includes amorphous silicon.

17. The method for forming a semiconductor structure according to claim 8, wherein: The material of the second spacer layer includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxide or silicon carbon boron nitride.

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