Clock generation circuit and interleaving sampling device
By generating clock signals with a 90° phase difference using a phase-locked loop clock unit and a clock distributor, the problem of sampling time interval mismatch among multiple ADC chips is solved, enabling synchronous interleaved sampling of four ADCs and improving sampling accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 迅芯微电子(苏州)股份有限公司
- Filing Date
- 2022-01-25
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies struggle to accurately control the clock phase of multiple ADC chips, leading to a mismatch in the sampling time intervals between the chips and limiting the sampling accuracy and resolution of the ADC.
A clock generation circuit consisting of a phase-locked loop clock unit, a phase-locked loop, and a clock distributor is used to generate and distribute differential signals to ensure that the clock signals of the four analog-to-digital converter chips have a phase difference of 90°, thereby achieving interleaved sampling of the four ADCs.
The sampling accuracy of the four-channel analog-to-digital converter chip was improved, sampling time interval mismatch was avoided, and synchronous sampling of the four ADCs was ensured.
Smart Images
Figure CN114531156B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of signal sampling technology, specifically to a clock generation circuit and an interleaving sampling device. Background Technology
[0002] High-speed analog-to-digital converters (ADCs) have a wide range of applications and promising prospects. Currently, ADCs are a very hot field.
[0003] The development speed of ADCs is limited by the constraints of semiconductor processing technology and technological levels. Based on the current state of CMOS technology, the minimum size of the process is constantly decreasing, the power supply voltage is continuously lowering, and the allowable amplitude of the input signal is becoming smaller, leading to a decrease in the signal-to-noise ratio. Resolution and sampling frequency are two important performance indicators of ADCs; the speed and accuracy of ADCs are contradictory, limiting the development of ADCs towards high speed and high accuracy. Increasing the sampling rate of an ADC inevitably reduces its resolution. Therefore, signal interleaving sampling can be achieved by controlling the clocks of multiple ADC chips. For example, when interleaving sampling is performed using two ADC chips, the differential clock signal can be directly split into two separate clock signals, thus ensuring a 180° phase difference between the two ADC chips.
[0004] In the above scheme, when multiple ADC chips are needed to interleave and sample signals, it is difficult to accurately control the clock phase of the multiple ADC chips. Summary of the Invention
[0005] This application provides a clock generation circuit and an interleaved sampling device, which can accurately control the clock phase of multiple ADC chips. The technical solution is as follows.
[0006] On the one hand, this application provides a clock generating circuit, which includes a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor, and a third clock distributor;
[0007] The phase-locked loop clock unit is connected to the first clock distributor to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal, and distribute them to the first phase-locked loop and the second phase-locked loop.
[0008] The first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to the second clock distributor so that the second clock distributor can convert the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180°.
[0009] The second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to a third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180°.
[0010] The phase difference between the second differential signal and the third differential signal is 90°;
[0011] The third, fourth, fifth, and sixth clock signals are respectively connected to the four analog-to-digital converter chips to control the interleaving sampling of the four analog-to-digital converter chips.
[0012] In one possible implementation, the phase-locked loop clock unit is further configured to send a reference clock to the first phase-locked loop and the second phase-locked loop respectively, so as to control the operating state of the first phase-locked loop and the second phase-locked loop.
[0013] In one possible implementation, the phase-locked loop clock unit includes a clock chip and a target phase-locked loop;
[0014] The clock chip transmits the generated reference clock to the target phase-locked loop, and the target phase-locked loop generates the first differential signal based on the reference clock.
[0015] In one possible implementation, the first phase-locked loop further includes a first D flip-flop and a first internal oscillator; the second phase-locked loop further includes a second D flip-flop and a second internal oscillator.
[0016] The first phase-locked loop converts the first clock signal into a second differential signal, including:
[0017] After the first internal oscillator generates a first candidate differential signal according to the first clock signal, it transmits the first candidate differential signal to the first D flip-flop to output the second differential signal.
[0018] The second phase-locked loop converts the second clock signal into a third differential signal, including:
[0019] After the second internal oscillator generates the second candidate differential signal according to the second clock signal, it transmits the second candidate differential signal to the second D flip-flop through an NOT gate to output the third differential signal.
[0020] In one possible implementation, the first phase-locked loop includes a third internal oscillator, a third D flip-flop, and a fourth D flip-flop; the second phase-locked loop further includes a fourth internal oscillator, a fifth D flip-flop, and a sixth D flip-flop.
[0021] The third internal oscillator is connected to the third D flip-flop;
[0022] The third internal oscillator is connected to the fourth D flip-flop via a NOT gate;
[0023] The fourth internal oscillator is connected to the fifth D flip-flop;
[0024] The fourth internal oscillator is connected to the fifth D flip-flop via a NOT gate;
[0025] The first phase-locked loop and the second phase-locked loop also include a chip register; the chip register is used to control the conduction state of each D flip-flop according to the data in the chip register.
[0026] On the other hand, this application also provides an interleaving sampling device, which includes any of the clock generation circuits of the above-mentioned optional methods;
[0027] The interleaved sampling device also includes sample-and-hold chips; each sample-and-hold chip is connected to the four analog-to-digital converter chip to process the collected data and send it to the four analog-to-digital converter chip.
[0028] In one possible implementation, the third, fourth, fifth, and sixth clock signals are respectively connected to the sample-and-hold chip to which the four analog-to-digital converter chips are connected, so as to control the data processing of the sample-and-hold chip.
[0029] In one possible implementation, the interleaving sampling device further includes individual delay chips;
[0030] The third, fourth, fifth, and sixth clock signals are processed by delay chips and then transmitted to the four analog-to-digital converter chips. The third, fourth, fifth, and sixth clock signals are processed by delay chips and then transmitted to sample-and-hold chips connected to the four analog-to-digital converter chips.
[0031] In one possible implementation, the interleaving sampling device further includes a sampling control chip; the sampling control chip is connected to the delay chip via a digital-to-analog converter chip.
[0032] In one possible implementation, the sampling control chip further includes an interleaving calibration module, which is used to calibrate the digital signals generated by the four analog-to-digital converter chips to obtain the target sampling result.
[0033] The technical solution provided in this application may include the following beneficial effects:
[0034] When interleaved sampling is required through four analog-to-digital converter (ADC) chips, the phase-locked loop (PLL) clock unit in the circuit generates a first differential signal, which is then transmitted to a clock distributor. The clock distributor splits the first differential signal into a first clock signal and a second clock signal with a phase difference of 180°. The first and second clock signals are then processed by the first and second PLLs respectively to generate a second and a third differential signal with a phase difference of 90°. These are then split into clock signals with a phase difference of 180° by the second and third clock distributors. The resulting third, fourth, fifth, and sixth clock signals have a 90° phase difference. Therefore, the interleaved sampling of the four ADC chips can be accurately controlled by the third, fourth, fifth, and sixth clock signals, avoiding sampling time interval mismatch between multiple ADC chips and improving the sampling accuracy when the four ADC chips perform interleaved sampling. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0036] Figure 1 This is a schematic diagram of a clock generating circuit according to an exemplary embodiment of this application.
[0037] Figure 2 A schematic diagram of a clock link according to an embodiment of this application is shown.
[0038] Figure 3 This is a schematic diagram of the structure of an interleaved sampling device according to an exemplary embodiment.
[0039] Figure 4 A schematic diagram of a phase-locked loop frequency output according to an embodiment of this application is shown.
[0040] Figure 5 This illustration shows another schematic diagram of the frequency output of a phase-locked loop according to an embodiment of this application.
[0041] Figure 6 A schematic diagram of a variable delay limit structure according to an embodiment of this application is shown. Detailed Implementation
[0042] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] It should be understood that the term "instruction" mentioned in the embodiments of this application can be a direct instruction, an indirect instruction, or an indication of a relationship. For example, A instructing B can mean that A directly instructs B, such as B being able to obtain information through A; it can also mean that A indirectly instructs B, such as A instructing C, so B can obtain information through C; or it can mean that there is a relationship between A and B.
[0044] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.
[0045] In the embodiments of this application, "predefined" can be achieved by pre-storing corresponding codes, tables or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices). This application does not limit the specific implementation method.
[0046] Figure 1 This is a schematic diagram illustrating the structure of a clock generating circuit according to an exemplary embodiment of this application. Figure 1 As shown, the clock generating circuit includes a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor, and a third clock distributor.
[0047] The phase-locked loop clock unit is connected to the first clock distributor to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal, and distribute them to the first phase-locked loop and the second phase-locked loop.
[0048] The first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to the second clock distributor, so that the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180°.
[0049] The second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to the third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180°.
[0050] The phase difference between the second differential signal and the third differential signal is 90°;
[0051] The third, fourth, fifth, and sixth clock signals are used to control the interleaved sampling of the four analog-to-digital converter (ADC).
[0052] To achieve interleaved sampling by an ADC, a clock link must first be constructed (i.e., as shown in the example). Figure 1 The clock generation circuit shown provides a sampling clock to four ADC chips. Considering the synchronization and equal-interval sampling of the four ADCs, a phase-locked loop and a crystal oscillator are needed to jointly generate a clock signal such as 3GHz. Currently, traditional ADC boards have two interleaved ADCs; only the clock chip needs to generate a differential signal to obtain a sampling clock with a 180° phase difference. However, this application proposes a method for constructing a four-way interleaved clock link.
[0053] Please refer to Figure 2 This illustrates a clock link schematic diagram related to an embodiment of this application. Figure 2 As shown, the clock distributor is a chip used for clock distribution. The first clock distributor splits the differential signal generated by the PLL 1 chip (i.e., the PLL clock unit) into two paths and distributes them to the two PLL 2 chips (i.e., ... Figure 1 The first and second phase-locked loops (PLLs) in the system provide clock signals. The clock generated by PLL 1 is derived from a reference clock; the clock chip provides a reference clock to PLL 1 to generate the necessary clock signals. The 3GHz differential signal output from the first PLL 2 chip (i.e., the first PLL) is divided into two signals with a 180-degree phase difference by clock buffer 1 (i.e., the second clock distributor). These two signals provide sampling clocks for the first and third ADCs (i.e., ADC0 and ADC3), respectively. The second PLL 2 chip (i.e., the second PLL) can generate a signal with a 90-degree phase difference relative to the output.
[0054] At this point, the differential signal generated by PLL 2 is also passed through the clock buffer (i.e., the third clock distributor) to generate two signals with a 180° phase difference, namely 90° and 270° phase, which are then sent to the second and fourth ADCs (i.e., ADC1 and ADC3). This enables the four ADCs to generate a 90° sampling clock phase, allowing the four ADCs to perform time-interleaved alternating sampling, achieving the initial design objective.
[0055] In one possible implementation of this application, the phase-locked loop clock unit is composed of a phase-locked loop circuit and a clock chip. After the clock chip generates a reference clock, it generates a first differential signal through the phase-locked loop circuit.
[0056] After the phase-locked loop circuit generates the first differential signal, it can input this first differential signal to the first clock distributor (i.e., clock buffer). The first clock distributor can distribute the first differential signal, for example, by converting it to two single-ended circuits via a PN converter, thus generating a first clock signal and a second clock signal. At this point, the phase difference between the first clock signal and the second clock signal is 180°. Assuming that the phase of the first clock signal is 0° at a specified time, then the phase of the second clock signal will be 180° at the same specified time.
[0057] At this point, the first clock signal is transmitted to the first phase-locked loop (PLL). The first PLL generates a second differential signal based on the first clock signal and transmits the second differential signal to the second clock distributor. The second clock distributor then converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180°. Now, assuming that the phase of the third clock signal is 0° at a specified time, the phase of the fourth time signal is 180° at the specified time.
[0058] At this time, the second clock signal is transmitted to the second phase-locked loop. The second phase-locked loop generates a third differential signal based on the first clock signal, and the phase difference between the third differential signal and the second differential signal is 90°. At this time, the third differential signal is converted into a fifth clock signal and a sixth clock signal with a phase difference of 180°. That is to say, the phase of the fifth clock signal at a specified time is 90°, and the phase of the sixth clock signal at a specified time is 270°, or the phase of the fifth clock signal at a specified time is 270°, and the phase of the sixth clock signal at a specified time is 90°.
[0059] Therefore, the third, fourth, fifth, and sixth clock signals constitute four clock signals with a 90° phase difference. By controlling the four analog-to-digital converter chips through these four clock signals, the four analog-to-digital converter chips can have the same sampling time and sampling interval, avoiding the mismatch of sampling intervals between multiple ADC chips and improving the sampling accuracy when the four analog-to-digital converter chips perform interleaved sampling.
[0060] In summary, when interleaved sampling is required through four analog-to-digital converters (ADCs), the phase-locked loop (PLL) clock unit in the circuit generates a first differential signal, which is then transmitted to a clock distributor. The clock distributor splits the first differential signal into a first clock signal and a second clock signal with a phase difference of 180°. These two clock signals are then processed by the first and second PLLs respectively, generating a second differential signal and a third differential signal with a phase difference of 90°. These are then further split by the second and third clock distributors into clock signals with a phase difference of 180°. The resulting third, fourth, fifth, and sixth clock signals have a 90° phase difference. Therefore, the interleaved sampling of the four ADCs can be accurately controlled using these clock signals, avoiding sampling time interval mismatch between multiple ADC chips and improving the sampling accuracy when the four ADCs perform interleaved sampling.
[0061] Figure 3 This is a schematic diagram illustrating the structure of an interleaved sampling device according to an exemplary embodiment. Figure 3 As shown, the interleaved sampling device includes a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor, and a third clock distributor;
[0062] The phase-locked loop clock unit includes a clock chip and a target phase-locked loop;
[0063] The clock chip transmits the generated reference clock to the target phase-locked loop, which generates a first differential signal based on the reference clock.
[0064] The phase-locked loop clock unit is connected to the first clock distributor to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal, and distribute them to the first phase-locked loop and the second phase-locked loop.
[0065] The first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to the second clock distributor, so that the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180°.
[0066] The second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to the third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180°.
[0067] The phase difference between the second differential signal and the third differential signal is 90°.
[0068] The principle of the above clock generation circuit is as follows: Figure 1 The principle of the clock generating circuit shown is similar, and will not be described again here.
[0069] In the embodiments of this application, such as Figure 3 As shown, the interleaved sampling device also includes the four analog-to-digital converter chips; the four analog-to-digital converter chips are respectively connected to the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal.
[0070] In order to precisely control the output signals of the first phase-locked loop and the second phase-locked loop to have a 90° phase difference, in one possible implementation, the first phase-locked loop also includes a first D flip-flop and a first internal oscillator; the second phase-locked loop also includes a second D flip-flop and a second internal oscillator.
[0071] After the first internal oscillator generates a first candidate differential signal according to the first clock signal, it transmits the first candidate differential signal to the first D flip-flop to output the second differential signal.
[0072] After the second internal oscillator generates the second candidate differential signal according to the second clock signal, it transmits the second candidate differential signal to the second D flip-flop through an NOT gate to output the third differential signal.
[0073] The first and second phase-locked loops also contain phase detectors, filters, frequency dividers, etc. (not shown in the figure) to control the internal oscillator to generate a signal of the corresponding frequency according to the input frequency.
[0074] Figure 4 A schematic diagram of a phase-locked loop frequency output according to an embodiment of this application is shown. Figure 4 As shown, the first internal oscillator (not shown) in the first phase-locked loop 401 can be connected to the first D flip-flop. Assuming the first internal oscillator of the first phase-locked loop outputs a clock signal with a frequency of 2f, the clock signal is divided by the first D flip-flop to a frequency of f. Furthermore, the second internal oscillator (not shown) of the second phase-locked loop 402 is connected to the second D flip-flop via an NOT gate. When the second internal oscillator of the second phase-locked loop outputs a clock signal with a frequency of 2f, the signal generated by the second phase-locked loop is inverted by the NOT gate to generate a 180° phase difference, which is then divided by the first D flip-flop, thus transforming the 180° phase difference into 90°.
[0075] In this embodiment, the phase difference between the signals received by the first phase-locked loop and the second phase-locked loop is 180°, therefore, after... Figure 3After the first phase-locked loop and the second phase-locked loop in the structure shown process the signal, the phase difference between the signals output by the first phase-locked loop and the second phase-locked loop should be 90° or 270°. That is, the first phase-locked loop leads the second phase-locked loop by 90° or lags the second phase-locked loop by 90°, so that the first phase-locked loop and the second phase-locked loop maintain a phase difference of 90°.
[0076] In another possible implementation, the first phase-locked loop includes a third internal oscillator, a third D flip-flop, and a fourth D flip-flop; the second phase-locked loop also includes a fourth internal oscillator, a fifth D flip-flop, and a sixth D flip-flop.
[0077] The third internal oscillator is connected to the third D flip-flop;
[0078] The third internal oscillator is connected to the fourth D flip-flop via a NOT gate;
[0079] The fourth internal oscillator is connected to the fifth D flip-flop;
[0080] The fourth internal oscillator is connected to the fifth D flip-flop via a NOT gate;
[0081] The first phase-locked loop and the second phase-locked loop also include a chip register; the chip register is used to control the conduction state of each D flip-flop according to the data in the chip register.
[0082] Figure 5 A schematic diagram of a phase-locked loop frequency output according to an embodiment of this application is shown. Figure 5 As shown, before generating a differential signal through the first phase-locked loop and the second phase-locked loop, the chip registers inside the first phase-locked loop and the second phase-locked loop can be configured to control one of the first phase-locked loops to be directly divided by a D flip-flop, while the other is divided by a D flip-flop after passing through an NOT gate, so that the output of phase-locked loop 2 and the input of phase-locked loop 1 have a 90-degree phase difference.
[0083] In one possible implementation, the phase-locked loop clock unit is further configured to send a reference clock to the first phase-locked loop and the second phase-locked loop respectively, so as to control the operating state of the first phase-locked loop and the second phase-locked loop.
[0084] The reference clock is also a crucial component of the clock link, ensuring the synchronous operation of the ADCs. The PLL clock unit generates two sysrefs (i.e., reference clocks) and sends them to the two PLL2 chips (i.e., the first PLL and the second PLL). The PLL2 chip only generates the corresponding phase synchronization signal for the ADCs upon receiving the sysref reference clock from the PLL clock unit. Thus, when the phase synchronization clock from the PLL2 chip is transmitted to the ADC chips, the four ADCs begin to sample alternately, ensuring synchronization among the four ADCs.
[0085] In this embodiment of the application, the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively connected to the four-channel analog-to-digital converter chip to control the interleaving sampling of the four-channel analog-to-digital converter chip.
[0086] In one possible implementation of the embodiments of this application, such as Figure 3 As shown, the interleaved sampling device also includes sample-and-hold chips (TH0 to TH3); each sample-and-hold chip is connected to the four analog-to-digital converter chips to process the collected data and send it to the four analog-to-digital converter chips.
[0087] In the data acquisition stage of an ADC, the sample-and-hold circuit is typically located at the very beginning of the ADC and is a crucial component of the system. The sample-and-hold circuit is used to sample and hold the input signal. Because any analog-to-digital converter requires a short period of time to complete quantization and encoding operations, and the analog signal is still changing during this short period, errors will occur. The accuracy of the signal sampled by the sample-and-hold circuit determines the maximum accuracy and maximum resolution of the ADC. In one possible implementation of this application, to adapt to the ADC's accuracy and sampling speed, the selected sample-and-hold chip is fabricated using SiGe-BiCMOS technology, possessing an 8GHz analog signal bandwidth and a maximum sampling rate supporting 4Gs / s, meeting the ADC's 3Gs / s sampling rate requirement.
[0088] The third, fourth, fifth, and sixth clock signals are respectively connected to the sample-and-hold chip connected to the four analog-to-digital converter chips to control the data processing of the sample-and-hold chip.
[0089] In one possible implementation, the interleaved sampling device also includes individual delay chips;
[0090] The third, fourth, fifth, and sixth clock signals are processed by delay chips and then transmitted to the four analog-to-digital converter chips. The third, fourth, fifth, and sixth clock signals are processed by delay chips and then transmitted to sample-and-hold chips connected to the four analog-to-digital converter chips.
[0091] In one possible implementation, the interleaved sampling device further includes a sampling control chip; the sampling control chip is connected to the delay chip via a digital-to-analog converter chip.
[0092] Ideally, time interleaving requires the four ADCs to sample evenly and alternately, with identical sampling clock intervals between adjacent channels. In actual time interleaving, the asymmetry between the sampling clock division and the driving circuit causes sampling timing deviations, which also affect the quantization results. In reality, the four ADCs do not sample exactly with a 90° phase difference, resulting in sampling time mismatch; therefore, a function to adjust the phase of the four ADCs is required. Please refer to [reference needed]. Figure 6 The diagram illustrates a variable delay time limit structure according to an embodiment of this application. Figure 6 As shown, a delay is generated by connecting a digital-to-analog converter (DAC) and a delay chip to fine-tune the phase of the ADC. A digital signal is sent from the FPGA to the DAC chip, allowing the DAC to generate an adjustable voltage within a certain range. The wideband delay chip has a delay adjustment range of 0-70ps, and the delay time changes with the input voltage magnitude; the delay control is linear with respect to the input voltage. A clock signal generated by a clock buffer is input to the delay chip, and after the voltage-controlled delay, it enters the next clock buffer. Two clocks are allocated to the sample-and-hold chip and the ADC respectively. In this way, all four ADCs have their own controllable delay function.
[0093] In one possible implementation, the sampling control chip further includes an interleaving calibration module, which is used to calibrate the digital signals generated by the four analog-to-digital converter chips to obtain the target sampling result.
[0094] In this embodiment of the application, time-interleaving technology is used to sample data during the data acquisition phase. The principle of time-interleaving technology is that multiple sub-channels are sampled alternately while maintaining the conversion performance of a single channel.
[0095] By overcoming the limitations of chip circuit design and manufacturing processes through time interleaving, the sampling rate can be greatly improved. However, time interleaving technology also has some drawbacks, such as offset mismatch, gain mismatch, and sampling timing deviation. These mismatches can seriously affect the performance of the ADC board, and the desired ADC performance can only be obtained by calibrating these errors to a certain range.
[0096] In one possible implementation of this application, the FPGA performs calibration via a calibration module after ADC data acquisition. The data sampled from the ADC passes through the JESD204B interface and is then calibrated via an interleaving calibration module. The calibrated data is stored in the BRAM. Calibration by the calibration module can eliminate the aforementioned errors to a certain extent, significantly improving the performance of the ADC board.
[0097] In summary, when interleaved sampling is required through four analog-to-digital converters (ADCs), the phase-locked loop (PLL) clock unit in the circuit generates a first differential signal, which is then transmitted to a clock distributor. The clock distributor splits the first differential signal into a first clock signal and a second clock signal with a phase difference of 180°. These two clock signals are then processed by the first and second PLLs respectively, generating a second differential signal and a third differential signal with a phase difference of 90°. These are then further split by the second and third clock distributors into clock signals with a phase difference of 180°. The resulting third, fourth, fifth, and sixth clock signals have a 90° phase difference. Therefore, the interleaved sampling of the four ADCs can be accurately controlled using these clock signals, avoiding sampling time interval mismatch between multiple ADC chips and improving the sampling accuracy when the four ADCs perform interleaved sampling.
[0098] Furthermore, the device described in this application uses a sample-and-hold circuit, which ensures the sampling rate and accuracy of the acquired data. It generates four clock links with a 90-degree phase difference and enables synchronous, sequential, alternating sampling by the four ADCs. Each of the four sub-channels has a corresponding variable delay limit function, allowing fine-tuning of the sampling timing of the four ADCs to achieve the final sampling time calibration function. The ADC board also applies the time interleaving calibration technology from within the ADC chip to the board, achieving gain error calibration and sampling interval mismatch calibration between the four ADCs. After calibration, the performance of the ADC board will be significantly improved.
[0099] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0100] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A clock generating circuit, characterized in that, The clock generation circuit includes a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor, and a third clock distributor; The phase-locked loop clock unit is connected to the first clock distributor to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal, and distribute them to the first phase-locked loop and the second phase-locked loop. The first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to the second clock distributor so that the second clock distributor can convert the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180°. The second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to a third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180°. The phase difference between the second differential signal and the third differential signal is 90°; The third, fourth, fifth, and sixth clock signals are used to control the interleaving sampling of the four analog-to-digital converter chips.
2. The clock generating circuit according to claim 1, characterized in that, The phase-locked loop clock unit is also used to send a reference clock to the first phase-locked loop and the second phase-locked loop respectively, so as to control the working state of the first phase-locked loop and the second phase-locked loop.
3. The clock generating circuit according to claim 2, characterized in that, The phase-locked loop clock unit includes a clock chip and a target phase-locked loop; The clock chip transmits the generated reference clock to the target phase-locked loop, and the target phase-locked loop generates the first differential signal based on the reference clock.
4. The clock generating circuit according to claim 3, characterized in that, The first phase-locked loop further includes a first D flip-flop and a first internal oscillator; the second phase-locked loop further includes a second D flip-flop and a second internal oscillator. The first phase-locked loop converts the first clock signal into a second differential signal, including: After the first internal oscillator generates a first candidate differential signal according to the first clock signal, it transmits the first candidate differential signal to the first D flip-flop to output the second differential signal. The second phase-locked loop converts the second clock signal into a third differential signal, including: After the second internal oscillator generates the second candidate differential signal according to the second clock signal, it transmits the second candidate differential signal to the second D flip-flop through an NOT gate to output the third differential signal.
5. The clock generating circuit according to claim 3, characterized in that, The first phase-locked loop includes a third internal oscillator, a third D flip-flop, and a fourth D flip-flop; the second phase-locked loop also includes a fourth internal oscillator, a fifth D flip-flop, and a sixth D flip-flop. The third internal oscillator is connected to the third D flip-flop; The third internal oscillator is connected to the fourth D flip-flop via a NOT gate; The fourth internal oscillator is connected to the fifth D flip-flop; The fourth internal oscillator is connected to the fifth D flip-flop via a NOT gate; The first phase-locked loop and the second phase-locked loop also include a chip register; the chip register is used to control the conduction state of each D flip-flop according to the data in the chip register.
6. An interleaved sampling device, characterized in that, The interleaving sampling device includes a clock generation circuit as described in any one of claims 1 to 5; The interleaving sampling device also includes the four analog-to-digital converter chips; the four analog-to-digital converter chips are respectively connected to the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal; The interleaved sampling device also includes sample-and-hold chips; each sample-and-hold chip is connected to the four analog-to-digital converter chip to process the collected data and send it to the four analog-to-digital converter chip.
7. The interleaved sampling device according to claim 6, characterized in that, The third, fourth, fifth, and sixth clock signals are respectively connected to the sample-and-hold chip connected to the four analog-to-digital converter chips to control the data processing of the sample-and-hold chip.
8. The interleaved sampling device according to claim 7, characterized in that, The interleaved sampling device also includes various delay chips; The third, fourth, fifth, and sixth clock signals are processed by delay chips and then transmitted to the four analog-to-digital converter chips. The third, fourth, fifth, and sixth clock signals are processed by delay chips and then transmitted to sample-and-hold chips connected to the four analog-to-digital converter chips.
9. The interleaved sampling device according to claim 8, characterized in that, The interleaved sampling device also includes a sampling control chip; the sampling control chip is connected to the delay chip through a digital-to-analog converter chip.
10. The interleaved sampling device according to claim 9, characterized in that, The sampling control chip also includes an interleaving calibration module, which is used to calibrate the digital signals generated by the four analog-to-digital converter chips to obtain the target sampling result.