Clock gating cell, integrated circuit, and latch circuit

Abstract

The present application relates to clock gating cells, integrated circuits, and latch circuits. A clock gating cell includes a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node, a second circuit configured to receive the first signal and generate an inverted first signal, a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, connect to the first circuit through the first node to generate the first signal, and generate an inverted output clock signal through a second node, and a fourth circuit configured to receive the first signal, connect to the third circuit through the second node to generate the inverted output clock signal, and generate the output clock signal, wherein the third circuit includes a pair of transistors that receive the input clock signal.

Description

Technical Field

[0001] The present invention relates to a clock gating unit, and more specifically, to a clock gating unit having low power consumption and an integrated circuit including the clock gating unit. Background Technology

[0002] In clock synchronization systems that include clock networks, clock gating units can be used as digital circuits to provide clock signals. Because clock gating units selectively output clock signals in response to control signals, the power efficiency of the system can be increased through the operation of the clock gating units.

[0003] However, even when there is no clock signal output, the clock gating unit still consumes power due to the clock signal. Summary of the Invention

[0004] The present invention provides a clock gating unit for reducing power consumption and an integrated circuit including the clock gating unit, the clock gating unit including transistor pairs and receiving clock signals.

[0005] According to an exemplary embodiment of the present invention, a clock gating unit is provided, comprising: a first circuit configured to receive an enable signal and an inverted output clock signal, and to generate a first signal via a first node; a second circuit configured to receive the first signal and generate the inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, to be connected to the first circuit via a first node to generate the first signal, and to generate the inverted output clock signal via a second node; and a fourth circuit configured to receive the first signal, to be connected to the third circuit via a second node to generate the inverted output clock signal, and to generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

[0006] According to an exemplary embodiment of the present invention, an integrated circuit is provided, the integrated circuit including a clock gating unit for receiving at least one control signal and an input clock signal and generating an output clock signal, wherein the clock gating unit includes: a first circuit including a first functional circuit configured to generate a first signal through a first node based on the at least one control signal and a first keeper circuit configured to maintain a voltage level of the first signal; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit including a second functional circuit configured to generate the first signal through a first node based on at least one control signal, a second keeper circuit configured to maintain a voltage level of the first signal, a first charging circuit configured to generate an inverted output clock signal by charging a second node based on the first signal, and a discharging circuit configured to discharge the second node; and a fourth circuit including a second charging circuit configured to generate an inverted output clock signal by charging a second node based on the first signal, and the third circuit including a transistor pair for receiving the input clock signal.

[0007] According to an exemplary embodiment of the present invention, a latch circuit is provided, comprising: a first circuit configured to receive an inverted output clock signal and a data signal, and to generate a first signal via a first node; a second circuit configured to receive a data signal, an input clock signal, and an output signal, to be connected to the first circuit via a first node to generate the first signal, and to generate an inverted output clock signal via a second node; a third circuit configured to be connected to the second circuit via a second node to generate an inverted output clock signal; and a fourth circuit configured to receive the first signal and generate the output signal and the inverted output signal, wherein the second circuit includes a pair of transistors for receiving the input clock signal. Attached Figure Description

[0008] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating an example embodiment of an integrated circuit (IC) according to a concept of the present invention;

[0010] Figure 2 This is a logic diagram of a clock gating unit according to an exemplary embodiment of the present invention;

[0011] Figure 3A and Figure 3B This is a circuit diagram of a clock gating unit according to an exemplary embodiment of the present invention;

[0012] Figure 4This is a circuit diagram of a clock gating unit according to an exemplary embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram illustrating the operation of a clock gating unit according to an exemplary embodiment of the present invention;

[0014] Figure 6 This is a timing diagram used to describe the operation of a clock gating unit according to an exemplary embodiment of the present invention;

[0015] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A and Figure 11B This is a circuit diagram of a clock gating unit according to an exemplary embodiment of the present invention;

[0016] Figure 12 This is a schematic diagram illustrating the logic symbols of a latch circuit according to an exemplary embodiment of the present invention;

[0017] Figure 13 This is a block diagram illustrating a latch circuit according to an embodiment of the concept of the present invention;

[0018] Figure 14 and Figure 15 This is a circuit diagram of a latch circuit according to an exemplary embodiment of the present invention;

[0019] Figure 16A and Figure 16B This is a schematic diagram illustrating a partial layout of the clock gating unit and latch circuitry according to an exemplary embodiment of the present invention;

[0020] Figure 17 This is a schematic diagram illustrating an IC including a clock gating unit according to an embodiment of the present invention; and

[0021] Figure 18 This is a flowchart of a method for manufacturing an IC according to an exemplary embodiment of the present invention. Detailed Implementation

[0022] Figure 1 This is a schematic diagram illustrating an example embodiment of an integrated circuit (IC) according to a concept of the present invention.

[0023] refer to Figure 1The clock gating unit 10 can be included in IC 1 manufactured using a semiconductor process. The clock gating unit 10 can also be referred to as a clock gating circuit or an integrated clock gating (ICG) unit. In this specification, the term "clock gating" can refer to the operation of pausing or resuming a digital circuit by selectively providing an output clock signal to a functional block.

[0024] Clock gating unit 10 can receive an input clock signal CLK and an enable signal E, and generate an output clock signal ECK. Clock gating unit 10 can be set to an enabled or disabled state based on whether the enable signal E is present. For example, when the enable signal E is at a first logic level (e.g., logic low), clock gating unit 10 can be set to a disabled state. Clock gating unit 10 in the disabled state can generate a constant-level output clock signal ECK.

[0025] For example, when the enable signal E is at a second logic level (e.g., logic high), the clock gating unit 10 can be set to an enabled state. The clock gating unit 10 in the enabled state can generate an output clock signal ECK that switches according to the input clock signal CLK.

[0026] Clock gating unit 10 can generate an output clock signal ECK and provide the output clock signal ECK to function block 15. Function block 15 can refer to a digital circuit that operates in response to the negative or positive edge of the output clock signal ECK. For example, function block 15 can be a flip-flop triggered by a positive edge or a flip-flop triggered by a negative edge.

[0027] The clock gating unit 10 may include circuit elements for directly receiving the input clock signal CLK. Although Figure 1 A circuit element, such as A, is shown, but multiple circuit elements can be provided. As the number of circuit elements used to receive the input clock signal increases, the self-power consumption of the clock gating unit 10 may increase due to the increased capacitance caused by the input clock signal CLK.

[0028] According to this embodiment, the clock gating unit 10 can reduce the capacitance caused by the input clock signal CLK by reducing the number of circuit elements that directly receive the input clock signal CLK. Therefore, the power consumption of the clock gating unit 10 caused by the input clock signal CLK can be reduced, thus realizing a low-power clock gating unit.

[0029] Figure 2 This is a logic diagram of a clock gating unit according to an exemplary embodiment of the present invention.

[0030] refer to Figure 2 The clock gating unit 10 may include a first circuit 11, a first inverter 12, and a second circuit 13. Figure 2 The logic diagram can be implemented with various circuit configurations.

[0031] The first circuit 11 can receive an enable signal E, an input clock signal CLK, a first signal SIG1, an inverted first signal SIG1N, and an inverted output clock signal ECKN, and can be connected to an intermediate node N11. For example, the first signal SIG1 can be generated from the intermediate node N11. In other words, the first signal SIG1 can be a signal at the intermediate node N11.

[0032] For example, the first circuit 11 may include a first OR gate 111 that receives an input clock signal CLK and a first signal SIG1 and generates a first result signal R1; a first AND gate 112 that receives an inverted first signal SIG1N and the first result signal R1 and generates a second result signal R2; a second inverter 113 that generates an inverted enable signal EN through an inverted enable signal E; a second OR gate 114 that receives the inverted enable signal EN from the second inverter 113 and the second result signal R2 and generates a third result signal R3; and a first NAND gate 115 that receives the third result signal R3 and an inverted output clock signal ECKN and generates the first signal SIG1. The first inverter 12 can generate an inverted first signal SIG1N by inverting the first signal SIG1.

[0033] The second circuit 13 can receive the inverted enable signal EN, the inverted first signal SIG1N, the input clock signal CLK and the first signal SIG1, and generate the output clock signal ECK.

[0034] For example, the second circuit 13 may include a third OR gate 131 that receives an inverted enable signal EN and an inverted output clock signal ECKN and generates a fourth result signal R4; a second AND gate 132 that receives an inverted first signal SIG1N and a fourth result signal R4 and generates a fifth result signal R5; a fourth OR gate 133 that receives an input clock signal CLK and a fifth result signal R5 and generates a sixth result signal R6; a second NAND gate 134 that receives a first signal SIG1N and a sixth result signal R6 and generates an inverted output clock signal ECKN; and a third inverter 135 that generates the output clock signal ECK by inverting the inverted output clock signal ECKN.

[0035] exist Figure 2 In the clock gate unit 10, the gate that directly receives the input clock signal CLK is the first OR gate 111 of the first circuit 11 and the fourth OR gate 133 of the second circuit 13. Figure 2The logic diagram is not limited to any circuit diagram. However, in the case where the input clock signal CLK is input to two gates, the power consumption of the clock gating unit 10 may increase due to the input clock signal CLK.

[0036] According to this embodiment, which will be described in more detail below, multiple gates for receiving the input clock signal CLK can be combined to implement a clock gate unit 10 that includes only a pair of transistors (in other words, two transistors) that directly receive the input clock signal CLK. Therefore, the power consumption of the clock gate unit 10 can be reduced, and with the implementation of the low-power clock gate unit 10, the power consumption of the IC 1 including the clock gate unit 10 can also be reduced.

[0037] Figure 3A and Figure 3B This is a circuit diagram of a clock gating unit according to an exemplary embodiment of the present invention.

[0038] Figure 3A According to the example embodiment Figure 2 The circuit diagram of the clock gating unit 10 is shown. The clock gating unit 10 may include first, second, third, and fourth blocks C1, C2, C3, and C4.

[0039] The first block C1 may include a first holding circuit C11 and a first functional circuit C12; the second block C2 may include a first charging circuit C21, a second functional circuit C22, a second holding circuit C23 and a discharging circuit C24; and the third block C3 may include a second charging circuit C31.

[0040] In this specification, a holding circuit can refer to a circuit that maintains the voltage level of a specific node at a specific value. A charging circuit can refer to a circuit that charges the voltage level of a specific node to a logic high level, and a discharging circuit can refer to a circuit that discharges the voltage level of a specific node to a logic low level. A functional circuit can refer to a circuit that performs logical operations based on input signals and operates according to the results of the operations.

[0041] Furthermore, the first and second holding circuits C11 and C23, the first and second functional circuits C12 and C22, the first and second charging circuits C21 and C31, and the discharging circuit C24 can each be implemented using a single transistor, as shown in the reference below. Figure 4 However, the present invention is not limited thereto.

[0042] The first C1 can receive the enable signal E and the inverted output clock signal ECKN, and can be connected to the power voltage node VDD, the first node N1, and the ground node. For example... Figure 3A As shown, the first signal SIG1 can be generated by the first node N1. In other words, the first signal SIG1 can be generated by the first node N1.

[0043] For example, the first block C1 may include a first holding circuit C11, a first functional circuit C12, and a first transistor N11.

[0044] The first hold circuit C11 can receive the inverted output clock signal ECKN and can be connected to the power voltage node VDD and the first node N1. For example, the first hold circuit C11 can hold the first signal SIG1 of the first node N1 at a specific logic level according to the inverted output clock signal ECKN. In other words, the first hold circuit C11 can hold the first signal SIG1 of the first node N1 at a specific logic level in response to the inverted output clock signal ECKN.

[0045] The first functional circuit C12 can receive an enable signal E and can be connected to the source of the first node N1 and the first transistor N11. For example, the first functional circuit C12 can generate an inverted enable signal EN by receiving the inverted enable signal E, and control the logic level of the first signal SIG1 of the first node N1 according to the inverted enable signal EN.

[0046] although Figure 2 The illustration shows a first functional circuit C12 receiving an enable signal E; however, the inventive concept is not limited thereto, and the first functional circuit C12 can be connected to multiple signal lines and receive multiple other signals. For example, the first functional circuit C12 can receive the enable signal E and a scan enable signal (e.g., ...). Figure 10 SE), indicating the test operation mode of the clock gating unit 10.

[0047] The first transistor N11 can receive an inverted output clock signal ECKN and can be connected to the first functional circuit C12 and the ground node. For example, the first transistor N11 can be connected between the first functional circuit C12 and the ground node and can be controlled by an inverted output clock signal ECKN applied to its gate.

[0048] The second C2 can receive the inverted enable signal EN, the inverted first signal SIG1N, and the input clock signal CLK, and can be connected to the power voltage node VDD, the first node N1, the second node N2, and the ground node. For example, the inverted output clock signal ECKN can be generated by the second node N2.

[0049] For example, the second block C2 may include a first charging circuit C21, a second functional circuit C22, a second holding circuit C23, second and third transistors P21 and N21, and a discharging circuit C24.

[0050] The first charging circuit C21 can receive the first signal SIG1 and can be connected to the power voltage node VDD and the third node N3. For example, the first charging circuit C21 can charge the second node N2 by turning the second transistor P21 connected to the third node N3 on / off. For example, the first charging circuit C21 can charge the first node N1 according to the operation result of the second functional circuit C22. Therefore, for example, the logic level of the first signal SIG1 generated by the first node N1 can be a logic high level. Figure 3A In the diagram, the circle shown in the first charging circuit C21 can represent an inverter. Therefore, the first charging circuit C21 can use the inverted first signal SIG1N.

[0051] The second functional circuit C22 can receive the enable signal E and can be connected to the first node N1 and the third node N3. Figure 3A In the diagram, the circle shown at the second functional circuit C22 can represent an inverter. Therefore, the second functional circuit C22 can use an inverted enable signal EN.

[0052] although Figure 3A The illustration shows the second functional circuit C22 receiving an inverted enable signal EN; however, the inventive concept is not limited thereto, and the second functional circuit C22 can receive multiple other signals. For example, the second functional circuit C22 can receive both an inverted enable signal EN and an inverted scan enable signal. Furthermore, as... Figure 2 As shown, the polarities of the signals used to control the first functional circuit C12 and the second functional circuit C22 can be opposite to each other.

[0053] The second holding circuit C23 can receive the inverted first signal SIG1N and can be connected to the first node N1 and the fourth node N4. For example, the second holding circuit C23 can hold the first signal SIG1 of the first node N1 at a specific logic level according to the inverted first signal SIG1N.

[0054] The second transistor P21 can receive the input clock signal CLK and can be connected to the second node N2 and the third node N3. For example, the second transistor P21 can be connected between the second node N2 and the third node N3 and can be controlled by the input clock signal CLK applied to its gate.

[0055] The third transistor N21 can receive the input clock signal CLK and can be connected to the fourth node N4 and the ground node. For example, the third transistor N21 can be connected between the fourth node N4 and the ground node and can be controlled by the input clock signal CLK applied to its gate.

[0056] The discharge circuit C24 can receive the first signal SIG1 and can be connected to the second node N2 and the fourth node N4. For example, the discharge circuit C24 can discharge the second node N2 by turning on / off the third transistor N21 connected through the fourth node N4. Therefore, for example, the logic level of the inverted output clock signal ECKN generated by the second node N2 can be a logic low level.

[0057] The third block C3 can receive the first signal SIG1 and the inverted output clock signal ECKN, generate the output clock signal ECK, and can be connected to the second node N2 and the power voltage node VDD. According to an exemplary embodiment of the present invention, the third block C3 may include a second charging circuit C31 and an inverter C32.

[0058] The second charging circuit C31 can receive the first signal SIG1 and can be connected to the power voltage node VDD and the second node N2. For example, the second charging circuit C31 can charge the second node N2. Therefore, for example, the logic level of the inverted output clock signal ECKN generated by the second node N2 can be a logic high level.

[0059] Inverter C32 can generate the output clock signal ECK by inverting the output clock signal ECKN. Here, the inverter C32 in the third C3 block can be omitted. In this case, the clock gating unit 10 can generate the inverted output clock signal ECKN instead of the output clock signal ECK.

[0060] The fourth C4 can generate an inverted first signal SIG1N by inverting the first signal SIG1. The fourth C4 can be implemented using an inverting circuit.

[0061] The first charging circuit C21 and the second charging circuit C31 can determine the logic level of the first signal SIG1 and the logic level of the inverted output clock signal ECKN under the control of the second transistor P21.

[0062] For example, when the logic level of the input clock signal CLK is logic low, the second transistor P21 can be turned on by the input clock signal CLK, and the first charging circuit C21 can determine the logic level of the inverted output clock signal ECKN of the second node N2.

[0063] For example, when the logic level of the input clock signal CLK is logic high, the second transistor P21 may be turned off by the input clock signal CLK, and the first charging circuit C21 cannot determine the logic level of the inverted output clock signal ECKN of the second node N2. In this case, the second charging circuit C31 can determine the logic level of the inverted output clock signal ECKN of the second node N2.

[0064] For example, when the logic level of the input clock signal CLK is logic low, the second transistor P21 can be turned on by the input clock signal CLK. In this case, based on the ON / OFF state of the second functional circuit C22, the second charging circuit C31 can determine the logic level of the first signal SIG1 of the first node N1.

[0065] In the clock gating unit 10 according to this embodiment, a first signal SIG1 can be generated based on the input clock signal CLK via a latch enable signal E. For example, when the logic level of the input clock signal CLK is logic low, the first signal SIG1 can be generated from the enable signal E, and when the logic level of the input clock signal CLK is logic high, the previous output value can be maintained.

[0066] Furthermore, when the logic level of the first signal SIG1 is logic low, the output clock signal ECK can remain logic low, and when the logic level of the first signal SIG1 is logic high, the output clock signal can be generated from the input clock signal CLK.

[0067] The clock gating unit according to the comparative example may include latch circuitry and logic gates, and since both the latch circuitry and the logic gates directly receive the input clock signal CLK, the power consumption due to the input clock signal CLK is significant. In contrast, according to this embodiment, the clock gating unit 10 can include only the transistor pair receiving the input clock signal CLK by merging the input clock signal CLK input to the latch circuitry and the input clock signal CLK input to the logic gates. Therefore, the parasitic capacitance due to the input clock signal CLK can be reduced, and the power consumption of the clock gating unit 10 can be decreased.

[0068] Figure 3B It can be Figure 2 An alternative embodiment may be provided in which the clock gating unit 15 may include a first, second, third and fourth block C15, C25, C35 and C45.

[0069] The first C15 may include a first holding circuit C115 and a first functional circuit C125; the second C25 may include a first charging circuit C215, a second functional circuit C225, a second holding circuit C235 and a discharging circuit C245; and the third C35 may include a second charging circuit C315.

[0070] and Figure 3A Unlike other circuits, the signals used to control the first holding circuit C115, the second holding circuit C235, and the discharge circuit C245 are not each limited to any one of the signals.

[0071] Furthermore, multiple control signals A1, A2, and A3 can be used to control the first functional circuit C125 and the second functional circuit C225, and any one of the control signals A1, A2, and A3 can be an enable signal E. Although Figure 3B Three control signals are shown, but the number of control signals is not limited to this.

[0072] In detail, the first block C15 may include a first functional circuit C125 and a first holding circuit C115. The first functional circuit C125 is configured to generate a first signal SIG1 through the first node N1 based on at least one of control signals A1, A2 and A3. The first holding circuit C115 is configured to hold the voltage level of the first signal SIG1.

[0073] The second block C25 may include: a second functional circuit C225 configured to generate a first signal SIG1 through the first node N1 based on at least one of control signals A1, A2, and A3; a second holding circuit C235 configured to hold the voltage level of the first signal SIG1; a first charging circuit C215 configured to generate an inverted output clock signal ECKN by charging the second node N2 based on the first signal SIG1; and a discharging circuit C245 configured to discharge the second node N2.

[0074] The third block C35 may include a second charging circuit C315, which is configured to generate an inverted output clock signal ECKN by charging the second node N2 based on the first signal SIG1.

[0075] The fourth C45 can be configured to receive the first signal SIG1 and generate an inverted first signal SIG1N.

[0076] Figure 4 This is a circuit diagram of a clock gating unit according to an exemplary embodiment of the present invention.

[0077] refer to Figure 4 The clock gating unit 10a may include a first, second, third and fourth block C1a, C2a, C3a and C4a. Figure 4 It can correspond to Figure 3A The embodiments are described below, and the following can be omitted. Figure 2The same description applies. Furthermore, in this specification, the transistor may have a structure providing complementary transistors (e.g., an n-channel transistor and a p-channel transistor), and as a non-limiting example, it may be implemented as a planar field-effect transistor (FET), a fin field-effect transistor (FinFET), a gate all-around field-effect transistor (GAAFET), a vertical field-effect transistor (VFET), etc.

[0078] The first block C1a may include an inverter I11a, a first PFET transistor P11a, and first and second NFET transistors N11a and N12a.

[0079] Inverter I11a can generate an inverted enable signal EN using an inverted enable signal E. A first PFET transistor P11a can be connected between the power voltage node VDD and the first node N1a, and can be controlled by an inverted output clock signal ECKN applied to its gate. First and second NFET transistors N11a and N12a can be connected in series between the first node N1a and the ground node, and can be controlled by the inverted enable signal EN and the inverted output clock signal ECKN, respectively. For example, the inverted enable signal EN can be applied to the gate of the first NFET transistor N11a, and the inverted output clock signal ECKN can be applied to the gate of the second NFET transistor N12a.

[0080] The second block C2a may include the third, fourth, and fifth PFET transistors P21a, P22a, and P23a, and the third, fourth, and fifth NFET transistors N21a, N22a, and N23a.

[0081] The third PFET transistor P21a can be connected between the power voltage node VDD and the third node N3a, and can be controlled by an inverted first signal SIG1N applied to its gate. The fourth PFET transistor P22a can be connected between the third node N3a and the first node N1a, and can be controlled by an inverted enable signal EN applied to its gate. The fifth PFET transistor P23a can be connected between the third node N3a and the second node N2a, and can be controlled by an input clock signal CLK applied to its gate.

[0082] The third NFET transistor N21a can be connected between the first node N1a and the fourth node N4a, and can be controlled by an inverted first signal SIG1N applied to its gate. The fourth NFET transistor N22a can be connected between the second node N2a and the fourth node N4a, and can be controlled by a first signal SIG1 applied to its gate. The fifth NFET transistor N23a can be connected between the fourth node N4a and the ground node, and can be controlled by an input clock signal CLK applied to its gate.

[0083] The third block C3a may include a sixth PFET transistor P31a and an inverter I31a. The sixth PFET transistor P31a may be connected between the power voltage node VDD and the second node N2a, and may be controlled by a first signal SIG1 applied to its gate. The inverter I31a may generate an output clock signal ECK by inverting the output clock signal ECKN.

[0084] The fourth block C4a may include an inverter I41a. Inverter I41a can generate an inverted first signal SIG1N by inverting the first signal SIG1.

[0085] Since the clock gating unit 10a according to this embodiment includes only a pair of transistors that directly receive the input clock signal CLK, the clock gating unit 10a can have a simplified layout. In other words, the connection from the gate line to the clock pins can be minimized.

[0086] For example, the clock gate unit 10a may be arranged to include only the gate line pair to which the input clock signal CLK is applied, and signals other than the input clock signal CLK may be input to the gate lines of the transistors adjacent to the fifth PFET transistor P23a and the fifth NFET transistor N23a.

[0087] In addition, Figure 4 In this circuit, the source and drain of the fifth PFET transistor P23a, which receives the input clock signal CLK, can be connected to an internal node of the circuit, rather than the power voltage node VDD or the ground node. The source of the fifth NFET transistor N23a can also be connected to an internal node of the circuit.

[0088] Figure 5 This is a schematic diagram illustrating the operation of a clock gating unit according to an exemplary embodiment of the present invention.

[0089] refer to Figure 5The fifth PFET transistor P23a and the fifth NFET transistor N23a, which receive the input clock signal CLK, can determine the logic levels of the first signal SIG1 generated by the first node N1a and the inverted output clock signal ECKN generated by the second node N2a. For example, the fifth PFET transistor P23a can control the charging path of the first node N1a and the second node N2a based on the input clock signal CLK, and the fifth NFET transistor N23a can control the discharging path of the first node N1a and the second node N2a based on the input clock signal CLK.

[0090] The fifth PFET transistor P23a can determine the logic level of the first signal SIG1 generated by the first node N1a through the first path R1. For example, the first path R1 can represent the charging path of the first signal SIG1.

[0091] In addition, the fifth PFET transistor P23a can determine the logic level of the inverted output clock signal ECKN generated by the second node N2a.

[0092] The logic level of the first signal SIG1 generated by the first node N1a can be determined by the second path R2. For example, the second path R2 can represent the discharge path of the first signal SIG1.

[0093] Furthermore, the fifth PFET transistor P23a can determine the logic level of the inverted output clock signal ECKN generated by the second node N2a via the third path R3. For example, the third path R3 can represent the discharge path of the inverted output clock signal ECKN.

[0094] As mentioned above, since a single transistor controls the charging or discharging of two signals, the number of circuit elements that directly receive the input clock signal can be reduced. In other words, the number of clock pins and the clock pin capacitance can be reduced.

[0095] Figure 6 This is a timing diagram used to describe the operation of a clock gating unit according to an exemplary embodiment of the present invention.

[0096] refer to Figure 6 It shows that according to Figure 4 The time elapsed signal in the clock gating unit 10a. Figure 6 In the timing diagram, the propagation delay can be ignored, and the input clock signal CLK can oscillate according to the period T.

[0097] At time t1, the input clock signal CLK can transition from logic low to logic high. The enable signal E can remain logic low, therefore the first signal SIG1 can remain logic low, the inverted output clock signal ECKN can remain logic high, and the output clock signal ECK can remain logic low.

[0098] At time t2, the enable signal E can transition from logic low to logic high. The input clock signal CLK can remain logic high, therefore the first signal SIG1 can remain logic low, the inverted output clock signal ECKN can remain logic high, and the output clock signal ECK can remain logic low.

[0099] At time t3, the input clock signal CLK can transition from logic high to logic low. The enable signal E can remain at logic high, and the first signal SIG1 can transition from logic low to logic high based on the enable signal E. The inverted output clock signal ECKN can remain at logic high, and the output clock signal ECK can remain at logic low.

[0100] At time t4, the input clock signal CLK can transition from logic low to logic high. The enable signal E can remain at logic high, and the first signal SIG1 can also remain at logic high. The inverted output clock signal ECKN can transition from logic high to logic low, therefore the output clock signal ECK can transition from logic low to logic high.

[0101] At time t5, the input clock signal CLK can remain at a logic high level, and the enable signal E can transition from a logic high level to a logic low level. Furthermore, the first signal SIG1 can remain at a logic high level, the inverted output clock signal ECKN can remain at a logic low level, and the output clock signal ECK can remain at a logic high level.

[0102] At time t6, when the input clock signal CLK transitions from logic high to logic low, the first signal SIG1 can also transition from logic high to logic low. Furthermore, the inverted output clock signal ECKN can transition from logic low to logic high, therefore the output clock signal ECK can transition from logic high to logic low.

[0103] At time t7 after one period T, the input clock signal CLK can transition from logic high to logic low. The enable signal E can remain logic low, therefore the first signal SIG1 can remain logic low, the inverted output clock signal ECKN can remain logic high, and the output clock signal ECK can remain logic low.

[0104] At time t8, the input clock signal CLK can remain at a logic low level, and the enable signal E can transition from a logic low level to a logic high level. Therefore, the first signal SIG1 can transition from a logic low level to a logic high level, the inverted output clock signal ECKN can remain at a logic high level, and the output clock signal ECK can remain at a logic low level.

[0105] At time t9, the input clock signal CLK can transition from logic low to logic high. The enable signal E can remain at logic high, and the first signal SIG1 can also remain at logic high. The inverted output clock signal ECKN can transition from logic high to logic low, therefore the output clock signal ECK can transition from logic low to logic high.

[0106] Similar to the clock gating unit according to the comparative example, in the clock gating units 10 and 10a according to this embodiment, a first signal SIG1 generated by latching the input clock signal CLK through the latch enable signal E can be generated, and an operation for generating the output clock signal ECK can be performed based on the first signal SIG1.

[0107] Although the clock gating unit according to the comparative example includes at least two transistor pairs for receiving the input clock signal CLK to perform the above operations, the clock gating units 10, 10a, 10b, 10c, 10d and 10e of the exemplary embodiments of the present invention include only one transistor pair for receiving the input clock signal CLK, thus reducing the input capacitance and power consumption caused by the input clock signal CLK.

[0108] Figures 7 to 10 , Figure 11A and Figure 11B This is a circuit diagram of a clock gating unit according to an exemplary embodiment of the present invention.

[0109] Figures 7 to 10 , Figure 11A and Figure 11B Each of the clock gating units 10b, 10c, 10d, 10e, 10f, and 10g is... Figure 2 An embodiment of the clock gating unit 10, and which may correspond to Figure 4 A modified embodiment of the clock gating unit 10a. Therefore, descriptions identical to those already given above can be omitted below.

[0110] In addition, according to Figures 7 to 9 The time elapsed signals in the clock gating units 10b, 10c, and 10d can be similar to those in the reference above. Figure 6 The timing diagrams describe those signals. Furthermore, in Figures 7 to 11BIn, corresponding to Figure 4 The components shown will be represented by "b", "c", "d", "e", "f", and "g", respectively. For example, Figure 7 The first PFET transistor P11b can correspond to Figure 4 The first PFET transistor P11a.

[0111] refer to Figure 7 The first, second, third, and fourth blocks C1b, C2b, C3b, and C4b can be respectively similar to Figure 4 The first to fourth blocks C1a to C4a. In an exemplary embodiment of the present invention, some of the transistors receiving the first signal SIG1 may receive a delayed first signal SIG1D instead of the first signal SIG1 via a buffer.

[0112] In an exemplary embodiment of the present invention, the fourth block C4b may include first and second inverters I41b and I42b to generate a delayed first signal SIG1D. The first inverter I41b can generate an inverted first signal SIG1N by inverting the first signal SIG1, and the second inverter I42b can generate a delayed first signal SIG1D by inverting the inverted first signal SIG1N.

[0113] At least one of the fourth NFET transistor N22b of the second block C2b and the sixth PFET transistor P31b of the third block C3b can receive the delayed first signal SIG1D instead of the first signal SIG1.

[0114] although Figure 7 The illustration shows that both the fourth NFET transistor N22b and the sixth PFET transistor P31b receive the delayed first signal SIG1D, but the inventive concept is not limited thereto, and the fourth NFET transistor N22b can receive the first signal SIG1, and the sixth PFET transistor P31b can receive the delayed first signal SIG1D.

[0115] refer to Figure 8 The first, second, third, and fourth blocks C1c, C2c, C3c, and C4c can be respectively similar to Figure 4 The first to fourth blocks C1a to C4a. In an exemplary embodiment of the inventive concept, Figure 4 At least one of the inverters I11a of the first C1a and I31a of the third C3a can be omitted.

[0116] In an exemplary embodiment of the present invention, the first C1c can directly receive the inverted enable signal EN from the outside, instead of the enable signal E. In an exemplary embodiment of the present invention, the third C3c can immediately output the inverted output clock signal ECKN generated by the second node N2c.

[0117] refer to Figure 9 The first, second, third, and fourth blocks C1d, C2d, C3d, and C4d can be respectively similar to Figure 4 The first to fourth blocks C1a to C4a. In an exemplary embodiment of the inventive concept, the first block C1d may be connected to the second block C2d instead of the power voltage node VDD. For example, the first PFET transistor P11d may be connected between the third node N3d of the second block C2d and the first node N1d, and may be controlled by an inverted output clock signal ECKN. In other words, because the first PFET transistor P11d is connected to an internal node of the clock gate unit 10d instead of the power voltage node VDD, the load on the wiring path in the layout can be reduced.

[0118] refer to Figure 10 The first, second, third, and fourth blocks C1e, C2e, C3e, and C4e can be respectively similar to Figure 4 The first to fourth blocks C1a to C4a. In an exemplary embodiment of the present invention, the clock gating unit 10e can operate in multiple operating modes. To achieve this, the clock gating unit 10e can also receive a scan enable signal SE.

[0119] In an exemplary embodiment of the present invention, the clock gating unit 10e can operate in a normal operating mode that performs data transmission according to the scan enable signal SE, or in a test mode that performs test operations. For example, when the scan enable signal SE is at a first logic level (e.g., logic low), the normal operating mode can be indicated, and when the scan enable signal SE is at a second logic level (e.g., logic high), the scan test mode can be indicated.

[0120] and Figure 4 Unlike the first C1a, the first C1e of the clock gating unit 10e can also include a NOR gate G11e to replace the inverter I11a. The NOR gate G11e can receive the enable signal E and the scan enable signal SE, and output the second signal SIG2.

[0121] The first NFET transistor N11e of the first block C1e can be connected between the source of the first node N1e and the second NFET transistor N12e, and can be controlled by the second signal SIG2 applied to its gate. Furthermore, the fourth PFET transistor P22e of the second block C2e can be controlled by the second signal SIG2 instead of the inverted enable signal EN.

[0122] Although it has been described in order Figures 7 to 10 The embodiments are as described above, but at least two of the embodiments can be copied and combined with each other. In the exemplary embodiments of the inventive concept, when Figure 8 and Figure 9 When the embodiments are combined, the first block C1d of the clock gating unit 10d can be connected to the second block C2d instead of the power voltage node VDD, and the inverters I11d of the first block C1d and I31d of the third block C3d can be omitted.

[0123] In an exemplary embodiment of the present invention, Figure 7 and Figure 10 The embodiments can be combined. See reference. Figure 11A The first block C1f of the clock gating unit 10f may include a NOR gate G11f, thereby operating in normal operation mode or scan test mode. Furthermore, the fourth block C4f may include a first inverter I41f, which generates an inverted first signal SIG1N by inverting the first signal SIG1, and a second inverter I42f can generate a delayed first signal SIG1D by inverting the inverted first signal SIG1N. Therefore, the sixth PFET transistor P31f of the third block C3f can receive the delayed first signal SIG1D through a buffer.

[0124] In an exemplary embodiment of the present invention, reference is made to... Figure 11B Compared to the third block C3f of the clock gating unit 10f, the third block C3g of the clock gating unit 10g may further include a seventh PFET transistor P32g. The seventh PFET transistor P32g may be connected between the second node N2g and the power voltage node VDD, and may be controlled by a clock input CLK applied to its gate. In an exemplary embodiment of the present invention, the number of seventh PFET transistors P32g may be one or more, wherein the number of seventh PFET transistors P32g may correspond to the number of fourth PFET transistors N22g and fifth PFET transistors N23g. Furthermore, the seventh PFET transistor P32g may also be added to... Figure 7 The third C3b Figure 9 The third C3d and Figure 10 The third C3e.

[0125] The clock gating unit 10g can drive the load unit by outputting a clock ECK to the load unit. In this case, when the parasitic capacitance of the load unit is large, the number of the fourth NFET transistor N22g, the fifth NFET transistor N23g, and the inverter I31g connected to the second node N2g can be increased, thereby increasing the strength of the inverted clock output ECKN and reducing the rise time of the inverted clock output ECKN.

[0126] According to an exemplary embodiment of the present invention, due to the addition of a seventh PFET transistor P32g, the inverted clock output ECKN can be balanced corresponding to the number of the fourth PFET transistor N22g and the fifth PFET transistor N23g. Therefore, total power consumption and / or loss of operating speed can be minimized, and the clock output ECK can be provided stably. Figure 12 This is a schematic diagram illustrating the logic symbols of a latch circuit according to an exemplary embodiment of the present invention, and Figure 13 This is a block diagram of a latch circuit according to an exemplary embodiment of the present invention.

[0127] Figure 12 This is a schematic diagram illustrating the logic symbols of a latch circuit according to an exemplary embodiment of the present invention, and Figure 13 This is a block diagram of a latch circuit according to an exemplary embodiment of the present invention.

[0128] refer to Figure 12 The latch circuit 20 can generate an output signal Q based on the data signal D in response to the input clock signal CLK. For example, the latch circuit 20 can be triggered in response to the negative or positive edge of the input clock signal CLK.

[0129] Figure 13 It can be as Figure 12 A block diagram of the latch circuit 20 in an embodiment.

[0130] The latch circuit 20 may include fifth, sixth, seventh, and eighth blocks C5, C6, C7, and C8. The fifth to eighth blocks C5 to C8 may be respectively similar to... Figure 2 The first to fourth blocks, C1 to C4. Therefore, descriptions identical to those already given above will be omitted below. See later for reference. Figure 14 and Figure 15 The first and second holding circuits C51 and C63, the first and second functional circuits C52 and C62, the first and second charging circuits C61 and C71, the discharging circuit C64, and the output circuit C8 may each include at least one transistor.

[0131] The fifth transistor, C5, can receive the inverted output clock signal ECKN and the data signal D, and can be connected to the power voltage node VDD, the fifth node N5, and the ground node. The fifth transistor, C5, may include a first holding circuit C51, a first functional circuit C52, and a fourth transistor N51.

[0132] The first holding circuit C51 can be similar to... Figure 3A The first holding circuit C11, and the fourth transistor N51 can be similar to Figure 3A The first transistor N11.

[0133] The first functional circuit C52 can receive the data signal D and can be connected to the source of the fifth node N5 and the fourth transistor N51. The third signal SIG3 can be generated by the fifth node N5.

[0134] The sixth block C6 can receive the data signal D, the output signal Q, the input clock signal CLK, and the inverted output signal QN, and can be connected to the power voltage node VDD, the fifth node N5, the sixth node N6, and the ground node. The sixth block C6 may include the second functional circuit C62, the second holding circuit C63, the first charging circuit C61, the fifth and sixth transistors P61 and N61, and the discharging circuit C64.

[0135] The second functional circuit C62 can receive the data signal D and can be connected to the fifth node N5 and the seventh node N7. Furthermore, in Figure 13 In the diagram, the circle shown at the second functional circuit C62 can represent an inverter. Therefore, the second functional circuit C62 can use the inverted data signal DN. Furthermore, the polarities of the signals used to control the first functional circuit C52 and the second functional circuit C62 can be opposite to each other.

[0136] The second holding circuit C63 can receive the output signal Q and can be connected to the fifth node N5 and the eighth node N8.

[0137] The first charging circuit C61 can receive the inverted output signal QN and can be connected to the power voltage node VDD and the seventh node N7. The circle shown at the first charging circuit C61 can represent an inverter. Therefore, the first charging circuit C61 can use the output signal Q.

[0138] The fifth transistor P61 can receive the input clock signal CLK and can be connected to the sixth node N6 and the seventh node N7. For example, the fifth transistor P61 can be connected between the sixth node N6 and the seventh node N7 and can be controlled by the input clock signal CLK applied to its gate. The inverted output clock signal ECKN can be generated by the sixth node N6.

[0139] The sixth transistor N61 can receive the input clock signal CLK and can be connected to the eighth node N8 and the ground node. For example, the sixth transistor N61 can be connected between the eighth node N8 and the ground node and can be controlled by the input clock signal CLK.

[0140] The discharge circuit C64 can receive the third signal SIG3 and can be connected to the sixth node N6 and the eighth node N8.

[0141] The seventh component C7 may include a second charging circuit C71. The second charging circuit C71 can receive an inverted output signal QN from the first charging circuit C61 and can be connected to the power voltage node VDD and the sixth node N6.

[0142] The eighth component, C8, can receive the third signal SIG3 and can generate the output signal Q and / or the inverted output signal QN.

[0143] Similar to the above, the first charging circuit C61 and the second charging circuit C71 can determine the logic level of the third signal SIG3 and the logic level of the inverted output clock signal ECKN under the control of the fifth transistor P61.

[0144] For example, when the logic level of the input clock signal CLK is logic low, the fifth transistor P61 can be turned on by the input clock signal CLK, and the first charging circuit C61 can determine the logic level of the inverted output clock signal ECKN of the sixth node N6.

[0145] For example, when the logic level of the input clock signal CLK is logic high, the fifth transistor P61 may be turned off by the input clock signal CLK, and the first charging circuit C61 cannot determine the logic level of the inverted output clock signal ECKN of the sixth node N6. In this case, the second charging circuit C71 can determine the logic level of the inverted output clock signal ECKN of the sixth node N6.

[0146] For example, when the logic level of the input clock signal CLK is logic low, the fifth transistor P61 can be turned on by the input clock signal CLK. In this case, based on the on / off state of the second functional circuit C62, the second charging circuit C71 can determine the logic level of the third signal SIG3 of the fifth node N5.

[0147] Because the latch circuit 20 according to this embodiment only includes a pair of transistors that receive the input clock signal CLK, a low-power latch circuit can be implemented, which reduces power consumption due to the input clock signal CLK.

[0148] Figure 14 and Figure 15This is a circuit diagram of a latch circuit according to an exemplary embodiment of the present invention.

[0149] refer to Figure 14 As Figure 13 In one embodiment, latch circuit 20a can operate in response to a negative edge of the input clock signal CLK input to it. In other words, latch circuit 20a can be a negative edge-triggered latch circuit.

[0150] The fifth block, C5a, can receive the data signal D and the inverted output clock signal ECKN, and can be connected to the fifth node, N5a. The third signal, SIG3, can be generated by the fifth node, N5a.

[0151] The fifth block C5a may include the seventh PFET transistor P51a and the sixth and seventh NFET transistors N51a and N52a.

[0152] The seventh PFET transistor P51a can be connected between the power voltage node VDD and the fifth node N5a, and can be controlled by the inverted output clock signal ECKN. The sixth and seventh NFET transistors N51a and N52a can be connected in series between the fifth node N5a and the ground node, and can be controlled by the data signal D and the inverted output clock signal ECKN, respectively.

[0153] The sixth block, C6a, can receive the output signal Q, the data signal D, the third signal SIG3, and the input clock signal CLK, and can be connected to the sixth node N6a. The inverted output clock signal ECKN can be generated by the sixth node N6a.

[0154] The sixth block C6a may include the eighth, ninth and tenth PFET transistors P61a, P62a and P63a, and the eighth, ninth and tenth NFET transistors N61a, N62a and N63a.

[0155] The eighth PFET transistor P61a can be connected between the power voltage node VDD and the seventh node N7a, and can be controlled by the output signal Q. The ninth PFET transistor P62a can be connected between the seventh node N7a and the fifth node N5a, and can be controlled by the data signal D. The tenth PFET transistor P63a can be connected between the seventh node N7a and the sixth node N6a, and can be controlled by the input clock signal CLK.

[0156] The eighth NFET transistor N61a can be connected between the fifth node N5a and the eighth node N8a, and can be controlled by the output signal Q. The ninth NFET transistor N62a can be connected between the sixth node N6a and the eighth node N8a, and can be controlled by the third signal SIG3. The tenth NFET transistor N63a can be connected between the eighth node N8a and the ground node, and can be controlled by the input clock signal CLK.

[0157] The seventh block C7a can be connected to the power voltage node VDD and the sixth node N6a. In an exemplary embodiment of the present invention, the seventh block C7a may include an eleventh PFET transistor P71a, which is connected between the power voltage node VDD and the sixth node N6a and is controlled by an inverted output signal QN.

[0158] In an exemplary embodiment of the present invention, the eighth block C8a may include an inverter I81a that generates an output signal Q by inverting the third signal SIG3 and an inverter I82a that generates an inverted output signal QN by inverting the output signal Q.

[0159] refer to Figure 15 As Figure 13 In one embodiment, latch circuit 20b can operate in response to a positive edge of the input clock signal CLK input to it. In other words, latch circuit 20b can be a positive edge-triggered latch circuit.

[0160] Because the fifth, sixth, seventh, and eighth blocks C5b, C6b, C7b, and C8b of latch circuit 20b can be respectively similar to Figure 13 The fifth to eighth blocks, C5a to C8a, therefore the descriptions identical to those already given above can be omitted below. Figure 15 In, corresponding to Figure 14 The elements shown will be represented by "b".

[0161] The fifth block C5b may include the twelfth and thirteenth PFET transistors P51b and P52b, and the eleventh NFET transistor N51b. The twelfth and thirteenth PFET transistors P51b and P52b may be connected in series between the power voltage node VDD and the fifth node N5b, and may be controlled by the inverted output clock signal ECKN and the data signal D, respectively. The eleventh NFET transistor N51b may be connected between the fifth node N5b and the ground node, and may be controlled by the inverted output clock signal ECKN.

[0162] The sixth block C6b may include the fourteenth, fifteenth and sixteenth PFET transistors P61b, P62b and P63b, and the twelfth, thirteenth and fourteenth NFET transistors N61b, N62b and N63b.

[0163] The fourteenth PFET transistor P61b can be connected between the power voltage node VDD and the seventh node N7b, and can be controlled by the input clock signal CLK. The fifteenth PFET transistor P62b can be connected between the fifth node N5b and the seventh node N7b, and can be controlled by the output signal Q. The sixteenth PFET transistor P63b can be connected between the sixth node N6b and the seventh node N7b, and can be controlled by the third signal SIG3.

[0164] The twelfth NFET transistor N61b can be connected between the fifth node N5b and the eighth node N8b, and can be controlled by the data signal D. The thirteenth NFET transistor N62b can be connected between the sixth node N6b and the eighth node N8b, and can be controlled by the input clock signal CLK. The fourteenth NFET transistor N63b can be connected between the eighth node N8b and the ground node, and can be controlled by the output signal Q.

[0165] The seventh block C7b can be connected to the ground node and the sixth node N6b. In an exemplary embodiment of the present invention, the seventh block C7b may further include a fifteenth NFET transistor N71b, which is connected between the ground node and the sixth node N6b and is controlled by an inverted output signal QN.

[0166] The eighth C8b can be similar to Figure 14 The eighth piece, C8a.

[0167] Based on the fifth node N5a and the sixth node N6a, Figure 14 The fifth to seventh blocks, C5a to C7a, can be divided into pull-up units and pull-down units. Similarly, based on the fifth node N5b and the sixth node N6b, Figure 15 The fifth to seventh blocks, C5b to C7b, can be divided into pull-up units and pull-down units.

[0168] For example, refer to Figure 14 In the fifth block C5a, the seventh PFET transistor P51a can be classified as a pull-up unit, while the sixth and seventh NFET transistors N51a and N52a can be classified as pull-down units. In the sixth block C6a, the eighth to tenth PFET transistors P61a, P62a, and P63a can be classified as pull-up units, while the eighth to tenth NFET transistors N61a, N62a, and N63a can be classified as pull-down units. In the seventh block C7a, the eleventh PFET transistor P71a can be classified as a pull-up unit.

[0169] refer to Figure 15In block C5b, the twelfth and thirteenth PFET transistors P51b and P52b can be classified as pull-up units, while the eleventh NFET transistor N51b can be classified as a pull-down unit. In block C6b, the fourteenth to sixteenth PFET transistors P61b, P62b, and P63b can be classified as pull-up units, while the twelfth to fourteenth NFET transistors N61b, N62b, and N63b can be classified as pull-down units. In block C7b, the fifteenth NFET transistor N71b can be classified as a pull-down unit.

[0170] By dividing the latch circuit 20a (triggered by the negative edge) and the latch circuit 20b (triggered by the positive edge) into pull-up and pull-down units, they can have a symmetrical structure around the fifth nodes N5a and N5b and the sixth nodes N6a and N6b. Furthermore, the pull-up units of the latch circuits 20a and 20b can be implemented using PFET transistors, while the pull-down units can be implemented using NFET transistors.

[0171] Figure 16A and Figure 16B This is a schematic diagram illustrating a partial layout of the clock gating unit and latch circuitry according to an exemplary embodiment of the present invention. For example, Figure 16A It can be shown schematically with Figure 4 A schematic diagram of the layout corresponding to the second block C2a of the clock gating unit 10a, more specifically, the fifth PFET transistor P23a and its surrounding area included in the second block C2a. For example, Figure 16B It can be shown schematically with Figure 15 A schematic diagram of the layout corresponding to the sixth block C6b of the clock gating unit 20b, more specifically, the thirteenth NFET transistor N62b and its surrounding area included in the sixth block C6b. However, the inventive concept is not limited thereto, and Figure 16B Can be with Figures 7 to 11B The second blocks C2b, C2c, C2d, C2e, and 2f of the clock gating units 10b, 10c, 10d, 10e, and 10f, and Figure 14 This corresponds to the sixth block C6a of the latch circuit 20a. The first layout L1 may be a schematic partial representation of the clock gating units 10b to 10f or the latch circuit 20a on a plane including the X and Y axes.

[0172] exist Figure 16A and Figure 16B For ease of illustration, only some layers and patterns may be shown, and vias may be shown even if they are located below the patterns of the wiring layers to indicate the connection between the patterns of the wiring layers and the patterns below them. Furthermore, patterns composed of conductive materials, such as the patterns of the wiring layers, may be referred to as conductive patterns, or simply as patterns.

[0173] like Figure 16A and 16B As shown, at least one gate electrode may extend in the Y-axis direction. Furthermore, at least one active region may extend in the X-axis direction and may form a transistor together with the gate electrode. In some embodiments of the inventive concept, at least one fin may extend along the X-axis direction in the active region and form a finned field-effect transistor together with the gate electrode.

[0174] The following will be referenced together. Figure 4 and Figure 16A A description is given, and for ease of explanation, it will be assumed, but not limited to, that the first layout L1 corresponds to the one included in the clock gating unit 10a ( Figure 4 The fifth PFET transistor P23a of the second block C2a and its surrounding area.

[0175] The first gate electrode G1 can be connected to the clock pattern P_CLK, and the input clock signal CLK can be applied to the clock pattern P_CLK. In the first region R1 of the PFET active region, the first pattern A, the second pattern B, and the first gate electrode G1 can form a PFET transistor. The PFET transistor can correspond to the fifth PFET transistor P23a of the clock gate unit 10a.

[0176] The first pattern A can be connected to the source or drain of the fifth PFET transistor P23a. For example, the first pattern A can correspond to the second node N2a, and the inverted output clock signal ECKN can be applied to it. The first pattern A can be connected to the output inverter. The second pattern B can be connected to the source or drain of the fifth PFET transistor P23a, and can correspond to the third node N3a, for example.

[0177] According to an exemplary embodiment of the invention, since the clock gating unit 10a includes only one PFET transistor and one NFET transistor for receiving the input clock signal CLK, signals other than the input clock signal CLK can be applied to the third pattern C connected to the second gate electrode G2. For example, an inverted first signal SIG1N provided to the gate of the third PFET transistor P21a or an inverted enable signal EN provided to the gate of the fourth PFET transistor P22a can be applied to the third pattern C.

[0178] Transistors other than the transistor that receives the input clock signal CLK, such as the third and fourth PFET transistors P21a and P22a adjacent to the fifth PFET transistor P23a, may not be electrically connected to the clock pattern P_CLK.

[0179] Furthermore, the first gate electrode G1 can form an NFET transistor in the active region of the NFET transistor. Therefore, due to the first gate electrode G1, the first layout L1 can include two transistors that receive the input clock signal CLK. Here, the source and drain of at least one of the two transistors can be connected to nodes other than the power voltage node VDD and the ground node. For example, the source of the PFET transistor formed in the first region R1 can be connected to the third node N3a, and the drain of the PFET transistor can be connected to the second node N2a.

[0180] refer to Figure 16B The second layout L2 can be with Figure 15 The schematic layout corresponding to the sixth block C6b of the clock gating unit 20b, and more specifically, the thirteenth NFET transistor N62b and its surrounding area included in the sixth block C6b. The second layout L2 may be a schematic representation of a portion of the latch circuit 20b in a plane including the X and Y axes.

[0181] The following will be referenced together. Figure 15 and Figure 16B A description is given, and for ease of explanation, it will be assumed, but not limited to, that the second layout L2 corresponds to latch circuit 20b ( Figure 15 The sixth block C6b includes the thirteenth NFET transistor N62b and its surrounding area. Furthermore, the following can be omitted from the references already mentioned above. Figure 16A The given description is the same as the given description.

[0182] The first gate electrode G1 can be connected to the clock pattern P_CLK, and the input clock signal CLK can be applied to the clock pattern P_CLK. In the second region R2 of the NFET active region, the first gate electrode G1 can form an NFET transistor. The NFET transistor can correspond to the thirteenth NFET transistor N62b of the latch circuit 20b. The fourth pattern D can be connected to the source or drain of the thirteenth NFET transistor N62b. For example, the fourth pattern D can correspond to the sixth node N6b, and the inverted output clock signal ECKN can be applied to it. The fifth pattern E can be connected to the source and drain of the thirteenth NFET transistor N62b, and can, for example, correspond to the eighth node N8b.

[0183] According to an exemplary embodiment of the invention, since the latch circuit 20b includes only one PFET transistor and one NFET transistor for receiving the input clock signal CLK, signals other than the input clock signal CLK can be applied to the sixth pattern F connected to the second gate electrode G2. For example, the output signal Q provided to the gate of the fifteenth PFET transistor P62b and the gate of the fourteenth NFET transistor N63b can be applied to the sixth pattern F.

[0184] Transistors other than the one that receives the input clock signal CLK, such as the fourteenth and fifteenth NFET transistors N63b and N71b adjacent to the thirteenth NFET transistor N62b, may not be electrically connected to the clock pattern P_CLK.

[0185] Furthermore, a PFET transistor can be formed in the PFET active region using the first gate electrode G1. Therefore, due to the first gate electrode G1, the second layout L2 can include two transistors that receive the input clock signal CLK. Here, the source and drain of at least one of the two transistors can be connected to nodes other than the power voltage node VDD and the ground node. For example, the source of the NFET transistor formed in the second region R2 can be connected to the sixth node N6b, and the drain of the NFET transistor can be connected to the eighth node N8b.

[0186] Figure 17 This is a schematic diagram illustrating an IC including a clock gating unit according to an example embodiment of a concept based on the present invention.

[0187] refer to Figure 17 The IC 100, which processes digital signals, may include a first clock gating unit CGC1, a second clock gating unit CGC2, a power controller PC, a first combinational logic block CL1, a second combinational logic block CL2, and multiple flip-flops PF1, PF2, NF1, and NF2. The IC 100 may include the components mentioned above. Figures 1 to 1 1 describes the clock gating unit.

[0188] The power controller PC can control the power of IC 100 and can generate a first enable signal E1 and a second enable signal E2. For example, the power controller PC can generate an inactive first enable signal E1 to reduce power consumption through digital circuitry including at least one first positive edge-triggered flip-flop PF1, a first combinational logic block CL1, and at least one second positive edge-triggered flip-flop PF2. Furthermore, the power controller PC can generate an inactive second enable signal E2 to reduce power consumption through digital circuitry including at least one first negative edge-triggered flip-flop NF1, a second combinational logic block CL2, and at least one second negative edge-triggered flip-flop NF2.

[0189] The first clock gating unit CGC1 can receive the input clock signal CLK and can stop or resume the supply of the first output clock signal ECK1 based on the first enable signal E1. For example, as referenced above. Figure 1 The first clock gating unit CGC1 can generate a first output clock signal ECK1, which remains at logic "0" in the disabled state. Therefore, the first output clock signal ECK1 can be provided to positive edge triggered flip-flops, such as at least one first positive edge triggered flip-flop PF1 and at least one second positive edge triggered flip-flop PF2. Furthermore, the second clock gating unit CGC2 can receive an input clock signal CLK and can stop or resume the supply of the second output clock signal ECK2 based on the second enable signal E2. For example, as referenced above... Figure 1 The second clock gating unit CGC2 can generate a second output clock signal ECK2, which is held at logic "1" in the disabled state. Therefore, the second output clock signal ECK2 can be provided to a negative edge triggered flip-flop, for example, at least one first negative edge triggered flip-flop NF1 and at least one second negative edge triggered flip-flop NF2.

[0190] Figure 18 This is a flowchart of a method for manufacturing an IC according to an exemplary embodiment of the present invention.

[0191] refer to Figure 18 It is possible to manufacture ICs that include clock gating units as described above (e.g., Figure 17 (of 100).

[0192] In some embodiments of the present invention, the clock gating unit may be a standard cell. A standard cell is a unit of layout included in an integrated circuit IC, and can be simply referred to as a cell. An integrated circuit IC may include multiple different standard cells, each of which can provide a unique function. The standard cell may have a structure that conforms to preset rules based on the semiconductor process used to manufacture the integrated circuit IC. For example, a standard cell may have a specific length or a multiple of a specific length in a plane perpendicular to the layer stacking direction.

[0193] The standard cell library (or cell library) D2 may include information about standard cells, such as functional information, characteristic information, layout information, etc., and may include information about clock-gated cells. As described above with reference to the attached figures, the clock-gated cells defined by the standard cell library D2 can provide not only high operational reliability, but also high efficiency, such as reduced area and low power consumption.

[0194] In operation S10, a logic synthesis operation for generating a netlist D3 from RTL data D1 can be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) can refer to a standard cell library D2 to perform logic synthesis from RTL data D1 constructed in Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and Verilog, thereby generating a netlist D3 including a bitstream or a netlist. The standard cell library D2 may include information about the good performance of clock-gated cells, and standard cells may be included in the integrated circuit IC that references such information during the logic synthesis process.

[0195] In operation S20, placement and routing (P&R) operations can be performed to generate layout data D4 from netlist D3. For example... Figure 18 As shown, the P&R operation S20 may include multiple sub-operations S21, S22, and S23. In sub-operation S21, operations for arranging standard cells can be performed. For example, a semiconductor design tool (e.g., a P&R tool) can refer to a standard cell library D2 to arrange multiple standard cells from a netlist D3. For example, a semiconductor design tool can refer to the standard cell library D2 to arrange the layout of clock-gated cells defined by netlist D3. In sub-operation S22, operations for generating interconnects can be performed. Interconnects can electrically connect output pins to input pins of standard cells and may include, for example, at least one via and at least one conductive pattern. In sub-operation S23, operations for generating layout data D4 can be performed. Layout data D4 may have, for example, a GDSII format and may include geometric information about the standard cells and interconnects.

[0196] In operation S30, optical proximity correction (OPC) can be performed. OPC can refer to the operation of forming a pattern of a desired shape by correcting distortions such as refraction caused by optical properties in photolithography included in the semiconductor process used to manufacture integrated circuit ICs, and the pattern on the mask can be determined by applying OPC to the layout data D4. In some embodiments of the inventive concept, the layout of the integrated circuit IC can be modified to a limited extent in operation S30, and the limited modification of the integrated circuit IC in operation S30 is a post-processing for optimizing the structure of the integrated circuit IC, and can be referred to as design polishing.

[0197] In operation S40, operations for manufacturing masks can be performed. For example, when OPC is applied to layout data D4, the pattern on the mask can be defined to form a pattern to be formed on multiple layers, and at least one mask (or photomask) for forming the corresponding pattern on the multiple layers can be fabricated.

[0198] In operation S50, operations for manufacturing an integrated circuit (IC) can be performed. For example, an IC can be manufactured by patterning multiple layers using at least one mask processed in operation S40. Figure 18 As shown, operation S50 may include sub-operations S51 and S52. In sub-operation S51, a front-end-of-line (FEOL) process may be performed. FEOL process refers to the process of forming individual devices such as transistors, capacitors, and resistors on a substrate during IC manufacturing. For example, FEOL process may include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate lines, and forming source and drain electrodes. In sub-operation S52, a back-end-of-line (BEOL) process may be performed. BEOL process refers to the process of interconnecting individual devices such as transistors, capacitors, and resistors during IC manufacturing. For example, BEOL process may include silanizing the gate, source, and drain regions, adding dielectrics, planarizing, forming vias, adding metal layers, forming through-holes, forming passivation layers, etc. Next, the IC can be packaged in a semiconductor package and used as a component in various applications. As mentioned above, due to the low power consumption characteristics of the clock-gated unit, the IC can exhibit low power consumption and high efficiency, thus improving the efficiency of applications including the IC.

[0199] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made thereto without departing from the spirit and scope of the inventive concept set forth in the appended claims.

Claims

1. A clock gating unit, comprising: The first circuit is configured to receive an enable signal and an inverted output clock signal, and generate a first signal through a first node; The second circuit is configured to receive the first signal and generate an inverted first signal. A third circuit is configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal by being connected to the second node. and A fourth circuit is configured to receive the first signal, connect to the third circuit via the second node to generate the inverted output clock signal, and generate the output clock signal. The third circuit includes a pair of transistors that receive the input clock signal.

2. The clock gating unit according to claim 1, wherein the third circuit includes a first transistor and a second transistor, each receiving the input clock signal. The first transistor is configured to control the charging paths of the first node and the second node based on the input clock signal, and The second transistor is configured to control the discharge paths of the first node and the second node based on the input clock signal.

3. The clock gating unit according to claim 1, wherein the first circuit comprises: The first inverter is configured to generate an inverted enable signal by inverting the enable signal; A first transistor is connected between the power voltage node and the first node, and receives the inverted output clock signal; and The second and third transistors are connected in series between the first node and the ground node. The second transistor receives the inverted enable signal, and The third transistor receives the inverted output clock signal.

4. The clock gating unit according to claim 1, wherein the clock gating unit is configured to also receive a scan enable signal. The first circuit includes a NOR gate configured to receive the enable signal and the scan enable signal and generate a second signal.

5. The clock gating unit according to claim 1, wherein the third circuit comprises: The first transistor is connected between the power voltage node and the third node and is controlled by the inverted first signal; The second transistor is connected between the third node and the first node and is controlled by an inverted enable signal; The third transistor is connected between the second node and the third node and is controlled by the input clock signal; A fourth transistor is connected between the first node and the fourth node and is controlled by the inverted first signal; The fifth transistor is connected between the second node and the fourth node and is controlled by the first signal; and The sixth transistor is connected between the ground node and the fourth node and is controlled by the input clock signal.

6. The clock gating unit according to claim 5, wherein the polarity of the third transistor and the polarity of the sixth transistor are opposite to each other.

7. The clock gating unit of claim 5, wherein the third transistor is configured to control the charging paths of the first node and the second node based on the input clock signal, and The sixth transistor is configured to control the discharge paths of the first node and the second node based on the input clock signal.

8. The clock gating unit according to claim 5, wherein, The second circuit generates a delayed first signal by inverting the inverted first signal, and The fifth transistor is subjected to the first signal with the aforementioned delay.

9. The clock gating unit according to claim 1, wherein the fourth circuit comprises: The first transistor is connected between the power voltage and the second node and is controlled by the first signal; and The first inverter is configured to generate the output clock signal by inverting the inverted output clock signal.

10. The clock gating unit according to claim 9, wherein, The second circuit is configured to generate a delayed first signal by inverting the inverted first signal, and The first transistor is subjected to the first signal with the aforementioned delay.

11. The clock gating unit of claim 10, wherein the fourth circuit further comprises at least one second transistor connected between the power voltage node and the second node and controlled by the input clock signal.

12. The clock gating unit of claim 11, wherein the number of the at least one second transistor corresponds to the number of a plurality of transistors, the plurality of transistors being included in the third circuit and connected between the second node and the ground node.

13. An integrated circuit, comprising a clock gating unit, the clock gating unit receiving at least one control signal and an input clock signal and generating an output clock signal, The clock gating unit includes: A first circuit includes a first functional circuit and a first holding circuit, wherein the first functional circuit is configured to generate a first signal through a first node based on the at least one control signal, and the first holding circuit is configured to hold the voltage level of the first signal. The second circuit is configured to receive the first signal and generate an inverted first signal. The third circuit includes a second functional circuit, a second holding circuit, a first charging circuit, and a discharging circuit. The second functional circuit is configured to generate the first signal through the first node based on the at least one control signal. The second holding circuit is configured to hold the voltage level of the first signal. The first charging circuit is configured to generate an inverted output clock signal by charging the second node based on the first signal. The discharging circuit is configured to discharge the second node. and The fourth circuit, including a second charging circuit, is configured to generate the inverted output clock signal by charging the second node based on the first signal, and The third circuit includes a pair of transistors that receive the input clock signal.

14. The integrated circuit of claim 13, wherein the first holding circuit is input to the inverted output clock signal. The second holding circuit is input with the inverted first signal, and The discharge circuit is input with the first signal.

15. The integrated circuit of claim 13, wherein the polarity of the control signal applied to the first charging circuit and the polarity of the control signal applied to the second charging circuit are opposite to each other.

16. The integrated circuit of claim 15, wherein the first charging circuit comprises a p-type field-effect transistor (PFET) for applying the inverted first signal, and The second charging circuit includes a PFET transistor that applies the first signal.

17. The integrated circuit of claim 14, wherein the third circuit further comprises a first transistor, the first transistor being input to the input clock signal and connected to the first charging circuit and the second charging circuit. When the first transistor is turned on, the second node is charged by the first charging circuit, and When the first transistor is turned off, the second node is charged by the second charging circuit.

18. The integrated circuit of claim 17, wherein the third circuit further comprises a second transistor configured to control the discharge paths of the first node and the second node.

19. A latch circuit, comprising: The first circuit is configured to receive an inverted output clock signal and a data signal, and to generate a first signal through a first node; The second circuit is configured to receive the data signal, the input clock signal, and the output signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal by being connected to the second node. A third circuit is configured to be connected to the second circuit via the second node to generate the inverted output clock signal; and A fourth circuit is configured to receive the first signal and generate an output signal and an inverted output signal. The second circuit includes a pair of transistors that receive the input clock signal.

20. The latch circuit of claim 19, wherein the latch circuit generates the output signal in response to the negative edge of the input clock signal.

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