Display device

Abstract

Disclosed is a display device including a display panel, an input sensor arranged on the display panel, a panel driving circuit that drives the display panel and generates a first driving voltage, and a readout circuit that controls the input sensor. The readout circuit receives the first driving voltage from the panel driving circuit, and outputs a transmission signal that controls the input sensor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0160336, filed on November 25, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure described herein relate to display devices. Background Technology

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet PCs, computers, navigation devices, game consoles, and the like include display devices for displaying images. In addition to general input methods such as buttons, keyboards, mice, or the like, electronic devices may also include display devices capable of providing a touch-based input method that allows users to easily and intuitively input information or commands.

[0005] Today, with the widespread use of portable electronic devices such as mobile phones, the demand for display devices that can minimize power consumption is increasing. Summary of the Invention

[0006] Embodiments of this disclosure provide a display device with reduced power consumption.

[0007] According to one embodiment, the display device includes a display panel, an input sensor disposed on the display panel, a panel driving circuit that drives the display panel and generates a first driving voltage, and a readout circuit that controls the input sensor. The readout circuit receives the first driving voltage from the panel driving circuit and outputs a transmission signal that controls the input sensor.

[0008] In one embodiment, the panel driving circuit may include a driving circuit that outputs control signals and image data signals to the display panel, and a voltage generator that receives input voltage and generates a first driving voltage and a second driving voltage necessary for the operation of the driving circuit.

[0009] In one embodiment, the readout circuit may include a sensor controller that outputs a transmission signal and a sensor voltage generator that receives a first drive voltage and generates a sensor voltage for operation of the sensor controller.

[0010] In an implementation, the first driving voltage may have a voltage level higher than the input voltage.

[0011] In one embodiment, the sensor voltage generator may include a charge pump that receives a first drive voltage and generates an output voltage having a voltage level higher than the first drive voltage, and a regulator that receives the output voltage of the charge pump and outputs the sensor voltage.

[0012] In one implementation, the first driving voltage may be 6V, and the sensor voltage may be 12V.

[0013] In an implementation, the regulator may be a low-dropout (LDO) regulator.

[0014] In one implementation, the readout circuit may include a sensor controller that outputs a transmission signal based on a first drive voltage.

[0015] In one embodiment, the input sensor may be directly mounted on the display panel. The input sensor may include a plurality of first sensing electrodes, a plurality of second sensing electrodes intersecting the plurality of first sensing electrodes, a plurality of first signal lines respectively connected to the plurality of first sensing electrodes, and a plurality of second signal lines respectively connected to the plurality of second sensing electrodes.

[0016] In one implementation, the readout circuit can output a transmit signal to a first signal line and receive a sense signal from a second signal line.

[0017] According to one embodiment, the display device includes a display layer, an input layer disposed on the display layer, a panel driving circuit electrically connected to the display layer, and a readout circuit electrically connected to the input layer. The panel driving circuit includes a voltage generator that generates a first driving voltage and a second driving voltage required for operation of the panel driving circuit. The readout circuit receives the first driving voltage from the voltage generator and outputs a transmission signal to be provided to the input layer.

[0018] In an embodiment, the panel driving circuit may further include a driving circuit that receives a second driving voltage and controls the display layer.

[0019] In an implementation, the readout circuit may include a sensor voltage generator that receives a first drive voltage and generates a sensor voltage, and a sensor controller that receives the sensor voltage and outputs a transmission signal.

[0020] In an implementation, the first driving voltage may have a voltage level higher than the input voltage.

[0021] In one embodiment, the sensor voltage generator may include a charge pump that receives a first drive voltage and generates an output voltage having a voltage level higher than the first drive voltage, and a regulator that receives the output voltage of the charge pump and outputs a sensor voltage.

[0022] In one implementation, the first driving voltage may be 6V, and the sensor voltage may be 12V.

[0023] In this implementation, the regulator may be an LDO regulator.

[0024] In one implementation, the readout circuit may include a sensor controller that outputs a transmission signal based on a first drive voltage.

[0025] In this embodiment, the input layer may be directly disposed on the display layer. The input layer may include a plurality of first sensing electrodes, a plurality of second sensing electrodes intersecting the plurality of first sensing electrodes, a plurality of first signal lines respectively connected to the plurality of first sensing electrodes, and a plurality of second signal lines respectively connected to the plurality of second sensing electrodes.

[0026] In one implementation, the readout circuit can output a transmit signal to a first signal line and receive a sense signal from a second signal line. Attached Figure Description

[0027] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 This is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0030] Figure 3 It is along Figure 2 The cross-sectional view of the display device is shown by line I-I'.

[0031] Figure 4 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0032] Figure 5 This is a plan view of a display panel according to an embodiment of the present disclosure.

[0033] Figure 6 This is a plan view of an input sensor according to an embodiment of the present disclosure.

[0034] Figure 7 This is a diagram illustrating the operation of the input sensor.

[0035] Figure 8 This is a block diagram showing the circuit configuration of the panel driving circuit and the readout circuit.

[0036] Figure 9 This is a block diagram showing the circuit configuration of the sensor voltage generator.

[0037] Figure 10 This is a block diagram illustrating the circuit configuration of the panel driving circuit and the readout circuit according to an embodiment of the present disclosure. Detailed Implementation

[0038] In the specification, when a component (or area, layer, part or the like) is referred to as being “on”, “connected to” or “linked to” another component, it should be understood that the former may be directly on, directly connected to or linked to the latter, and may also be on, connected to or linked to the latter via a third intermediary component.

[0039] Similar reference numerals refer to similar parts. Furthermore, in the accompanying drawings, the thickness, scale, and dimensions of parts are exaggerated for the purpose of effectively describing the technical content. The word "and / or" includes one or more combinations of the associated listed items.

[0040] The terms "first," "second," etc., are used to describe various components, but the components are not limited by the terminology. The terminology is only used to distinguish one component from another. For example, without departing from the spirit or scope of this disclosure, a first component may be named a second component, and vice versa. Unless otherwise stated, the singular form includes the plural form.

[0041] Furthermore, the terms "under," "beneath," "on," and "above" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative and are used with reference to the directions indicated in the drawings.

[0042] It will be understood that the wording “include,” “comprise,” “have,” etc., indicates the presence of the features, quantities, steps, operations, elements or components, or combinations thereof described in the specification, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements or components, or combinations thereof.

[0043] Unless otherwise specified, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0044] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0045] Figure 1 This is a perspective view of a display device DD according to an embodiment of the present disclosure.

[0046] like Figure 1As shown, the display device DD can display the image IM via the display surface DD-IS. The display surface DD-IS is parallel to the surface defined by the first directional axis DR1 and the second directional axis DR2. The normal direction of the display surface DD-IS, that is, the thickness direction of the display device DD, corresponds to the third directional axis DR3.

[0047] The front (or upper) and rear (or lower) surfaces of each part or component described later are divided by a third directional axis DR3. However, the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3 shown in the embodiments are merely examples. Hereinafter, the first to third directions are defined as directions indicated by the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3, respectively. The first to third directions are labeled with the same reference numerals as those used for the first directional axis DR1 to the third directional axis DR3.

[0048] In embodiments of this disclosure, a display device DD is shown, including but not limited to a flat display surface. The display device DD may also include a curved display surface. The display device DD may include a three-dimensional (3D) display surface. The 3D display surface may include multiple display areas facing different directions. For example, the 3D display surface may include a polygonal columnar display surface.

[0049] The display device DD according to embodiments of the present disclosure may be, but is not limited to, a rigid display device. For example, the display device DD according to embodiments of the present disclosure may be a flexible display device. Flexible display devices may include foldable display devices, bent-type display devices with partial bending, or sliding display devices.

[0050] In the implementation, Figure 1 A display device DD suitable for mobile phone terminals is shown. Although in Figure 1 Not shown, but a mobile phone terminal can be implemented by arranging electronic modules, camera modules, power modules, and similar modules mounted on the motherboard together with the display device DD in a bracket / housing. According to embodiments of this disclosure, the display device DD can be applied to small and medium-sized electronic devices such as tablet PCs, vehicle navigation systems, game consoles, smartwatches, or the like, as well as large electronic devices such as televisions, monitors, or the like.

[0051] like Figure 1 As shown, the display surface DD-IS includes an image area DD-DA displaying the image IM and a border area DD-NDA adjacent to the image area DD-DA. The border area DD-NDA refers to the area where no image is displayed. Figure 1 The image shows a clock and icon as an example of an image IM.

[0052] like Figure 1 As shown, the image region DD-DA may have a substantially rectangular shape. "Substantially rectangular shape" includes not only mathematically defined rectangular shapes, but also rectangular shapes that define the boundaries of curves but do not define the vertices in the vertex region (or corner region).

[0053] The border area DD-NDA may surround the image area DD-DA, but is not limited to this. For example, the image area DD-DA and the border area DD-NDA may be designed with different shapes. The border area DD-NDA may be arranged only on one side of the image area DD-DA. Depending on the combination of the display device DD and another component of the electronic device (not shown), the border area DD-NDA may not be exposed to the outside.

[0054] The display device DD according to embodiments of the present disclosure can detect externally applied user input TC. User input TC can be applied by one or a combination of various external inputs, such as a part of the user's body, an instrument such as a stylus, and the like. The display device DD can detect user input TC by detecting changes in one or a combination of reflected light, temperature, pressure, ultrasound, and electromagnetic fields in response to the user input TC. In this embodiment, although it is assumed that the user input TC is a touch input applied by the user's hand to the front surface of the display device DD, this input scheme for user input TC is an example. As described above, various input schemes can be used to provide user input TC. Furthermore, depending on the structure of the display device DD, the display device DD can detect user input TC applied to the side or bottom surface of the display device DD, and is not limited to this embodiment.

[0055] Figure 2 This is an exploded perspective view of a display device DD according to an embodiment of the present disclosure.

[0056] Reference Figure 2 The display device DD may include a window WP, an anti-reflective panel (anti-reflector) RPP, a display module DM, and a housing HU. For example... Figure 1 and Figure 2 As shown, in an embodiment, the appearance of the display device DD can be formed by connecting the window WP and the housing HU.

[0057] The window WP protects the upper surface of the display panel DP. The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The window WP may include a multilayer structure or a single-layer structure. For example, the window WP may include multiple plastic films bonded by adhesive, or it may include a glass substrate and plastic films bonded by adhesive.

[0058] An anti-reflective panel RPP can be disposed below the window WP. The anti-reflective panel RPP reduces the reflectivity of external light incident from the upper surface of the window WP. In embodiments of this disclosure, the anti-reflective panel RPP may be omitted or may be embedded in the display module DM.

[0059] The display module DM can display an image IM and detect external input. The display module DM may include a display panel DP, an input sensor IS, and a printed circuit board FCB.

[0060] The display panel DP can be limited to the same as Figure 1 The effective region AA corresponding to the image region DD-DA shown in the figure and the region with Figure 1 The border area DD-NDA shown corresponds to the outer region NAA. The display panel DP can essentially generate the image IM (refer to...). Figure 1 The configuration of the image IM generated in the effective area AA of the display panel DP is perceived visually by the user from the outside through the window WP.

[0061] The input sensor IS detects external input applied from the outside. As described above, the input sensor IS can detect external input provided to the window WP.

[0062] The display panel DP may include a pad area PP. Multiple signal pads DP-PD and IS-PD (see reference) may be arranged in the pad area PP of the display panel DP. Figure 5 The display panel DP can be electrically connected to the printed circuit board FCB via pads. In one embodiment, a driver chip that generates signals necessary for the operation of the display panel DP can be installed in the pad area PP.

[0063] The printed circuit board (FCB) may include various drive circuits for driving the display panel (DP) and the input sensor (IS), connectors for power supply, or the like. In one embodiment, the FCB may include a panel drive circuit (PDC) for driving the display panel (DP) and a readout circuit (ROC) for driving the input sensor (IS).

[0064] The panel driver circuit PDC can be electrically connected to the display panel DP to control the display panel DP. The readout circuit ROC can be electrically connected to the input sensor IS to control the input sensor IS.

[0065] Each of the panel driver circuit PDC and the readout circuit ROC can be formed as an integrated circuit and can be mounted on a printed circuit board FCB. In an embodiment, the panel driver circuit PDC and the readout circuit ROC can be integrated into a single integrated circuit. The panel driver circuit PDC may be referred to as a "drive controller," "timing controller," "master controller," or similar names. The readout circuit ROC may be referred to in various ways as an "input driver circuit," "sensor driver circuit," and "touch driver circuit."

[0066] The housing HU includes a bottom portion BP and side walls SW. The side walls SW extend from the bottom portion BP. The housing HU can accommodate a display panel DP within a receiving space defined by the bottom portion BP and the side walls SW. A window WP can be connected to the side walls SW of the housing HU. The side walls SW of the housing HU can support the exterior of the window WP.

[0067] The housing HU may comprise a material with relatively high rigidity. For example, the housing HU may comprise glass, plastic, or metal, or may comprise multiple frames and / or multiple panels composed of combinations thereof. The housing HU stably protects the components of the display device DD housed within its internal space from external impacts.

[0068] Figure 3 It is along Figure 2 The cross-sectional view of the display device DD is shown by line I-I'.

[0069] Figure 3 A cross-section of the display device DD, defined by the first directional axis DR1 and the third directional axis DR3, is shown. Figure 3 The components of the display device DD are shown in a simple explanation of their stacking relationship.

[0070] According to embodiments of this disclosure, the display device DD may include a display panel DP, an input sensor IS, an anti-reflective panel RPP, and a window WP. At least a portion of the components among the display panel DP, input sensor IS, anti-reflective panel RPP, and window WP may be formed in a continuous process. Alternatively, at least a portion of the components may be joined together by adhesive members. In one embodiment, the input sensor IS and the anti-reflective panel RPP may be joined together by adhesive member AD1. The anti-reflective panel RPP and the window WP may be joined together by adhesive member AD2.

[0071] Each of adhesive components AD1 and AD2 may refer to a transparent adhesive component, such as a pressure-sensitive adhesive (PSA) film, an optically clear adhesive (OCA) film, or an optically clear resin (OCR). Adhesive components described later may include general-purpose adhesives or pressure-sensitive adhesives. In embodiments of this disclosure, the anti-reflective panel RPP and window WP may be replaced with other components or may be omitted.

[0072] exist Figure 3 In this embodiment, the input sensor IS, anti-reflective panel RPP, and window WP, formed together with the display panel DP via a continuous process, are directly disposed on the display panel DP. In this specification, "component B is directly disposed on component A" means that no separate adhesive layer / adhesive member is inserted between component A and component B. Component B is formed via a continuous process on the substrate surface provided by component A after component A is formed.

[0073] In one embodiment, each of the antireflective panel RPP and window WP is of the "panel" type, and the input sensor IS is of the "layer" type. A "panel" type component includes a substrate layer providing a base surface, such as a synthetic resin film, composite film, glass substrate, or the like. However, the substrate layer may be omitted in a "layer" type component. In other words, a "layer" type component is disposed on a base surface provided by another component. In another embodiment of this disclosure, the antireflective panel RPP and window WP may be of the "layer" type. In another embodiment, the display panel DP may be of the "layer" type. In other words, the display panel DP may be referred to as the "display layer," and the input sensor IS may be referred to as the "sensor layer."

[0074] The display panel (DP) generates an image, and the input sensor (IS) acquires the coordinate information of external inputs (e.g., touch events). Although in Figure 3 Not shown separately, but the display device DD according to embodiments of the present disclosure may further include a protective member disposed on the lower surface (or bottom surface) of the display panel DP. The protective member and the display panel DP may be joined by an adhesive member.

[0075] The display panel DP according to embodiments of this disclosure may be, but is not particularly limited to, a light-emitting display panel. In embodiments, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The panel is distinguished according to the material of the light-emitting element. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and / or quantum rods. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0076] The anti-reflective panel RPP reduces the reflectivity of external light incident from the upper surface of the window WP. An anti-reflective panel RPP according to embodiments of this disclosure may include a retarder and a polarizer. The retarder may be of a film type or a liquid crystal coating type. The polarizer may also be of a film type or a liquid crystal coating type. A film-type panel may include a stretched synthetic resin film, and a liquid crystal coating-type panel may include liquid crystals arranged in a predetermined array. Each of the retarder and polarizer may also include a protective film. The retarder and polarizer themselves may define a base layer of the anti-reflective panel RPP. Alternatively, the protective film may define a base layer of the anti-reflective panel RPP.

[0077] An anti-reflective panel RPP according to an embodiment of the present disclosure may include color filters. The color filters have a predetermined array. The array of color filters can be determined by taking into account the emission colors of the pixels included in the display panel DP. The anti-reflective panel RPP may also include a black matrix adjacent to the color filters.

[0078] An anti-reflective panel RPP according to embodiments of the present disclosure may include a destructive interference structure. In an embodiment, the destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers from each other. First reflected light and second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may destructively interfere with each other, thereby reducing the reflectivity of external light.

[0079] A window WP according to embodiments of this disclosure may include a glass substrate and / or a synthetic resin film. The window WP is not limited to a single layer. A window WP may include two or more films bonded together by adhesive members. Although in Figure 3 Not shown separately, but the window WP may also include a functional coating. The functional coating may include an anti-fingerprint layer, an anti-reflective layer, a hard coating, and similar layers.

[0080] The input sensor IS and the display panel DP will be described in detail later.

[0081] Figure 4 This is a cross-sectional view of a display device DD according to an embodiment of the present disclosure.

[0082] Reference Figure 4 The display panel DP includes a substrate layer 110. At least one inorganic layer is formed on the upper surface of the substrate layer 110. The inorganic layer may include at least one selected from aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In an embodiment, the display panel DP is shown to include a buffer layer BFL.

[0083] The buffer layer BFL can improve the bonding strength between the substrate layer 110 and the semiconductor pattern. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0084] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor patterns may include, but are not limited to, polycrystalline silicon. For example, the semiconductor patterns may include amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductors.

[0085] Figure 4Only a portion of the semiconductor pattern is shown, and the semiconductor pattern may also be arranged in another region. The semiconductor pattern may be arranged according to a specific rule throughout the pixel. The semiconductor pattern may have different electrical properties depending on whether the semiconductor pattern is doped. The semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type dopant or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region may be an undoped region, or it may be a region doped at a lower concentration than the first region.

[0086] The conductivity of the first region is greater than that of the second region. The first region can function essentially as an electrode or signal line. The second region can essentially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of a transistor. Another portion can be the source or drain of a transistor. Yet another portion can be a connecting electrode or a connecting signal line.

[0087] The display panel DP may include multiple pixels PX (see reference). Figure 5 In an implementation, each of the pixels PX may include multiple transistors, capacitors, and light-emitting elements. Figure 4 The diagram shows only one transistor TR among multiple transistors and the light-emitting element ED included in each of the pixels PX.

[0088] The source (SC), active region (AL), and drain (DR) of a transistor (TR) can be formed using a semiconductor pattern. The source (SC) and drain (DR) can extend from the active region (AL) in opposite directions in a cross-section. A portion of the connection signal wiring (SCL) formed using the semiconductor pattern is... Figure 4 As shown in [the image]. Although in [the image] Figure 4 Not shown separately, but the connection signal wiring SCL can be electrically connected to the drain DR of transistor TR in the plan view.

[0089] A first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with multiple pixels in a common manner and may cover a semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only can the first insulating layer 10 be an inorganic layer and / or an organic layer, but the insulating layer of the circuit layer 120, which will be described later, may also be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0090] A gate GT of a transistor TR is disposed on the first insulating layer 10. The gate GT may be part of a metal pattern. The gate GT vertically overlaps with the active region AL. In a process of doping semiconductor patterns, the gate GT may be used as a mask.

[0091] A second insulating layer 20 is disposed on the first insulating layer 10 and may cover the gate GT. The second insulating layer 20 may commonly overlap with the pixel. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0092] A third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single-layer structure or a multi-layer structure. In an embodiment, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0093] A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the connection signal wiring SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0094] A fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0095] A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0096] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0097] A light-emitting element layer 130 may be disposed on the circuit layer 120. The light-emitting element layer 130 may include a light-emitting element ED. In embodiments, the light-emitting element layer 130 may include organic light-emitting materials, quantum dots, micro LEDs, or nano LEDs. Hereinafter, the light-emitting element ED is described as an organic light-emitting element, but is not particularly limited thereto.

[0098] The light-emitting element ED may include a first electrode AE, a light-emitting layer EL, and a second electrode CE.

[0099] The first electrode AE ​​can be disposed on the sixth insulating layer 60. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the contact hole CNT-3 passing through the sixth insulating layer 60.

[0100] A pixel defining film 70 may be disposed on a sixth insulating layer 60 and may cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining film 70. The opening 70-OP of the pixel defining film 70 exposes at least a portion of the first electrode AE.

[0101] Figure 2 The effective area AA shown may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA. In an embodiment, the light-emitting area PXA is defined to correspond to a portion of the first electrode AE ​​exposed by the opening 70-OP.

[0102] A light-emitting layer EL can be disposed on a first electrode AE. The light-emitting layer EL can be disposed in the region corresponding to the opening 70-OP. That is, the light-emitting layer EL can be formed individually in each of the plurality of pixels. When the light-emitting layer EL is formed individually in each of the plurality of pixels, each of the plurality of light-emitting layers EL can emit light of at least one color selected from blue, red, and green. However, this disclosure is not limited thereto, and the light-emitting layers EL can be continuous and publicly provided to each of the plurality of pixels. In this case, the light-emitting layer EL can provide blue light or white light.

[0103] The second electrode CE can be disposed on the light-emitting layer EL. The second electrode CE can be disposed together in multiple pixels.

[0104] Despite Figure 4 Not shown, but a hole control layer may be inserted between the first electrode AE ​​and the light-emitting layer EL. The hole control layer may be commonly arranged in the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer may be inserted between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer. Using an aperture mask, the hole control layer and the electron control layer may be commonly formed in multiple pixels.

[0105] An encapsulation layer 140 may be disposed on the light-emitting element layer 130. The encapsulation layer 140 may include inorganic layers, organic layers and inorganic layers stacked in sequence, but the layers constituting the encapsulation layer 140 are not limited to these.

[0106] The inorganic layer protects the light-emitting element layer 130 from moisture and oxygen; the organic layer protects the light-emitting element layer 130 from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or similar layers. The organic layer may include, but is not limited to, an acrylic-based organic layer.

[0107] The input sensor IS may include a substrate layer 201, a first conductive layer 202, a detection insulating layer 203, a second conductive layer 204, and a cover insulating layer 205.

[0108] The substrate 201 may be an inorganic layer comprising at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the substrate 201 may be an organic layer comprising epoxy resin, acrylic resin, or imide resin. The substrate 201 may have a monolayer structure or may have a multilayer structure stacked on a third-direction DR3.

[0109] Each of the first conductive layer 202 and the second conductive layer 204 may have a single-layer structure or may have a multi-layer structure stacked on the third-direction DR3.

[0110] The conductive layer of a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium zinc tin oxide (IZTO), or the like. Furthermore, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, graphene, and the like.

[0111] The conductive layer in a multilayer structure may include a metal layer. In one embodiment, the metal layer may have a titanium / aluminum / titanium three-layer structure. The conductive layer in a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0112] The detection of at least one of the insulating layer 203 and the covering insulating layer 205 may include an inorganic film. The inorganic film may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0113] The detection of at least one of the insulating layer 203 and the covering insulating layer 205 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and naphthyl resin.

[0114] Figure 5 This is a plan view of a display panel DP according to an embodiment of the present disclosure.

[0115] like Figure 5 As shown, the display panel DP may include a scan drive circuit SDC, multiple signal lines (hereinafter referred to as "signal lines") SGL, multiple signal pads (hereinafter referred to as "signal pads") DP-PD and IS-PD, and multiple pixels (hereinafter referred to as "pixels") PX.

[0116] The scan drive circuit SDC generates multiple scan signals (hereinafter referred to as "scan signals") and sequentially outputs them to multiple scan lines (hereinafter referred to as "scan lines") SL, which will be described later. The scan drive circuit SDC can output not only scan signals to pixel PX, but also other control signals to pixel PX.

[0117] The scan drive circuit SDC may include multiple transistors formed using the same process as that used to form the transistors in the pixel PX.

[0118] The signal line SGL may include scan lines SL, data lines DL, power lines PL, emission control lines EML, and control signal lines CSL. Each scan line SL is connected to a corresponding pixel PX among pixels PX; each data line DL is connected to a corresponding pixel PX among pixels PX; and each emission control line EML is connected to a corresponding pixel PX among pixels PX. The power line PL is connected to a common ground with multiple pixels PX. The control signal line CSL provides control signals to the scan drive circuit SDC. The power line PL provides the voltage necessary for the operation of pixels PX. The power line PL may include multiple lines that provide different voltages to each other.

[0119] In an implementation, the signal line SGL may further include auxiliary lines SSL. Each of the auxiliary lines SSL refers to a signal line electrically connected to the input sensor IS (see reference). Figure 6 In embodiments of this disclosure, the auxiliary lines SSL may be omitted. Multiple auxiliary lines SSL are respectively connected to multiple contact holes CNT. The auxiliary lines SSL can be electrically connected via the contact holes CNT to the signal lines of the input sensor IS, described later (see reference). Figure 6 ).

[0120] Signal pads DP-PD and IS-PD may include a first type of signal pad DP-PD connected to data line DL, power line PL, and control signal line CSL, and a second type of signal pad IS-PD connected to auxiliary line SSL. The first type of signal pad DP-PD and the second type of signal pad IS-PD are arranged adjacent to each other in a pad area PP defined in a portion of the peripheral area NAA. The stacking structure of the first type of signal pad DP-PD is no different from that of the second type of signal pad IS-PD; furthermore, the structural material of the first type of signal pad DP-PD is no different from that of the second type of signal pad IS-PD. The first type of signal pad DP-PD and the second type of signal pad IS-PD can be formed using the same process.

[0121] The effective area AA can be defined as the area where pixels PX are arranged. Multiple electronic components are arranged in the effective area AA. The electronic components include an organic light-emitting diode included in each of the pixels PX and a pixel driving circuit connected to the organic light-emitting diode.

[0122] Despite Figure 5 Not shown, but each of the pixels PX may include multiple transistors, capacitors, and organic light-emitting diodes. The pixel PX is electrically connected to the scan line SL, data line DL, light emission control line EML, and power line PL, and emits light in response to signals received through the scan line SL, data line DL, light emission control line EML, and power line PL.

[0123] The first type signal pad DP-PD and the second type signal pad IS-PD of the display panel DP can be electrically connected to Figure 2 The printed circuit board FCB shown in the figure.

[0124] Figure 5 A portion of the display panel DP shown is bendable. A portion of the peripheral region NAA of the display panel DP is bendable and can be bent about a bending axis parallel to the first direction DR1. The bending axis may be defined to overlap with a portion of the control signal line CSL, a portion of the data line DL, and a portion of the auxiliary line SSL.

[0125] Figure 6 This is a plan view of the input sensor IS according to an embodiment of the present disclosure.

[0126] Reference Figure 6 The input sensor IS may include a sensing area SA and a non-sensing area NSA. The sensing area SA may be an area activated based on an electrical signal. In an embodiment, the sensing area SA may be the area that senses the input. The non-sensing area NSA may surround the sensing area SA. The sensing area SA may correspond to... Figure 5The effective area AA, and the non-sensing area NSA can correspond to Figure 5 The outer region NAA.

[0127] The input sensor IS includes first sensing electrodes SA1 to SA14 and second sensing electrodes SB1 to SB10 formed on a substrate layer 201. The first sensing electrodes SA1 to SA14 and the second sensing electrodes SB1 to SB10 are arranged in a sensing region SA. The first sensing electrodes SA1 to SA14 and the second sensing electrodes SB1 to SB10 are electrically insulated from each other and intersect within the sensing region SA. In embodiments of this disclosure, the input sensor IS includes first sensing electrodes SA1 to SA14 and second sensing electrodes SB1 to SB10, but this disclosure is not limited thereto. The number of first sensing electrodes and the number of second sensing electrodes may vary. Figure 6 The diagram shows that the number of first sensing electrodes is greater than the number of second sensing electrodes. However, in another embodiment, the number of second sensing electrodes may not be less than the number of first sensing electrodes.

[0128] The input sensor IS can obtain position information related to external input by the change in mutual capacitance between the first sensing electrodes SA1 to SA14 and the second sensing electrodes SB1 to SB10.

[0129] The input sensor IS may further include first transmit lines TL1 to fourteenth transmit lines TL14 and first receive lines RL1 to tenth receive lines RL10. The first transmit lines TL1 to fourteenth transmit lines TL14 and the first receive lines RL1 to tenth receive lines RL10 may be arranged in the non-sensing region NSA. The first transmit lines TL1 to fourteenth transmit lines TL14 are electrically connected to the sides of the first sensing electrodes SA1 to SA14, respectively. The first receive lines RL1 to tenth receive lines RL10 are electrically connected to the sides of the second sensing electrodes SB1 to SB10, respectively. However, this disclosure is not limited thereto. In embodiments of this disclosure, the input sensor IS may further include receive lines electrically connected to other sides of the second sensing electrodes SB1 to SB10, respectively.

[0130] One of the intersections of the first sensing electrodes SA1 to SA14 and the second sensing electrodes SB1 to SB10 can be defined as a sensing unit SU.

[0131] The first transmitting line TL1 to the fourteenth transmitting line TL14 and the first receiving line RL1 to the tenth receiving line RL10 can be electrically connected via contact hole CNT. Figure 5 The auxiliary line SSL is shown.

[0132] Figure 7 This is a diagram illustrating the operation of the input sensor IS. Figure 7 yes Figure 6 An enlarged view of region A1 in the image.

[0133] Reference Figure 6 and Figure 7 Each of the first sensing electrodes SA1 to SA14 can function as a transmitting electrode. Each of the second sensing electrodes SB1 to SB10 can function as a receiving electrode. The readout circuit ROC can detect external input by detecting the change in mutual capacitance formed between the first sensing electrodes SA1 to SA14 and the second sensing electrodes SB1 to SB10.

[0134] For ease of description, Figure 7 Only shown Figure 6 The first sensing electrodes SA1 and SA2 among the first sensing electrodes SA1 to SA14 shown herein, and Figure 6 The second sensing electrodes SB1 and SB2 are shown among the second sensing electrodes SB1 to SB10. Figure 6 The first sensing electrodes SA3 to SA14 shown in the figure and Figure 6 The second sensing electrodes SB3 to SB10 shown can also be driven in the same manner as the first sensing electrodes SA1 and SA2 and the second sensing electrodes SB1 and SB2.

[0135] The readout circuit ROC provides transmit signals TX1 and TX2 to the first sensing electrodes SA1 and SA2, respectively. The readout circuit ROC receives sensing signals RX1 and RX2 from the second sensing electrodes SB1 and SB2, respectively. Therefore, the readout circuit ROC compares the transmit signals TX1 and TX2 with the sensing signals RX1 and RX2 corresponding to the transmit signals TX1 and TX2, respectively, and can generate a reading based on the changes in the sensing signals RX1 and RX2, for the user input TC (see reference). Figure 1 The coordinates of the position.

[0136] Figure 8 This is a block diagram showing the circuit configuration of the panel driver circuit PDC and the readout circuit ROC.

[0137] Reference Figure 8 The panel driving circuit PDC includes a driving circuit 300 and a voltage generator 310.

[0138] The drive circuit 300 can output the display panel DP to be passed (refer to...) Figure 5 The control signal line CSL provides the control signal CTRL to the scan drive circuit SDC and the data signal DATA to be provided to the data line DL. In an embodiment, the drive circuit 300 may output the control signal CTRL and the data signal DATA based on signals provided from the host (or application processor (AP)) (not shown).

[0139] Voltage generator 310 can receive an input voltage VIN from an external source and can generate the voltage necessary for the operation of the panel drive circuit PDC. Voltage generator 310 can generate a first drive voltage VD1 necessary for the operation of the readout circuit ROC. Voltage generator 310 can generate a second drive voltage VD2 required by the drive circuit 300 in the panel drive circuit PDC. The second drive voltage VD2 can include various voltages. In an embodiment, the second drive voltage VD2 can include voltages to be provided to the scan drive circuit SDC (see reference). Figure 5 The high level of the clock signal corresponds to a high gate voltage, and the low level of the clock signal corresponds to a low gate voltage. Furthermore, the voltage generator 310 can also output the voltage to be supplied to... Figure 5 The voltage of the pixels PX of the display panel DP shown.

[0140] although Figure 8 Not shown, but the input voltage VIN can be a voltage supplied by an external power source or battery. In another embodiment, although... Figure 8 Not shown, but the input voltage VIN can be a voltage generator such as a DC-DC converter or a power management integrated circuit (PMIC) located in the printed circuit board FCB.

[0141] The readout circuit ROC includes a sensor controller 400 and a sensor voltage generator 410. The sensor controller 400 can output the voltage to be supplied to... Figure 6 The first sensing electrodes SA1 to SA14 shown transmit signals TX1 to TX14, and can receive sensing signals RX1 to RX10 from the second sensing electrodes SB1 to SB10.

[0142] The sensor voltage generator 410 receives a first drive voltage VD1 from the panel drive circuit PDC and generates the sensor voltage VS required for the operation of the readout circuit ROC. In this embodiment, the sensor voltage VS can generate the voltage required for the sensor controller 400 to transmit signals TX1 to TX14.

[0143] Each of the transmitted signals TX1 to TX14 may be a pulse wave signal that oscillates between high and low voltage. In an embodiment, the high voltage of each of the transmitted signals TX1 to TX14 may be a high voltage of 12V.

[0144] The sensor voltage generator 410 can receive voltage supplied from a voltage generator (not shown) such as a DC-DC converter or PMIC disposed on the printed circuit board FCB. When the voltage supplied by the voltage generator disposed on the printed circuit board FCB is a low voltage of 1.7V, 3.3V or similar value, the sensor voltage generator 410 needs to include two or more charge pumps to generate a high voltage of 12V.

[0145] In one embodiment, the sensor voltage generator 410 may include a first charge pump and a second charge pump. The first charge pump receives a 3.3V voltage from a voltage generator disposed on a printed circuit board FCB and outputs a 5.5V output voltage. The second charge pump receives the 5.5V output voltage from the first charge pump and generates a high voltage of 12V.

[0146] In this paper, the power consumption of the first charge pump can be approximately 300 microwatts (μW), and the power consumption of the second charge pump can be 970 μW. The total power consumption of the sensor voltage generator 410, including the two charge pumps, can be 1270 μW.

[0147] In one embodiment, the sensor voltage generator 410 receives a first drive voltage VD1 generated by the voltage generator 310 in the panel driving circuit PDC. The first drive voltage VD1 output from the voltage generator 310 may have a voltage level higher than the input voltage VIN. In one embodiment, the first drive voltage VD1 may be 6V.

[0148] As described above, voltage generator 310 may include generating voltage to be supplied to scan drive circuit SDC (refer to...). Figure 5 The high level of the clock signal corresponds to a regulator and / or charge pump with a high gate voltage. Therefore, the voltage generator 310 may not require a separate charge pump to generate the first drive voltage VD1, and may output one of the second drive voltages VD2 as the first drive voltage VD1. That is, the first drive voltage VD1 may have the same voltage level as one of the second drive voltages VD2.

[0149] In one embodiment, voltage generator 310 can generate a first drive voltage VD1 having a voltage level suitable for sensor voltage generator 410 by using one of the second drive voltages VD2. In another embodiment, the first drive voltage VD1 may have a lower voltage level than one of the second drive voltages VD2.

[0150] Figure 9 This is a block diagram showing the circuit configuration of the sensor voltage generator 410.

[0151] Reference Figure 9 The sensor voltage generator 410 includes a charge pump 411 and a regulator 412. The charge pump 411 increases the voltage level of the first drive voltage VD1 and outputs an output voltage VOUT. Therefore, the output voltage VOUT output from the charge pump 411 has a higher voltage level than the first drive voltage VD1.

[0152] Regulator 412 receives the output voltage VOUT from charge pump 411 and outputs the sensor voltage VS. Even with changes in load current, regulator 412 can maintain a uniform voltage level of the sensor voltage VS. In an embodiment, regulator 412 can be implemented using a low dropout (LDO) regulator. Due to its low power consumption and low voltage drop, the LDO regulator is suitable as a linear regulator for portable electronic devices.

[0153] like Figure 9 As shown, the sensor voltage generator 410 uses data from... Figure 8 The voltage generator 310 in the panel driving circuit PDC shown outputs a first driving voltage VD1 to generate the sensor voltage VS, and therefore only a single charge pump 411 is required. Thus, the display device DD (refer to...) Figure 1 The power consumption can be minimized.

[0154] Figure 10 This is a block diagram illustrating the circuit configuration of the panel driver circuit PDC and the readout circuit ROC-1 according to an embodiment of the present disclosure.

[0155] Reference Figure 10 The panel driving circuit PDC includes a driving circuit 300 and a voltage generator 310. Figure 10 The drive circuit 300 and voltage generator 310 shown have the same characteristics as... Figure 8 The drive circuit 300 and voltage generator 310 shown have the same circuit configuration, and are configured in the same way as... Figure 8 The drive circuit 300 and voltage generator 310 shown operate in the same manner. Therefore, the same reference numerals / labels are used, and redundant descriptions are omitted.

[0156] The readout circuit ROC-1 includes a sensor controller 405. The sensor controller 405 receives a first drive voltage VD1 from the panel drive circuit PDC and can output voltages to be supplied to... Figure 6 The first sensing electrodes SA1 to SA14 shown transmit signals TX1 to TX14, and can receive sensing signals RX1 to RX10 from the second sensing electrodes SB1 to SB10 respectively.

[0157] because Figure 10 The readout circuit ROC-1 shown does not include a charge pump, so the sensor controller 405 receives the first drive voltage VD1 from the panel drive circuit PDC.

[0158] As described above, each of the transmitted signals TX1 to TX14 can be a pulse wave signal that oscillates between high and low voltages. When the high voltage of each of the transmitted signals TX1 to TX14 is, for example, 6V, the readout circuit ROC-1 may not require a separate charge pump.

[0159] In this configuration, the sensor controller 405 in the readout circuit ROC-1 can directly receive the first drive voltage VD1 from the panel drive circuit PDC. The readout circuit ROC-1 does not include a charge pump, thus minimizing power consumption compared to readout circuits with one or two charge pumps.

[0160] The readout circuit of the display device with the above configuration can generate the sensor voltage using the drive voltage generated by the panel driving circuit. The readout circuit minimizes the number of charge pumps required to generate the sensor voltage. Therefore, the circuit configuration of the readout circuit can be simple, and the power consumption of the readout circuit can be reduced.

[0161] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: Display panel; An input sensor is arranged on the display panel; A panel driving circuit, wherein the panel driving circuit drives the display panel and generates a first driving voltage; as well as The readout circuit controls the input sensor. The readout circuit receives the first driving voltage from the panel driving circuit and outputs a transmission signal to control the input sensor. The readout circuit includes: Sensor controller, the sensor controller outputting the transmitted signal; and A sensor voltage generator receives the first drive voltage and generates a sensor voltage for the operation of the sensor controller.

2. The display device according to claim 1, wherein, The panel driving circuit includes: A driving circuit that outputs control signals and image data signals to the display panel; and A voltage generator that receives an input voltage and generates a first drive voltage and a second drive voltage necessary for the operation of the drive circuit.

3. The display device according to claim 2, wherein, The first driving voltage has a voltage level higher than the input voltage.

4. The display device according to claim 3, wherein, The sensor voltage generator includes: A charge pump that receives the first driving voltage and generates an output voltage having a voltage level higher than the first driving voltage; and A regulator that receives the output voltage of the charge pump and outputs the sensor voltage.

5. The display device according to claim 4, wherein, The first driving voltage is 6V, and The sensor voltage is 12V.

6. The display device according to claim 4, wherein, The regulator is a low differential pressure regulator.

7. The display device according to claim 1, wherein, The readout circuit includes: A sensor controller that outputs the transmitted signal based on the first driving voltage.

8. The display device according to claim 1, wherein, The input sensor is directly mounted on the display panel, and The input sensor includes: Multiple first sensing electrodes; A plurality of second sensing electrodes, wherein the plurality of second sensing electrodes intersect with the plurality of first sensing electrodes; A plurality of first signal lines, the plurality of first signal lines being respectively connected to the plurality of first sensing electrodes; and A plurality of second signal lines are respectively connected to the plurality of second sensing electrodes.

9. A display device, comprising: Display layer; An input layer is disposed on the display layer; A panel driving circuit, which is electrically connected to the display layer; as well as The readout circuit is electrically connected to the input layer. The panel driving circuit includes a voltage generator that receives an input voltage and generates a first driving voltage and a second driving voltage required for the operation of the panel driving circuit. The readout circuit receives the first driving voltage from the voltage generator and outputs a transmission signal to be provided to the input layer. The readout circuit includes: Sensor controller, the sensor controller outputting the transmitted signal; and A sensor voltage generator receives the first drive voltage and generates a sensor voltage for the operation of the sensor controller.

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