Bus arbitration circuit and data transmission system comprising the same

Abstract

The present invention provides a bus arbitration circuit and a data transmission system including the same, which do not reduce the transmission speed of a bus. The present invention includes a first bus terminal connected to a host bus, a second bus terminal connected to a local bus, a first output circuit having an output terminal connected to the first bus terminal, a second output circuit having an output terminal connected to the second bus terminal, a control circuit including a first input terminal into which data of the first bus terminal is input, a second input terminal into which data of the second bus terminal is input, a control signal output terminal, and an output terminal that outputs data to an input terminal of the first output circuit, and a switch circuit having an input terminal connected to the first bus terminal, a control terminal connected to the control signal output terminal of the control circuit, and an output terminal that outputs data of the host bus to an input terminal of the second output circuit.

Description

Technical Field

[0001] This invention relates to a bus arbitration circuit and a data transmission system including the same. Background Technology

[0002] A known data transmission system is a system that transmits data between a master integrated circuit (IC) and multiple slave ICs via the I2C bus, which serves as a serial data bus.

[0003] Figure 3 This is a block diagram representing a data transmission system based on the I2C protocol.

[0004] In the data transmission system 200, the master IC 230 is connected to multiple slave ICs 231 to 237 via two bus lines, serial data line 210 and clock line 220, and data transmission according to the I2C protocol is performed using these bus lines (for example, see Patent Document 1).

[0005] However, the data transmission system based on the I2C protocol was developed as a simple internal bus system, and therefore a multi-layered system with a host bus and a local bus was not conceived.

[0006] [Existing Technical Documents]

[0007] [Patent Literature]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2002-189697 Summary of the Invention

[0009] [The problem the invention aims to solve]

[0010] Multilayer systems include a bus arbitration circuit between the host bus and the local buses. This bus arbitration circuit typically includes a transmission gate, which acts as a bidirectional switch connecting the host bus and the local buses. However, since the transmission gate is closed during arbitration, slave ICs connected directly to each local bus are connected to the host bus. Therefore, an increase in the number of slave ICs in the overall system leads to a decrease in bus data transfer speed.

[0011] The present invention was made in view of the aforementioned problems, and its object is to provide a bus arbitration circuit that does not reduce the bus transmission speed.

[0012] [Technical means to solve the problem]

[0013] The bus arbitration circuit of the present invention is characterized by comprising: a first bus terminal connected to the host bus; a second bus terminal connected to the local bus; a first output circuit with an output terminal connected to the first bus terminal; a second output circuit with an output terminal connected to the second bus terminal; a control circuit including a first input terminal, a second input terminal, a control signal output terminal, and an output terminal, wherein data from the first bus terminal is input at the first input terminal, data from the second bus terminal is input at the second input terminal, and data is output from the output terminal to the input terminal of the first output circuit; and a switching circuit with an input terminal connected to the first bus terminal, a control terminal connected to the control signal output terminal of the control circuit, and data from the host bus being output from the output terminal to the input terminal of the second output circuit.

[0014] [The effects of the invention]

[0015] According to the present invention, a bus arbitration circuit can be provided, wherein since a switching circuit and an output circuit are used in the output from the host bus to the local bus, and an output circuit is used in the output from the local bus to the host bus, the data transmission speed is not reduced because the slave IC of the local bus is not directly connected to the host bus. Attached Figure Description

[0016] Figure 1 This is a circuit diagram illustrating the bus arbitration circuit of this embodiment.

[0017] Figure 2 This is a block diagram illustrating a multi-layer data transmission system including the bus arbitration circuit of this embodiment.

[0018] Figure 3 This is a block diagram representing a data transmission system based on the I2C protocol.

[0019] [Explanation of Symbols]

[0020] 10, 11, 12: Serial data lines

[0021] 20, 21, 22: Clock lines

[0022] 30: Main IC

[0023] 41, 42: Hub IC

[0024] 51, 52, 53, 54, 55, 56: From IC

[0025] 100: Data transmission system

[0026] 411, 412: NMOS transistors

[0027] 413: Control Circuit

[0028] 414: Switching circuit

[0029] 415: Trigger circuit

[0030] 416: Multiplexer

[0031] 200: Data transmission system

[0032] 210: Serial data line

[0033] 220: Clock line

[0034] 230: Main IC

[0035] 231-237: From IC Detailed Implementation

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0037] Figure 2 This is a block diagram illustrating a multi-layer data transmission system 100 including the bus arbitration circuit of this embodiment.

[0038] The data transmission system 100 includes: a serial data line 10 and a clock line 20 serving as a host bus; a serial data line 11 and a clock line 21 serving as a first local bus; a serial data line 12 and a clock line 22 serving as a second local bus; a master IC 30; hub ICs 41 to 42 serving as bus arbitration circuits; and slave ICs 51 to 56. These bus lines are connected to the power supply lines via pull-up resistors, but only the pull-up resistors for serial data line 10 and clock line 20 are shown in the figure; the others are omitted.

[0039] Main IC 30 is connected to the host bus. Slave ICs 51 to 52 are connected to the host bus. Hub IC 41 is connected between the host bus and the first local bus. Hub IC 42 is connected between the host bus and the second local bus.

[0040] IC 53 to IC 54 are connected to the first local bus. IC 55 to IC 56 are connected to the second local bus.

[0041] Figure 1 This is a circuit diagram illustrating the bus arbitration circuit of this embodiment.

[0042] The following description focuses on hub IC 41, which serves as the bus arbitration circuit. However, for simplicity, only the serial data lines are shown for the host bus and local bus. The clock line is connected in the same manner as the serial data lines. Furthermore, hub IC 42 has the same structure as hub IC 41.

[0043] Hub IC 41 includes: a first bus terminal connected to a serial data line 10 via a pull-up resistor and connected to a power supply line; a second bus terminal connected to a serial data line 11 via a pull-up resistor and connected to a power supply line; an N-channel metal-oxide-semiconductor (NMOS) transistor 411, which is a first output circuit connected to the first bus terminal; an NMOS transistor 412, which is a second output circuit connected to the second bus terminal; a control circuit 413; a switching circuit 414; a flip-flop (F / F) circuit 415; and a multiplexer 416. In this embodiment, the switching circuit 414 is composed of a NOR circuit. The control circuit 413 includes an output terminal, a first input terminal, a second input terminal, a clock output terminal, a first control signal output terminal, a second control signal output terminal, and a data output terminal. Furthermore, serial data line 10 and serial data line 11 are connected to the same power supply line, but they can also be connected to different power supply lines.

[0044] The drain of NMOS transistor 411 is connected to the first bus terminal, the gate is connected to the output terminal of control circuit 413, and the source is connected to the ground terminal. The drain of NMOS transistor 412 is connected to the second bus terminal, the gate is connected to the output terminal of multiplexer 416, and the source is connected to the ground terminal. The first input terminal of control circuit 413 is connected to the first bus terminal, the second input terminal is connected to the output terminal of trigger circuit 415, the clock output terminal is connected to the clock terminal of trigger circuit 415, the first control signal output terminal is connected to the control terminal of switch circuit 414, the second control signal output terminal is connected to the control terminal of multiplexer 416, and the data output terminal is connected to the first input terminal of multiplexer 416. The input terminal of switch circuit 414 is connected to the first bus terminal, and the output terminal is connected to the second input terminal of multiplexer 416. The input terminal of trigger circuit 415 is connected to the second bus terminal via a NOT circuit. Furthermore, since the output circuit is composed of NMOS transistors, a NOT circuit is placed at the second bus terminal for logical compliance purposes, but logical compliance can also be achieved anywhere, such as in the control circuit.

[0045] In this embodiment, the hub IC 41 forms an open-drain output circuit with respect to serial data lines 10 and 11. Furthermore, other hub ICs or slave ICs also form the same output circuit. This is a necessary structure for arbitration; outside of arbitration, it is configured as a complementary metal-oxide-semiconductor (CMOS) output circuit, but this is omitted in the figures. Additionally, the multiplexer 416 is controlled to output a signal from the switching circuit 414 to the NMOS transistor 412 during arbitration, and otherwise outputs a signal from the data output terminal of the control circuit 413. Therefore, in the following description of arbitration, it is assumed that the multiplexer 416 is controlled to output a signal from the switching circuit 414 to the NMOS transistor 412.

[0046] The main IC 30 outputs a startcondition signal to the serial data line 10 to query each IC for a request. When the startcondition signal is input, slave ICs 51 to 52 output their own address signals according to the clock signal if a request is received.

[0047] When a start condition signal is input, hub ICs 41 and 42 output start condition signals to each local bus. Furthermore, hub ICs 41 and 42, upon request, combine the address signals of each local bus with their own address signals to output a combined address signal to the host bus. This provides the function of controlling the connection between the host bus and each local bus to stably implement arbitration.

[0048] When a start condition signal is input from IC 53 to IC 56, the IC 53 outputs its own address signal according to the clock signal if requested.

[0049] Secondly, refer to Figure 1 and Figure 2 The arbitration operation of a multilayer data transmission system including the bus arbitration circuit of this embodiment will be described. The operation of hub IC 41 will be described, assuming that hub IC 42 also performs the same operation.

[0050] The master IC 30 outputs a start condition signal to the serial data line 10 to query each IC for a request. The start condition signal is input to hub ICs 41-42 and slave ICs 51-52, which are connected to the master bus. The start condition signal is, for example, the moment when the serial data line 10 drops from a high level to a low level while the clock signal is maintained at a high (Hi) level.

[0051] Hub IC 41 receives a start condition signal from the first bus terminal. The start condition signal is input to the first input terminal of control circuit 413 and the input terminal of switch circuit 414. In standby mode, switch circuit 414 is controlled to be closed according to the control signal from control circuit 413. Figure 1 In this circuit, the switching circuit 414 is composed of a NOR circuit, so the control circuit 413 outputs a low level at the control signal output terminal. Therefore, the start condition signal input from the serial data line 10 to the first bus terminal is output from the second bus terminal to the serial data line 11 via the switching circuit 414 and the NMOS transistor 412.

[0052] That is, the start condition signal output by the master IC 30 is also input to slave ICs 53 to 54, which are connected to the serial data line 11, which serves as a local bus. Therefore, slave ICs 51 to 56 can determine whether a query request has been received by inputting the start condition signal output by the master IC 30.

[0053] Secondly, when the clock signal drops, the requesting hub IC and slave IC output their own address data to the serial data line according to the input clock signal. At this time, the hub IC combines the address data of the local bus with its own address data and outputs it to the host bus.

[0054] The operation of hub IC 41 at this time will be described in detail.

[0055] Control circuit 413 outputs a high level at the first control signal output terminal in sync with the falling clock signal, controlling switch circuit 414 to be in an open-circuit state. By controlling switch circuit 414 to the open-circuit state, address data of serial data line 10 will not be transmitted to serial data line 11. If controlled in this way, arbitration can be performed only within serial data line 11, i.e., the local bus.

[0056] After a first predetermined time elapses since the clock signal begins to fall, the control circuit 413 outputs a clock signal at the clock output terminal. Here, the first predetermined time is the time until the address data on the serial data line 11 stabilizes. When a clock signal is input to the clock terminal, the trigger circuit 415 latches the signal corresponding to the arbitration result of the local bus and outputs it to the output terminal. When the trigger circuit 415 inputs the arbitration result of the local bus to the second input terminal, the control circuit 413, upon request from the hub IC 41, combines it with its own address data and outputs the address data to the gate of the NMOS transistor 411.

[0057] Therefore, the address data of serial data line 11 is transmitted to serial data line 10, so that the address data of all hub ICs connected to the host bus and local bus on the host bus are arbitrated with that of the slave ICs.

[0058] After a second predetermined time elapses following the fall of the clock signal, control circuit 413 outputs a low level at the control signal output terminal, thereby closing switch circuit 414. When switch circuit 414 is closed, address data from serial data line 10 is transmitted to serial data line 11, i.e., the arbitration result between all hub ICs and slave ICs is transmitted to slave ICs 53 and 54. Here, the second predetermined time is the time until trigger circuit 415 finishes latching the signal corresponding to the arbitration result of the local bus.

[0059] Regarding arbitration using address data, it is explained that the hub IC or slave IC with the smallest address data has priority in requesting address data. That is, a hub IC or slave IC with address data of 0 (low level) in this instance can also output address data on the falling edge of the next clock signal. If the serial data line is low, then a hub IC or slave IC with address data of 1 (high level) in this instance cannot output address data on the falling edge of the next clock signal. In other words, these ICs will not participate in arbitration thereafter.

[0060] Furthermore, the master IC 30 outputs a clock signal with the same number of bits as the address data, repeating the aforementioned action, thereby performing arbitration on the serial data line 10. The master IC 30 then accepts the request from the IC determined through arbitration.

[0061] As explained above, the bus arbitration circuit in this embodiment uses a switching circuit and an output circuit for output from the host bus to the local bus, and an output circuit for output from the local bus to the host bus. Therefore, there are no slave ICs on the local bus directly connected to the host bus. Consequently, even if the number of slave ICs connected to the local bus increases, the data transmission speed will not be reduced.

[0062] The embodiments of the present invention have been described above, but the present invention is not limited to the described embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0063] For example, a trigger circuit 415 may be included between the second input terminal and the second bus terminal of the control circuit 413, but it is not limited to any circuit that latches signals. Alternatively, if the control circuit 413 is configured to control the data at the second input terminal to be valid after a first predetermined time, the trigger circuit 415 may not be included. Furthermore, the switching circuit 414 may be constructed using a NOR circuit, but it is not limited to this if it is constructed according to input and output logic. Additionally, while it has been described as initiating arbitration by sending a start condition signal from the main IC, it may also be a signal output from a hub IC or other signals.

Claims

1. A bus arbitration circuit, characterized in that, include: The first bus terminal is connected to the host bus; The second bus terminal connects to the local bus. The first output circuit has its output terminals connected to the first bus terminals. The second output circuit has its output terminals connected to the second bus terminals. The control circuit includes a first input terminal, a second input terminal, a control signal output terminal, and an output terminal. Data from the first bus terminal is input at the first input terminal, data from the second bus terminal is input at the second input terminal, and data is output from the output terminal of the control circuit to the input terminal of the first output circuit. as well as A switching circuit, wherein the input terminal of the switching circuit is connected to the first bus terminal, and the control terminal is connected to the control signal output terminal of the control circuit, outputting host bus data from the output terminal of the switching circuit to the input terminal of the second output circuit. In standby mode, the switching circuit is controlled to be closed according to the control signal from the control circuit, and the start condition signal input to the input terminal of the switching circuit is output from the output terminal of the switching circuit. In the standby state, after the start condition signal is input to the first input terminal, when the clock signal of the control circuit drops, the control circuit controls the switching circuit to an open circuit state through the control signal.

2. The bus arbitration circuit according to claim 1, characterized in that: A trigger circuit is included between the second input terminal and the second bus terminal of the control circuit. The trigger circuit receives data from the second bus terminal at its input terminal and receives a clock signal from the control circuit at its clock terminal. The output terminal of the trigger circuit is connected to the second input terminal of the control circuit.

3. The bus arbitration circuit according to claim 1 or 2, characterized in that: The first output circuit and the second output circuit are composed of N-channel metal-oxide-semiconductor transistors.

4. A data transmission system, characterized in that, include: The master integrated circuit and slave integrated circuit are connected to the host bus; The bus arbitration circuit according to any one of claims 1 to 3 is connected to the host bus; Local bus, connected to the bus arbitration circuit; and From the integrated circuit, it is connected to the local bus.

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