Data processing device and display device

Abstract

The present invention relates to a data processing apparatus and a display apparatus, and more particularly, to a data processing apparatus and a display apparatus for selectively applying an image quality improvement function in consideration of characteristics according to positions on a display panel.

Description

Technical Field

[0001] This embodiment relates to a data processing device and a display device. Background Technology

[0002] Multiple data lines and gate lines can be arranged on the display panel, and pixels can be defined at the intersections of the data lines and gate lines.

[0003] Each pixel includes a transistor that is turned on by a gate signal supplied to the gate line.

[0004] When the transistor is turned on, the data line is connected to the pixel, supplying a data voltage to the pixel. Furthermore, the brightness of the pixel varies according to the magnitude of the data voltage, thereby displaying an image on the display panel.

[0005] Here, due to the parasitic capacitance between the gate line and the gate node of the transistor, the gate signal may be affected by the kickback voltage.

[0006] Furthermore, an increase in one or more of the display panel size and resolution may increase the load on the display panel, which could reduce the slew rate of the gate signal.

[0007] The aforementioned recoil phenomenon or reduced slew rate may cause flickering, afterimages, and brightness imbalances in the images displayed on the display panel.

[0008] In other words, image quality may be degraded due to image quality degradation phenomena such as backlash and reduced slew rate caused by the gate signal.

[0009] To minimize image quality degradation, the image quality improvement function applies gate pulse modulation (GPM) to the gate signal to reduce the slope of the falling edge of the gate signal, or further applies one or more of overdrive and underdrive voltages to the base voltage of the gate signal.

[0010] Here, as one or more of the size and resolution of the display panel increase, the number of gate driver integrated circuits (ICs) that supply gate signals to the display panel increases.

[0011] In addition, image quality improvement functions are applied to multiple gate driver ICs simultaneously.

[0012] As display panels become larger, the degree of image quality degradation may vary across different panel locations covered by multiple gate driver ICs. Therefore, existing methods that simultaneously apply image quality improvement functions to multiple gate driver ICs are insufficient to prevent image quality degradation that occurs differently across panel locations. Summary of the Invention

[0013] Against this backdrop, the present invention provides a technique for selectively applying image quality improvement functions taking into account the positional characteristics on a display panel.

[0014] In view of the above, in one aspect, this embodiment provides a data processing apparatus, including: a clock generation circuit configured to generate a gate clock signal and send the gate clock signal to a first gate driver integrated circuit, namely a first gate driver IC and a second gate driver IC; and a first control signal generation circuit configured to generate an operation control signal and send the operation control signal to the first gate driver IC and the second gate driver IC via a common signal line connected to the first gate driver IC and the second gate driver IC, wherein the operation control signal is used to enable only a first image quality improvement circuit included in the first gate driver IC during a first time interval during which the first gate driver IC outputs a first gate signal according to the gate clock signal, and to disable both the first image quality improvement circuit and the second image quality improvement circuit included in the second gate driver IC during a second time interval during which the second gate driver IC outputs a second gate signal according to the gate clock signal.

[0015] In another embodiment, this embodiment provides a display device, including: a first gate driver integrated circuit, i.e., a first gate driver IC, which includes a first gate signal generation circuit and a first image quality improvement circuit. The first gate signal generation circuit is configured to output a first gate signal according to a gate clock signal during a first time interval, and the first image quality improvement circuit is configured to improve the image quality degraded due to the first gate signal by modifying the pulse waveform of the first gate signal; and a second gate driver IC, which includes a second gate signal generation circuit and a second image quality improvement circuit. The second gate signal generation circuit is configured to output a second gate signal according to the gate clock signal during a second time interval after the first time interval, and the second image quality improvement circuit... The device is configured to improve image quality degraded due to the second gate signal by modifying the pulse waveform of the second gate signal; and a data processing device configured to generate the gate clock signal and send the gate clock signal to the first gate driver IC and the second gate driver IC, and configured to generate an operation control signal and send the operation control signal to the first gate driver IC and the second gate driver IC via a common signal line connected to the first gate driver IC and the second gate driver IC, the operation control signal being used to enable only the first image quality improvement circuit during the first time interval and to disable both the first image quality improvement circuit and the second image quality improvement circuit during the second time interval.

[0016] The first image quality improvement circuit can be configured to output a gate pulse modulation signal, i.e., a GPM signal, to the first gate signal generation circuit to modify the pulse waveform of the first gate signal during the first time interval.

[0017] The first image quality improvement circuit can be configured to further apply one or more of an overdrive voltage and an underdrive voltage to the base voltage of the first gate signal during the first time interval, thereby modifying the pulse waveform of the first gate signal.

[0018] The operation control signal includes a pulse generation interval corresponding to the first time interval and a pulse non-generation interval corresponding to the second time interval.

[0019] The display device may further include a display panel configured to receive a first gate signal from the first gate driver IC during a first time interval to display an image on a first display area, and to receive a second gate signal from the second gate driver IC during a second time interval to display an image on a second display area.

[0020] Although image quality degradation may occur due to the first gate signal, the degraded image quality is improved by the first image quality improvement circuit in the first display area, and image quality degradation due to the second gate signal may not occur in the second display area.

[0021] As described above, according to this embodiment, since the image quality improvement function is selectively applied according to the panel position, the image quality degradation that occurs differently between panel positions can be effectively improved. Attached Figure Description

[0022] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment.

[0023] Figure 2 This is a diagram illustrating a data processing apparatus, a gate driving apparatus, and a display panel according to an embodiment.

[0024] Figure 3 This is a diagram illustrating the configuration of a data processing apparatus according to an embodiment.

[0025] Figure 4 This is a diagram illustrating the configuration of the gate driver IC according to an embodiment.

[0026] Figure 5 This is a diagram illustrating the configuration of the gate signal lines according to an embodiment.

[0027] Figure 6 , Figure 7 and Figure 8 This is a diagram illustrating a configuration in which an image quality improvement function is selectively applied in a display device according to an embodiment. Detailed Implementation

[0028] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment.

[0029] refer to Figure 1 The display device 100 may include a display panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140, etc.

[0030] Multiple data lines DL, multiple gate lines GL, and multiple pixels P can be arranged on the display panel 110.

[0031] Display panel 110 can be a liquid crystal display panel. Display panel 110 can also be other types of panels, such as organic light-emitting diode (OLED) panels.

[0032] The gate driving device 130 can supply a gate signal, either an on or off voltage, to the gate line GL. When an on-voltage gate signal is supplied to pixel P, pixel P can be connected to the data line DL. Conversely, when an off-voltage gate signal is supplied to pixel P, the connection between pixel P and the data line DL is released.

[0033] The gate driving device 130 described above may include a plurality of gate driving integrated circuits (ICs).

[0034] The data driving device 120 supplies a data voltage to the data line DL. The data voltage supplied to the data line DL can be supplied to the pixel P according to the gate signal.

[0035] The aforementioned data driving device 120 may include multiple data driving ICs.

[0036] The data processing device 140 can send control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 can send a gate control signal GCS to the gate driving device 130 to start scanning. The gate control signal GCS may include a gate start pulse GSP and a gate clock signal GCLK. The gate start pulse GSP included in the gate control signal GCS may include a pulse for controlling the output timing of a first gate signal during a frame time period.

[0037] The data processing device 140 can output image data IMG to the data driving device 120. Furthermore, the data processing device 140 can send a data control signal DCS, which is used to control the data driving device 120 to supply data voltage to each pixel P.

[0038] In one embodiment, the data processing device 140 may send an operation control signal to the gate driving device 130 to selectively enable the image quality improvement function provided in each of the plurality of gate driving ICs. Furthermore, the data processing device 140 may send an output control signal to the gate driving device 130 for controlling the output of the image quality improvement function.

[0039] The following will describe in detail the configuration in which the data processing device 140 selectively enables the image quality improvement function provided in each of the multiple gate driver ICs.

[0040] Figure 2 This is a diagram illustrating a data processing apparatus, a gate driving apparatus, and a display panel according to an embodiment.

[0041] refer to Figure 2The data processing device 140 can be connected to a plurality of gate driver ICs included in the gate driver device 130. Hereinafter, the description will assume that the plurality of gate driver ICs are configured as a first gate driver IC 210 and a second gate driver IC 220.

[0042] The first gate driver IC 210 and the second gate driver IC 220 can send gate signals to different areas in the display panel 110.

[0043] For example, the first gate driver IC 210 can send a first gate signal to the first display area D1, and the second gate driver IC 220 can send a second gate signal to the second display area D2. Here, the first display area D1 and the second display area D2 can be obtained by dividing the display panel 110 in the horizontal direction.

[0044] In this embodiment, due to the gate signal, the display panel 110 may experience different image quality degradation phenomena between display areas. For example, the first display area D1 may have image quality degradation due to the first gate signal, while the second display area D2 may not have image quality degradation due to the second gate signal.

[0045] In this scenario, during the first time interval during which the first gate driver IC 210 sends the first gate signal to the first display area D1, the data processing device 140 can enable the image quality improvement function of the first gate driver IC 210 and disable the image quality improvement function of the second gate driver IC 220. Furthermore, during the second time interval during which the second gate driver IC 220 sends the second gate signal to the second display area D2, the data processing device 140 can disable both the image quality improvement functions of the first gate driver IC 210 and the second gate driver IC 220.

[0046] Therefore, such as Figure 3 As shown, the data processing device 140 may include a clock generation circuit 310, a first control signal generation circuit 320, and a second control signal generation circuit 330, while as Figure 4 As shown, the first gate driver IC 210 may include a first gate signal generation circuit 212 and a first image quality improvement circuit 214. Furthermore, as... Figure 4 As shown, the second gate driver IC220 may include a second gate signal generation circuit 222 and a second image quality improvement circuit 224.

[0047] exist Figure 3In the process, the clock generation circuit 310 generates a gate clock signal GCLK and sends the gate clock signal GCLK to the first gate driver IC 210 and the second gate driver IC 220.

[0048] The first control signal generation circuit 320 generates an operation control signal CTR and sends it to both the first gate driver IC 210 and the second gate driver IC 220. Figure 6 As shown, the operation control signal CTR can be the first gate signal output by the first gate driver IC210 according to the gate clock signal GCLK. Figure 6 During the first time interval t1 of GS_1-1 to GS_1-n, only the control signal of the first image quality improvement circuit 214 of the first gate driver IC 210 is enabled, and the second gate driver IC 220 outputs the second gate signal according to the gate clock signal GCLK. Figure 6 During the second time interval t2 of GS_2-1 to GS_2-n, both the second image quality improvement circuit 224 and the first image quality improvement circuit 214 of the second gate driver IC 220 are disabled.

[0049] The operation control signal may include a first pulse Pulse1, which enables only the first image quality improvement circuit 214 during a first time interval, and includes a pulse non-generation interval corresponding to a second time interval t2. Figure 6 In this process, the rising edge r_edge of the first pulse Pulse1 can be formed at the moment when the first gate driver IC 210 first outputs the first gate signal. Furthermore, the falling edge f_edge of the first pulse Pulse1 can be formed at the moment when the first gate driver IC 210 completes the output of the first gate signal.

[0050] In this embodiment, configuration information for generating the operation control signal CTR can be obtained by performing multiple tests on the display panel 110, and the first control signal generation circuit 320 can store the configuration information during the manufacturing process of the display device 100.

[0051] In other words, the first control signal generation circuit 320 can generate an operation control signal CTR based on pre-stored configuration information.

[0052] The second control signal generation circuit 330 can generate an output control signal CTR_out for controlling the outputs of the first image quality improvement circuit 214 and the second image quality improvement circuit 224, and can send the output control signal CTR_out to both the first gate driver IC 210 and the second gate driver IC 220.

[0053] Here, the output control signal CTR_out can be a signal that controls the output time and output size of the first image quality improvement circuit 214 and the second image quality improvement circuit 224.

[0054] Since the first image quality improvement circuit 214 is enabled by the operation control signal CTR during the first time interval, the first image quality improvement circuit 214 can control the output time and output size according to the output control signal CTR_out. However, since the second image quality improvement circuit 224 is disabled by the operation control signal CTR, the second image quality improvement circuit 224 does not control the output according to the output control signal CTR_out.

[0055] On the other hand, Figure 4 In the first gate driver IC 210, the first gate signal generation circuit 212 can shift according to the gate clock signal GCLK and output the first gate signal GS_1 during the first time interval t1 from the time of receiving the gate start pulse.

[0056] When the first gate driver IC 210 is adjacent to the data processing device 140, the first gate signal generation circuit 212 can receive the first gate start pulse GSP1 from the data processing device 140, such as... Figure 4 As shown.

[0057] Furthermore, the first gate signal generation circuit 212 can receive the gate clock signal GCLK from the data processing device 140. For example... Figure 5 As shown, the first gate signal generation circuit 212 can receive the first gate start pulse GSP1 through the first signal line 510, and can receive the gate clock signal GCLK through the first common signal line 520.

[0058] The specific configuration of the first gate signal generation circuit 212 outputting the first gate signal GS_1 is as follows.

[0059] The first gate signal generation circuit 212 can preferentially output the first gate signal GS_1-1 using the first gate start pulse GSP1 and the gate clock signal GCLK. Furthermore, the first gate signal generation circuit 212 can sequentially shift the phase of the preferentially output first gate signal to output a signal such as... Figure 6 The second GS_1-2 to the nth GS_1-n are shown. Accordingly, the first gate signal generation circuit 212 can sequentially send multiple phase-shifted first gate signals GS_1-1 to GS_1-n to the first display area D1.

[0060] The first gate signal generation circuit 212 can output a second gate start pulse GSP2 to the second gate driver IC 220 when it completes the output of the first gate signal GS_1 (that is, when the nth signal GS_1-n of the first gate signal GS_1 is output).

[0061] The first image quality improvement circuit 214 can change the pulse waveform of the first gate signal GS_1, thereby improving the image quality deteriorated due to the first gate signal. Here, the image quality deterioration phenomenon can be at least one of recoil phenomenon and slew rate reduction phenomenon.

[0062] In this embodiment, the first image quality improvement circuit 214 can receive an operation control signal CTR from the data processing device 140, and can also receive an output control signal CTR_out. The first image quality improvement circuit 214 can receive the operation control signal CTR through a second common signal line 530, and can receive the output control signal CTR_out through a third common signal line 540.

[0063] The first image quality improvement circuit 214 can identify whether the first pulse Pulse1 is included in the operation control signal CTR.

[0064] In other words, the first image quality improvement circuit 214 can identify whether the time of the rising edge r_edge of the pulse included in the operation control signal CTR and the time of the initial output first gate signal GS_1 are the same, or whether the difference between the two is within the error range.

[0065] like Figure 6 As shown, if the time of the rising edge r_edge of the pulse is the same as the time of the initial output of the first gate signal GS_1, or if the difference between the two is within the error range, the first image quality improvement circuit 214 can be enabled according to the operation control signal CTR, thereby changing the pulse waveform of the first gate signal GS_1.

[0066] In this embodiment, the first image quality improvement circuit 214 can output a gate pulse modulated (GPM) signal to the first gate signal generation circuit 212. Therefore, during the first time interval t1, the pulse waveform of the first gate signal GS_1 output from the first gate signal generation circuit 212 can be as follows: Figure 6 The image has been changed. For example... Figure 6 As shown, when the gradient of the falling edge of the pulse waveform of the first gate signal GS_1 changes to a gentler gradient, the recoil phenomenon can be eliminated or mitigated, thereby preventing image quality degradation.

[0067] In an embodiment, the first image quality improvement circuit 214 may further apply one or more of an overdrive voltage and an underdrive voltage to the base voltage of the first gate signal GS_1, as follows: Figure 7 The pulse waveform of the first gate signal GS_1 is shown.

[0068] Specifically, the first image quality improvement circuit 214 can also apply an overdrive voltage OD to the base high voltage BVH of the first gate signal GS_1, thereby achieving the desired effect. Figure 7 The pulse waveform of the first gate signal GS_1 is changed as shown in 7A.

[0069] The first image quality improvement circuit 214 can also apply an underdrive voltage UD to the base low voltage BVL of the first gate signal, thereby... Figure 7 The pulse waveform of the first gate signal GS_1 is changed as shown in 7B.

[0070] Furthermore, the first image quality improvement circuit 214 can also apply an overdrive voltage OD to the base high voltage BVH of the first gate signal, and can also apply an underdrive voltage UD to the base low voltage BVL, thereby achieving the desired effect. Figure 7 The pulse waveform of the first gate signal GS_1 is changed as shown in 7C.

[0071] Therefore, the slew rate of the gate signal GS_1 can be increased, thereby preventing image quality degradation due to the decrease in slew rate.

[0072] exist Figure 4 In the second gate driver IC 220, the second gate signal generation circuit 222 can output the second gate signal GS_2 according to the gate clock signal GCLK during a second time interval t2 starting from the time when the first gate signal generation circuit 212 receives the second gate start pulse GSP2. Figure 5 As shown, the second gate signal generation circuit 222 can receive the gate clock signal GCLK through the first common signal line 520.

[0073] The following describes the detailed configuration of the second gate signal generation circuit 222 outputting the second gate signal GS_2.

[0074] The second gate signal generation circuit 222 can initially output the second gate signal GS_2-1 using the second gate start pulse GSP2 and the gate clock signal GCLK. Furthermore, the second gate signal generation circuit 222 can sequentially shift the phase of the initially output second gate signal and can output the second GS_2-2 to the nth GS_2-n, as shown below. Figure 6 As shown, the second gate signal generation circuit 222 can sequentially supply multiple phase-shifted second gate signals GS_2-1 to GS_2-n to the second display area D2.

[0075] The second image quality improvement circuit 224 can improve the image quality degradation caused by the second gate signal GS_2 by changing the pulse waveform of the second gate signal GS_2.

[0076] In this embodiment, the second image quality improvement circuit 224 can receive an operation control signal CTR from the data processing device 140, and can also receive an output control signal CTR_out. The second image quality improvement circuit 224 can receive the operation control signal CTR through a second common signal line 530, and can receive the output control signal CTR_out through a third common signal line 540.

[0077] As described above, the first common signal line 520 to the third common signal line 540 cause the first gate driver IC 210 and the second gate driver IC 220 to jointly receive signals from the data processing device 140.

[0078] On the other hand, the second image quality improvement circuit 224 can identify whether the time of the rising edge r_edge of the pulse included in the operation control signal CTR is the same as the time of the initial output second gate signal GS_2, or whether the difference between the two is within the error range.

[0079] like Figure 6 As shown, if the time of the rising edge r_edge of the pulse formation and the time of the initial output of the second gate signal GS_2 are different, the second image quality improvement circuit 224 can be disabled according to the operation control signal CTR. In other words, the image quality improvement function of the second gate driver IC 220 can be disabled by the operation control signal CTR.

[0080] As described above, since the display device 100 according to the embodiment can select one or more gate driver ICs to enable the image quality improvement function among a plurality of gate driver ICs according to the characteristics of the display area connected to each gate driver IC, rather than enabling the image quality improvement function of these plurality of gate driver ICs simultaneously, it can effectively prevent image quality degradation that occurs differently at different locations on the display panel 110.

[0081] on the other hand, Figures 2 to 6 It has already been stated that the number of gate driver ICs is limited to two, and the number of gate driver ICs enabled according to the operation control signal CTR is limited to one. However, the embodiments are not limited to this, and as... Figure 8 As shown, the number of gate driver ICs can be three or more, and the number of gate driver ICs enabled according to the operation control signal CTR can also be two or more (e.g., Figure 8 (GDIC1 and GDIC3 in the middle).

[0082] In addition, the operation control signal CTR can be repeated in units of frames of image data IMG.

[0083] Specifically, the image quality improvement function of GDIC1 can be enabled during the first time interval t1, which is the operation time interval of GDIC1 in a frame, according to the first pulse Pulse1 of the operation control signal CTR, thereby improving the image quality of the display area to which GDIC1 is connected.

[0084] Subsequently, the image quality improvement functions of all GDICs can be disabled during the second time interval t2, which is the operating time interval of GDIC2. Furthermore, during the third time interval t3, which is the operating time interval of GDIC3, the image quality improvement function of GDIC3 can be enabled according to the second pulse Pulse2 of the operation control signal CTR, thereby improving the image quality of the display area to which GDIC3 is connected.

[0085] Subsequently, the image quality improvement functions of all GDICs can be deactivated again during the fourth time interval t4, which is the operating time interval of GDIC4. Furthermore, GDIC1 through GDIC4 can repeat the above configuration in the next frame.

[0086] Cross-reference to related applications

[0087] This application claims Korean Patent Application No. 10-2020-0155764, filed on November 19, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A data processing apparatus, comprising: A clock generation circuit is configured to generate a gate clock signal and send the gate clock signal to multiple gate driver integrated circuits, i.e., ICs. as well as A first control signal generation circuit is configured to generate an operation control signal and send the operation control signal to all of the plurality of gate driver ICs via a common signal line connected to the plurality of gate driver ICs. in: Each of the plurality of gate driver ICs outputs a corresponding gate signal during a specific time interval within a frame time period. The operation control signal includes a pulse signal corresponding to a first time interval in which the first gate driver IC outputs the first gate signal. The rising edge of the pulse signal occurs when the first gate driver IC initially outputs the first gate signal, and the falling edge of the pulse signal occurs when the first gate driver IC completes the output of the first gate signal. The operation control signal is configured to enable only the first image quality improvement circuit included in the first gate driver IC during the first time interval, and to disable all image quality improvement circuits included in the plurality of gate driver ICs during the second time interval during which the second gate driver IC outputs the second gate signal.

2. The data processing apparatus according to claim 1, wherein, The operation control signal includes a pulse non-generation interval corresponding to the second time interval.

3. The data processing apparatus of claim 1 further includes a second control signal generation circuit, the second control signal generation circuit being configured to generate an output control signal for controlling the output of the first image quality improvement circuit and the second image quality improvement circuit included in the second gate driver IC, and to send the output control signal to all of the plurality of gate driver ICs via another common signal line connected to the plurality of gate driver ICs.

4. The data processing apparatus according to claim 3, wherein, The first image quality improvement circuit is configured to modify the pulse waveform of the first gate signal according to the output control signal during the first time interval.

5. A display device, comprising: Multiple gate driver integrated circuits, i.e., ICs, each gate driver IC includes a gate signal generation circuit and an image quality improvement circuit. The gate signal generation circuit is configured to output a gate signal according to a gate clock signal during a corresponding time interval within a frame time period. The image quality improvement circuit is configured to modify the pulse waveform of the gate signal. A data processing device configured to generate the gate clock signal and send the gate clock signal to the plurality of gate driver ICs, and configured to generate an operation control signal. in: The operation control signal includes a pulse signal corresponding to a first time interval in which the first gate driver IC outputs the first gate signal. The rising edge of the pulse signal occurs when the first gate driver IC initially outputs the first gate signal, and the falling edge of the pulse signal occurs when the first gate driver IC completes the output of the first gate signal. The operation control signal is configured to enable only the image quality improvement circuitry included in the first gate driver IC during the first time interval, and to disable all image quality improvement circuitry included in the plurality of gate driver ICs during the second time interval during which the second gate driver IC outputs the second gate signal. The operation control signal is sent to all of the plurality of gate driver ICs via a common signal line.

6. The display device according to claim 5, wherein, The image quality improvement circuit included in the first gate driver IC is configured to output a gate pulse modulation signal, i.e., a GPM signal, to the first gate signal generation circuit to modify the pulse waveform of the first gate signal during the first time interval.

7. The display device according to claim 5, wherein, The image quality improvement circuit included in the first gate driver IC is configured to further apply one or more of an overdrive voltage and an underdrive voltage to the base voltage of the first gate signal during the first time interval, thereby modifying the pulse waveform of the first gate signal.

8. The display device according to claim 5, wherein, The operation control signal includes a pulse generation interval corresponding to the first time interval and a pulse non-generation interval corresponding to the second time interval.

9. The display device of claim 5, further comprising a display panel configured to receive a first gate signal from the first gate driver IC during the first time interval to display an image on a first display area, and to receive a second gate signal from the second gate driver IC during the second time interval to display an image on a second display area.

10. The display device according to claim 9, wherein, Although image quality degradation occurs due to the first gate signal, the degraded image quality is improved in the first display area by the image quality improvement circuit included in the first gate driver IC, and no image quality degradation occurs in the second display area due to the second gate signal.

11. The display device according to claim 5, wherein, Image quality degradation includes at least one of recoil and reduced slew rate.

Images