Display device

Abstract

A display device is provided. The display device includes a display panel including a plurality of pixels respectively connected to corresponding data lines of a plurality of data lines and respectively connected to corresponding scan lines of a plurality of scan lines, a data driving circuit for driving the plurality of data lines, a scan driving circuit for driving the plurality of scan lines, and a driving controller for dividing the display panel into a first display area and a second display area during a multi-frequency mode and controlling the data driving circuit and the scan driving circuit such that the first display area is driven at a first driving frequency and the second display area is driven at a second driving frequency lower than the first driving frequency. During the multi-frequency mode, the driving controller divides the second display area into a plurality of blocks and alternately drives the plurality of blocks in each frame.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0150366, filed on November 11, 2020, which is hereby incorporated by reference for all purposes, as if fully set forth herein. Technical Field

[0003] The embodiments of the present invention described herein relate to display devices. Background Technology

[0004] Organic light-emitting diodes (OLEDs) in display devices use organic light-emitting diodes (OLEDs) to generate light through the recombination of electrons and holes to display images. These OLEDs offer advantages such as high response speed and low power consumption.

[0005] An organic light-emitting display device includes pixels connected to data lines and scan lines. Each pixel typically includes an organic light-emitting diode (OLED) and a circuit unit for controlling the amount of current flowing through the OLED. The circuit unit controls the amount of current flowing from a first driving voltage source through the OLED to a second driving voltage source in response to a data signal. In this case, light of a predetermined brightness is generated in response to the amount of current flowing through the OLED.

[0006] As the application areas of display devices diversify, multiple images that are different from each other can be displayed simultaneously on a single display device. Summary of the Invention

[0007] For display devices that display multiple images simultaneously, there is a need for technologies that reduce power consumption while preventing the degradation of display quality.

[0008] Embodiments of the present invention provide a display device and a driving method thereof that can reduce power consumption and prevent degradation of display quality.

[0009] Embodiments of the present invention provide a display device comprising: a display panel including a plurality of pixels, the plurality of pixels being respectively connected to corresponding data lines among a plurality of data lines and respectively connected to corresponding scan lines among a plurality of scan lines; a data driving circuit driving the plurality of data lines; a scan driving circuit driving the plurality of scan lines; and a driving controller: dividing the display panel into a first display area and a second display area, and controlling the data driving circuit and the scan driving circuit during a multi-frequency mode such that the first display area is driven at a first driving frequency and the second display area is driven at a second driving frequency lower than the first driving frequency, wherein during the multi-frequency mode, the driving controller divides the second display area into a plurality of blocks and drives the blocks in the plurality of blocks in each frame.

[0010] In an embodiment, consecutive frames of a multi-frequency mode may have the same duration as each other.

[0011] In an embodiment, in normal mode, the drive controller can control the data drive circuit and the scan drive circuit so that the first display area and the second display area are driven at a normal frequency, wherein the second drive frequency is lower than the normal frequency.

[0012] In an embodiment, the first driving frequency may be higher than the normal frequency.

[0013] In one embodiment, during multi-frequency mode, the drive controller can alternately drive multiple blocks of the second display area in each frame.

[0014] In an embodiment, the scan driving circuit may include multiple driving stages, and one of the driving stages may drive a first scan line among multiple scan lines.

[0015] In an embodiment, one of the multiple driver stages may include: a first output terminal connected to a first scan line; a second output terminal outputting a carry signal; a driver circuit that determines the signal level of each of the first node and the second node in response to a clock signal and a previous carry signal; and a masking circuit that outputs a first scan signal to the first output terminal in response to the signal of the first node, the signal of the second node, and a masking clock signal, wherein the first node is electrically connected to the second output terminal, and the previous carry signal is a carry signal output from the previous driver stage among the multiple driver stages.

[0016] In one embodiment, the drive controller may drive only the first block of a plurality of blocks during the first frame. The drive controller may also drive only the second block of a plurality of blocks during a second frame that follows the first frame.

[0017] In an embodiment, the first frame and the second frame may have the same duration.

[0018] In one embodiment, the masking clock signal can indicate the drive / non-drive state of each of the plurality of blocks in the second display area.

[0019] In one embodiment, each of the plurality of driver levels corresponding to the first block may mask the first scan signal during the second frame.

[0020] In one embodiment, when multiple drive levels corresponding to the first block are driven during the second frame, the drive controller can set the frequency of the clock signal to a frequency higher than the normal frequency.

[0021] In an embodiment, a driver stage among multiple driver stages may further include a first voltage terminal receiving a first voltage and a second voltage terminal receiving a second voltage. The masking circuit includes: a first masking transistor connected between the second voltage terminal and the first output terminal, and including a gate electrode connected to the second node; and a second masking transistor connected between the first output terminal and an input terminal receiving a masking clock signal, and including a gate electrode connected to the first node.

[0022] In an embodiment, the scan driving circuit may include multiple driving stages, and one of the driving stages may drive a first scan line and a second scan line among multiple scan lines.

[0023] In an embodiment, a driver stage among a plurality of driver stages may include: a first output terminal connected to a first scan line; a second output terminal connected to a second scan line; a driver circuit that outputs a second scan signal to the second output terminal in response to a clock signal and a previous carry signal; a first masking circuit that outputs the first scan signal to the first output terminal at a predetermined level in response to a first masking signal; and a second masking circuit that connects the first output terminal and the second output terminal in response to a second masking signal to output the second scan signal as the first scan signal, wherein the previous carry signal is the second scan signal output from the previous driver stage among the plurality of driver stages.

[0024] In one embodiment, the drive controller may drive only the first block of a plurality of blocks during the first frame. The drive controller may also drive only the second block of a plurality of blocks during a second frame that follows the first frame.

[0025] In an embodiment, the first masking signal and the second masking signal can indicate the driving / non-driving state of each of the plurality of blocks in the second display area.

[0026] In one embodiment, each of the plurality of driver levels corresponding to the first block may mask the first scan signal during the second frame.

[0027] In an embodiment, during the multi-frequency mode, the image signal provided to the first display area may be a moving image signal, and the image signal provided to the second display area may be a still image signal.

[0028] In an embodiment of the present invention, the display device includes: a display panel including a plurality of pixels, the plurality of pixels being respectively connected to corresponding data lines among a plurality of data lines and respectively connected to corresponding scan lines among a plurality of scan lines; a data driving circuit driving the plurality of data lines; a scan driving circuit driving the plurality of scan lines; and a driving controller: determining an operation mode based on an input signal, and controlling the data driving circuit and the scan driving circuit such that, when the operation mode is a multi-frequency mode, a first display area of ​​the display panel is driven at a first driving frequency, and a second display area of ​​the display panel is driven at a second driving frequency, wherein the driving controller outputs a masking clock signal, and the scan driving circuit drives a first portion of the second display area without driving a second portion of the second display area in response to the masking clock signal during the multi-frequency mode.

[0029] In an embodiment, in a plan view, a first non-folded area, a folded area, and a second non-folded area may be defined in a display panel, wherein the first non-folded area corresponds to a first display area, the second non-folded area corresponds to a second display area, a first portion of the folded area corresponds to the first display area, and a second portion of the folded area corresponds to the second display area.

[0030] In an embodiment, consecutive frames of a multi-frequency mode may have the same duration as each other.

[0031] In an embodiment, during a multi-frequency mode, the drive controller can divide the second display area into multiple blocks, output a masking clock signal to drive the block corresponding to the first portion of the multiple blocks, and may not drive at least one block corresponding to the second portion of the multiple blocks. Attached Figure Description

[0032] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to describe the principles of the invention. In the drawings:

[0033] Figure 1 This is a plan view of an embodiment of the display device according to the present invention;

[0034] Figure 2A and Figure 2B This is a perspective view of an embodiment of a display device according to the present invention;

[0035] Figure 3A This is a view used to describe the operation of the display device in normal mode;

[0036] Figure 3B and Figure 3C Each is a view used to describe the operation of the display device in multi-frequency mode;

[0037] Figure 4 This is a block diagram of an embodiment of a display device according to the present invention;

[0038] Figure 5 This is an equivalent circuit diagram of one embodiment of a pixel according to the present invention;

[0039] Figure 6 It is used to describe Figure 4 A timing diagram of the operation of one of the pixels in a display device;

[0040] Figure 7 This is a block diagram of an embodiment of the scan driver according to the present invention;

[0041] Figure 8 It shows Figure 7 The j-th driver level (j is a positive integer) is shown in the driver level diagram.

[0042] Figure 9A and Figure 9B Each is shown Figure 7 The timing diagram shows the operation of the (j-1)th drive stage, the jth drive stage, and the (j+1)th drive stage in the scan driver shown.

[0043] Figure 10 It is shown in Figure 3A The timing diagram of the start signal and third clock signal provided from the drive controller to the scan driver and the image signal provided to the display panel in normal mode;

[0044] Figure 11 It is shown in Figure 3B Timing diagram of the start signal and third clock signal provided from the drive controller to the scan driver and the image signal provided to the display panel in the multi-frequency mode;

[0045] Figure 12 It is shown in Figure 3C Timing diagram of the start signal and third clock signal provided from the drive controller to the scan driver and the image signal provided to the display panel in the multi-frequency mode;

[0046] Figure 13 It is a description Figure 12 The timing diagram of some of the start signals, third clock signals, and image signals in the frame shown;

[0047] Figure 14A It is shown Figure 13 The enlarged timing diagram of the first frame shown;

[0048] Figure 14B It is shown Figure 13 The enlarged timing diagram of the second frame shown;

[0049] Figure 14C It is shown Figure 13 The enlarged timing diagram of the third frame shown;

[0050] Figure 15 It is shown in Figure 3C Timing diagram of the start signal and third clock signal provided from the drive controller to the scan driver and the image signal provided to the display panel in the multi-frequency mode;

[0051] Figure 16 This is a block diagram of an embodiment of the scanning drive circuit according to the present invention;

[0052] Figure 17 It shows Figure 16 The j-th driver level shown; and

[0053] Figure 18A and Figure 18B Each is shown Figure 16 The timing diagram shows the operation of the (j-1)th drive stage, the jth drive stage, and the (j+1)th drive stage in the scan drive circuit shown. Detailed Implementation

[0054] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “linked to” another element or layer, it can be directly on, directly connected to, or directly linked to the other element or layer, or an intermediary element or layer may exist.

[0055] Similar reference numerals throughout this specification refer to similar elements. In the drawn figures, the thickness, scale, and dimensions of the elements are exaggerated for the purpose of effective description of the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of the invention, the first element, component, area, layer, or portion discussed below can be referred to as the second element, component, area, layer, or portion. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well.

[0057] Spatial relative terms, such as “below,” “under,” “down,” “above,” and “above,” may be used herein for the convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the drawn figures. It will be understood that, in addition to the orientations depicted in the drawn figures, spatial relative terms are intended to cover different orientations of the apparatus in use or operation.

[0058] It will also be understood that, when used in this specification, the terms “comprising” or “having” indicate the presence of the stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or clusters thereof.

[0059] Given the measurements discussed and the errors associated with a particular number of measurements (i.e., the limitations of the measurement system), as used herein, “about” or “approximately” includes the stated values ​​and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0060] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein. Terms such as “unit” may refer, for example, to a circuit or processor.

[0061] The invention will be explained in detail below with reference to the accompanying drawings.

[0062] Figure 1 This is a plan view of an embodiment of the display device DD according to the present invention.

[0063] Figure 1 A portable terminal is illustrated as an embodiment of a display device DD according to the present invention. The portable terminal may include a tablet PC, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), game console, watch-type electronic device, or the like. However, the invention is not limited thereto. Embodiments of the invention can be used in large electronic devices such as televisions and outdoor digital billboards, as well as in small and medium-sized electronic devices such as PCs, laptops, kiosks, vehicle navigation devices, and cameras. These are merely embodiments, and it is self-evident that embodiments of the invention can also be used in other electronic devices, provided that the embodiments do not depart from the invention.

[0064] like Figure 1 As shown, the display surface displaying the first image IM1 and the second image IM2 is parallel to the plane defined by the first direction DR1 and the second direction DR2. The display device DD includes a plurality of regions divided on the display surface. The display surface includes a display area DA for displaying the first image IM1 and the second image IM2 and a non-display area NDA adjacent to the display area DA. The non-display area NDA may also be referred to as a border area. In an embodiment, the display area DA may be quadrilateral in shape. The non-display area NDA surrounds the display area DA. Although not shown, but as an example, a partially curved shape may be included in the display device DD. As a result, the display area DA may have a curved shape.

[0065] The display area DA of the display device DD includes a first display area DA1 and a second display area DA2. In a predetermined application, a first image IM1 may be displayed in the first display area DA1, and a second image IM2 may be displayed in the second display area DA2. In an embodiment, for example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or text information with a long variation period.

[0066] In this embodiment, the display device DD can drive the first display area DA1, which displays moving images, at a normal frequency, and can drive the second display area DA2, which displays still images, at a lower frequency than the normal frequency. The display device DD can reduce power consumption by reducing the driving frequency of the second display area DA2.

[0067] The size of each of the first display area DA1 and the second display area DA2 can be preset and changed by an application. In an embodiment, when the first display area DA1 displays a still image and the second display area DA2 displays a moving image, the first display area DA1 can be driven at a low frequency, and the second display area DA2 can be driven at a normal frequency. Furthermore, the display area DA can be divided into three or more display areas, and the driving frequency of each of the multiple display areas can be determined according to the type of image (e.g., still image or moving image) displayed in the corresponding one of the multiple display areas.

[0068] Figure 2A and Figure 2B This is a perspective view of the display device DD2 according to the present invention. Figure 2A The display device DD2 is shown in its unfolded state, and Figure 2B The display device DD2 is shown in a folded state.

[0069] like Figure 2A and Figure 2BAs shown, the display device DD2 includes a display area DA and a non-display area NDA. The display device DD2 can display images through the display area DA. When the display device DD2 is unfolded, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The thickness direction of the display device DD2 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Accordingly, a front surface (or top surface) and a rear surface (or bottom surface) of each of the components constituting the display device DD2 may be defined based on the third direction DR3. The non-display area NDA may also be referred to as a border area. In an embodiment, the display area DA may be quadrilateral in shape. The non-display area NDA surrounds the display area DA.

[0070] The display area DA may include a first non-folded area NFA1, a folded area FA, and a second non-folded area NFA2. The folded area FA may be bent about a folding axis FX extending in the first direction DR1.

[0071] When the display device DD2 is folded, the first non-folded area NFA1 and the second non-folded area NFA2 can face each other. Correspondingly, in the fully folded state, the display area DA may not be exposed to the outside, which can be referred to as inward folding. However, the operation of the display device DD2 is not limited to this.

[0072] In embodiments of the present invention, for example, when the display device DD2 is folded, the first non-folded region NFA1 and the second non-folded region NFA2 may face away from each other. Accordingly, in the folded state, the first non-folded region NFA1 may be exposed to the outside, which may be referred to as an outward fold.

[0073] Display device DD2 may perform only one of the inward folding and outward folding operations. In an alternative embodiment, display device DD2 may perform both inward folding and outward folding operations. In this case, the same area of ​​display device DD2 (e.g., the folding area FA) may be folded inward and outward. In an alternative embodiment, a portion of display device DD2 may be folded inward and another portion may be folded outward.

[0074] Although Figure 2A and Figure 2B One folded region and two non-folded regions are shown as an example, but the number of each of the folded and non-folded regions is not limited thereto. In embodiments, for example, the display device DD2 may include three or more non-folded regions and a plurality of folded regions respectively arranged between adjacent non-folded regions.

[0075] Although Figure 2A and Figure 2BThe illustration shows a case where the folding axis FX is parallel to the minor axis of the display device DD2, but the invention is not limited thereto. In embodiments, for example, the folding axis FX may extend along the major axis of the display device DD2 (e.g., in a direction parallel to the second direction DR2). In this case, the first non-folding region NFA1, the folding region FA, and the second non-folding region NFA2 may be arranged sequentially in the first direction DR1.

[0076] Multiple display areas DA1 and DA2 can be defined within the display area DA of the display device DD2. Two display areas DA1 and DA2 are shown in... Figure 2A However, the number of multiple display areas DA1 and DA2 is not limited to this.

[0077] Multiple display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. In an embodiment, for example, the first display area DA1 may be the area displaying a first image IM1, and the second display area DA2 may be the area displaying a second image IM2; however, embodiments of the present invention are not limited thereto. In an embodiment, for example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or an image with a long period of change (e.g., text information).

[0078] The display device DD2 in this embodiment can operate differently depending on the operating mode. The operating mode may include a normal mode and a multi-frequency mode. During normal mode, the display device DD2 can drive both the first display area DA1 and the second display area DA2 at a normal frequency. During multi-frequency mode, the display device DD2 in this embodiment can drive the first display area DA1 displaying the first image IM1 at a first driving frequency, and can drive the second display area DA2 displaying the second image IM2 at a second driving frequency lower than the normal frequency. In this embodiment, the first driving frequency may be equal to the normal frequency.

[0079] The size of each of the first display area DA1 and the second display area DA2 can be preset and changed by an application. In an embodiment, the first display area DA1 may correspond to the first non-folding area NFA1, and the second display area DA2 may correspond to the second non-folding area NFA2. Furthermore, a first portion of the folding area FA may correspond to the first display area DA1, and a second portion of the folding area FA may correspond to the second display area DA2.

[0080] In this embodiment, the entire folded area FA may correspond to only one of the first display area DA1 and the second display area DA2.

[0081] In this embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, and the second display area DA2 may correspond to a second portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2. Accordingly, the surface area of ​​the first display area DA1 may be smaller than the surface area of ​​the second display area DA2.

[0082] In this embodiment, the first display area DA1 may correspond to a first portion of the first non-folded area NFA1, the folded area FA, and the second non-folded area NFA2, and the second display area DA2 may correspond to a second portion of the second non-folded area NFA2. Accordingly, the surface area of ​​the second display area DA2 may be smaller than the surface area of ​​the first display area DA1.

[0083] like Figure 2B As shown, when the folding area FA is folded, the first display area DA1 can correspond to the first non-folding area NFA1, and the second display area DA2 can correspond to the folding area FA and the second non-folding area NFA2.

[0084] Although Figure 2A and Figure 2B A display device DD2 with a folding region is shown in one embodiment of the display device, but the invention is not limited thereto. In another embodiment of the invention, for example, the display device may have two or more folding regions, or may be a rollable display device, a slidable display device, or the like.

[0085] Although in the following text, Figure 1 The display device DD shown is described as an example, but the description of the display device DD is equally applicable. Figure 2A and Figure 2B The display device DD2 shown is shown.

[0086] Figure 3A This is a view used to describe the operation of the display device DD in normal mode. Figure 3B and Figure 3C Each is a view used to describe the operation of the display device DD in multi-frequency mode.

[0087] Reference Figure 3A The first image IM1 displayed in the first display area DA1 can be a moving image, and the second image IM2 displayed in the second display area DA2 can be a still image or an image with a long period of change (e.g., an icon image). Figure 1 The first image IM1 shown in the first display area DA1 and the second image IM2 shown in the second display area DA2 are merely examples, and various images can be displayed on the display device DD.

[0088] In normal NFM mode, the driving frequency of each of the first display area DA1 and the second display area DA2 of the display device DD is the normal frequency. In an embodiment, the normal frequency may be approximately 60 Hz. For example, in normal NFM mode, for approximately one second, frames F1 to F60 (refer to) can be displayed in the first display area DA1 and the second display area DA2 of the display device DD. Figure 10 (Image of ).

[0089] Reference Figure 3B In the multi-frequency mode MFMa, the display device DD can set the driving frequency of a first display area DA1 that displays a first image IM1 (i.e., a moving image) to a first driving frequency, and can set the driving frequency of a second display area DA2 that displays a second image IM2 (i.e., a still image) to a second driving frequency lower than the first driving frequency. In an embodiment, for example, when the normal frequency is about 60 Hz, the first driving frequency can be about 90 Hz, and the second driving frequency can be about 30 Hz. The first and second driving frequencies can be varied. In an embodiment, for example, the first driving frequency can be a frequency higher than the normal frequency (e.g., about 100 Hz, about 144 Hz, etc.), and the second driving frequency can be a frequency lower than the normal frequency (e.g., about 30 Hz, about 10 Hz, about 1 Hz, etc.). In another embodiment, the first driving frequency can be equal to the normal frequency, and the second driving frequency can be a frequency lower than the normal frequency (e.g., about 30 Hz, about 10 Hz, about 1 Hz, etc.).

[0090] For approximately one second, when the first driving frequency is approximately 90Hz and the second driving frequency is approximately 30Hz in the multi-frequency mode MFMa, the first image IM1 is displayed in each of the first frames F1 to F90 in the first display area DA1 of the display device DD. In the second display area DA2, the second image IM2 is displayed every three frames, that is, the second image IM2 is displayed only in frames F1, F4, F7, ..., and F88, and no image is displayed in the remaining frames F2, F3, F5, F6, ..., F89 and F90.

[0091] exist Figure 3C Under the multi-frequency mode MFMb shown, in order to... Figure 3B In the same manner as the multi-frequency mode MFMa shown, the drive frequency of the first display area DA1 of the display device DD that will display the first image IM1 (i.e., the moving image) is set to the first drive frequency, and the drive frequency of the second display area DA2 that will display the second image IM2 (i.e., the still image) is set to the second drive frequency, which is lower than the first drive frequency.

[0092] exist Figure 3CIn the multi-frequency mode MFMb shown, the display device DD can divide the second display area DA2 into a first block DA2-1, a second block DA2-2, and a third block DA2-3, and can drive the first block DA2-1, the second block DA2-2, and the third block DA2-3 alternately and sequentially.

[0093] In each of frames (3a+1) F1, F4, ..., and F88, for example, the display device DD displays an image in the first block DA2-1 of the second display area DA2 and does not display images in the second block DA2-2 and the third block DA2-3. Here, a can be an integer equal to or greater than 0 and equal to or less than 29.

[0094] In each of frames (3a+2) F2, F5, ..., and F89, the display device DD displays an image in the second block DA2-2 of the second display area DA2 and does not display an image in the first block DA2-1 and the third block DA2-3.

[0095] In each of frames (3a+3) F3, F6, ..., and F90, the display device DD displays an image in the third block DA2-3 of the second display area DA2 and does not display an image in the first block DA2-1 and the second block DA2-2.

[0096] That is, since a second image IM2 for the entire second display area DA2 can be displayed during three frames (e.g., first frame F1, second frame F2 and third frame F3), the second driving frequency of the second display area DA2 can be about 30Hz.

[0097] The operation of the display device DD in multi-frequency mode MFMb will be described in detail later.

[0098] Figure 4 This is a block diagram of an embodiment of the display device DD according to the present invention.

[0099] Reference Figure 4 The display device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0100] The drive controller 100 receives the image input signal RGB and the control signal CTRL. The drive controller 100 generates the image data signal DATA, obtained by converting the data format of the image input signal RGB, according to the interface specification with the data drive circuit 200. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and a light emission control signal ECS.

[0101] The data drive circuit 200 receives a data control signal DCS and an image data signal DATA from the drive controller 100. The data drive circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1 to DLm (where m is a natural number greater than 1), which will be described later. The data signals are analog voltages corresponding to the grayscale values ​​of the image data signal DATA.

[0102] Voltage generator 300 generates the voltages required for the operation of display panel DP. In this embodiment, voltage generator 300 generates a first drive voltage ELVDD, a second drive voltage ELVSS, and an initialization voltage VINT.

[0103] The display panel DP includes first scan lines GIL0 to GILn (n is a natural number greater than 1), second scan lines GWL1 to GWLn, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. The display panel DP may also include a scan driving circuit SD and a light emission driving circuit EDC. In an embodiment, the scan driving circuit SD is arranged on a first side of the display panel DP (e.g., Figure 4 (Left side of the image). The first scan lines GIL0 to GILn and the second scan lines GWL1 to GWLn extend from the scan drive circuit SD in the first direction DR1.

[0104] The light-emitting drive circuit EDC is arranged on the second side of the display panel DP (e.g., Figure 4 (Right side of the diagram). Light emission control lines EML1 to EMLn extend from the light emission driving circuit EDC in the direction opposite to the first direction DR1. In an embodiment, the light emission driving circuit EDC may receive a light emission control signal ECS from the drive controller 100.

[0105] The first scan lines GIL0 to GILn, the second scan lines GWL1 to GWLn, and the light emission control lines EML1 to EMLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data driving circuit 200 in the opposite direction to the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.

[0106] exist Figure 4 In the example shown, the scan driving circuit SD and the light-emitting driving circuit EDC are arranged facing each other with pixel PX between them, but the invention is not limited thereto. In embodiments, for example, the scan driving circuit SD and the light-emitting driving circuit EDC may be arranged adjacent to each other on one of the first and second sides of the display panel DP. In embodiments, the scan driving circuit SD and the light-emitting driving circuit EDC may be configured as a single circuit.

[0107] Multiple pixels PX are electrically connected to first scan lines GIL0 to GILn, to second scan lines GWL1 to GWLn, to light emission control lines EML1 to EMLn, and to data lines DL1 to DLm. Each of the multiple pixels PX may be electrically connected to three scan lines and one light emission control line. In an embodiment, for example, as... Figure 4 As shown, each of the pixels PX in the first row can be connected to scan lines GIL0, GIL1, and GWL1, as well as the emission control line EML1. Additionally, each of the pixels PX in the second row can be connected to scan lines GIL1, GIL2, and GWL2, as well as the emission control line EML2.

[0108] Each of the multiple pixels PX includes a light-emitting diode (ED) (see reference). Figure 5 ) and the pixel circuit unit PXC (refer to) that controls the light emission of the light-emitting diode ED. Figure 5 In an embodiment, for example, the light-emitting diode ED may be an organic light-emitting diode. The pixel circuit unit PXC may include multiple transistors and capacitors. The scan drive circuit SD may include transistors provided using the same process as the transistors of the pixel circuit unit PXC.

[0109] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and an initialization voltage VINT from the voltage generator 300.

[0110] The scan drive circuit SD receives a scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SD can output a first scan signal to the first scan lines GIL0 to GILn and a second scan signal to the second scan lines GWL1 to GWLn. The circuit configuration and operation of the scan drive circuit SD will be described in detail later.

[0111] The drive controller 100 in this embodiment can divide the display panel DP into a first display area DA1 based on the image input signal RGB (refer to...). Figure 1 ) and the second display area DA2 (refer to) Figure 1 Furthermore, the drive controller 100 operates in multi-frequency mode MFMb (see reference). Figure 3C The output signal is at least one masking signal indicating the drive / non-drive state of the first block DA2-1, the second block DA2-2, and the third block DA2-3 in the second display area DA2. This at least one masking signal may be included in the scan control signal SCS.

[0112] Figure 5 This is an equivalent circuit diagram of one embodiment of the pixel PX according to the present invention.

[0113] Figure 5 It shows the connection to Figure 4 The diagram shows the equivalent circuit diagram of pixel PXij for the i-th data line DL1 to DLm, the (j-1)-th first scan line GILj-1 and the j-th first scan line GILj for the first scan lines GIL0 to GILn, the j-th second scan line GWLj for the second scan lines GWL1 to GWLn, and the j-th light emission control line EMLj for the light emission control lines EML1 to EMLn. Here, i and j can be natural numbers equal to or less than m and n, respectively.

[0114] Figure 4 Each of the plurality of pixels PX shown may have the same as Figure 5 The equivalent circuit diagram of pixel PXij shown has the same circuit configuration. In this embodiment, the pixel circuit unit PXC of pixel PXij includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Furthermore, each of the first transistors T1 to the seventh transistor T7 is a P-type transistor having a low-temperature polycrystalline silicon (“LTPS”) semiconductor layer. However, each of the first transistors T1 to the seventh transistor T7 is not limited to this, and may be an N-type transistor having an oxide semiconductor semiconductor layer. In this embodiment, at least one of the first transistors T1 to the seventh transistor T7 may be an N-type transistor, and the remainder may be P-type transistors. Additionally, the circuit configuration of pixel PX of the present invention is not limited to... Figure 5 Circuit configuration. Figure 5 The pixel circuit unit PXC shown is merely an example, and the configuration of the pixel circuit unit PXC can be modified and implemented.

[0115] Reference Figure 5 In this embodiment, the pixel PXij of the display device DD includes a first transistor T1 to a seventh transistor T7, a capacitor Cst, and at least one light-emitting diode ED. In this embodiment, an example of a pixel PXij including one light-emitting diode ED will be described.

[0116] The (j-1)th first scan line GILj-1, the jth first scan line GILj, the jth second scan line GWLj, and the jth light emission control line EMLj can respectively transmit the (j-1)th first scan signal GIj-1, the jth first scan signal GIj, the jth second scan signal GWj, and the jth light emission control signal EMj. The i-th data line DL transmits the i-th data signal Di. The i-th data signal Di can have the same characteristics as the input to the display device DD (refer to...). Figure 4 ) image input signal RGB (reference) Figure 4The corresponding voltage levels are: the first driving voltage line VL1, the second driving voltage line VL2, and the third driving voltage line VL3, which can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, and the initialization voltage VINT.

[0117] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted from the i-th data line DLi according to the switching operation of the second transistor T2, and can provide a drive current Id to the light-emitting diode ED.

[0118] The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line GILj. The second transistor T2 can be turned on according to the j-th first scan signal GIj transmitted through the j-th first scan line GILj, and can transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0119] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line GILj. The third transistor T3 can be turned on according to the j-th first scan signal GIj transmitted through the j-th first scan line GILj, so as to connect the gate electrode and the second electrode of the first transistor T1 to each other, and therefore the first transistor T1 can be connected in the form of a diode.

[0120] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third drive voltage line VL3 for transmitting the initialization voltage VINT, and a gate electrode connected to the (j-1)th first scan line GILj-1. The fourth transistor T4 can be turned on according to the (j-1)th first scan signal GIj-1 transmitted through the (j-1)th first scan line GILj-1 to transmit the initialization voltage VINT to the gate electrode of the first transistor T1, and thus can perform an initialization operation that initializes the voltage of the gate electrode of the first transistor T1.

[0121] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th light emission control line EMLj.

[0122] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the j-th light-emitting control line EMLj.

[0123] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously according to the j-th light emission control signal EMj received through the j-th light emission control line EMLj, and thus the first driving voltage ELVDD can be compensated and transmitted to the light emission diode ED through the first transistor T1 connected in the form of a diode.

[0124] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the j-th second scan line GWLj.

[0125] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second driving voltage line VL2, which transmits the second driving voltage ELVSS. The configuration of pixel PXij in the embodiments is not limited to... Figure 5 The configuration shown can be varied, and the number of each of the transistors and capacitors included in a pixel PXij and their connection relationships can be changed in various ways.

[0126] Figure 6 It is used to describe Figure 4 A timing diagram illustrating an embodiment of the operation of one of the pixels PX in a display device DD. (Refer to...) Figure 5 and Figure 6 The operation of pixel PXij of the display device DD in the embodiment is described.

[0127] Reference Figure 5 and Figure 6 During the initialization period in frame F, a low-level first scan signal GIj-1 is provided through the (j-1)th first scan line GILj-1. In response to the low-level first scan signal GIj-1, the fourth transistor T4 is turned on, and the initialization voltage VINT is transmitted through the fourth transistor T4 to the gate electrode of the first transistor T1, thereby initializing the first transistor T1.

[0128] Subsequently, when a low-level first scan signal GIj is provided via the j-th first scan line GILj during the data programming and compensation period, the third transistor T3 is turned on. The first transistor T1 is connected as a diode via the turned-on third transistor T3 and is forward biased. Furthermore, the second transistor T2 is turned on via the low-level first scan signal GIj. Then, a compensation voltage Di-Vth, obtained by subtracting the threshold voltage Vth of the first transistor T1 from the i-th data signal Di provided by the i-th data line DL1, is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage Di-Vth.

[0129] The first driving voltage ELVDD and the compensation voltage Di-Vth can be applied to both ends of the capacitor Cst, and the charge corresponding to the voltage difference between the two ends can be stored in the capacitor Cst.

[0130] The seventh transistor T7 is turned on by receiving a low-level second scan signal GWj via the j-th second scan line GWLj. Due to the seventh transistor T7, a portion of the drive current Id can flow through the seventh transistor T7 as a bypass current Ibp.

[0131] When the light-emitting diode ED emits light even when the minimum drive current for displaying a black image in the first transistor T1 flows as the drive current Id, the black image is not displayed correctly. Accordingly, in the embodiment of the invention, the seventh transistor T7 in pixel PXij can shunt a portion of the minimum drive current of the first transistor T1 as a bypass current Ibp to a current path other than the current path toward the light-emitting diode ED. Here, the minimum drive current of the first transistor T1 refers to the current under the condition that the first transistor T1 is turned off because the gate-source voltage of the first transistor T1 is lower than the threshold voltage Vth. As described above, the minimum drive current under the condition that the first transistor T1 is turned off (e.g., a current of about 10 picoamperes (pA) or less) is transmitted to the light-emitting diode ED, thereby allowing the black image to be displayed. When the minimum drive current flows to display a black image, the shunt transmission of the bypass current Ibp can have a strong effect; however, when a large drive current flows to display images such as general images and white images, the bypass current Ibp can be said to have a small effect. Accordingly, when the drive current Id used to display a black image flows, the luminous current Ied of the light-emitting diode ED, obtained by subtracting the bypass current Ibp flowing through the seventh transistor T7 from the drive current Id, has a minimum current level sufficient to accurately display a black image. Consequently, by using the seventh transistor T7 to achieve an image with accurate black brightness, contrast is improved. In this embodiment, the bypass signal is a low-level second scan signal GWj, but it is not limited to this.

[0132] Subsequently, during the light-emitting period, the level of the j-th light-emitting control signal EMj provided from the j-th light-emitting control line EMLj changes from high to low. During the light-emitting period, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level j-th light-emitting control signal EMj. Then, the drive current Id is generated based on the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and the drive current Id is provided to the light-emitting diode ED through the sixth transistor T6, so that the light-emitting current Ied flows through the light-emitting diode ED.

[0133] Figure 7 This is a block diagram of an embodiment of the scan driver SD1 according to the present invention. Figure 7 The scan driver SD1 shown outputs the first scan signal GI0 to GIn. Besides... Figure 7 In addition to the scan drive SD1 shown, Figure 4 The scan drive circuit SD shown may also include a second scan signal GW1 to GWn (see Figure 16 The scan driver (not shown).

[0134] Reference Figure 7 The scan driver SD1 includes drive levels ST0 to STn.

[0135] Each of the drive levels ST0 to STn Figure 4 The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3. The third clock signal CLK3 can act as a masking signal. The third clock signal CLK3 can also be referred to as the masking clock signal. The third clock signal CLK3 can indicate the first DA2-1, the second DA2-2, and the third DA2-3 (see reference). Figure 3C The signal indicating the driving / non-driving state.

[0136] In response to the third clock signal CLK3, during the multi-frequency mode MFMb, each of the drive stages ST0 to STn can drive the first portion of the second display area DA2 and may not drive the second portion of the second display area DA2.

[0137] During the multi-frequency mode MFMb, the drive controller 100 can divide the second display area DA2 into multiple blocks (e.g., a first block DA2-1, a second block DA2-2, and a third block DA2-3), and can output a third clock signal CLK3 to drive at least one of the first blocks DA2-1, the second blocks DA2-2, and the third blocks DA2-3 corresponding to the first portion, and to not drive at least one of the first blocks DA2-1, the second blocks DA2-2, and the third blocks DA2-3 corresponding to the second portion.

[0138] Each of the drive stages ST0 to STn receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 4 The drive controller 100 or voltage generator 300 shown is provided.

[0139] In this embodiment, the driver stages ST0 to STn output first scan signals GI0 to GIn and carry signals CR0 to CRn-1. The first scan signals GI0 to GIn are respectively provided to... Figure 4 The first scan lines shown are GIL0 to GILn. The j-th drive level STj (refer to...) is among drive levels ST0 to STn. Figure 8 and Figure 9A The carry signal CRj output can be provided to the (j+1)th driver STj+1 after the j-th driver STj (refer to...). Figure 9A ).

[0140] Driver stage ST0 can receive a start signal FLM as a carry signal. Driver stages ST1 to STn have a subordinate connection relationship where each of driver stages ST1 to STn receives a carry signal output from the previous driver stage as a carry signal. In an embodiment, for example, driver stage ST1 receives a carry signal CR0 output from the previous driver stage ST0, and driver stage ST2 receives a carry signal CR1 output from the previous driver stage ST1. Although, in Figure 7 In this embodiment, the carry signal CRj output from the j-th driver stage STj is provided to the (j+1)-th driver stage STj+1, but the invention is not limited thereto. In this embodiment, the carry signal CRj output from the j-th driver stage STj can be provided as the carry signal of the (j+k)-th driver stage STj+k (where j and k are each a natural number).

[0141] Figure 8 It shows Figure 7 The j-th driver STj (j is a positive integer) is shown among the driver levels ST0 to STn. Figure 7Each of the plurality of driver levels ST0 to STn shown may include the same circuit configuration as the j-th driver level STj. Hereinafter, the j-th driver level STj is also referred to as driver level STj, and the j-th first scan signal GIj is also referred to as first scan signal GIj.

[0142] Reference Figure 8 The driver stage STj includes a driver circuit DC, a masking circuit MSC, first input terminals IN1 to fourth input terminals IN4, a first voltage terminal V1 and a second voltage terminal V2, and a first output terminal OUT1 and a second output terminal OUT2. The driver circuit DC includes transistors PT1 to PT7 and capacitors PC1 and PC2.

[0143] The DC drive circuit receives the first clock signal CLK1, the second clock signal CLK2, the carry signal CRj-1, and the third clock signal CLK3 through the first input terminal IN1 to the fourth input terminal IN4, respectively. The DC drive circuit receives the first voltage VGL and the second voltage VGH through the first voltage terminal V1 and the second voltage terminal V2, respectively. The DC drive circuit outputs the first scan signal GIj and the carry signal CRj through the first output terminal OUT1 and the second output terminal OUT2, respectively. The carry signal CRj can be provided to the (j+1)th drive stage STj+1 after the j-th drive stage STj as the carry signal CRj. The carry signal CRj-1 received through the third input terminal IN3 can be used as the carry signal from... Figure 7 The carry signal CRj-1 is shown as the output of the previous driver stage STj-1. Figure 7 The carry signal of the drive stage ST0 shown can be the start signal FLM.

[0144] In an embodiment, for example, Figure 7 In the driver stages ST0 to STn shown, each of the driver stages (e.g., odd-numbered driver stages) receives a first clock signal CLK1 at its first input terminal IN1 and a second clock signal CLK2 at its second input terminal IN2. In an embodiment, for example, each of the driver stages ST0 to STn (e.g., even-numbered driver stages) receives the second clock signal CLK2 at its first input terminal IN1 and the first clock signal CLK1 at its second input terminal IN2.

[0145] Transistor PT1 is connected between the third input terminal IN3 and the first node N1 and includes a gate electrode connected to the first input terminal IN1. Transistor PT2 is connected between the second voltage terminal V2 and the third node N3 and includes a gate electrode connected to the second node N2. Transistor PT3 is connected between the third node N3 and the first node N1 and includes a gate electrode connected to the second input terminal IN2.

[0146] Transistor PT4 is connected between the second node N2 and the first input terminal IN1 and includes a gate electrode connected to the first node N1. Transistor PT5 is connected between the second node N2 and the first voltage terminal V1 and includes a gate electrode connected to the first input terminal IN1. Transistor PT6 is connected between the second voltage terminal V2 and the second output terminal OUT2 and includes a gate electrode connected to the second node N2. Transistor PT7 is connected between the second output terminal OUT2 and the second input terminal IN2 and includes a gate electrode connected to the first node N1.

[0147] Capacitor PC1 is connected between the first node N1 and the second output terminal OUT2. Capacitor PC2 is connected between the second voltage terminal V2 and the second node N2.

[0148] The masking circuit MSC includes a first masking transistor MT1 and a second masking transistor MT2. The first masking transistor MT1 can stop (or mask) the output of the first scan signal GIj in response to a signal from the second node N2. The first masking transistor MT1 is connected between the second voltage terminal V2 and the first output terminal OUT1 and includes a gate electrode connected to the second node N2.

[0149] The second masking transistor MT2 is connected between the first output terminal OUT1 and the fourth input terminal IN4 and includes a gate electrode connected to the second output terminal OUT2.

[0150] Figure 9A and Figure 9B Each is shown Figure 7 The timing diagram shows the operation of the (j-1)th drive level STj-1, the jth drive level STj, and the (j+1)th drive level STj+1 in the scan driver SD1.

[0151] Reference Figure 7 , Figure 8 and Figure 9A The first clock signal CLK1 and the second clock signal CLK2 are signals with the same frequency that transition to an active level (e.g., a low level) during different horizontal time periods H. Each of the horizontal time periods H drives the display panel DP (refer to...). Figure 4 The time period of pixels PX in a row on the first direction DR1. For example, the horizontal time period H may include the (j-4)th horizontal time period Hj-4, the (j-3)th horizontal time period Hj-3, the (j-2)th horizontal time period Hj-2, the (j-1)th horizontal time period Hj-1, the jth horizontal time period Hj, and the (j+1)th horizontal time period Hj+1.

[0152] The operation of the (j-1)th driver level STj-1 is as follows.

[0153] The (j-1)th driver stage STj-1 receives the second clock signal CLK2 through the first input terminal IN1 and the first clock signal CLK1 through the second input terminal IN2.

[0154] When the second clock signal CLK2 received via the first input terminal IN1 is low during the (j-2)th level period Hj-2, transistor PT1 in the DC drive circuit is turned on. With transistor PT1 on, the low-level carry signal CRj-2 is transmitted to the first node N1 via transistor PT1. When the second clock signal CLK2 is low, transistor PT5 is turned on, and the second node N2 discharges to the first voltage VGL. When the second node N2 is low, transistor PT6 is turned on, and the second output terminal OUT2 outputs a high-level carry signal CRj-1. Furthermore, when the first node N1 is low, transistor PT7 is turned on, and therefore the second output terminal OUT is held high by the first clock signal CLK1 received via the second input terminal IN2.

[0155] When the second clock signal CLK2 is high during the (j-1)th horizontal period Hj-1, transistor PT5 is turned off, and the level of the second node N2 becomes high through the conducting transistor PT4, causing transistor PT6 and the first masking transistor MT1 to turn off. When the first clock signal CLK1 received through the second input terminal IN2 is low, the level of the first node N1 is changed to a level lower than the low level of the first node N1 through capacitor PC1, and transistor PT7 is turned on, allowing the second output terminal OUT2 to output a low-level carry signal CRj-1. Because the third clock signal CLK3 is low when the second output terminal OUT2 outputs a low-level carry signal CRj-1, the first scan signal GIj-1 output to the first output terminal OUT1 is also activated at a low level. That is, the (j-1)th driver stage STj-1 outputs a low-level first scan signal GIj-1 and a low-level carry signal CRj-1 during the (j-1)th horizontal period Hj-1.

[0156] During the j-th horizontal time period Hj, the third clock signal CLK3 transitions from low to high.

[0157] The STj operation of the j-th driver level is as follows.

[0158] The j-th driver stage STj receives the first clock signal CLK1 through the first input terminal IN1 and the second clock signal CLK2 through the second input terminal IN2.

[0159] When the first clock signal CLK1 is low during the (j-1)th level period Hj-1, transistor PT1 is turned on. With transistor PT1 on, the low-level carry signal CRj-1 is transmitted to the first node N1 via transistor PT1. When the first clock signal CLK1 is low, transistor PT5 is turned on, and the second node N2 discharges to the first voltage VGL. When the second node N2 is low, transistor PT6 is turned on, and the second output terminal OUT2 outputs a high-level carry signal CRj. Furthermore, when the first node N1 is low, transistor PT7 is turned on, and therefore, the second output terminal OUT2 remains high due to the second clock signal CLK2 received via the second input terminal IN2.

[0160] When the first clock signal CLK1 is high during the j-th horizontal time period Hj, transistor PT5 is turned off, and the level of the second node N2 becomes high through the conducting transistor PT4, causing transistor PT6 to turn off. When the second clock signal CLK2 received through the second input terminal IN2 is low, the level of the first node N1 is changed to a level lower than the low level of the first node N1 through capacitor PC1, so that the second output terminal OUT2 can output a low-level carry signal CRj. At this time, the third clock signal CLK3 is high, and therefore, the first scan signal GIj is held high through the second masking transistor MT2. That is, the j-th driver stage STj outputs a high-level first scan signal GIj and a low-level carry signal CRj during the j-th horizontal time period Hj.

[0161] The (j+1)th driver-level STj+1 operation is as follows.

[0162] The (j+1)th driver stage STj+1 receives the second clock signal CLK2 through the first input terminal IN1 and the first clock signal CLK1 through the second input terminal IN2.

[0163] When the second clock signal CLK2 received via the first input terminal IN1 is low during the j-th level period Hj, transistor PT1 in the DC drive circuit is turned on. With transistor PT1 on, a low-level carry signal CRj is transmitted to the first node N1 via transistor PT1. When the second clock signal CLK2 is low, transistor PT5 is turned on, and the second node N2 discharges to the first voltage VGL. When the second node N2 is low, transistor PT6 is turned on, and the second output terminal OUT2 outputs a high-level carry signal CRj+1. Furthermore, when the first node N1 is low, transistor PT7 is turned on, and therefore, the second output terminal OUT2 remains high due to the first clock signal CLK1 received via the second input terminal IN2.

[0164] When the second clock signal CLK2 is high during the (j+1)th horizontal period Hj+1, transistor PT5 is turned off, and the level of the second node N2 becomes high through the conducting transistor PT4, causing transistor PT6 and the first masking transistor MT1 to turn off. When the first clock signal CLK1 received through the second input terminal IN2 is low, the level of the first node N1 is changed to a level lower than the low level of the first node N1 through capacitor PC1, and transistor PT7 is turned on, so that the second output terminal OUT2 can output a low-level carry signal CRj+1. Because the third clock signal CLK3 is high when the second output terminal OUT2 outputs the low-level carry signal CRj+1, the first scan signal GIj+1 output to the first output terminal OUT1 remains high. That is, the (j+1)th driver stage STj+1 outputs a high-level first scan signal GIj+1 and a low-level carry signal CRj+1 during the (j+1)th horizontal period Hj+1.

[0165] like Figure 7 , Figure 8 and Figure 9A As shown, when the third clock signal CLK3 changes from low level to high level, the first scan signals GIj and GIj+1 can remain in the high-level inactive state, and the carry signals CRj and CRj+1 can be transmitted to the corresponding subsequent stages respectively.

[0166] Figure 9B A method is shown to keep the carry signal CRj+1 and the first scan signals GIj and GIj+1 in an inactive state at a high level.

[0167] Reference Figure 7 , Figure 8 and Figure 9B When the first clock signal CLK1 is high during the j-th horizontal time period Hj, transistor PT5 of the j-th driver stage STj is turned off, and the level of the second node N2 becomes high through the conducting transistor PT4, causing transistor PT6 to turn off. When the second clock signal CLK2 received through the second input terminal IN2 is low, the level of the first node N1 is changed to a level lower than the low level of the first node N1 through capacitor PC1, and transistor PT7 is turned on, so that the second output terminal OUT2 can output a low-level carry signal CRj. At this time, the first scan signal GIj is kept high through the high-level third clock signal CLK3. That is, the j-th driver stage STj outputs a high-level first scan signal GIj and a low-level carry signal CRj during the j-th horizontal time period Hj.

[0168] During the (j+1)th horizontal period Hj+1, transistor PT5 is turned on by a low-level second clock signal CLK2 received via the first input terminal IN1. The second node N2 is held low by the turned-on transistor PT5, and transistor PT6 is turned on. Accordingly, a high-level carry signal CRj+1 is output. The first scan signal GIj+1 is held high by a high-level third clock signal CLK3. That is, the (j+1)th driver stage STj+1 outputs a high-level first scan signal GIj+1 and a high-level carry signal CRj+1 during the (j+1)th horizontal period Hj+1.

[0169] like Figure 9A and Figure 9B As shown, the third clock signal CLK3 can mask the outputs of the first scan signals GIj and GIj+1. Furthermore, when both the first clock signal CLK1 and the second clock signal CLK2 are low, the output of the carry signal CRj+1 can be masked.

[0170] Figure 10 It is shown in Figure 3A In normal NFM mode, from the drive controller 100 (refer to...) Figure 4 Provided to scan driver SD1 (refer to) Figure 7 The timing diagram of the start signal FLM, the third clock signal CLK3, and the image signal DS provided to the display panel DP.

[0171] Reference Figure 4 and Figure 10 The start signal FLM can be activated at a low level in each of the multiple frames from frame 1 to frame 60 (F60) in normal mode NFM. During normal mode NFM, the third clock signal CLK3 remains low. When the third clock signal CLK3 is low, the driver stages ST0 to STn can output the first scan signals GI0 to GIn, respectively.

[0172] In the embodiment, each of the first frame F1 to the 60th frame F60 has the same duration of approximately 16 milliseconds (ms).

[0173] In normal NFM mode, the image signal DS provided to the display panel DP can include the signal to be displayed. Figure 1 The image signals D1 to D60 in the first display area DA1 and the second display area DA2 shown in the figure.

[0174] Figure 11 It is shown in Figure 3B Multi-frequency mode MFMa from drive controller 100 (refer to) Figure 4 Provided to scan driver SD1 (refer to) Figure 7The timing diagram of the start signal FLM, the third clock signal CLK3, and the image signal DS provided to the display panel DP.

[0175] Reference Figure 4 and Figure 11 In the multi-frequency mode MFMa, the display device DD can set the driving frequency of the first display area DA1 that displays the first image IM1 (i.e., a moving image) to a first driving frequency, and can set the driving frequency of the second display area DA2 that displays the second image IM2 (i.e., a still image) to a second driving frequency lower than the first driving frequency. In an embodiment, for example, when the normal frequency is about 60Hz, the first driving frequency may be about 90Hz, and the second driving frequency may be about 30Hz.

[0176] In an embodiment, for example, a portion of the image signal DS provided to the display panel DP in frames (3a+1) F1, F4, ..., and F88 may include the image signal to be displayed on the display panel DP. Figure 1 The (3a+1)th image signals D1, D4, ..., D88 in the first display area DA1 and the second display area DA2 shown.

[0177] Another portion of the image signal DS provided to the display panel DP in frames (3a+2) and (3a+3) F2, F3, F5, F6, ..., F89 and F90 may include the portion to be displayed. Figure 1 The first display area DA1 shown contains the (3a+2)th image signal and the (3a+3)th image signals D2a, D3a, D5a, D6a, ..., D89a and D90a.

[0178] In an embodiment, for example, the duration of each of frames F1, F4, ..., and F88 in frame (3a+1) may be approximately 16 ms, and the duration of each of frames F2, F3, F5, F6, ..., F89 and F90 in frames (3a+2) and (3a+3) may be approximately 8 ms.

[0179] When Figure 11 As shown, when there is a difference in the duration between the first frame F1 and the 90th frame F90, the deviation in pixel emission time caused by the difference in frame switching speed (or frame rate) can be perceived by the user as a flickering phenomenon.

[0180] Figure 12 It is shown in Figure 3C Multi-frequency mode MFMb from drive controller 100 (refer to) Figure 4 Provided to scan driver SD1 (refer to) Figure 7 The timing diagram of the start signal FLM, the third clock signal CLK3, and the image signal DS provided to the display panel DP.

[0181] Reference Figure 3C and Figure 12 In the multi-frequency mode MFMb, the display device DD can set the driving frequency of the first display area DA1 that displays the first image IM1 (i.e., a moving image) to a first driving frequency, and can set the driving frequency of the second display area DA2 that displays the second image IM2 (i.e., a still image) to a second driving frequency lower than the first driving frequency. In an embodiment, for example, when the normal frequency is about 60 Hz, the first driving frequency may be about 90 Hz, and the second driving frequency may be about 30 Hz.

[0182] The image signal DS provided to the display panel DP in each of the first frame F1 to the 90th frame F90 may include image signals DD1 to DD90, each of which includes the image signals to be displayed. Figure 1 The image signal in the first display area DA1 and the image signal to be displayed in a portion of the second display area DA2 are shown.

[0183] Figure 13 It is shown Figure 12 The timing diagrams of the start signal FLM, the third clock signal CLK3, and the image signal DS in some frames F1, F2, and F3 shown in the frame diagram.

[0184] Figure 14A It is shown Figure 13 The enlarged timing diagram of the first frame F1 shown.

[0185] Figure 14B It is shown Figure 13 The enlarged timing diagram of the second frame F2 shown.

[0186] Figure 14C It is shown Figure 13 The enlarged timing diagram of the third frame F3 shown.

[0187] Reference Figure 3C , Figure 13 and Figure 14A During the first frame F1, the image signal DD1 provided to the display panel DP includes a first area image signal D1a to be displayed in the first display area DA1 and a first block image signal D1b-1 to be displayed in the first block DA2-1 of the second display area DA2. The third clock signal CLK3 goes high after the last scan line of the first block DA2-1 is driven, and therefore the first scan signal to be provided to the first scan line of the second block DA2-2 can be kept high.

[0188] During the first frame F1, the first clock signal CLK1 and the second clock signal CLK2 can be maintained at the second drive frequency (e.g., about 30Hz).

[0189] Reference Figure 3C , Figure 13 and Figure 14B During the second frame F2, the image signal DD2 provided to the display panel DP includes a first area image signal D2a to be displayed in the first display area DA1 and a second block image signal D1b-2 to be displayed in the second block DA2-2 of the second display area DA2. The third clock signal CLK3 goes high after the last scan line of the first display area DA1 is driven, and therefore the first scan signal to be provided to the first scan line of the first block DA2-1 can be kept high.

[0190] During the first delay time t2a, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 may be kept higher than the second drive frequency (e.g., about 30 Hz). In an embodiment, for example, during the first delay time t2a, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 may be tens of times (e.g., about 20 to about 40 times) the second drive frequency.

[0191] As the frequencies of the first clock signal CLK1 and the second clock signal CLK2 increase, the operating speed of the driver stage corresponding to the first DA2-1 becomes higher. As the frequencies of the first clock signal CLK1 and the second clock signal CLK2 increase, the transmission speed of the carry signal of the driver stage corresponding to the first DA2-1 can also increase.

[0192] The third clock signal CLK3 goes low after the first delay time t2a has elapsed, and thus the first scan signal can be driven low from the first scan line of the second DA2-2. The third clock signal CLK3 goes high after the last scan line of the second DA2-2 has been driven, and thus the first scan signal to be provided to the first scan line of the third DA2-3 can be kept high.

[0193] Reference Figure 3C , Figure 13 and Figure 14CDuring the third frame F3, the image signal DD3 provided to the display panel DP includes a first area image signal D3a to be displayed in the first display area DA1 and a third block image signal D1b-3 to be displayed in the third block DA2-3 of the second display area DA2. The third clock signal CLK3 goes high after the last scan line of the first display area DA1 is driven, and therefore the first scan signal to be provided from the first scan line of the first block DA2-1 to the last scan line of the second block DA2-2 can be kept high.

[0194] During the second delay time t2c, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 may be kept higher than the second drive frequency (e.g., about 30 Hz). In an embodiment, for example, during the second delay time t2c, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 may be tens of times (e.g., about 20 to about 40 times) the second drive frequency.

[0195] As the frequencies of the first clock signal CLK1 and the second clock signal CLK2 increase, the operating speed of the driver stages corresponding to the first DA2-1 and the second DA2-2 becomes higher. As the frequencies of the first clock signal CLK1 and the second clock signal CLK2 increase, the transmission speed of the carry signal of the driver stages corresponding to the first DA2-1 and the second DA2-2 can also increase.

[0196] The third clock signal CLK3 can go low after the second delay time t2c has elapsed, and thus can drive the first scan signal at a low level starting from the first scan line of the third DA2-3.

[0197] In the first frame F1, the time t1 for which the first area image signal D1a corresponding to the first display area DA1 is provided to the display panel DP can be, for example, about 8ms. The time t2 for which the first block image signal D1b-1 corresponding to the first block DA2-1 of the second display area DA2 is provided to the display panel DP can be, for example, about 3ms.

[0198] In the second frame F2, the time t1 for the first area image signal D2a corresponding to the first display area DA1 to be provided to the display panel DP can be, for example, about 8ms. The sum t2 of the first delay time t2a and the time t2b for the second image signal D1b-2 corresponding to the second block DA2-2 of the second display area DA2 to be provided to the display panel DP can be, for example, about 3ms (t2 = t2a + t2b).

[0199] In the third frame F3, the time t1 for the first area image signal D3a corresponding to the first display area DA1 to be provided to the display panel DP can be, for example, about 8ms. The sum t2 of the second delay time t2c and the time t2d for the third image signal D1b-3 corresponding to the third block DA2-3 of the second display area DA2 to be provided to the display panel DP can be, for example, about 3ms (t2=t2c+t2d).

[0200] In this embodiment, the first delay time t2a is the carry transmission time of the driver stage corresponding to the first DA2-1, and the second delay time t2c is the carry transmission time of the driver stages corresponding to the first DA2-1 and the second DA2-2. Accordingly, the second delay time t2c can be longer than the first delay time t2a.

[0201] Figure 13 The method shown for driving the first frame F1 to the third frame F3 can be used in driving Figure 12 The fourth frame F4 to the 90th frame F90 shown are repeated.

[0202] Reference Figure 3C and Figure 12 In the multi-frequency mode MFMb, the drive frequency of the first display area DA1 of the display device DD that will display the first image IM1 (i.e., the moving image) is set to the first drive frequency, and the drive frequency of the second display area DA2 that will display the second image IM2 (i.e., the still image) is set to the second drive frequency, which is lower than the first drive frequency.

[0203] In the multi-frequency mode MFMb, the display device DD can set the driving frequency of the second display area DA2 to a second driving frequency lower than the first driving frequency by dividing the second display area DA2 into a first block DA2-1, a second block DA2-2 and a third block DA2-3 and driving the first block DA2-1, the second block DA2-2 and the third block DA2-3 alternately and sequentially.

[0204] As described above, even when the first driving frequency of the first display area DA1 and the second driving frequency of the second display area DA2 are different from each other, the duration of each of the first frame F1 to the 90th frame F90 can be kept constant, for example, about 11 ms. Since the duration of the first frame F1 to the 90th frame F90 becomes consistent, display quality degradation such as jitter can be prevented.

[0205] The number of blocks in the second display area DA2 can be determined based on the ratio of the first driving frequency of the first display area DA1 to the second driving frequency of the second display area DA2.

[0206] Table 1 below shows the number of blocks in the second display area DA2 based on the first driving frequency of the first display area DA1 and the second driving frequency of the second display area DA2.

[0207] [Table 1]

[0208]

[0209] Figure 15 It is shown in Figure 3C Multi-frequency mode MFMb from drive controller 100 (refer to) Figure 4 Provided to scan driver SD1 (refer to) Figure 7 The timing diagram of the start signal FLM, the third clock signal CLK3, and the image signal DS provided to the display panel DP.

[0210] Reference Figure 15 In multi-frequency mode, the display device DD can set the driving frequency of a first display area DA1 that displays a first image IM1 (i.e., a moving image) to a first driving frequency, and can set the driving frequency of a second display area DA2 that displays a second image IM2 (i.e., a still image) to a second driving frequency lower than the first driving frequency. In an embodiment, for example, when the normal frequency is about 60Hz, the first driving frequency may be about 90Hz, and the second driving frequency may be about 30Hz.

[0211] The display device DD can be with Figure 11 The first frame F1 to the third frame F3 are driven in the same way as in the multi-frequency mode MFMa shown, and can be used in conjunction with... Figure 12 The fourth frame F4 to the 90th frame F90 are driven in the same way as in the multi-frequency mode MFMb shown.

[0212] That is, the display device DD can be prepared during the first frame F1 to the third frame F3 to drive the first block DA2-1, the second block DA2-2 and the third block DA2-3 of the second display area DA2 in the fourth frame F4 to the 90th frame F90.

[0213] Figure 16 This is a block diagram of an embodiment of the scan drive circuit SD according to the present invention. Figure 16 The scan drive circuit SD shown outputs a first scan signal GI0 to GIn and a second scan signal GW0 and a second scan signal GW1 to GWn.

[0214] Reference Figure 16 The scan drive circuit SD includes drive stages STA0 to STAN.

[0215] Each of the drive levels STA0 to STAN Figure 4The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a first masking signal MS1, and a second masking signal MS2. The first masking signal MS1 and the second masking signal MS2 can be signals indicating the drive / non-drive state of the first DA2-1, the second DA2-2, and the third DA2-3. Each of the drive stages STA0 to STAN receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 4 The drive controller 100 or voltage generator 300 shown is provided.

[0216] In this embodiment, the driver stages STA0 to STAN output first scan signals GI0 to GIn and second scan signals GW0 to GWn. The first scan signals GI0 to GIn are respectively provided to... Figure 4 The first scan lines GIL0 to GILn are shown in the diagram. The second scan signals GW1 to GWn are respectively provided to… Figure 4 The second scan lines GWL1 to GWLn are shown in the figure.

[0217] The second scan signal GWj output from the j-th driver stage STAj among driver stages STA0 to STAN can be provided as the carry signal of the (j+1)-th driver stage STAj+1 after the j-th driver stage STAj.

[0218] Figure 17 It shows Figure 16 The j-th driver level STAj (j is a positive integer) is shown among the driver levels STA0 to STAN. Figure 16 Each of the plurality of driver levels STA0 to STAN shown may include the same circuit configuration as the j-th driver level STAj. Hereinafter, the j-th driver level STAj is also referred to as driver level STAj.

[0219] Reference Figure 17 The driver stage STAj includes a driver circuit DC, a first masking circuit MSC1 and a second masking circuit MSC2, first input terminals IN1 to fifth input terminals IN5, a first voltage terminal V1 and a second voltage terminal V2, and a first output terminal OUT1 and a second output terminal OUT2. The driver circuit DC includes transistors PT1 to PT7 and capacitors PC1 and PC2, and has... Figure 8 The circuit configuration of the DC drive circuit shown is the same as and is the same as... Figure 8 The circuit configuration of the DC drive circuit shown operates similarly, so a repeated description will not be given.

[0220] The first masking circuit MSC1 includes a first masking transistor MT11, and the second masking circuit MSC2 includes a second masking transistor MT12. The first masking transistor MT11 can be connected between the second voltage terminal V2 and the first output terminal OUT1, and can stop (or mask) the output of the first scan signal GIj in response to a first masking signal MS1 input from the fourth input terminal IN4. The second masking transistor MT12 can be connected between the first output terminal OUT1 and the second output terminal OUT2, and can stop (or mask) the output of the second scan signal GWj in response to a second masking signal MS2 input from the fifth input terminal IN5. The second scan signal GWj output from the j-th driver stage STAj can be provided as the carry signal CRj of the (j+1)-th driver stage STAj+1. Similarly, the j-th driver stage STAj receives the second scan signal GWj-1 output from the (j-1)-th driver stage STAj-1 as the carry signal CRj-1 via the third input terminal IN3.

[0221] Figure 18A and Figure 18B Each shows Figure 16 The timing diagram shows the operation of the (j-1)th driver stage STAj-1, the jth driver stage STAj, and the (j+1)th driver stage STAj+1 in the scan driver circuit SD shown.

[0222] The operations of the (j-1)th driver level STAj-1, the jth driver level STAj, and the (j+1)th driver level STAj+1 are related to Figure 9A and Figure 9B The operations of the (j-1)th drive level STj-1, the jth drive level STj, and the (j+1)th drive level STj+1 in the scan driver SD1 shown are similar, and therefore will not be described again.

[0223] Reference Figure 17 and Figure 18A When the first masking signal MS1 transitions from high to low during the j-th horizontal time period Hj, the first masking transistor MT11 is turned on, and therefore the first scan signal GIj remains at the second voltage VGH (i.e., high level). Furthermore, when the second masking signal MS2 transitions from low to high, the second masking transistor MT12 is turned off, thereby disconnecting the electrical connection between the first output terminal OUT1 and the second output terminal OUT2. Accordingly, the second scan signal GWj can be determined based on the voltage level of the connection node between transistors PT6 and PT7 in the DC drive circuit, independent of the first scan signal GIj.

[0224] Because transistor PT6 is turned off and transistor PT7 is turned on during the j-th horizontal time period Hj, the second scan signal GWj can be switched to a low level by the second clock signal CLK2 received via the second input terminal IN2.

[0225] Because the first masking signal MS1 is at a low level during the (j+1)th horizontal time period Hj+1, the first scan signal GIj+1 output from the (j+1)th driver stage STAj+1 remains at the second voltage VGH (i.e., high level). The drive circuit DC in the (j+1)th driver stage STAj+1 can receive the second scan signal GWj from the j-th driver stage STAj as a carry signal CRj, and can output the low-level second scan signal GWj+1.

[0226] Figure 18B A method is shown to keep the second scan signal GWj+1 and the first scan signals GIj and GIj+1 in a high-level inactive state.

[0227] Reference Figure 17 and Figure 18B In the j-th drive stage STAj, when the first clock signal CLK1 is high during the j-th horizontal time period Hj, transistor PT5 is turned off, and the level of the second node N2 becomes high through the conducting transistor PT4, causing transistor PT6 to turn off. When the second clock signal CLK2 received through the second input terminal IN2 is low, the level of the first node N1 is changed to a level lower than the low level of the first node N1 through capacitor PC1, and transistor PT7 is turned on, so that the second output terminal OUT2 can output a low-level second scan signal GWj. At this time, because the first masking transistor MT11 is turned on through the low-level first masking signal MS1, the first scan signal GIj output to the first output terminal OUT1 remains high during the j-th horizontal time period Hj.

[0228] In the (j+1)th drive stage STAj+1, transistor PT5 is turned on during the (j+1)th horizontal period Hj+1 by receiving a low-level second clock signal CLK2 from the first input terminal IN1. The second node N2 is held low by the turned-on transistor PT5, and transistor PT6 is turned on. Correspondingly, a high-level second scan signal GWj+1 can be output.

[0229] like Figure 18A and Figure 18B As shown, the first masking signal MS1 and the second masking signal MS2 can mask the outputs of the first scan signals GIj and GIj+1. Furthermore, when both the first clock signal CLK1 and the second clock signal CLK2 are at a low level, they can mask the output of the second scan signal GWj+1.

[0230] because Figure 17 The driver stage STAj shown can selectively mask the second scan signal GWj and the first scan signal GIj, so the driver stage STAj can... Figure 3C Operation under the multi-frequency mode MFMb shown.

[0231] When a moving image is displayed in the first display area and a still image is displayed in the second display area, the display device with the above configuration can operate in a multi-frequency mode where the first display area is driven at a first driving frequency and the second display area is driven at a second driving frequency. Specifically, the display device can drive the second display area at the second driving frequency by dividing the second display area into multiple blocks and driving the multiple blocks alternately. Accordingly, the time period of each of the multiple frames becomes constant, and thus it is possible to prevent display quality degradation.

[0232] While embodiments of the invention have been described herein, it is to be understood that various changes and modifications can be made by those skilled in the art within the spirit and scope of the invention. The embodiments described herein are not intended to limit the technical spirit and scope of the invention, and all technical spirit within the scope of the appended claims or their equivalents will be interpreted as being included within the scope of the invention.

Claims

1. A display device, comprising: The display panel includes multiple pixels, which are respectively connected to corresponding data lines in multiple data lines and respectively connected to corresponding scan lines in multiple scan lines; Data driving circuit, driving the plurality of data lines; A scan drive circuit that drives the plurality of scan lines in response to a clock signal; as well as Drive controller: The display panel is divided into a first display area and a second display area; During multi-frequency mode, the data driving circuit and the scanning driving circuit are controlled such that the first display area is driven at a first driving frequency, and the second display area is driven at a second driving frequency lower than the first driving frequency. and During the multi-frequency mode, the second display area is divided into multiple blocks, and the blocks within the multiple blocks are driven in each frame. The drive controller controls the data drive circuit and the scan drive circuit to sequentially drive the first block of the plurality of blocks in the first display area and the second display area during the first frame of the multi-frequency mode. The drive controller controls the data drive circuit and the scan drive circuit to sequentially drive the second block of the plurality of blocks in the first display area and the second display area during a second frame that is consecutive to the first frame in the multi-frequency mode. The second frame includes a first time period, a delayed time period continuous with the first time period, and a second time period continuous with the delayed time period. During the first time period, the drive controller provides the display panel with a first area image signal corresponding to the first display area. During the second time period, the drive controller provides the display panel with the second block image signal corresponding to the second block, and The first clock signal in the clock signal has a higher frequency during the delay period than the frequency of the first clock signal during each of the first and second time periods.

2. The display device as claimed in claim 1, wherein, The consecutive frames of the multi-frequency mode have the same duration.

3. The display device as claimed in claim 1, wherein, In normal mode, the drive controller controls the data drive circuit and the scan drive circuit so that the first display area and the second display area are driven at a normal frequency. in, The second driving frequency is lower than the normal frequency, and The first driving frequency is higher than the normal frequency.

4. The display device as claimed in claim 1, wherein, During the multi-frequency mode, the drive controller alternately drives the plurality of blocks of the second display area in each frame.

5. The display device as claimed in claim 1, wherein, The scanning drive circuit includes multiple drive stages, and One of the plurality of driver levels drives the first scan line among the plurality of scan lines.

6. The display device as claimed in claim 5, wherein, The drive controller outputs a masking clock signal, and The driver level among the plurality of driver levels includes: The first output terminal is connected to the first scan line; The second output terminal outputs a carry signal. The driving circuit, in response to the clock signal and the previous carry signal, determines the signal level of each of the first and second nodes; and The masking circuit, in response to the signal from the first node, the signal from the second node, and the masking clock signal, outputs a first scan signal to the first output terminal. in, The first node is electrically connected to the second output terminal, and The previous carry signal is the carry signal output from the previous driver stage among the plurality of driver stages.

7. The display device as claimed in claim 6, wherein, The first frame and the second frame have the same duration.

8. The display device as claimed in claim 6, wherein, The masking clock signal indicates the drive / non-drive state of each of the plurality of blocks in the second display area.

9. The display device as claimed in claim 6, wherein, Each of the plurality of driver levels corresponding to the first block masks the first scan signal during the second frame.

10. The display device as claimed in claim 6, wherein, The driving stage in the plurality of driving stages further includes a first voltage terminal for receiving a first voltage and a second voltage terminal for receiving a second voltage. The masking circuit includes: A first masking transistor is connected between the second voltage terminal and the first output terminal, and includes a gate electrode connected to the second node; and A second masking transistor is connected between the first output terminal and the input terminal that receives the masking clock signal, and includes a gate electrode electrically connected to the first node.

11. The display device as claimed in claim 1, wherein, The scanning drive circuit includes multiple drive stages, and The driving stage of the plurality of driving stages drives the first scan line and the second scan line among the plurality of scan lines.

12. The display device as claimed in claim 11, wherein, The driver level among the plurality of driver levels includes: The first output terminal is connected to the first scan line; The second output terminal is connected to the second scan line; The driving circuit outputs a second scan signal to the second output terminal in response to the clock signal and the previous carry signal; A first masking circuit, in response to a first masking signal, outputs a first scan signal to the first output terminal at a predetermined level; and The second masking circuit, in response to a second masking signal, connects the first output terminal and the second output terminal to output the second scan signal as the first scan signal. The previous carry signal is the second scan signal output from the previous drive stage among the plurality of drive stages.

Images