Techniques for mitigating asymmetric long-delay stress

Abstract

This application relates to techniques for mitigating asymmetric long delay stress. A memory device can activate a memory cell during a first phase of an access operation cycle. The memory device can write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device can maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device can write the second state to the memory cell during a third phase of the access operation cycle after the second phase of the access operation cycle. The memory device can precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 103,552, filed November 24, 2020, entitled “Techniques to Mitigate Asymmetric Long Delay Stress,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to techniques for mitigating asymmetric long-delay stress. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM, on the other hand, may lose its stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memory but can also have non-volatile properties because it uses ferroelectric capacitors as storage devices. Summary of the Invention

[0006] A method is described. For example, the method may include: activating a memory cell during a first phase of an access operation cycle; writing a first state or a second state to the memory cell during the first phase of the access operation cycle; maintaining the first state or the second state at the memory cell during a second phase of the access operation cycle following the first phase of the access operation cycle; and precharging the memory cell during a third phase of the access operation cycle following the second phase of the access operation cycle.

[0007] Another method is described. For example, the method may include: activating a memory cell during a first phase of an access operation cycle; maintaining a first state or a second state at the memory cell during a second phase of the access operation cycle following the first phase; writing the second state to the memory cell during a third phase of the access operation cycle following the second phase; and precharging during the third phase of the access operation cycle and at least in part based on writing the second state to the memory cell.

[0008] An apparatus is described. The apparatus may include: a memory array comprising a plurality of memory cells; and a controller coupled to the memory array and configured to cause the apparatus to: activate a memory cell among the plurality of memory cells during a first phase of an access operation cycle; write a first state or a second state to the memory cell during the first phase of the access operation cycle; maintain the first state or the second state at the memory cell during a second phase of the access operation cycle following the first phase of the access operation cycle; and precharge the memory cell during a third phase of the access operation cycle following the second phase of the access operation cycle.

[0009] Another device is described. The device may include: a memory array comprising a plurality of memory cells; and a controller coupled to the memory array and configured to cause the device to: activate a memory cell during a first phase of an access operation cycle; maintain a first or second state at the memory cell during a second phase of the access operation cycle following the first phase; write the second state at the memory cell during a third phase of the access operation cycle following the second phase; and precharge during the third phase of the access operation cycle and at least in part based on writing the second state at the memory cell. Attached Figure Description

[0010] Figure 1 Examples of systems that support techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein.

[0011] Figure 2 This document describes examples of memory dies that support techniques for mitigating asymmetric long delay stress, based on examples disclosed herein.

[0012] Figure 3 This document describes an example of an access operation loop flowchart that supports techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein.

[0013] Figure 4A and 4B This document describes an example of an access operation cycle timing diagram that supports techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein.

[0014] Figure 5 This document describes an example of an access timing diagram that supports techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein.

[0015] Figure 6 A block diagram illustrating a memory device that supports techniques for mitigating asymmetric long delay stress, based on examples disclosed herein.

[0016] Figure 7 A block diagram illustrating a memory device that supports techniques for mitigating asymmetric long delay stress, based on examples disclosed herein.

[0017] Figure 8 and 9 The flowchart illustrates one or more methods for mitigating asymmetric long-delay stress, based on examples disclosed herein. Detailed Implementation

[0018] A memory device can operate memory cells according to a cell access operation cycle. For example, in the first phase of a cell access operation cycle, the memory device can perform an activation operation on the memory cell (which may be referred to herein as activation). In the second phase of the cell access operation cycle, which occurs after the first phase, the memory device can perform one or more logic operations (e.g., read and / or write) on the memory cell. In the third phase of the cell access operation cycle, which occurs after the second phase, the memory device can perform a precharge operation on the memory cell (which may be referred to herein as precharge). As part of the first phase, the memory device can write a first state (e.g., apply a voltage or current associated with logic '1' or logic '0') to the memory cell. As part of the second phase, the memory device can maintain the first state at the memory cell. As part of the third phase, the memory device can either continue to maintain the first state or write a second state to the memory cell.

[0019] In some instances, memory cells may experience asymmetric long delay (ALD) when read (e.g., a relatively long delay when reading a first state that can be stored by the memory cell compared to reading a second state that can be stored by the memory cell), at least in part because the memory device maintains the first state at the memory cell during the second phase. For example, if the memory device reads the cell with, for example, a positive voltage, the memory cell may experience a longer delay when reading '0' than when reading '1' (e.g., ALD0). However, if the memory device reads the cell with, for example, a negative voltage, the memory cell may experience a longer delay when reading '1' than when reading '0' (i.e., ALD1). As the memory cell continues to experience stress from ALD0 and / or ALD1, the memory cell may experience increased losses from cell residual polarization and may eventually lead to intrinsic closure of the cell read window (RW), as well as other disadvantages.

[0020] To mitigate the stress associated with asymmetric long delays (e.g., ALD0, ALD1), the memory device may write a first state or a second state (e.g., randomly, according to a random distribution, or according to a generated distribution) to the memory cell during the first phase of an access operation cycle. By doing so (e.g., randomly) writing the first state or the second state, or according to a distribution (e.g., a random distribution, a generated distribution), the memory device can reduce the number of times the memory cell experiences asymmetric long delay stress. Additionally, during the third phase and before performing a precharge, the memory device may write the first state to the memory cell. Writing the first state to the memory cell before performing a precharge allows the memory device to perform a precharge while the memory cell is in the first state, and simultaneously, the asymmetric long delay stress is mitigated.

[0021] First, as referenced Figures 1 to 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figures 3 to 5 The features of this disclosure are described in the context of the access operation loop flowchart and access operation loop timing diagram. (See references...) Figures 6 to 9 The apparatus diagrams and flowcharts described herein, relating to techniques for mitigating asymmetric long-delay stress, are used to further illustrate and describe these and other features of this disclosure, and reference is made to the apparatus diagrams and flowcharts.

[0022] Figure 1 This document describes an example of a system 100 that supports techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include electronic device components, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system that can be used to store data from one or more other components of system 100.

[0024] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes within, for example, a computing device, mobile computing device, wireless device, graphics processing device, computer, notebook computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a separate device or component that can be used to provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 may be used to store data of components of host device 105. In some instances, memory device 110 may act as a slave device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0027] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0028] Processor 125 may be used to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0031] Memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may contain a single memory array 170. A 3D memory die 160 may contain two or more memory arrays 170, which may be stacked one on top of the other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in a 3D memory die 160 may be referred to as a stack, hierarchy, layer, or die. A 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two-high stacked memory arrays, three-high stacked memory arrays, four-high stacked memory arrays, five-high stacked memory arrays, six-high stacked memory arrays, seven-high stacked memory arrays, eight-high stacked memory arrays). In some 3D memory dies 160, different stacks may share at least one common access line, such that some stacks may share at least one of word lines, digital lines, or board lines.

[0032] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and are used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0033] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0034] A local memory controller 165 (e.g., locally for memory die 160) may include circuitry, logic, or components that can be used to control the operation of memory die 160. In some instances, the local memory controller 165 may be used to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers that may be used to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0035] External memory controller 120 may be used to enable the communication of one or more information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120, or the functionality described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0036] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to serve as part of a channel.

[0037] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or double data rate (DDR) signaling may be used to convey signaling via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be recorded for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be recorded for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0038] In some instances, CA channel 186 can be used to communicate commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, the command carried by CA channel 186 may carry a read command with an address containing the desired data. In some instances, CA channel 186 may contain any number of signal paths (e.g., eight or nine signal paths) for decoding one or more of the address or command data.

[0039] In some instances, data channel 190 can be used to communicate one or more data or control information between host device 105 and memory device 110. For example, data channel 190 can communicate information to be written to or read from memory device 110 (e.g., bidirectional).

[0040] Memory device 110 can operate memory cells of memory array 170 according to cell access operation cycles (e.g., via device memory controller 155 and / or local memory controller 165). For example, in a first phase of a cell access operation cycle, memory device 110 can perform activation on a memory cell. In a second phase of a cell access operation cycle occurring after the first phase, memory device 110 can perform one or more logical operations (e.g., read and / or write) on the memory cell. In a third phase of a cell access operation cycle occurring after the second phase, memory device 110 can perform pre-charge on the memory cell. As part of the first phase, memory device 110 can write a first state (e.g., apply a voltage or current associated with logic '1' or logic '0') to the memory cell. During the second phase, memory device 110 can maintain the first state at the memory cell. During the third phase, memory device 110 can continue to maintain the first state or can write a second state to the memory cell.

[0041] In some instances, memory cells may experience asymmetric long delay (ALD) when read, at least in part because memory device 110 maintains a first state at the memory cell during the second phase. For example, if memory device 110 reads the cell with, for example, a positive voltage, the memory cell may experience a longer delay when reading '0' than when reading '1' (e.g., ALD0). However, if memory device 110 reads the cell with, for example, a negative voltage, the memory cell may experience a longer delay when reading '1' than when reading '0' (i.e., ALD1). As the memory cell continues to experience stress from ALD0 and / or ALD1, the memory cell may experience increased losses from cell residual polarization and may eventually lead to the inherent closure of the cell read window (RW), as well as other disadvantages.

[0042] To mitigate the stress associated with ALD0 and / or ALD1, memory device 110 may write a first state or a second state (e.g., randomly, according to a random distribution, or according to a generated distribution) to the memory cell during a first phase of an access operation cycle. For example, the memory device may include a generator (e.g., a random generator) configured to generate one of the first or second states (e.g., randomly, according to a random distribution, or according to a generated distribution). By writing the first or second state or according to a distribution (e.g., randomly, using a random distribution, using a generated distribution), memory device 110 can reduce the number of times the memory cell experiences ALD0 and / or ALD1 stress. Additionally, during a third phase and before performing a precharge, memory device 110 may write the first state to the memory cell. Writing the first state to the memory cell before performing a precharge allows memory device 110 to perform a precharge even when the memory cell is in the first state and the ALD stress is mitigated. In some instances, the methods described herein can also be applied to resistor-based arrays and / or ferroelectric field-effect transistor (FeFET)-based arrays, as well as other implementations.

[0043] Figure 2 This document describes an example of a memory die 200 that supports techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein. The memory die 200 may be used as a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logical states (e.g., programmed as one of a set of two or more possible states). For example, memory cell 205 may be used to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., a multi-level memory cell) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference]. Figure 1 The memory array 170 is described.

[0044] Memory cell 205 may store states (e.g., polarization states or dielectric charges) representing programmable states in a capacitor. In a FeRAM architecture, memory cell 205 may include capacitor 240, which contains ferroelectric material to store charges and / or polarizations representing programmable states. Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0045] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, and board lines 220) arranged in a pattern such as a grid. Access lines may be conductive lines coupled to memory cells 205 and used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, bit lines, or board lines, or the like, are interchangeable without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210, digital lines 215, and / or board lines 220.

[0046] Memory cell 205 can be accessed, for example, by activating or selecting access lines such as word line 210, digital line 215, and / or board line 220. A single memory cell 205 can be accessed at its intersection by biasing word line 210, digital line 215, and board line 220 (e.g., by applying voltage to word line 210, digital line 215, or board line 220). Activating or selecting word line 210, digital line 215, or board line 220 may involve applying voltage to the respective line.

[0047] Access to memory cell 205 can be controlled via row decoder 225, column decoder 230, and board driver 235. For example, row decoder 225 receives row addresses from local memory controller 265 and activates word lines 210 based on the received row addresses. Column decoder 230 receives column addresses from local memory controller 265 and activates digital lines 215 based on the received column addresses. Board driver 235 receives board addresses from local memory controller 265 and activates board lines 220 based on the received board addresses.

[0048] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the activation switch assembly 245. The capacitor 240 can be electrically connected to the digital line 215 using the switch assembly 245. For example, when the activation switch assembly 245 is deactivated, the capacitor 240 can be isolated from the digital line 215, and when the switch assembly 245 is activated, the capacitor 240 can be coupled to the digital line 215.

[0049] Word line 210 may be a conductive line electrically connected to the memory cell 205 for performing access operations on the memory cell 205. In some architectures, word line 210 may be electrically connected to the gate of a switching component 245 of the memory cell 205 and may be used to control the switching component 245 of the memory cell. In some architectures, word line 210 may be electrically connected to the node of a capacitor in the memory cell 205, and the memory cell 205 may not include a switching component.

[0050] Digital line 215 may be a conductive line connecting memory cell 205 to sensing component 250. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 245 of memory cell 205 may be used to selectively couple and / or isolate capacitor 240 of memory cell 205 from digital line 215. In some architectures, memory cell 205 may be in (e.g., continuous) electronic communication with digital line 215.

[0051] The board line 220 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. The board line 220 may be in electronic communication with a node (e.g., the bottom of the cell) of the capacitor 240. The board line 220 may cooperate with the digital line 215 to bias the capacitor 240 during access operations on the memory cell 205.

[0052] Sensing component 250 can determine the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers to amplify the signal output of memory cell 205. Sensing component 250 can compare the signal received from memory cell 205 across digital line 215 with reference 255 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 250 (e.g., to input / output 260) and can indicate the detected logic state to another component of memory device 110 including memory die 200.

[0053] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 may be used as a reference. Figure 1 Examples of the described local memory controller 165. In some instances, one or more of the row decoder 225, column decoder 230, board driver 235, and sensing components 250 may co-locate with the local memory controller 265. The local memory controller 265 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transmit data from memory die 200 to host device 105 based on the performance of one or more operations. The local memory controller 265 may generate row signals and column address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0054] The local memory controller 265 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0055] The local memory controller 265 can be used to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 265 can identify the target memory cell 205 to which a write operation will be performed. The local memory controller 265 can identify target word lines 210, target digital lines 215, and target board lines 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word lines 210, target digital lines 215, and target board lines 220 (e.g., by applying a voltage to word lines 210, digital lines 215, or board lines 220) to access the target memory cell 205. The local memory controller 265 can apply a specific signal (e.g., a write pulse) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 240 of the memory cell 205. The pulse used for the write operation may contain one or more voltage levels over a period of time.

[0056] The local memory controller 265 can be used to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 265 can identify the target memory cell 205 to which the read operation will be performed. The local memory controller 265 can identify the target word line 210, target digital line 215, and target board line 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word line 210, target digital line 215, and target board line 220 (e.g., by applying voltage to the word line 210, digital line 215, or board line 220) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sensing component 250 in response to a bias access line. The sensing component 250 can amplify the signal. The local memory controller 265 can activate the sensing component 250 (e.g., a latching sensing component) and then compare the signal received from the memory cell 205 with a reference 255. Based on the comparison, the sensing component 250 can determine the logic state stored in the memory cell 205.

[0057] When memory cells 205 cycle in a distributed manner and wait in the same state between performing activation and performing precharge, the memory device (e.g., the memory die containing memory die 200) may have an enabled fault mechanism. Such instances where cell cycles are distributed in time with memory cells 205 and where memory cells 205 wait in the same state between performing activation and precharge can be referred to as distributed cycling. In some instances, during distributed cycling, the memory device may perform random precharge flip (FOP), which may prevent this situation (e.g., the cells waiting in the same state between performing activation and performing precharge) from occurring, or may reduce the frequency of this occurrence.

[0058] However, in some instances, if the memory device performs consecutive open page accesses, memory cell 205 waits with a state applied during activation (e.g., logic '1' or '0' as a function of the read quadrant). Such a cyclic pattern may be referred to as an ALD about 1 (e.g., ALD1) or an ALD about 0 (e.g., ALD0). The delay about 1 or 0 may be caused at least in part by reading the memory cell through a sense amplifier (e.g., a 2pr sense amplifier). For example, ALD0 stress may occur when reading with a positive voltage (e.g., in the first read quadrant of the memory cell), and ALD1 stress may occur when reading with a negative voltage (e.g., in the third quadrant of the memory cell). Typically, ALD can increase the loss of the cell's residual polarization (e.g., compared to the loss caused by a fast cycle of the same number of cycles), which may cause the inherent shutdown of the cell's RW. This RW shutdown may not be mitigated using error correction codes (ECC) and other techniques, at least in part, due to this inherent behavior. Read margin can be used to keep the RW open to avoid read failures.

[0059] The techniques described herein can be used to avoid and / or mitigate systematic ALD0 and / or ALD1 cell stress during consecutive open page accesses. For example, random write-back can be used at the end of activation to ensure that memory cell 205 spends open page time alternating between two levels (e.g., a first level associated with logic '1' and a second level associated with logic '0') (e.g., the time between activation and precharge). Alternatively, the memory device can perform write operations before precharge to ensure that one level is written at a time at the memory cell. Such techniques can reduce cell wear during consecutive open page times and / or improve cell failure time during consecutive open page times. Additionally or alternatively, such techniques can address (e.g., remove) ALD1 and / or ALD0 failure mechanisms with little or no impact on access time (e.g., row-to-column address latency, which may be referred to as tRCD).

[0060] Figure 3 This document describes an example of an access operation cycle flowchart 300 supporting techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein. The access operation cycle flowchart 300 may represent one or more methods performed by a memory device (e.g., memory device 110) on a memory cell (e.g., memory cell 205) during a cell access operation cycle. The cell access operation cycle may include a first stage 302, a second stage 303, and a third stage 304. The second stage 303 may follow the first stage 302, and the third stage 304 may follow the second stage 303. In some instances, the first stage 302, the second stage 303, and / or the third stage 304 may at least partially overlap.

[0061] During the first phase 302 of the cell access operation cycle, at 305, the memory device may perform activation on the memory cell (e.g., the memory device may activate the memory cell). In some instances, performing activation may involve sensing the state of the memory cell and / or making data available for read operations. In some instances, performing activation may involve the memory device writing a first state (e.g., logic '1') to the memory cell.

[0062] Alternatively, during the first phase 302 of the cell access operation cycle, at 310, the memory device may (e.g., using random toggles) write back to a first state or a second state (e.g., logic '0'). For example, the memory device may (e.g., according to a random distribution, according to a generated distribution generated by one or more components) (e.g., randomly) select one of the first state or the second state and write back to the selected state of the first state or the second state. In some instances, 310 may occur after 305 (e.g., 310 may not partially overlap with 305). In other instances, the memory device may select one of the first state or the second state based on one or more factors (e.g., the memory device may select one of the first state or the second state in a non-random manner using a generated distribution that can be generated by the memory device, received from another device, loaded from a lookup table or other stored source, or based on an instruction received from another device). It should be noted that since the data of the memory cell has already been sensed during the first phase 302, the access time (e.g., tRCD) may not change. In some instances, 310 may be part of a fourth stage between the first stage 302 and the second stage 303 (e.g., the write phase of 310 may be added to or included as part of the minimum row activity time (e.g., tRAS_min)).

[0063] At 315, during the second phase 303 of the cell access operation cycle, the memory device may perform one or more logical operations on the memory cell. For example, the memory device may perform a read or a write operation on the memory cell. In some instances, the memory device may maintain either a first state or a second state during the second phase 303 of the cell access operation cycle (e.g., write back to either state of the memory cell at 310). In some instances, the second phase 303 may be limited by a maximum latency (e.g., a maximum latency given by the row activity time (e.g., tRAS)).

[0064] During the third phase 304 of the cell access operation cycle, at 320, the memory device may write a first state to the memory cell. By writing the first state to the memory cell, the memory cell can recover the first state (e.g., in the case where a second state is written to the memory cell at 310). Alternatively or concurrently, during the third phase 304, at 325, the memory device may perform a precharge on the memory cell (e.g., the memory device may precharge the memory cell). In some instances, performing a precharge may involve the memory device (e.g., using random flipping) writing a second state to the memory cell. For example, the memory device may (e.g., according to a random distribution) randomly select one of the first state or the second state, and may write the selected state from the first state or the second state. In some instances, 325 may be performed after 320. In other instances, the memory device may select one of the first state or the second state based on one or more factors (e.g., the memory device may select one of the first state or the second state in a non-random manner).

[0065] The techniques described herein can be used to avoid and / or mitigate systematic ALD0 and / or ALD1 cell stress during continuous open page access. For example, performing a write-back at 310 ensures that memory cell spending alternates between two levels (e.g., a first level associated with logic '1' and a second level associated with logic '0') in a second phase 303. Additionally, performing a write at 320 before performing a precharge ensures that one level is written at a time at the memory cell. Such techniques can reduce cell wear during continuous open page time and / or improve cell failure time during continuous open page time. Alternatively, such techniques can address (e.g., remove) ALD1 and / or ALD0 failure mechanisms with little or no impact on access time (e.g., tRCD).

[0066] Figure 4A and 4B Examples of access operation cycle timing diagrams 400-a and 400-b are provided to illustrate techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein. Figure 4AThis can represent a timing diagram of an access operation cycle when a memory device (e.g., memory device 110) performs a positive activation (e.g., activation in the first quadrant) on a memory cell (e.g., memory cell 205), and Figure 4B It can represent a timing diagram of an access operation cycle when the memory device performs negative activation (e.g., activation in the third quadrant) on a memory cell. Figure 4A and / or Figure 4B The timing diagrams shown may be implemented or executed by system 100 and / or memory die 200, or may be related to said system and / or memory die, as well as other implementations or examples.

[0067] In the access operation cycle timing diagram 400-a, the cell access operation cycle may include a first stage 402-a, a second stage 403-a, and a third stage 404-a. The second stage 403-a may follow the first stage 402-a, and the third stage 404-a may follow the second stage 403-a. During the first stage 402-a of the cell access operation cycle, at 405-a, the memory device may perform positive activation on a memory cell (e.g., the memory device may activate a memory cell in the first quadrant). In some instances, performing activation may involve the memory device writing a first state (e.g., logic '0') to the memory cell. Alternatively or additionally, during the first stage 402-a of the cell access operation cycle, at 410-a, the memory device may (e.g., using random toggles) write back either the first state or the second state (e.g., logic '1'). For example, the memory device may (e.g., according to a random distribution) randomly select one of the first state or the second state and may write back the selected state from the first state or the second state.

[0068] During the second phase 403-a of the cell access operation cycle, the memory device may perform one or more logical operations on the memory cell. For example, the memory device may perform a read or a write operation on the memory cell. In some instances, the memory device may maintain a first state or a second state during the second phase 403-a of the cell access operation cycle (e.g., write back to either state of the memory cell at 410-a). In some instances, the second phase 403-a may represent an open page time, in which the row buffer of the memory cell remains open.

[0069] During the third phase 404-a of the cell access operation cycle, at 415-a, the memory device may write a first state to the memory cell. Alternatively, during the third phase 404-a, at 420-a, the memory device may perform a precharge on the memory cell (e.g., the memory device may precharge the memory cell). In some instances, performing a precharge may involve the memory device (e.g., using random flip-flops) writing a second state to the memory cell. For example, the memory device may (e.g., according to a random distribution) randomly select one of the first state or the second state, and may write the selected state of the first state or the second state (e.g., the memory device may perform a FOP).

[0070] In the access operation cycle timing diagram 400-b, the cell access operation cycle may include a first stage 402-b, a second stage 403-b, and a third stage 404-b. The second stage 403-b may follow the first stage 402-b, and the third stage 404-b may follow the second stage 403-b. During the first stage 402-b of the cell access operation cycle, at 405-b, the memory device may perform a negative activation on the memory cell (e.g., the memory device may activate the memory cell in the third quadrant). In some instances, performing activation may involve the memory device writing a first state (e.g., logic '1') to the memory cell. Alternatively or additionally, during the first stage 402-b of the cell access operation cycle, at 410-b, the memory device may (e.g., using a random toggle generated by the memory device) write back the first state or the second state (e.g., logic '0'). For example, the memory device may (e.g., according to a random distribution) randomly select one of a first state or a second state, and may write back to the selected state in the first state or the second state.

[0071] During the second phase 403-b of the cell access operation cycle, the memory device may perform one or more logical operations on the memory cell. For example, the memory device may perform a read or a write operation on the memory cell. In some instances, the memory device may maintain a first state or a second state during the second phase 403-b of the cell access operation cycle (e.g., write back to either state of the memory cell at 410-b). In some instances, the second phase 403-b may represent an open page time, in which the row buffer of the memory cell remains open.

[0072] During the third phase 404-b of the cell access operation cycle, at 415-b, the memory device may write a first state to the memory cell. Alternatively, during the third phase 404-b, at 420-b, the memory device may perform a precharge on the memory cell (e.g., the memory device may precharge the memory cell). In some instances, performing a precharge may involve the memory device (e.g., using random flip-flops) writing a second state to the memory cell. For example, the memory device may (e.g., according to a random distribution) randomly select one of the first or second states and write the selected state (e.g., the memory device may perform a FOP).

[0073] Figure 5 This illustrates an example of an access operation cycle timing diagram 500 that supports techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein. Figure 5 A timing diagram may be shown illustrating the access operation cycle of the voltage of one or more components of a memory device (e.g., memory device 110).

[0074] Digital line voltage 515 can represent digital lines (e.g., as referenced). Figure 2 The voltage on the described digital line 215. Digital line voltage 515-a can represent the voltage on the digital line whenever a memory cell stores a first state (e.g., logic '1'), and digital line voltage 515-b can represent the voltage on the digital line whenever a memory cell stores a second state (e.g., logic '0'). Word line voltage 520 can represent the voltage on the word line (e.g., as described in reference). Figure 2 The voltage on the described word line 210. Cell bottom voltage 525 may represent the cell bottom associated with the memory cell (e.g., as shown in reference 525). Figure 2 The voltage at the node between the described switching assembly 245 and capacitor 240. When the memory cell stores a first state, the cell bottom voltage 525-a can represent the voltage at the bottom of the cell, and when the memory cell stores a second state, the cell bottom voltage 525-b can represent the voltage at the bottom of the cell. The board line voltage 530 can represent the voltage at the board line (e.g., as shown in the reference). Figure 2 The voltage at the described plate line 220).

[0075] The voltages described herein may be at one or more voltage levels. For example, a first voltage level 505-a may represent a ground voltage (e.g., 0 volts); a second voltage level 505-b may represent a voltage level higher than the first voltage level 505-a (e.g., digital line voltage (DLV)); a third voltage level 505-c may represent a voltage level higher than the second voltage level 505-b; a fourth voltage level 505-d may represent a voltage level higher than the third voltage level 505-c (e.g., 3.2V); a fifth voltage level 505-e may represent a voltage level higher than the fourth voltage level 505-d (e.g., 3.4V); and a sixth voltage level 505-f may represent a voltage level higher than the fifth voltage level 505-e (e.g., 3.6V).

[0076] Prior to 510-a, the memory device may be in an idle mode. At 510-b, charge may be applied to the digital line. Therefore, the digital line voltage 515 may begin to transition from a first voltage level 505-a to a second voltage level 505-b at 510-b. At 510-c, the word line voltage 520 may transition from the first voltage level 505-a to a fifth voltage level 505-e. Additionally, at 510-c, the cell bottom voltage 525 may transition from the first voltage level 505-a to the second voltage level 505-b. Between 510-c and 510-d, the memory device may perform signal formation associated with activation. Between 510-e and 510-f, the memory device may perform signal amplification, and between 510-f and 510-g, the memory device may activate its sense amplifier. In some instances, one or more of the times between one of 510-a to 510-g and another of 510-a to 510-g may correspond to, as referenced Figure 3 The 305 described.

[0077] Between 510-g and 510-h, if the memory cell stores a first state, then the digital line voltage 515 may follow digital line voltage 515-a. Alternatively, if the memory cell stores a second state, then the digital line voltage 515 may follow digital line voltage 515-b. Digital line voltage 515-b may (e.g., over time) decrease by a greater amount relative to digital line voltage 515-a. At or after 510-h, the memory device may write the first state or the second state back to the memory cell (e.g., as referenced). Figure 3 (As described in 310).

[0078] Between 510-h and 510-i, the digital line voltage 515-b may transition to a first voltage level 505-a, and the digital line voltage 515-a may transition to or be maintained at a second voltage level 505-b. In some instances, one or more of the times between one of 510-g to 510-i and the other of 510-g to 510-i may correspond to, as referenced... Figure 3 The 315 described herein may be associated with one or more access operations, such as performing one or more read operations and / or one or more write operations.

[0079] At 510-i, the memory device can write the first state to a memory cell (e.g., as referenced). Figure 3 (As described in 320). Alternatively or additionally, at or after 510-i, the memory device may begin pre-charging the memory cell. For example, at 510-i, the digital line voltage 515-b may transition from a first voltage level 505-a to a second voltage level 505-b. After or at 510-i, if the memory cell stores a first state (e.g., logic '1'), then the cell bottom voltage 525-a may transition from the second voltage level 505-b to a higher level, and then may re-stabilize at the second voltage level 505-b. Alternatively, if the memory cell stores a second state (e.g., logic '0'), then the cell bottom voltage 525-b may transition from the first voltage level 505-a to a higher level, and then may re-stabilize at the first voltage level 505-a. After or at 510-i, the board line voltage 530 may transition from the first voltage level 505-a to the seventh voltage level (e.g., a voltage level higher than the second voltage level 505-b but lower than the third voltage level 505-c).

[0080] After transitioning to the seventh voltage level, the board line voltage 530 can transition back to the first voltage level 505-a. After the board line voltage 530 transitions back to the first voltage level 505-a, the digital line voltage 515 can transition from the second voltage level 505-b to the first voltage level 505-a. After the digital line voltage 515 transitions to the first voltage level 505-a, the word line voltage 520 can transition to the first voltage level 505-a. At 510-j, each of the digital line voltage 515, word line voltage 520, cell bottom voltage 525, and board line voltage 530 can be at the first voltage level 505-a, and the memory device can be in an idle mode. In some instances, at least some time spanning between 510-i and 510-j can correspond to as referenced. Figure 3 The 325 described herein can be associated with performing a precharge on a memory cell.

[0081] Figure 6A block diagram 600 illustrates a memory device 605 supporting techniques for mitigating asymmetric long delay stress, based on examples disclosed herein. The memory device 605 may be as described in the references... Figures 3 to 5 Examples of aspects of the described memory device. Memory device 605 may include a memory cell activation component 610, a memory cell write component 615, a state maintenance component 620, a memory cell precharge component 625, and a state selection component 630. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0082] The memory cell activation component 610 can activate the memory cell during the first phase of the access operation cycle.

[0083] The memory cell writing component 615 may write a first state or a second state to the memory cell during the first phase of the access operation cycle. In some instances, the memory cell writing component 615 may write a second state to the memory cell during the third phase of the access operation cycle based on writing the first state or the second state to the memory cell during the first phase of the access operation cycle. In some instances, the memory cell writing component 615 may write the first state or the second state to the memory cell during the third phase of the access operation cycle, as part of precharging the memory cell, based on writing the second state to the memory cell during the third phase of the access operation cycle. In some instances, the memory cell writing component 615 writes the first state to the memory cell during the third phase of the access operation cycle before precharging the memory cell. In some instances, the memory cell writing component 615 may write the second state to the memory cell during the first phase of the access operation cycle, as part of activating the memory cell.

[0084] The state maintenance component 620 can maintain a first state or a second state at the memory cell during the second phase of the access operation cycle following the first phase of the access operation cycle.

[0085] The memory cell precharge component 625 can precharge the memory cells during the third phase of the access operation cycle after the second phase of the access operation cycle.

[0086] The state selection component 630 may randomly select a first state or a second state to write the first state or the second state to the memory cell as part of the pre-charging of the memory cell. In some instances, the state selection component 630 may randomly select a first state or a second state to write the first state or the second state to the memory cell during the first phase of an access operation cycle.

[0087] Figure 7A block diagram 700 illustrates a memory device 705 supporting techniques for mitigating asymmetric long delay stress, based on examples disclosed herein. The memory device 705 may be as described in the references... Figures 3 to 5 Examples of aspects of the described memory device. Memory device 705 may include a memory cell activation component 710, a state maintenance component 715, a memory cell write component 720, a memory cell precharge component 725, and a selection component 730. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0088] The memory cell activation component 710 can activate the memory cell during the first phase of the access operation cycle.

[0089] The state maintenance component 715 can maintain a first state or a second state at the memory cell during the second phase of the access operation cycle following the first phase of the access operation cycle.

[0090] The memory cell writing component 720 may write a second state to a memory cell during a third phase of an access operation cycle following a second phase of the access operation cycle. In some instances, the memory cell writing component 720 may write a first state or a second state to a memory cell during a first phase of the access operation cycle, wherein maintaining the first state or the second state at the memory cell during the second phase of the access operation cycle is based on writing the first state or the second state at the memory cell during the first phase of the access operation cycle. In some instances, the memory cell writing component 720 may write the first state or the second state at the memory cell during the third phase of the access operation cycle and as part of pre-charging the memory cell, based on writing the second state at the memory cell during the third phase of the access operation cycle. In some instances, the memory cell writing component 720 may write the second state at the memory cell during the first phase of the access operation cycle and as part of activating the memory cell.

[0091] The memory cell precharge component 725 can precharge during the third phase of the access operation cycle and based on writing a second state to the memory cell.

[0092] Selection component 730 may randomly select a first state or a second state at a memory cell to write the first state or the second state at the memory cell during the first phase of an access operation cycle. In some instances, selection component 730 may randomly select a first state or a second state to write the first state or the second state at the memory cell as part of a pre-charge of the memory cell.

[0093] Figure 8The flowchart illustrates one or more methods 800 supporting techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein. Operation of method 800 may be implemented by a memory device or its components as described herein. For example, operation of method 800 may be performed as described in the references... Figure 6 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0094] At 805, the memory device can activate memory cells during the first phase of an access operation cycle. The operation of 805 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 6 The described aspect of the memory cell activation component performing the operation of 805.

[0095] At 810, the memory device may write a first state or a second state to a memory cell during the first phase of an access operation cycle. The operation of 810 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 6 The described aspect of the memory cell write component performs the operation of 810.

[0096] At 815, the memory device may maintain a first state or a second state at the memory cell during the second phase of the access operation cycle following the first phase of the access operation cycle. The operation of 815 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 6 The described aspect of the state maintenance component performs the operation of 815.

[0097] At 820, the memory device may precharge memory cells during the third phase of the access operation cycle following the second phase of the access operation cycle. The operation of 820 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 6 The described memory cell precharge component performs an aspect of the operation of 820.

[0098] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: activating a memory cell during a first phase of an access operation cycle; writing a first state or a second state to the memory cell during the first phase of the access operation cycle; maintaining the first state or the second state at the memory cell during a second phase of an access operation cycle following the first phase of the access operation cycle; and pre-charging the memory cell during a third phase of an access operation cycle following the second phase of the access operation cycle.

[0099] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing operations such as writing a first state or a second state to a memory cell during the first phase of an access operation cycle and writing a second state to a memory cell during the third phase of an access operation cycle.

[0100] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for performing the following: writing a second state to a memory cell during the third phase of an access operation cycle and writing a first or second state to a memory cell during the third phase of the access operation cycle and as part of precharging the memory cell.

[0101] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for performing the following: randomly selecting a first state or a second state to write the first state or the second state into the memory cell as part of precharging the memory cell.

[0102] In some instances of the method 800 and device described herein, writing the first state to the memory cell during the third phase of the access operation cycle occurs before the memory cell is precharged.

[0103] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing the following: writing a second state to a memory cell during the first phase of an access operation cycle and as part of activating the memory cell.

[0104] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing the following: randomly selecting a first state or a second state to write the first state or the second state to a memory cell during the first phase of an access operation cycle.

[0105] Figure 9 The flowchart illustrates one or more methods 900 supporting techniques for mitigating asymmetric long-delay stress, based on examples disclosed herein. Operation of method 900 may be implemented by a memory device or its components as described herein. For example, operation of method 900 may be performed as described in the references... Figure 7 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0106] At 905, the memory device may activate a memory cell during the first phase of an access operation cycle. The operation at 905 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described aspect of the memory cell activation component performing operation 905.

[0107] At 910, the memory device may maintain a first state or a second state at the memory cell during the second phase of the access operation cycle following the first phase of the access operation cycle. The operation of 910 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described aspect of the state maintenance component performs the operation 910.

[0108] At 915, the memory device may write the second state to the memory cell during the third phase of the access operation cycle following the second phase of the access operation cycle. The operation at 915 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described aspect of the memory cell write component performs the operation of 915.

[0109] At 920, the memory device may be precharged during the third phase of the access operation cycle and based on writing the second state to the memory cell. The operation at 920 can be performed according to the method described herein. In some instances, it can be performed as described in the reference... Figure 7 The described aspect of the memory cell precharge component performs the operation of 920.

[0110] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: activating a memory cell during a first phase of an access operation cycle; maintaining a first or second state at the memory cell during a second phase of an access operation cycle following the first phase of the access operation cycle; writing a second state to the memory cell during a third phase of an access operation cycle following the second phase of the access operation cycle; and pre-charging during the third phase of the access operation cycle and based on writing the second state to the memory cell.

[0111] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for performing operations such as writing a first state or a second state to a memory cell during a first phase of an access operation cycle, wherein maintaining the first state or the second state at the memory cell during a second phase of the access operation cycle may be based on writing the first state or the second state at the memory cell during the first phase of the access operation cycle.

[0112] Some instances of the method 900 and apparatus described herein may further include operations, features, components, or instructions for performing the following: randomly selecting a first state or a second state at a memory cell to write the first state or the second state at the memory cell during the first phase of an access operation cycle.

[0113] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for performing the following: writing a second state at a memory cell during the third phase of an access operation cycle and writing a first or second state at a memory cell during the third phase of the access operation cycle and as part of precharging the memory cell.

[0114] Some examples of the method 900 and apparatus described herein may further include operations, features, components, or instructions for performing the following: randomly selecting a first state or a second state to write the first state or the second state at the memory cell as part of precharging the memory cell.

[0115] Some instances of the method 900 and device described herein may further include operations, features, components, or instructions for performing the following: writing a second state at a memory cell during the first phase of an access operation cycle and as part of activating the memory cell.

[0116] It should be noted that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0117] An apparatus is described. The apparatus may include: a memory array comprising a set of memory cells; and a controller coupled to the memory array and configured to cause the apparatus to perform the following operations and / or may include components for performing the following operations: activating a memory cell among a plurality of memory cells during a first phase of an access operation cycle; writing a first state or a second state to a memory cell during the first phase of an access operation cycle; maintaining the first state or the second state at a memory cell during a second phase of an access operation cycle following the first phase of the access operation cycle; and pre-charging the memory cell during a third phase of an access operation cycle following the second phase of the access operation cycle.

[0118] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: writing a first state or a second state to a memory cell during the third phase of the access operation cycle based on writing a first state or a second state to a memory cell during the first phase of the access operation cycle.

[0119] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: writing a second state at a memory cell during the third phase of an access operation cycle and writing a first state or a second state at a memory cell during the third phase of an access operation cycle and as part of precharging the memory cell.

[0120] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: writing a second state at a memory cell during the first phase of an access operation cycle and as part of activating the memory cell.

[0121] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: selecting a first state or a second state to write the first state or the second state at a memory cell during the first phase of an access operation cycle.

[0122] In some instances, each memory cell in the set of memory cells includes a ferroelectric capacitor configured to store a charge corresponding to a first state or a second state.

[0123] An apparatus is described. The apparatus may include: a memory array comprising a set of memory cells; a controller coupled to the memory array and configured to cause the apparatus to perform the following operations and / or may include means for performing the following operations: activating memory cells during a first phase of an access operation cycle; maintaining a first or second state at the memory cells during a second phase of an access operation cycle following the first phase of the access operation cycle; writing a second state at the memory cells during a third phase of an access operation cycle following the second phase of the access operation cycle; and precharging during the third phase of the access operation cycle and at least in part based on writing the second state at the memory cells.

[0124] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: writing a first state or a second state to a memory cell during a first phase of an access operation cycle, wherein maintaining the first state or the second state at the memory cell during a second phase of the access operation cycle may be based on writing the first state or the second state to the memory cell during the first phase of the access operation cycle.

[0125] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: selecting a first state or a second state at a memory cell to write the first state or the second state at the memory cell during a first phase of an access operation cycle.

[0126] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: writing a second state at a memory cell during the third phase of an access operation cycle and writing a first state or a second state at a memory cell during the third phase of an access operation cycle and as part of precharging the memory cell.

[0127] Some instances may further include a controller that can be used to enable the device to perform the following operations and / or include components for performing the following operations: writing a second state at a memory cell during the first phase of an access operation cycle and as part of activating the memory cell.

[0128] In some instances, each memory cell in the set of memory cells includes a ferroelectric capacitor configured to store a charge corresponding to a first state or a second state.

[0129] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0130] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0131] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via conductive paths, while in a closed-circuit relationship, signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0132] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller affects the change that prevents signals from flowing between the components using previously permitted conductive paths.

[0133] As used in this article, the term “generally” means that the modified characteristic (e.g., a verb or adjective modified by the term “generally”) does not have to be absolutely close but is close enough to achieve the advantage of the characteristic.

[0134] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0135] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (e.g., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (e.g., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0136] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other examples. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0137] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by a second reference numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0138] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0139] For example, the various illustrative blocks and modules described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0140] As used herein, the word "or" in a list of items contained in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (e.g., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0141] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory cell, comprising: The memory cell is activated during the first phase of the access operation cycle; At the first moment of the first phase of the access operation cycle, the first state is written to the memory cell; During the first phase of the access operation cycle, at a second time different from the first time, the first state or the second state is written to the memory cell; The first state or the second state is maintained at the memory cell during the second phase of the access operation cycle following the first phase of the access operation cycle. as well as The memory cell is precharged during the third phase of the access operation cycle following the second phase of the access operation cycle.

2. The method according to claim 1, further comprising: The first state or the second state is randomly selected to write the first state or the second state to the memory cell during the first phase of the access operation cycle.

3. The method according to claim 1, further comprising: At least in part, this is based on writing the first state or the second state to the memory cell during the first phase of the access operation cycle and writing the second state to the memory cell during the third phase of the access operation cycle.

4. The method of claim 3, further comprising: The second state is written to the memory cell during the third phase of the access operation cycle, while the first state or the second state is written to the memory cell during the third phase of the access operation cycle and as part of precharging the memory cell.

5. The method of claim 4, further comprising: The first state or the second state is randomly selected as part of the pre-charging of the memory cell and written into the memory cell.

6. The method of claim 3, wherein writing the first state to the memory cell during the third phase of the access operation cycle occurs before the memory cell is precharged.

7. The method of claim 1, further comprising: The second state is written to the memory cell during the first phase of the access operation cycle and as part of activating the memory cell.

8. A method for operating a memory cell, comprising: The memory cell is activated during the first phase of the access operation cycle; During the second phase of the access operation cycle following the first phase of the access operation cycle, the first state or the second state is maintained at the memory cell. The second state is written to the memory cell during the third phase of the access operation cycle following the second phase of the access operation cycle. At least in part, the second state is written to the memory cell during the third phase of the access operation cycle, and the first state or the second state is written to the memory cell during the third phase of the access operation cycle and as part of precharging the memory cell. as well as Precharging is performed during the third phase of the access operation cycle and at least in part based on writing the second state to the memory cell.

9. The method of claim 8, further comprising: During the first phase of the access operation cycle, the first state or the second state is written to the memory cell, wherein the first state or the second state is maintained at the memory cell during the second phase of the access operation cycle at least in part based on the writing of the first state or the second state at the memory cell during the first phase of the access operation cycle.

10. The method of claim 9, further comprising: The first state or the second state is randomly selected at the memory cell to write the first state or the second state at the memory cell during the first phase of the access operation cycle.

11. The method of claim 8, wherein the memory cell includes a ferroelectric capacitor to store a charge corresponding to the first state or the second state.

12. The method of claim 8, further comprising: The first state or the second state is randomly selected to be written into the memory cell as part of the pre-charging of the memory cell.

13. The method of claim 8, further comprising: During the first phase of the access operation cycle and as part of activating the memory cell, the second state is written to the memory cell.

14. A memory device comprising: A memory array, which comprises multiple memory cells; as well as A controller, coupled to the memory array and capable of enabling the memory device to perform the following operations: During the first phase of the access operation cycle, the memory cells among the plurality of memory cells are activated; At the first moment of the first phase of the access operation cycle, the first state is written to the memory cell; During the first phase of the access operation cycle, at a second time different from the first time, the first state or the second state is written to the memory cell; The first state or the second state is maintained at the memory cell during the second phase of the access operation cycle following the first phase of the access operation cycle. as well as The memory cell is precharged during the third phase of the access operation cycle following the second phase of the access operation cycle.

15. The memory device of claim 14, wherein the controller is further configured to cause the memory device to perform the following operations: The second state is written to the memory cell during the third phase of the access operation cycle, based at least in part on writing the first state or the second state to the memory cell during the first phase of the access operation cycle.

16. The memory device of claim 15, wherein the controller is further configured to cause the memory device to perform the following operations: The second state is written to the memory cell during the third phase of the access operation cycle, while the first state or the second state is written to the memory cell during the third phase of the access operation cycle and as part of precharging the memory cell.

17. The memory device of claim 14, wherein the controller is further configured to cause the memory device to perform the following operations: During the first phase of the access operation cycle and as part of activating the memory cell, the second state is written to the memory cell.

18. The memory device of claim 14, wherein the controller is further configured to cause the memory device to perform the following operations: Select the first state or the second state to write the first state or the second state to the memory cell during the first phase of the access operation cycle.

19. The memory device of claim 14, wherein each of the plurality of memory cells includes a ferroelectric capacitor configured to store a charge corresponding to the first state or the second state.

20. A memory device comprising: A memory array, which comprises multiple memory cells; as well as A controller, coupled to the memory array and capable of enabling the memory device to perform the following operations: Activate the memory cell during the first phase of the access operation cycle; During the second phase of the access operation cycle following the first phase of the access operation cycle, the first state or the second state is maintained at the memory cell. The second state is written to the memory cell during the third phase of the access operation cycle following the second phase of the access operation cycle. At least in part, the second state is written to the memory cell during the third phase of the access operation cycle, and the first state or the second state is written to the memory cell during the third phase of the access operation cycle and as part of precharging the memory cell. as well as Precharging is performed during the third phase of the access operation cycle and at least in part based on writing the second state at the memory cell.

21. The memory device of claim 20, wherein the controller is further configured to cause the memory device to perform the following operations: During the first phase of the access operation cycle, the first state or the second state is written to the memory cell, wherein the first state or the second state is maintained at the memory cell during the second phase of the access operation cycle at least in part based on the writing of the first state or the second state to the memory cell during the first phase of the access operation cycle.

22. The memory device of claim 21, wherein the controller is further configured to cause the memory device to perform the following operations: Select the first state or the second state at the memory cell to write the first state or the second state at the memory cell during the first phase of the access operation cycle.

23. The memory device of claim 21, wherein the controller is configured to select the first state or the second state, comprising the controller being configured to cause the memory device to perform the following operations: The first state or the second state is randomly selected to write the first state or the second state to the memory cell during the first phase of the access operation cycle.

24. The memory device of claim 20, wherein the controller is further configured to cause the memory device to perform the following operations: During the first phase of the access operation cycle and as part of activating the memory cell, the second state is written to the memory cell.

25. The memory device of claim 20, wherein each of the plurality of memory cells includes a ferroelectric capacitor configured to store a charge corresponding to the first state or the second state.

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