Managed memory system with multiple priority queues

Abstract

This application is directed to a managed memory system with multiple priority queues. Memory access commands can be received from a host and stored in a command queue. A first subset of commands and a second subset of commands associated with a first priority and a second priority, respectively, can be determined. The first and second subsets can be routed from the command queue to a first queue and a second queue, respectively. The first and second subsets can be processed at a storage controller according to first and second processing programs that can run in parallel according to parameters for a priority ordering between the first and second priorities, to third and fourth queues, respectively. Data associated with the commands can be received from the host, temporarily stored in a buffer, and then moved to a storage memory (for write commands), or retrieved from a storage memory, temporarily stored in the buffer, and then transmitted to the host (for read commands).

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 951,985, filed November 18, 2020, entitled “Managed Memory Systems with Multiple Priority Queues,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to managed memory systems with multiple priority queues. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any one of the two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describes a non-transitory computer-readable medium storing code. In some instances, the non-transitory computer-readable medium storing code may contain instructions that, when executed by a processor of a memory device, cause the memory device to: receive a memory access command from a host at an interface; store the memory access command in a command queue; determine a first subset of memory access commands associated with a first priority and a second subset of memory access commands associated with a second priority; route the first subset of memory access commands associated with the first priority from the command queue to a first queue; route the second subset of memory access commands associated with the second priority from the command queue to a second queue; store data associated with the memory access command in a buffer coupled to the interface; and, by including one or more of the instructions... A processor of a processor processes a first subset of memory access commands from a first queue to a third queue, the third queue being associated with a first priority, at a memory controller according to a first processing program; processes a second subset of memory access commands from a second queue to a fourth queue, the fourth queue being associated with a second priority, at the memory controller according to a second processing program, wherein the execution units of the processor run the first and second processing programs in parallel according to one or more parameters for priority sorting between the first and second priorities; and moves the data associated with the memory access commands between the buffer and the storage memory comprising multiple memory units via the memory controller.

[0007] Describe a device. The device may include an interface configured to receive memory access commands from a host and to send and receive data associated with the memory access commands. The interface may include: a command queue configured to store the memory access commands received by the interface; and a processor. The processor may include: an execution unit; a first queue configured to store a first subset of memory access commands associated with a first priority; a second queue configured to store a second subset of memory access commands associated with a second priority; and one or more command routers configured to obtain the memory access commands from the command queues, determine the first subset and the second subset of the memory access commands, and store the first subset and the second subset in the first queue and the second queue, respectively. The interface may further include: a buffer coupled to the interface and configured to store the data associated with the memory access commands; a storage memory having a plurality of memory cells; and a storage controller configured to move the data associated with the memory access commands between the buffer and the storage memory. The storage controller may include: a third queue associated with the first priority; and a fourth queue associated with the second priority. The processor may be configured to process a first subset of memory access commands from the first queue to the third queue according to a first processing program and to process a second subset of memory access commands from the second queue to the fourth queue according to a second processing program, wherein the first and second processing programs are configured to run in parallel via the execution unit according to one or more parameters for priority ordering between the first and second priorities.

[0008] A memory device is described. The memory device may include: a storage memory having a plurality of memory cells; and a processor coupled to the storage memory. The processor may be operable such that the memory device performs the following operations: receiving memory access commands from a host at an interface; storing the memory access commands in a command queue; determining a first subset of memory access commands associated with a first priority and a second subset of memory access commands associated with a second priority; routing the first subset of memory access commands associated with the first priority from the command queue to a first queue; routing the second subset of memory access commands associated with the second priority from the command queue to a second queue; storing data associated with the memory access commands in a buffer coupled to the interface; and in a memory controller. The execution unit processes a first subset of memory access commands from the first queue to a third queue, the third queue being associated with the first priority, according to a first processing procedure; processes a second subset of memory access commands from the second queue to a fourth queue, the fourth queue being associated with the second priority, according to a second processing procedure at the storage controller, wherein the execution unit runs the first and second processing procedures in parallel according to one or more parameters for priority sorting between the first and second priorities; and moves the data associated with the memory access commands between the buffer and the storage memory via the storage controller. Attached Figure Description

[0009] Figure 1 This document describes instances of systems that support managed memory systems with multiple priority queues, based on the examples disclosed herein.

[0010] Figure 2 This document describes instances of systems that support managed memory systems with multiple priority queues, based on the examples disclosed herein.

[0011] Figure 3 This document describes instances of systems that support managed memory systems with multiple priority queues, based on the examples disclosed herein.

[0012] Figure 4 This document describes an example of a system control graph that supports managed memory systems with multiple priority queues, based on the examples disclosed herein.

[0013] Figure 5 The diagram illustrates an example of a state machine supporting a managed memory system with multiple priority queues, according to aspects of this disclosure.

[0014] Figure 6A block diagram of a memory system supporting a managed memory system with multiple priority queues is shown, according to aspects of this disclosure.

[0015] Figure 7 A flowchart illustrating a method for supporting a managed memory system with multiple priority queues, based on an example disclosed herein. Detailed Implementation

[0016] Currently managed NAND systems are implemented as a combination of hardware and firmware. The hardware may include logic for data and command processing (e.g., queuing commands) and logic for moving, buffering, and storing data between interfaces and buffers. The firmware executes command processing. In some cases, commands may be associated with multiple different priorities. Because the firmware runs on a processor (e.g., a CPU) with execution units (e.g., a single execution unit), managing command processing according to command priority presents challenges in implementing command processing priorities and preventing pauses attributable to multiple queue priorities.

[0017] The techniques described herein involve implementing multiple handlers for processing commands from hardware and firmware queues. A managed NAND system may implement command queues for receiving commands and separate hardware queues for each priority level at both the front-end and back-end. Processors may run command handlers in parallel and move commands from the front-end hardware queue to the back-end hardware queue according to priority. For example, the command handler in the firmware may have parameters associated with priority ordering, and the execution of the handler may be controlled by or informed by these parameters. The managed NAND system may have a separate bus for command transfer from the front-end to the back-end.

[0018] First, as referenced Figure 1 and 2 Features of this disclosure are described in the context of the systems and apparatus described herein. (See references...) Figure 3-5 Features of this disclosure are described in the context of the systems, apparatus, and figures described herein. (See references to...) Figure 6 and 7 The device diagrams and flowcharts describing the managed memory system with multiple priority queues are illustrated and these and other features of this disclosure are described with reference to the device diagrams and flowcharts.

[0019] Figure 1 This is an example of system 100 that supports a managed memory system with multiple priority queues, based on the examples disclosed herein. System 100 includes a host system 105 coupled to memory system 110.

[0020] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0022] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations according to examples described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to host system 105 or contained in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 105 may use memory system 110, for example, to write data to and read data from memory system 110. Although Figure 1 A memory system 110 is shown, but it should be understood that the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, UFS interfaces, eMMC interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, USB interfaces, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR), Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR). In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 or memory device 140 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 or memory device 140 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Although in Figure 1 The example shows a memory device 130 and a memory device 140, but it should be understood that the memory system 110 may contain any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may not have memory devices 130 or memory devices 140.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with memory device 130 or memory device 140 to perform operations such as reading, writing, erasing, or refreshing data at memory device 130 or memory device 140, and other such operations that may generally be referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or memory device 140 to execute such commands (e.g., at a memory array within one or more memory devices 130 or memory device 140). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to memory device 130 or memory device 140. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 or 140 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with memory devices 130 or 140 into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with memory device 130 or memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 130 or memory device 140.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115.

[0029] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells. In some instances, memory device 140 may (e.g., by host system 105) support random access operations with reduced latency relative to memory device 130, or may provide one or more other performance differences relative to memory device 130.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0031] In some instances, memory device 130 or memory device 140 may each include (e.g., on the same die or within the same package) a local controller 135 or a local controller 145, which can perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 with the same page address within the corresponding plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0037] System 100 may include any number of non-transitory computer-readable media supporting a managed memory system with multiple priority queues. For example, host system 105, memory system controller 115, memory device 130, or memory device 140 may include or otherwise access one or more non-transitory computer-readable media containing storage instructions (e.g., firmware) for performing functions attributable herein to host system 105, memory system controller 115, memory device 130, or memory device 140. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, memory device 130 (e.g., by local controller 135), or memory device 140 (e.g., by local controller 145), may cause host system 105, memory system controller 115, memory device 130, or memory device 140 to perform the associated functions described herein.

[0038] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] Figure 2 This document describes an instance of system 200 that supports managed memory systems with multiple priority queues, based on the examples disclosed herein. System 200 may be a reference. Figure 1An example of the described system 100. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 when requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may be implemented with reference to Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0040] As described below, memory system 210 may include memory device set 240 for storing data transferred between memory system 210 and host system 205, for example, in response to receiving an access command from host system 205. Memory device set 240 may include data as described in reference... Figure 1 and 2 The memory device set 240 may include NAND memory, PCM, custom memory, 3D XPoint, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0041] Memory system 210 may include memory controller 230 for controlling the transfer of data directly into and out of memory device set 240, such as for storing data, retrieving data, and determining the memory location from which data is stored and retrieved. Memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device. In some cases, a single memory controller 230 may be used to control multiple memory devices of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, memory controller 230 may be implemented as described in reference [reference missing]. Figure 1 The aspects of the local controller 135 described.

[0042] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data being transferred between the host system and the memory device set 240. The interface 220, buffer 225, and memory controller 230 provide functionality associated with moving data between the host system 205 and the memory device set 240 (e.g., as shown by data path 250), and may be collectively referred to as the data path component.

[0043] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for the disposal of command bursts and the asynchronous storage or transmission of buffered data with bursts. Buffer 225 may include relatively fast memory, such as certain types of volatile memory, such as DRAM, 3D XPoint, or MRAM, and / or hardware accelerators to allow for fast storage and retrieval of data entering and leaving buffer 225. Buffer 225 may include data path switching components (e.g., crosspoint switches) for bidirectional data transfer between buffer 225 and other components.

[0044] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 may be a non-cached buffer. That is, data may not be read directly from buffer 225 by the host system 205. For example, read commands may be placed in a queue without requiring an address to be matched against an address already in the buffer (e.g., no cached address matching, Content Addressable Memory (CAM) lookup operation is required).

[0045] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be a reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0046] In some cases, one or more queues (e.g., received command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, when memory system 210 processes more than one access command from host system 205 in parallel. Although received command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively, this is for illustrative purposes only. Queues (if used) can be located anywhere within memory system 210. In some cases, received command queue 260 and storage queue 270 can be hardware queues (e.g., dedicated registers or memories in interface 220 and storage controller 230, respectively).

[0047] Data transferred between host system 205 and memory device set 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 can control how and when data is transferred between host system 205 and memory device set 240 by communicating with data path components on bus 235 (e.g., using a protocol specific to memory system 210).

[0048] When host system 205 sends an access command to memory system 210, interface 220 can receive the command, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. After receiving each access command, interface 220 can, for example, transmit the command to memory system controller 215 via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0049] The memory system controller 215 can determine that an access command has been received based on communication from interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving the command from the received command queue 260. After, for example, the command has been retrieved from the received command queue 260 by the memory system controller 215, the command can be removed from the command queue 260. In some cases, the memory system controller 215 can cause interface 220 to remove the command from the received command queue 260, for example, via bus 235.

[0050] After confirming that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device set 240 and transmitting the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device set 240.

[0051] In either case, the memory system controller 215 may use the buffer 225 for temporary storage of data being received from or sent to the host system 205. The buffer 225 may be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers for orientation addressing in the buffer) may be performed by hardware circuitry (e.g., logic gates).

[0052] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0053] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, access commands can be added to buffer queue 265 via memory system controller 215 and can be retained in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be processed in parallel.

[0054] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example via bus 235, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the data stored in buffer 225 from buffer queue 265. Interface 220 may indicate to memory system controller 215, for example via bus 235, when the data transfer to buffer 225 has been completed.

[0055] Once the written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can, for instance, use bus 235 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for instance, indicate to memory system controller 215 via bus 235 when data transfer to memory devices in memory device set 240 has been completed.

[0056] In some cases, storage queue 270 can be used to assist in the transfer of write data. Storage queue 270 may contain entries for each access command and may include, for example, a buffer pointer (e.g., an address) indicating where the data associated with the command is stored in buffer 225, and a storage pointer (e.g., an address) indicating the location of the data associated with the memory device set 240. In some cases, storage controller 230 may obtain the location of the data to be obtained from buffer 225 from buffer queue 265 or storage queue 270. Storage controller 230 may manage the locations within memory device set 240 used for storing data (e.g., performing wear leveling, garbage collection, etc.). Entries may be added to storage queue 270, for example, via memory system controller 215. After data transfer is complete, the entries may be removed from storage queue 270, for example, via storage controller 230 or memory system controller 215.

[0057] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the read command, for example via firmware (e.g., controller firmware) or hardware.

[0058] In some cases, buffer queue 265 can be used to assist buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands.

[0059] If buffer 225 has sufficient space to store the read data, then memory system controller 215 may, for example, cause memory controller 230 to retrieve the data associated with the read command from memory device 240 via bus 235 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 may, for example, indicate to memory system controller 215 via bus 235 when the data transfer to buffer 225 has been completed.

[0060] In some cases, storage queue 270 can be used to assist in the transfer of read data. In some cases, storage controller 230 can obtain the location of data to be retrieved from memory device set 240 from storage queue 270. In some cases, storage controller 230 can obtain the location of data to be stored in buffer 225 from buffer queue 265. In some cases, storage controller 230 can obtain the location of data to be stored in buffer 225 from storage queue 270.

[0061] Once data has been stored in buffer 225 by storage controller 230, it can be transferred from buffer 225 to host system 205. For example, storage system controller 215 may cause interface 220 to retrieve data from buffer 225 using data path 250, for example via bus 235, and transmit the data to host system 205, for example according to a protocol (e.g., UFS protocol or eMMC protocol). Interface 220 may indicate to storage system controller 215, for example via bus 235, when the data transfer to host system 205 has been completed.

[0062] The memory system controller 215 can execute received commands in a sequence (e.g., according to the order of the received command queue 260, in a first-in-first-out order). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moved into and stored in buffer 225, the command can remain in buffer queue 265. When the processing of the command is complete (e.g., when the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, via the memory system controller 215. When a command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0063] The memory system controller 215 may be additionally configured for operations associated with the memory device set 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device set 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more adjacent LBAs may be non-adjacent physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0064] Figure 3This document describes an instance of system 300 that supports a managed memory system with multiple priority queues, based on the examples disclosed herein. System 300 can be configured to store data received from host system 305 and send data to host system 305 when requested by host system 305 using a memory access command (e.g., a read command or a write command). System 300 may be a reference Figure 2 An example of the described system 200 or memory system 210.

[0065] System 300 may include a front-end 310, a middle-end 315, and a back-end 320 for moving data between host system 305 and storage device 325. System 300 may also include a CPU 330 that controls data movement by communicating with components via a high-priority bus 302 and a low-priority bus 303. The high-priority bus 302 can be used for higher-priority traffic compared to the low-priority bus 303. In some cases, a single bus may exist instead of separate high-priority and low-priority buses. System 300 may be implemented with reference to... Figure 2 The described aspects of the memory system 210. For example, the front end 310, the middle end 315, and the back end 320 may each incorporate aspects of the interface 220, the buffer 225, and the memory controller 230. Thus, the front end 310, the middle end 315, and the back end 320 may be referred to herein as the interface 220, the buffer 225, and the memory controller 230, respectively. The CPU 330 may be an instance of the memory system controller 215 and may include an execution unit (not shown). The CPU 330 may include a single execution unit. The execution unit may include, for example, an arithmetic logic unit (ALU), a control unit (CU), an address generation unit (AGU), a floating-point unit (FPU), a load-memory unit (LSU), or a branch execution unit (BEU), and may be referred to as a "core".

[0066] System 300 may also include one or more queues controlling the processing of access commands and the movement of corresponding data. Command queue 335 may be used to store access commands received from host system 305. Command queue 335 may be used as a reference. Figure 2 The discussion focuses on an instance of the received command queue 260.

[0067] Submission queue (SQ) 340 and completion queue (CQ) 345 can be used to store information about each access command being processed, including, for example, the command, one or more memory locations associated with the command, and processing status. Separate SQs 340 and CQs 345 may exist for access commands of different priorities. For example, such as... Figure 3As shown, SQ 340 and CQ 345 may include SQ 340-a and 340-c and CQ 345-a and 345-c for access commands of first priority, and SQ 340-b and 340-d and CQ 345-b and 345-d for access commands of second priority. In some cases, the first priority may correspond to a higher priority relative to the second priority. Therefore, "high" priority and "low" priority may be used herein to refer to "first" priority and "second" priority. Although the discussion herein pertains to two priorities, it should be understood that the concepts discussed herein are applicable to systems that handle access commands with more than two priorities. For example, for systems with more than two priorities, additional SQ 340 and CQ 345 corresponding to the additional priorities may be used.

[0068] When host system 305 sends an access command to system 300, the command can be received at front-end 310, for example, via host protocol interface 350. The access command can be added to command queue 335, for example, via front-end 310, to convey the command to CPU 330. In some cases, access commands can be added to command queue 335 in the order they are received from host system 305.

[0069] CPU 330 can determine that an access command has been received using command queue 335. In some cases, CPU 330 can receive a signal, such as an IRQ signal, from front end 310 when an access command is received. In some cases, CPU 330 can monitor command queue 335 or its state to determine when a new access command has been received.

[0070] Access command information can be obtained from the command queue 335, for example, via the CPU 330 through the high-priority bus 302 or the low-priority bus 303. The CPU 330 can then determine the priority and type of the access command, and subsequently queue the access command for execution, as discussed in more detail below. Access commands can be removed from the command queue, for example, via the CPU 330.

[0071] To process write commands received from host system 305, entries corresponding to the write commands can be added to front-end CQ 345-a or CQ 345-b, for example, via CPU 330 based on command priority. In some cases, CQ 345 entries may contain location pointers (e.g., pointers to memory locations) indicating the location of temporarily stored data within buffer 355 of mid-end 315. In some cases, the front-end may obtain the pointer to the next buffer to be used from the hardware accelerator of mid-end 315. Buffer queues can be used to track buffers 355, as referenced. Figure 2 The discussion.

[0072] Based on the information in the corresponding front-end CQ 345 entry, data received from the host system 305 can be stored in the buffer 355, for example, via the front-end 310, or via the multipoint bridge 370. Front-end CQ 345 entries corresponding to write commands can be removed, for example, via the front-end 310 or the CPU 330. When data is stored in the buffer 355, entries can be added, for example, via the front-end 310 based on the command priority to the front-end SQ 340-a or SQ 340-b, to indicate that data corresponding to the write command is in the buffer 355.

[0073] Based on the entries added to the front-end SQ 340-a or SQ 340-b, corresponding entries can be added to the back-end SQ 340-c or SQ 340-d, for example, via the CPU 330 based on command priority. Back-end SQ 340 entries may contain pointers to the location of data already stored in buffer 355. Back-end SQ 340 entries may contain location pointers indicating the location of data stored in storage device 325 (e.g., pointers to memory locations within memory device 240). When no longer needed, front-end SQ 340 entries can be removed, for example, via the CPU 330.

[0074] Using backends SQ 340-c and SQ 340-d, the order in which backend 320 processes corresponding commands can be determined, for example, through arbitration logic. While commands in higher-priority SQ 340-c can be prioritized, lower-priority SQ 340-d should still be processed in a timely manner. Arbitration logic can be one way to ensure this occurs. Arbitration logic can also optimize command processing. In one instance, the arbitration logic can monitor higher-priority SQ 340-c and lower-priority SQ 340-d, determine the order in which corresponding commands are processed, and move entries accordingly from each queue to a separate backend queue. Backend 320 can then process the commands based on their order in said separate queue. Other arbitration schemes can also be used, as discussed below.

[0075] When a write command corresponding to an entry added to the backend SQ 340 is processed, the data corresponding to the write command can be retrieved from the buffer 355 via the backend 320 and stored in the storage device 325, for example, via the storage controller 360 based on the backend SQ 340 entry. The storage controller 360 may be a reference. Figure 2 An example of the storage controller 230 is discussed.

[0076] Storage device 325 may include a reference Figure 2The described set of one or more memory devices 240. For example, the memory device set 240 may include NAND memory, PCM, custom memory, 3D XPoint, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM. To communicate with the memory devices, the memory controller 360 may use one or more memory interfaces 365, each employing one or more protocols specific to the memory device type. When no longer needed, the backend SQ 340 entry corresponding to a write command may be removed, for example, via backend 320 or CPU 330.

[0077] Once data has been stored in storage device 325, an entry can be added to backend CQ 345-c or CQ 345-d, for example, via backend 320 based on command priority, to indicate that data corresponding to a write command has been successfully written to storage device 325. Based on the entry added to backend CQ 345, CPU 330 can be informed that the command was successfully completed. The corresponding backend CQ 345 entry can be removed, for example, via CPU 330.

[0078] To process read commands received from host system 305, one or more entries corresponding to the read command may be added to backend SQ 340-c or SQ 340-d, for example, by CPU 330 based on command priority. In some cases, a single SQ 340 entry may be used for a read command. In some cases, the read command may be decoded into several internal read command entries to be added to the corresponding backend SQ 340. In some cases, the backend SQ 340 entry may contain a location pointer indicating the location within storage device 325 from which data will be obtained (e.g., a pointer to a memory location within memory device 240). In some cases, the SQ 340 entry may contain a location pointer indicating the location within buffer 355 where data will be temporarily stored (e.g., a pointer to a memory location). In some cases, the backend may obtain the pointer to the next buffer to be used from the hardware accelerator of midend 315.

[0079] Using the information in the corresponding backend SQ 340 entry, the data associated with the read command can be retrieved from the storage device 325, for example, via the storage controller 360 through the storage interface 365, and the data can be temporarily stored in the buffer 355. When no longer needed, the backend SQ 340 entry can be removed, for example, via the backend 320 or the CPU 330. When data is already stored in the buffer 355, an entry can be added, for example, via the backend 320 based on the command priority to the backend CQ 345-c or CQ 345-d to indicate that the data corresponding to the read command is in the buffer 355.

[0080] Based on the entries added to the backend CQ 345-c or CQ 345-d, corresponding entries can be added to the frontend CQ 345-a or CQ 345-b, for example, via CPU 330 based on command priority. The frontend CQ 345 entries may contain pointers to the location of data stored within buffer 355. When no longer needed, the backend CQ 345 entries can be removed, for example, via CPU 330.

[0081] Based on the entries added to the front-end CQ 345-a or CQ 345-b, data corresponding to a read command can be obtained from buffer 355 (e.g., using the orientation pointer within the corresponding CQ 345 entry) and transmitted to the host system 305, for example, via the host protocol interface 350 through the front-end 310. When no longer needed, the front-end CQ 345 entry can be removed, for example, via the CPU 330 or the front-end 310.

[0082] When determining the order in which read commands are sent to host system 305, entries in high-priority CQ 345-a can take precedence over entries in low-priority CQ 345-b. Once data has been sent to host system 305, entries can be added, for example, via front-end 310 to front-end SQ 340-a or SQ 340-b based on command priority to indicate that data has been successfully sent to the host. Based on the entries added to front-end SQ 340, CPU 330 can determine that the command was successfully completed. The corresponding front-end SQ 340 entry can be removed, for example, via CPU 330.

[0083] Figure 4 This document describes an example of a system control diagram 400 supporting a managed memory system with multiple priority queues, based on the examples disclosed herein. System control diagram 400 illustrates the flow of access commands received from the host through... Figure 3 The system 300 is processed by the CPU 330. In some cases, the processors and queues shown within the CPU 330 may be executed and located within firmware, while the queues within the front end 310 and back end 320 may be located within hardware. In some cases, some or all of the processors may be run by the execution unit of the CPU 330. Using the queues and other components shown in the system control diagram 400, the received commands can be processed according to their priority and position within the queue.

[0084] For reference Figure 3As described, access commands received from host system 305 can be added to command queue 335. Commands can be retrieved from command queue 335 via CPU 330 and processed by command processor 405. Command processor 405 can decode the commands to determine the priority level of each command. In some systems, one or more fields in the access command can indicate the priority level of the command. Each command can be routed from the command queue to the corresponding priority queue 410 based on the determined priority. For example, if the command is of high priority, it can be placed in high priority queue 410-a; if the command is of low priority, it can be placed in low priority queue 410-b.

[0085] One or more command routers 415 can determine how access commands in priority queue 410 should be routed. To do this, command router 415 can determine the access type corresponding to each command. For example, command router 415 can determine whether the access command is a read command or a write command. Each command can be placed in the corresponding processor queue 420 based on the determined priority and type. For example, for a command from high priority queue 410-a, if the command is a write type, it can be placed in high write processor queue 420-a1, and if the command is a read type, it can be placed in high read processor queue 420-a2. For a command from low priority queue 410-b, if the command is a write type, it can be placed in low write processor queue 420-b1, and if the command is a read type, it can be placed in low read processor queue 420-b2. Although two command routers 415-a and 415-b are shown, they can be combined into a single router (as needed).

[0086] The arbitration logic can also be used by the command router 415 to determine the order in which high-priority and low-priority commands can be processed. This arbitration logic can be referenced above. Figure 3 The arbitration logic discussed may be used in place of or replace the aforementioned arbitration logic. As discussed above, although higher-priority access commands may take precedence over lower-priority access commands, lower-priority commands can still be processed in a timely manner (e.g., without pausing). See below for reference. Figure 5 Here is an example of such arbitration logic. In one example, when a low-priority command has not yet been processed within the minimum time frame, the command can be moved up in order.

[0087] One or more processors 425 may process access commands in processor queue 420. In some cases, a single processor 425 may be used for each processor queue 420. For example, a high write processor 425-a1 may process access commands in high write processor queue 420-a1, a high read processor 425-a2 may process access commands in high read processor queue 420-a2, a low write processor 425-b1 may process access commands in low write processor queue 420-b1, and a low read processor 425-b2 may process access commands in low read processor queue 420-b2.

[0088] In some cases, each processor 425 may operate independently of the other processors. That is, processors 425 may run in parallel with each other. In other words, each processor may be an active handler, but only one handler will execute in a given instruction loop. Each of the processors 425 may be a different thread. Execution units may switch between processors 425 based on thread or handler scheduling (e.g., scrambling resources such as program counters, registers, stack pointers, memory addresses, page tables, or kernel resources). In some cases, switching between processors 425 may take into account the priority ordering of processors 425 (e.g., providing more processing resources or execution loops for a high-read processor 425-a2 compared to a low-read processor 425-b2). In some cases, when an access command is added to the processor queue 420, the processor 425 associated with the processor queue may be activated to begin command execution.

[0089] To execute access commands, the processor 425 may use a front end 310 and a back end 320. For example, see reference... Figure 3 The processing of commands is controlled in a manner described above. Processor 425 may use either a write command state machine 430 or a read command state machine 435 (if applicable). In one instance, the priority ordering of access commands executed by the write command state machine 430 or the read command state machine 435 may be based on the number of commands in each processor queue 420. The write command state machine 430 or the read command state machine 435 may manipulate the front-end CQ 345 and the back-end SQ 340 based on inputs 440 from the front-end SQ 340 and inputs 445 from the back-end CQ 345, as described above. A high-priority processor 425-a may utilize high-priority CQs and SQs, and a low-priority processor 425-b may utilize low-priority SQs and CQs.

[0090] For example, for a write command, write processors 425-a1 and 425-b1 may i) add an entry to the front-end CQ 345 so that the front-end 310 is aware of the write command, and include a pointer to the location in the buffer where the received data will be stored; ii) determine from the front-end SQ 340 when the data has been stored in the buffer; iii) add an entry to the back-end SQ 340 so that the back-end 320 is aware of the write command, and include a pointer to the location in the buffer where the data is located and a pointer to the location in the storage device 325 where the data will be stored; and iv) determine from the back-end CQ 345 when the data corresponding to the write command has been successfully written to the storage device 325.

[0091] As another example, for a read command, read handlers 425-a2 and 425-b2 may i) add an entry to backend SQ 340 to inform backend 320 of the read command, and include a pointer to the location of the data to be read in storage device 325 and a pointer to the location of the data to be stored in buffer; ii) determine from backend CQ 345 when the data has been stored in buffer; iii) add an entry to frontend CQ 345 to inform frontend 310 of the read command, and include a pointer to the location of the data in buffer; and iv) determine from frontend SQ 340 when the data corresponding to the read command has been successfully transmitted to host system 305.

[0092] Processor handlers 425 can run in parallel to process access commands in their respective handler queues 420. In some cases, a task scheduler (not shown) can be used to avoid conflicts between processor handlers 425 and to prioritize the execution of access commands based on various factors such as the priority of the access commands, the number of access commands in each handler queue 420, etc.

[0093] The CPU 330's processor and / or one or more queues may be combined as needed. For example, command processing and command routing may be combined such that when an access command is retrieved from command queue 335, the access command can be placed in its corresponding processor queue 420 without first placing it in priority queue 410.

[0094] Processors can be used for additional priorities and / or types. For example, if third priority is used, then CPU 330 can use three priority queues 410, three routers 415, six processor queues 420, and six processor processors 425. This can be adapted to accommodate other priority numbers and access types.

[0095] Figure 5The diagram illustrates an example of a state machine 500 supporting a managed memory system with multiple priority queues, according to the examples disclosed herein. State machine 500 may be an example of a pause-prevention handler that prevents pauses caused by multiple queue priorities. State machine 500 can handle concurrent high-priority and low-priority traffic so that low-priority commands do not pause. State machine 500 may be a reference. Figure 4 Examples of the arbitration logic discussed.

[0096] During operation, command router 415 can periodically analyze priority queue 410 and move any command from it to processor queue 420 using a modified polling technique. During each analysis, command router 415 can determine command N, which is located in high-priority queue 410-a and low-priority queue 410-b, respectively. H and N L The number. When at least one of the priority queues 410 is not empty (N H >0 or N L When >0), state machine 500 can be entered from state 505. If the high-priority queue 410-a is not empty (N H If the priority queue 410-a is empty and the priority queue is not empty (N > 0), then the logic can proceed along path 510 to state 525. H =0, N L If the value is >0), then the logic can follow path 515 to enter state 530.

[0097] In state 525, corresponding to N H Commands can be routed from high-priority queue 410-a to the corresponding high-write processor queue 420-a1 or high-read processor queue 420-a2. That is, as N H Each command that is partially counted can be removed from or dequeued from the high-priority queue 410-a and added to one of the high-handler queues 420-a. During routing, the command handler 405 may add new entries to the high-priority queue 410-a. These new entries may be ignored and not routed. That is, new entries may not be considered for routing until the next entry into state 525.

[0098] Once command routing is complete in state 525, priority queue 410 can be checked again to determine if any new commands were added to the queue during routing. To do this, commands N, which are in high-priority queue 410-a and low-priority queue 410-b respectively, can be re-identified. H and N L The number. If the low-priority queue 410-b is not empty (N L >0) while the high-priority queue 410-a is empty (NH =0) or the anti-pause condition is met (e.g., the first number of commands from high-priority queue 410-a have been processed consecutively), then the logic can follow path 540 to enter state 530 to route the newly added low-priority entry to one of the low-priority processor queues 420-b. If low-priority queue 410-b is empty but high-priority queue 410-a is not empty (N H >0, N L If the priority is 0, then the logic can re-enter state 525, as shown by path 535, to route the newly added high-priority entry to one of the high-priority queues 420-a. If both priority queues are empty (N... H =0, N L If the value is 0, then state machine 500 can be exited.

[0099] In state 530, corresponding to N L Commands can be routed from low-priority queue 410-b to the corresponding low-write processor queue 420-b1 or low-read processor queue 420-b2. That is, as N L Each command that is partially counted can be removed from or dequeued from the low-priority queue 410-b and added to one of the low-handler queues 420-b. During routing, the command handler 405 may add new entries to the low-priority queue 410-b. These new entries may be ignored and not routed. That is, new entries may not be considered for routing until the next entry into state 530.

[0100] Once command routing is complete in state 530, priority queue 410 can be checked again to determine if any new commands were added to the queue during routing. To do this, commands N that are in high-priority queue 410-a and low-priority queue 410-b can be checked again. H and N L The number. If the high-priority queue 410-a is not empty (N H >0) while the low-priority queue 410-a is empty (N L =0) or the anti-pause condition is met (e.g., a second number of commands from high-priority queue 410-a have been processed consecutively), then the logic can follow path 520 to enter state 525 to route the newly added high-priority entry to one of the high-handler queues 420-a. In some cases, the number of the second command may be less than the number of the first command. If high-priority queue 410-a is empty but low-priority queue 410-b is not empty (N H =0, N LIf the priority is >0), then the logic can re-enter state 530, as shown by path 545, to route the newly added low-priority entry to one of the low-priority queues 420-b. If both priority queues are empty (N... H =0, N L If the value is 0, then state machine 500 can be exited.

[0101] The method described above, moving along paths 520 and 540 between states 525 and 530, can continue until both priority queues become empty, at which point state machine 500 can be exited. This allows for timely execution of low-priority commands without pausing.

[0102] Figure 6 A block diagram 600 illustrates a memory system 605 supporting a managed memory system with multiple priority queues, according to an example disclosed herein. The memory system 605 may be as described in the references... Figure 2-5 Examples of aspects of the described memory system are shown. Memory system 605 may include a host interface 610, a command priority determiner 615, a command router 620, a data router 625, a command processor 630, and a memory controller 635. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0103] The host interface 610 can receive memory access commands from the host at the interface. In some instances, the host interface 610 can store memory access commands in a command queue. In some instances, the host interface 610 can send data retrieved from a buffer to the host via the interface. In some instances, the host interface 610 can send a first subset of data associated with a first subset of memory access commands to the host. In some instances, the host interface 610 can send a second subset of data associated with a second subset of memory access commands to the host. In some instances, the host interface 610 can receive data associated with memory write commands from the host via the interface.

[0104] Command priority determiner 615 can determine a first subset of memory access commands associated with a first priority and a second subset of memory access commands associated with a second priority. In some cases, the first subset of memory access commands may be associated with read commands associated with the first priority. In some cases, the second subset of memory access commands may be associated with read commands associated with the second priority. In some instances, command priority determiner 615 can determine a third subset of memory access commands associated with write commands associated with the first priority and a fourth subset of memory access commands associated with write commands associated with the second priority.

[0105] Command router 620 can route a first subset of memory access commands associated with a first priority from the command queue to the first queue. In some instances, command router 620 can route a second subset of memory access commands associated with a second priority from the command queue to the second queue. In some instances, command router 620 can route a third subset of memory access commands associated with a first priority from the command queue to the fifth queue. In some instances, command router 620 can route a fourth subset of memory access commands associated with a second priority from the command queue to the sixth queue.

[0106] Data router 625 can store data associated with memory access commands in a buffer coupled to an interface. In some instances, data router 625 can retrieve data associated with memory read commands from the buffer via the interface.

[0107] Command processor 630 can process a first subset of memory access commands from a first queue to a third queue, associated with a first priority, at the memory controller according to a first processing program via a processor including an execution unit. In some instances, command processor 630 can process a second subset of memory access commands from a second queue to a fourth queue, associated with a second priority, at the memory controller according to a second processing program via a processor. In some instances, the execution unit can run the first and second processing programs in parallel according to one or more parameters used for priority sorting between the first and second priorities.

[0108] In some instances, when a memory access command has not yet been processed within a minimum time frame, the command processor 630 may move the memory access commands in the fourth queue upwards in order. In some instances, the command processor 630 may process a third subset of memory access commands from the fifth queue to the third queue at the memory controller according to a third processing program. In some instances, the command processor 630 may process a fourth subset of memory access commands from the sixth queue to the fourth queue at the memory controller according to a fourth processing program. In some instances, the execution unit may run the third and fourth processing programs in parallel with the first and second processing programs according to one or more parameters used for priority sorting between the first and second priorities.

[0109] In some cases, memory access commands include memory read commands. In other cases, memory access commands include memory write commands.

[0110] The memory controller 635 can move data associated with memory access commands between a buffer and a storage memory containing a set of memory cells. In some instances, the memory controller 635 can move data between the buffer and the storage memory based on the contents of a third queue and a fourth queue. In some instances, the memory controller 635 can determine the order in which memory access commands for the third queue and the fourth queue are processed based on their respective first and second priorities. In some instances, the memory controller 635 can move data between the buffer and the storage memory based on the order in which memory access commands for the third queue and the fourth queue are processed.

[0111] In some instances, the storage controller 635 may move data associated with a memory read command from the storage memory to a buffer. In some instances, the storage controller 635 may move data from the buffer to the storage memory. In some instances, the storage controller 635 may move data from the buffer to the storage memory based on arbitration logic that determines the order in which memory access commands for the third and fourth queues are processed based on their respective first and second priorities.

[0112] Figure 7 A flowchart illustrating a method for supporting a managed memory system with multiple priority queues according to aspects of this disclosure is shown. The operation of method 700 can be implemented by a memory system or its components as described herein. For example, it can be implemented by, as referenced... Figure 6 The described memory system performs the operations of method 700. In some instances, the memory system may execute an instruction set to control the functional elements of the memory system to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0113] At 705, the memory system can receive memory access commands from the host at the interface. The operation of 705 can be performed according to the method described herein. In some instances, it can be done via reference. Figure 6 The described host interface performs the 705 operation.

[0114] At 710, the memory system can store memory access commands in a command queue. The operation at 710 can be performed according to the method described herein. In some instances, it can be done via reference. Figure 6 The described host interface performs the operations of 710.

[0115] At 715, the memory system can determine a first subset of memory access commands associated with a first priority and a second subset of memory access commands associated with a second priority. The operation at 715 can be performed according to the method described herein. In some instances, it can be done by referring to... Figure 6 The described command priority determiner performs 715 aspects of the operation.

[0116] At 720, the memory system can route a first subset of memory access commands associated with the first priority from the command queue to the first queue. The operation at 720 can be performed according to the method described herein. In some instances, it can be done via reference... Figure 6 The described command router performs the 720 operation.

[0117] At point 725, the memory system can route a second subset of memory access commands associated with the second priority from the command queue to the second queue. The operation at point 725 can be performed according to the method described herein. In some instances, it can be done via reference... Figure 6 The described command router performs the operation of 725.

[0118] At 730, the memory system can store data associated with memory access commands in a buffer coupled to the interface. The operation of 730 can be performed according to the method described herein. In some instances, it can be done via reference... Figure 6 The described command router performs the operations of 730.

[0119] At 735, the memory system can process a first subset of memory access commands from a first queue to a third queue, associated with a first priority, at the memory controller via a processor containing an execution unit, according to a first processing program. The operation at 735 can be performed according to the method described herein. In some instances, it can be performed by reference... Figure 6 The described command processor performs the operations of 735.

[0120] At 740, the memory system can process a second subset of memory access commands from a second queue to a fourth queue, associated with a second priority, at the memory controller via a processor, according to a second processing program. The execution unit runs the first and second processing programs in parallel based on one or more parameters for priority sorting between the first and second priorities. The operation at 740 can be performed according to the method described herein. In some instances, it can be achieved by referring to… Figure 6 The described command processor performs 740 operations.

[0121] At 745, the memory system can move data associated with memory access commands between a buffer and a storage memory containing a set of memory cells via a memory controller. The operation of 745 can be performed according to the method described herein. In some instances, it can be done via a reference. Figure 6 The described aspect of the storage controller performs the operation of 745.

[0122] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving memory access commands from a host at an interface; storing the memory access commands in a command queue; determining a first subset of memory access commands associated with a first priority and a second subset of memory access commands associated with a second priority; routing the first subset of memory access commands associated with the first priority from the command queue to a first queue; routing the second subset of memory access commands associated with the second priority from the command queue to a second queue; storing data associated with the memory access commands in a buffer coupled to the interface; and so on. The processor, which includes execution units, processes a first subset of memory access commands from a first queue to a third queue, associated with a first priority, at the memory controller according to a first processing program; the processor processes a second subset of memory access commands from a second queue to a fourth queue, associated with a second priority, at the memory controller according to a second processing program, wherein the execution units run the first and second processing programs in parallel according to one or more parameters for priority sorting between the first and second priorities; and the memory controller moves data associated with the memory access commands between a buffer and a storage memory containing a set of memory cells.

[0123] In some instances of the method 700 and apparatus described herein, moving data between a buffer and a storage memory may include operations, features, means, or instructions for moving data between the buffer and the storage memory based on the contents of a third queue and a fourth queue.

[0124] Some instances of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for determining the order in which memory access commands for processing the third and fourth queues are processed by a storage controller based on the respective first and second priorities of the third and fourth queues.

[0125] In some instances of the method 700 and apparatus described herein, moving data between a buffer and a storage memory may include operations, features, means, or instructions for moving data between the buffer and the storage memory based on the order in which memory access commands for processing a third queue and a fourth queue are processed.

[0126] In some instances of the method 700 and apparatus described herein, determining the order of processing memory access commands in the third and fourth queues may include operations, features, means, or instructions for moving the memory access commands in the fourth queue upwards in order when the memory access commands have not yet been processed within a minimum time frame.

[0127] In some instances of the method 700 and device described herein, the memory access command includes a memory read command. In some instances of the method 700 and device described herein, the memory access command includes a memory write command.

[0128] In some instances of the method 700 and apparatus described herein, moving data between a buffer and a storage memory may include operations, features, means, or instructions for moving data associated with a memory read command from the storage memory to the buffer via a storage controller.

[0129] Some instances of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for retrieving data associated with a memory read command from a buffer via an interface; and sending the data retrieved from the buffer to a host via an interface.

[0130] In some instances of the method 700 and apparatus described herein, sending data retrieved from a buffer to a host may include operations, features, means, or instructions for sending a first subset of data associated with a first subset of memory access commands to the host, and sending a second subset of data associated with a second subset of memory access commands to the host.

[0131] Some instances of the method 700 and device described herein may additionally include operations, features, means, or instructions for receiving data associated with a memory write command from a host via an interface.

[0132] In some instances of the method 700 and apparatus described herein, moving data between a buffer and a storage memory may include operations, features, means, or instructions for moving data from the buffer to the storage memory via a storage controller.

[0133] In some instances of the method 700 and apparatus described herein, moving data from a buffer to a storage memory may include operations, features, means, or instructions for moving data from a buffer to a storage memory via a storage controller based on arbitration logic, said arbitration logic determining the order in which memory access commands for processing the third and fourth queues are processed based on corresponding first and second priorities of the third and fourth queues.

[0134] In some instances of the method 700 and apparatus described herein, the first subset of memory access commands may be associated with read commands of the first priority, and the second subset of memory access commands may be associated with read commands of the second priority.

[0135] Some examples of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for: determining a third subset of memory access commands associated with a write command associated with a first priority and a fourth subset of memory access commands associated with a write command associated with a second priority; routing the third subset of memory access commands associated with the first priority from the command queue to a fifth queue; routing the fourth subset of memory access commands associated with the second priority from the command queue to a sixth queue; processing the third subset of memory access commands from the fifth queue to the third queue at the memory controller by the processor according to a third processing program; and processing the fourth subset of memory access commands from the sixth queue to the fourth queue at the memory controller by the processor according to a fourth processing program, wherein the execution unit may run the third and fourth processing programs in parallel with the first and second processing programs according to one or more parameters for priority ordering between the first and second priorities.

[0136] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0137] Describe an apparatus. The apparatus may include an interface configured to receive memory access commands from a host and to send and receive data associated with the memory access commands. The interface may include a processor. The processor may include a first queue configured to store a first subset of memory access commands associated with a first priority; a second queue configured to store a second subset of memory access commands associated with a second priority; and one or more command routers configured to obtain the memory access commands from the command queues, determine the first and second subsets of the memory access commands, and store the first and second subsets in the first and second queues, respectively. The apparatus may also include a buffer coupled to the interface and configured to store the data associated with the memory access commands. The apparatus may also include a storage memory containing a plurality of memory cells. The apparatus may further include a storage controller configured to move the data associated with the memory access commands between the buffer and the storage memory. The storage controller may include a third queue associated with the first priority and a fourth queue associated with the second priority. The processor may be configured to process a first subset of memory access commands from the first queue to the third queue according to a first processing program and a second subset of memory access commands from the second queue to the fourth queue according to a second processing program, wherein the first and second processing programs are configured to run in parallel by the execution unit according to one or more parameters for priority sorting between the first and second priorities.

[0138] In some instances, the storage controller may additionally include arbitration logic configured to determine the order in which memory access commands for the third and fourth queues are processed, based on the respective first and second priorities of the third and fourth queues. In some instances, the storage controller may be configured to move data associated with the memory access commands for the third and fourth queues based on the order in which the memory access commands for the third and fourth queues are processed.

[0139] In some instances, the processor may additionally include a fifth queue and a sixth queue. A first subset of memory access commands may be associated with read commands of the first priority. A second subset of memory access commands may be associated with read commands of the second priority. The fifth queue may be configured to store a third subset of memory access commands associated with write commands of the first priority. The sixth queue may be configured to store a fourth subset of memory access commands associated with write commands of the second priority.

[0140] In some instances, the one or more command routers may be further configured to determine a third subset and a fourth subset of the memory access commands and store the third subset and the fourth subset in the fifth queue and the sixth queue, respectively. The processor may be further configured to process the third subset of memory access commands from the fifth queue to the third queue according to a third processing program and to process the fourth subset of memory access commands from the sixth queue to the fourth queue according to a fourth processing program. The third and fourth processing programs may be configured to run in parallel with the first and second processing programs via the execution unit according to one or more parameters for priority sorting between the first priority and the second priority.

[0141] In some instances, the processor may additionally include operations, features, means, or instructions for processing memory access commands when a memory access command associated with the second priority may not have been processed within a minimum time frame.

[0142] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0143] As used herein, the terms “electronic communication,” “conductive contact,” “connection,” and “coupling” refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is a conductive path between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the signal flow between connected components for a period of time.

[0144] As used herein, the term "coupling" refers to a condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between the components via a conductive path, and in which a signal is allowed to travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0145] As used herein, the term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0146] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0147] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0148] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0149] Some or all of the functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the function may be one or more instructions or codes stored on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including those distributed such that portions of the function are implemented in different physical orientations.

[0150] For example, the various illustrative blocks and modules described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0151] Furthermore, as used herein, the word "or" used in the list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0152] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: Receive memory access commands from the host at the interface; The memory access commands are stored in a command queue; Determine a first subset of memory access commands associated with the first priority and a second subset of memory access commands associated with the second priority; The first subset of memory access commands associated with the first priority is routed from the command queue to the first queue; The second subset of memory access commands associated with the second priority is routed from the command queue to the second queue; The data associated with the memory access command is stored in a buffer coupled to the interface; One of the processors transmits a first subset of memory access commands from a first queue at the memory controller to a third queue at the memory controller, the third queue being associated with the first priority, according to a first processing program. In parallel with transferring the first subset of memory access commands from the first queue to the third queue, the processor transfers the second subset of memory access commands from the second queue at the memory controller to a fourth queue at the memory controller according to a second processing program. The fourth queue is associated with a second priority, wherein the processor's execution unit processes the first subset of memory access commands and the second subset of memory access commands in parallel according to the number of memory access commands in the command queue, which is sorted by priority between the first priority and the second priority. and The data associated with the memory access command is moved between the buffer and the storage memory comprising multiple memory cells via the storage controller.

2. The non-transitory computer-readable medium of claim 1, wherein the movement of the data between the buffer and the storage memory by the storage controller is based at least in part on the contents of the third queue and the fourth queue.

3. The non-transitory computer-readable medium of claim 1, further comprising, when executed by the one or more processors of the electronic device, causing the electronic device to perform the following operations: The storage controller determines the order in which the memory access commands of the third and fourth queues are processed, based at least in part on the corresponding first and second priorities of the third and fourth queues.

4. The non-transitory computer-readable medium of claim 3, wherein the movement of the data between the buffer and the storage memory by the storage controller is at least in part based on the order in which the memory access commands of the third queue and the fourth queue are processed.

5. The non-transitory computer-readable medium according to claim 3, wherein: The determination of the order of processing the memory access commands of the third and fourth queues includes moving the memory access commands of the fourth queue upwards in order when the memory access commands have not yet been processed within the minimum time frame.

6. The non-transitory computer-readable medium of claim 1, wherein the memory access command includes a memory read command, and wherein moving the data between the buffer and the storage memory includes moving the data associated with the memory read command from the storage memory to the buffer via the storage controller; and The non-transitory computer-readable medium includes additional instructions that, when executed by one or more processors of the electronic device, cause the electronic device to perform the following operations: The data associated with the memory read command is retrieved from the buffer via the interface; and The data retrieved from the buffer will be sent to the host via the interface.

7. The non-transitory computer-readable medium of claim 6, wherein the data transmitted to the host includes a first subset of data associated with a first subset of the memory access commands and a second subset of data associated with a second subset of the memory access commands.

8. The non-transitory computer-readable medium of claim 1, wherein the memory access command includes a memory write command; and The non-transitory computer-readable medium includes additional instructions that, when executed by one or more processors of the electronic device, cause the electronic device to perform the following operations: The data associated with the memory write command is received from the host through the interface, wherein moving the data between the buffer and the storage memory includes moving the data from the buffer to the storage memory via the storage controller.

9. The non-transitory computer-readable medium of claim 8, wherein the movement of data from the buffer to the storage memory by the storage controller is at least in part based on arbitration logic, the arbitration logic determining the order in which the memory access commands of the third queue and the fourth queue are processed based on the respective first priority and second priority of the third queue and the fourth queue.

10. The non-transitory computer-readable medium of claim 1, wherein the first subset of memory access commands is associated with read commands of the first priority, and the second subset of memory access commands is associated with read commands of the second priority, and The non-transitory computer-readable medium includes additional instructions that, when executed by one or more processors of the electronic device, cause the electronic device to perform the following operations: Determine a third subset of memory access commands associated with write commands of the first priority and a fourth subset of memory access commands associated with write commands of the second priority; The third subset of memory access commands associated with the first priority is routed from the command queue to the fifth queue; The fourth subset of memory access commands associated with the second priority is routed from the command queue to the sixth queue; The processor processes the third subset of memory access commands from the fifth queue to the third queue at the memory controller according to the third processing program; and The processor processes a fourth subset of memory access commands from the sixth queue to the fourth queue at the memory controller according to a fourth processing program, wherein the execution unit of the processor runs the third and fourth processing programs in parallel with the first and second processing programs according to the number of memory access commands in the command queues sorted according to the priority between the first priority and the second priority.

11. A memory device comprising: An interface configured to receive memory access commands from a host and to send and receive data associated with the memory access commands, the interface including: A command queue, configured to store the memory access commands received by the interface; Processor, comprising: Execution unit; The first queue is configured to store a first subset of memory access commands associated with a first priority; The second queue is configured to store a second subset of memory access commands associated with a second priority; and One or more command routers are configured to obtain the memory access commands from the command queue, determine a first subset and a second subset of the memory access commands, and store the first subset and the second subset in the first queue and the second queue, respectively. A buffer, coupled to the interface and configured to store the data associated with the memory access command; Storage memory, which includes multiple memory cells; and A storage controller configured to move the data associated with the memory access command between the buffer and the storage memory, the storage controller comprising: The third queue associated with the first priority; and The fourth queue associated with the second priority, The processor is configured to transfer a first subset of memory access commands from a first queue at the memory controller to a third queue at the memory controller according to a first processing program, and to transfer a second subset of memory access commands from a second queue at the memory controller to a fourth queue at the memory controller according to a second processing program, in parallel with transferring the first subset of memory access commands from the first queue to the third queue, wherein processing the first subset of memory access commands and processing the second subset of memory access commands are configured to be performed in parallel by the execution unit according to the number of memory access commands in the command queues sorted according to a priority between a first priority and a second priority.

12. The memory device of claim 11, wherein the memory controller further includes arbitration logic configured to determine the order in which the memory access commands of the third queue and the fourth queue are processed, based at least in part on a corresponding first priority and a second priority of the third queue and the fourth queue.

13. The memory device of claim 12, wherein the memory controller is configured to move the data associated with the memory access commands of the third and fourth queues based at least in part on the order in which the memory access commands of the third and fourth queues are processed.

14. The memory device of claim 11, wherein the processor further comprises: Fifth queue; and Sixth queue, in: The first subset of memory access commands is associated with read commands of the first priority. The second subset of memory access commands is associated with read commands of the second priority. The fifth queue is configured to store a third subset of memory access commands associated with write commands of the first priority; and The sixth queue is configured to store a fourth subset of memory access commands associated with write commands of the second priority.

15. The memory device of claim 14, wherein: The one or more command routers are further configured to determine a third subset and a fourth subset of the memory access commands and store the third subset and the fourth subset in the fifth queue and the sixth queue, respectively; and The processor is further configured to process a third subset of memory access commands from the fifth queue to the third queue according to a third processing program and to process a fourth subset of memory access commands from the sixth queue to the fourth queue according to a fourth processing program, wherein the third and fourth processing programs are configured to run in parallel with the first and second processing programs by means of the execution unit based on the number of memory access commands in the command queues sorted according to the priority between the first and second priorities.

16. The memory device of claim 11, wherein the processor further comprises: The logic is configured to process the memory access command when the memory access command associated with the second priority has not yet been processed within the minimum time frame.

17. A memory device comprising: Storage memory, which includes multiple memory cells; and A processor coupled to the storage memory and operable to cause the memory device to perform the following operations: Receive memory access commands from the host at the interface; The memory access commands are stored in a command queue; Determine a first subset of memory access commands associated with the first priority and a second subset of memory access commands associated with the second priority; The first subset of memory access commands associated with the first priority is routed from the command queue to the first queue; The second subset of memory access commands associated with the second priority is routed from the command queue to the second queue; The data associated with the memory access command is stored in a buffer coupled to the interface; According to the first processing procedure, the first subset of memory access commands is transferred from the first queue at the memory controller to the third queue at the memory controller, the third queue being associated with the first priority; In parallel with transferring the first subset of memory access commands from the first queue to the third queue, a second subset of memory access commands is transferred from the second queue at the memory controller to a fourth queue at the memory controller according to a second processing procedure, the fourth queue being associated with a second priority, wherein the first subset of memory access commands and the second subset of memory access commands are processed in parallel by the execution unit of the processor according to the number of memory access commands in the command queues sorted by priority between the first priority and the second priority; and The data associated with the memory access command is moved between the buffer and the storage memory via the storage controller.

18. The memory device of claim 17, wherein the processor is further operable to cause the memory device to perform the following operations: The storage controller determines the order in which the memory access commands of the third and fourth queues are processed, based at least in part on the corresponding first and second priorities of the third and fourth queues.

19. The memory device of claim 18, wherein the movement of the data between the buffer and the storage memory by the memory controller is based at least in part on the order in which the memory access commands of the third queue and the fourth queue are processed.

20. The memory device of claim 17, wherein the first subset of memory access commands is associated with read commands of the first priority, and the second subset of memory access commands is associated with read commands of the second priority, and The processor is further operable to cause the memory device to perform the following operations: Determine a third subset of memory access commands associated with write commands of the first priority and a fourth subset of memory access commands associated with write commands of the second priority; The third subset of memory access commands associated with the first priority is routed from the command queue to the fifth queue; The fourth subset of memory access commands associated with the second priority is routed from the command queue to the sixth queue; The processor processes the third subset of memory access commands from the fifth queue to the third queue at the memory controller according to the third processing program; and The processor processes a fourth subset of memory access commands from the sixth queue to the fourth queue at the memory controller according to a fourth processing program, wherein the execution unit runs the third and fourth processing programs in parallel with the first and second processing programs according to the number of memory access commands in the command queues sorted according to the priority between the first and second priorities.

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