Memory device and operating method using single pulse smart verify

Abstract

A memory device and method of operation are provided. The device includes a block of memory cells, each memory cell connected to one of a plurality of word lines and arranged in a string, and configured to hold a threshold voltage. A control circuit is coupled to the word lines and the string, determines a program low tail voltage of a distribution of the threshold voltage after a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program low tail voltage, and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells has a desired program low tail voltage without further program pulses.

Description

TECHNICAL FIELD

[0001] This application relates to non-volatile memory devices and operations of non-volatile memory devices. BACKGROUND

[0002] This section provides background information which is not necessarily prior art related to the present disclosure.

[0003] Semiconductor memory is used in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.

[0004] Some non-volatile memory utilizes a floating gate positioned above a semiconductor substrate and insulated from a channel region in the semiconductor substrate. The floating gate is positioned between a source region and a drain region. A control gate is disposed above the floating gate and insulated therefrom. The threshold voltage of the transistor is controlled by a cyclic condition charge amount held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate to allow conduction between its source and drain before the transistor turns on is controlled by the charge level on the floating gate.

[0005] Some non-volatile memory utilizes a charge-trapping layer to store information. One such example has an oxide-nitride-oxide (ONO) region, where the nitride (e.g., SiN) acts as a charge-trapping layer to store information. When the memory cell is programmed, an electron is stored in the charge-trapping layer.

[0006] Non-volatile memory can have a 2D architecture or a 3D architecture. Ultra-high density memory devices have been adopted that use 3D stacked memory structures with strings of memory cells. One such memory device is sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductor and insulator layers. The conductor layers can act as word lines. Memory holes are drilled in the layers to simultaneously define many memory layers. NAND strings are then formed by filling the memory holes with appropriate material. Straight NAND strings extend in one memory hole, while tubular or U-shaped NAND strings (P-BiCS) include a pair of vertical columns of memory cells that extend in two memory holes and are joined by a pipe connection. The pipe connection can be made of undoped polysilicon. A back gate can surround the pipe connection to control conduction of the pipe connection. Control gates of the memory cells are provided by the conductor layers.

[0007] Prior to programming a particular non-volatile memory device, such as a NAND flash memory device, the memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gates. For other devices, the erase operation removes electrons from the charge-trapping layers. After erasing, it is necessary to determine a program voltage to be used to program the memory cells in a program operation. As the memory cells are repeatedly programmed and erased, it can be necessary to adjust the program voltage used accordingly. SUMMARY

[0008] This section provides a general summary of the disclosure, and not a comprehensive disclosure of its full scope or all of its features and advantages.

[0009] A goal of the present disclosure is to provide a memory device and a method of operating a memory device that addresses and overcomes the above-mentioned shortcomings.

[0010] Accordingly, one aspect of the present disclosure provides a device including a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines. The memory cells are also arranged in a string and configured to hold a threshold voltage within a common range of threshold voltages defining a threshold window. A control circuit is coupled to the plurality of word lines and the string. The control circuit is configured to determine a program low tail voltage of a distribution of threshold voltages of the memory cells after a first program pulse of a program operation having a first program voltage. The program low tail voltage corresponds to a cycling condition of the memory cells. The control circuit calculates a second program voltage for a second program pulse of the program operation based on the program low tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of threshold voltages of the memory cells has a desired program low tail voltage without further program pulses.

[0011] According to another aspect of the present disclosure, a controller is in communication with a memory device including a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines. The memory cells are arranged in a string and configured to hold a threshold voltage within a common range of threshold voltages defining a threshold window. The controller is configured to determine a program low tail voltage of a distribution of threshold voltages of the memory cells after a first program pulse of a program operation having a first program voltage. The program low tail voltage corresponds to a cycling condition of the memory cells. The controller then calculates a second program voltage for a second program pulse of the program operation based on the program low tail voltage. The controller instructs the memory device to apply the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of threshold voltages of the memory cells has a desired program low tail voltage without further program pulses.

[0012] According to additional aspects of the present disclosure, a method of operating a memory device is provided. The memory device includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines. The memory cells are arranged in strings and are configured to hold threshold voltages within a common range of threshold voltages defining a threshold window. The method includes the step of determining a program low tail voltage of a distribution of threshold voltages of the memory cells after a first program pulse of a program operation having a first program voltage, the program low tail voltage corresponding to a cycling condition of the memory cells. The method continues with the steps of calculating a second program voltage for a second program pulse of the program operation based on the program low tail voltage, and applying to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of threshold voltages of the memory cells have a desired program low tail voltage without further program pulses.

[0013] Other suitable ranges will become apparent from the description provided herein. The description and specific examples in this summary are intended only to illustrate and not to limit the scope of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0014] The drawings described herein are for purposes of illustration only and are not intended to limit the scope of the present disclosure.

[0015] Figure 1A is a top view of a NAND string according to aspects of the present disclosure;

[0016] Figure 1B is an equivalent circuit diagram of Figure 1A the NAND string of

[0017] Figure 2 is a cross-sectional view of the NAND string of Figure 1A according to aspects of the present disclosure;

[0018] Figure 3 depicts three example NAND strings shown in Figures 1A-2 according to aspects of the present disclosure;

[0019] Figure 4 is a block diagram of an array 400 of NAND flash memory cells including Figure 3 BLKO and additional blocks BLK1 and BLK2 according to aspects of the present disclosure;

[0020] Figure 5A is a block diagram depicting one embodiment of a sense block according to aspects of the present disclosure;

[0021] Figure 5B is a block diagram of a sense block according to aspects of the present disclosure including Figure 4Block diagram of a non-volatile memory system of an array 400;

[0022] Figure 6 Flowchart describing one embodiment of a method for programming a non-volatile memory in accordance with aspects of the present disclosure;

[0023] Figure 7 Illustrating a binary memory with a population of cells where each cell is in one of two possible states in accordance with aspects of the present disclosure;

[0024] Figure 8 Demonstrating a distribution of memory cells after application of different first program voltages in accordance with aspects of the present disclosure;

[0025] Figure 9 Demonstrating a cumulative distribution function of conductive memory cells after a first program pulse and then after a second program pulse in accordance with aspects of the present disclosure;

[0026] Figure 10 Demonstrating test data of a memory device showing that one or two verify operations can encompass all variations due to word line location, temperature, and cycling in accordance with aspects of the present disclosure;

[0027] Figure 11 Demonstrating a program operation including a first program pulse and a first verify operation and a second verify operation in accordance with aspects of the present disclosure;

[0028] Figures 12A-12C Illustrating an example cumulative distribution function voltage curve of an example memory cell during a single pulse verify in accordance with aspects of the present disclosure;

[0029] Figure 13 Table illustrating a comparison between a single pulse smart verify, a zero pulse smart verify, and a smart verify operation in accordance with aspects of the present disclosure;

[0030] Figure 14A Illustrating steps of an exemplary method of measuring a program slope of a memory cell in accordance with aspects of the present disclosure;

[0031] Figure 14B Demonstrating that a program slope does not vary with cycling or starting program voltage in accordance with aspects of the present disclosure;

[0032] Figure 15 Demonstrating a low tail position comparison between a first program voltage of a first program pulse and a second program voltage of a second program pulse using the same first program voltage value in accordance with aspects of the present disclosure; and

[0033] Figures 16-19 Illustrating steps of a method of operating a memory device in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0034] In the following description, details are set forth to provide an understanding of the disclosure. In some examples, descriptions of certain circuits, structures, and techniques are omitted in order to not obscure the disclosure.

[0035] In general, the disclosure relates to non-volatile memory devices of the type that are well suited for use in many applications. Non-volatile memory devices and associated methods of operation will be described in connection with one or more example embodiments. However, the particular example embodiments disclosed are merely for sufficient clarity and are not intended to limit the disclosure. Specifically, example embodiments are provided for the sufficient clarity and to convey the principles of the disclosure to enable one of ordinary skill in the art to understand and practice the disclosure. In particular, example embodiments are provided to enable the disclosure to be full and complete and to convey the scope of the disclosure to the skilled person. Numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. Those skilled in the art will understand that the example embodiments can be practiced without the specific details, and that example embodiments can be implemented in many different forms. The particular example embodiments are not to be interpreted as limiting the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

[0036] In some memory devices or apparatuses, memory cells are joined to one another, for example, in NAND strings in blocks or sub-blocks. Each NAND string includes a number of memory cells connected in series between one or more drain-side SG transistors (SGD transistors) on a drain side of the NAND string connected to a bit line, and one or more source-side SG transistors (SGS transistors) on a source side of the NAND string connected to a source line. In addition, the memory cells can be arranged with a common control gate line (e.g., a word line) that acts as a control gate. A set of word lines extends from the source side of a block to the drain side of the block. Memory cells can be connected in other types of strings, and can also be connected in other ways.

[0037] In 3D memory structures, memory cells can be arranged in stacked vertical strings, where the stack includes alternating conductive layers and dielectric layers. The conductive layers act as word lines connected to the memory cells. The memory cells can include data memory cells that are eligible to store user data and dummy or non-data memory cells that are not eligible to store user data.

[0038] Prior to programming a particular non-volatile memory device, the memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gates of the memory cells being erased. Alternatively, the erase operation removes electrons from the charge-trapping layers.

[0039] During a program operation, memory cells are programmed according to a word line programming order. For example, programming can start from the source side word lines of a block and proceed to the drain side word lines of the block. In one approach, programming of each word line is completed before programming of the next word line. For example, a first word line WL0 is programmed using one or more program pulses until programming is complete. Next, a second word line WL1 is programmed using one or more program pulses until programming is complete, and so on. A program pulse can include a set of increasing program voltages applied to a word line in a respective program loop or program-verify iteration. A verify operation or pass can be performed after each program voltage to determine whether a memory cell has completed programming. When programming of a memory cell is complete, the memory cell can be locked from further programming while programming of other memory cells continues in subsequent program loops.

[0040] Each memory cell can be associated with a data state according to write data in a program command. Based on its data state, a memory cell will remain in an erased state or be programmed to a program data state. For example, in a one bit-per-cell memory device, there are two data states, including an erased state and a program state (see Figure 7 ).

[0041] After programming of memory cells, data can be read back in a read operation. A read operation can involve applying a series of read voltages to a word line while sensing circuitry determines whether a cell connected to the word line is in a conductive state or a non-conductive state. If the cell is in a non-conductive state, the threshold voltage Vt or Vth of the memory cell is beyond the read voltage. The read voltage is set to a level expected to be between threshold voltage levels of adjacent data states.

[0042] As a program voltage is applied to a word line associated with a memory cell programmed during a program operation, it is necessary to determine the program voltage VPGM (voltage applied to the respective word line) to be used to program the memory cell in the program operation. As memory cells cycle (i.e., are repeatedly programmed and erased), it can be necessary to adjust the program voltage utilized. One approach to determining the program voltage is to utilize 2 or 3 pulses of the program voltage and then read or verify the threshold voltage of selected memory cells (this approach can be referred to as "smart verify"). Nonetheless, applying two, three, or more pulses to determine the correct program voltage can significantly impact the speed of the program operation.

[0043] The technology disclosed herein can be applied to 3D NAND, but is not necessarily limited thereto. A NAND flash memory structure can have a plurality of transistors arranged in series between two select gates. The series of transistors and select gates are referred to as a NAND string. Figure 1A is a top view showing one NAND string.Figure 1B is its equivalent circuit. Figure 1A and 1B The NAND string depicted in FIG. 1 includes four transistors 100, 102, 104, and 106 connected in series and sandwiched between a first select gate 120 and a second select gate 122. The select gate 120 connects the NAND string to a bit line 126. The select gate 122 connects the NAND string to a source line 128. The select gate 120 is controlled by applying an appropriate voltage to a control gate 120CG. The select gate 122 is controlled by applying an appropriate voltage to a control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to a word line WL3, the control gate 102CG is connected to a word line WL2, the control gate 104CG is connected to a word line WL1, and the control gate 106CG is connected to a word line WLO. In one embodiment, the transistors 100, 102, 104, and 106 are each a memory cell. In other embodiments, a memory cell can include multiple transistors or can be different than depicted. The select gate 120 is connected to a select line SGD. The select gate 122 is connected to a select line SGS.

[0044] Figure 2 A cross-sectional view of one embodiment of the NAND string described above is provided. Figure 2This refers to 2D NAND strings formed in a substrate. The transistors of the NAND string are formed in a p-well region 140. The p-well region can be located within an n-well region 142 of a p-type substrate 144. Each transistor comprises a stacked gate structure consisting of a control gate (100CG, 102CG, 104CG, and 106CG) and a floating gate (100FG, 102FG, 104FG, and 106FG). The floating gate is formed on the surface of the p-well on top of an oxide or other dielectric film. The control gate is above the floating gate, where an inter-polysilicon dielectric layer separates the control gate and the floating gate. The control gates of memory cells (100, 102, 104, and 106) form word lines. N+ doped layers 130, 132, 134, 136, and 138 are shared between adjacent cells, thereby connecting the cells in series to form a NAND string. These N+ doped layers form the source and drain of each of the cells. For example, N+ doped layer 130 acts as the drain of transistor 122 and the source of transistor 106, N+ doped layer 132 acts as the drain of transistor 106 and the source of transistor 104, N+ doped layer 134 acts as the drain of transistor 104 and the source of transistor 102, N+ doped layer 136 acts as the drain of transistor 102 and the source of transistor 100, and N+ doped layer 138 acts as the drain of transistor 100 and the source of transistor 120. N+ doped layer 126 is connected to the bit line of the NAND string, while N+ doped layer 128 is connected to the common source line of multiple NAND strings.

[0045] It should be noted that, although Figures 1A-2 The illustration shows four memory cells in a NAND string, but the use of four transistors is provided only as an example. NAND strings used with the techniques described herein may have fewer than four memory cells or more than four memory cells. For example, some NAND strings will contain 8, 16, 32, 64 or more memory cells.

[0046] Each memory cell can store data represented in analog or digital form. When storing one bit of digital data, the range of possible threshold voltages for the memory cell is divided into two ranges, which are assigned logic data "1" and "0" (see, for example, see below). Figure 7 In one example of NAND flash memory, the voltage threshold is negative after erasing the memory cell and is defined as logic "1". The threshold voltage is positive after a programming operation and is defined as logic "0". When the threshold voltage is negative and a read operation is attempted by applying 0V to the control gate, the memory cell is turned on to indicate that a positive logic 1 is stored. When the threshold voltage is positive and a read operation is attempted by applying 0V to the control gate, the memory cell is not turned on, indicating that a logic 0 is stored.

[0047] Other types of non-volatile memory, in addition to NAND flash memory, can also be used with the present technology.

[0048] Another type of memory cell available in flash EEPROM systems utilizes non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between and insulates a conductive control gate and a memory cell channel above a semiconductor substrate. Programming is effected by the injection of electrons from the cell channel into the nitride, where they are trapped and stored within a limited region. This stored charge then changes the threshold voltage of a portion of the cell channel in a detectable manner. Erasing is effected by the injection of hot holes into the nitride. Similar cells can be provided in a split-gate configuration, where a doped polysilicon gate extends over part of the memory cell channel to form a separate select transistor.

[0049] In another approach, two bits are stored in each NROM cell, with the ONO dielectric extending across the channel between the source and drain diffusions. The charge for one data bit is located in the dielectric adjacent to the drain, and the charge for the other data bit is located in the dielectric adjacent to the source. Multi-state data storage is implemented by separately reading the binary states of the spatially-separated charge storage regions within the dielectric.

[0050] Figure 3 Three example NAND strings are depicted in block BLKO shown, for example Figures 1A-2 Three example NAND strings are depicted in block BLKO shown, for example

[0051] Example NAND string NSO includes storage elements 301,..., 302-306,..., 307 and corresponding control gates CG63,... CG32-CG28,... CGO, SGS transistor 308 has control gate CGsgs and SGD transistor 300 has control gate CGsgd. Another example NAND string NSl includes storage elements 311,..., 312-316,..., 317, SGS transistor 318 and SGD transistor 310. Another example NAND string NS2 includes storage elements 321,..., 322-326,..., 327, SGS transistor 328 and SGD transistor 320. NAND strings NSO, NS2,... are even numbered and NAND strings NSl, NS3 (not shown),... are odd numbered. Similarly, bit lines BL0, BL2,... are even numbered and NAND strings BLl, BL3 (not shown),... are odd numbered. The storage elements can store user data and / or non-user data.

[0052] Figure 4 is an array 400 of NAND flash memory cells including Figure 3 BLKO and additional blocks BLKl and BLK2. Along each column, a bit line (BL) is coupled to the drain terminal of the drain select gate of a NAND string. Along each row of NAND strings, a source line (SL) can connect all source terminals of the source select gates of the NAND strings (e.g., at SEO of NSO).

[0053] The array of storage elements is divided into a number of blocks of storage elements (e.g., BLKO-BLK2), where each block includes a set of one or more NAND strings in communication with a common set of word lines, SGS lines, and SGD lines. Each NAND string is also in communication with a corresponding bit line. For example, BLKO includes NAND strings NSO, NSl,..., NSn-l in communication with BL0, BLl,... BLn-l, respectively, and WL0-WL63 SGS and SGD. BLKl includes NAND strings NSaO, NSal,..., NSan-l in communication with BL0, BLl,... BLn-l, respectively, and WL0a-WL63a, SGSa and SGDa. BLK2 includes NAND strings NSbO, NSbl,..., NSbn-l in communication with BL0, BLl,... BLn-l, respectively, and WL0b-WL63b, SGSb and SGDb.

[0054] As is common with flash EEPROM systems, blocks are the erase unit. That is, each block contains the smallest number of storage elements that are erased together. Each block is typically divided into pages. Pages are the minimum programming unit. One or more pages of data are typically stored in a row of storage elements. For example, a row typically contains a number of interleaved pages, or it can constitute a page. All storage elements of a page are read or programmed together. In addition, a page can store user data from one or more sectors. Sectors are logical concepts used by the host as a convenient unit of user data; they typically contain no extra overhead data, which is confined to the controller. The extra overhead data can include an error correction code (ECC) that has been calculated from the user data of a sector. Part of the controller (described below) calculates the ECC when data is being programmed into the array, and also checks the ECC when data is being read from the array. Alternatively, the ECC and / or other extra overhead data is stored in a different page, or even a different block, than the user data to which it pertains.

[0055] Sectors of user data are typically 512 bytes, corresponding to the size of sectors in disk drives. Extra overhead data is typically an additional 16-20 bytes. A number of pages form a block, any number of pages from 8 pages, for example, up to 32, 64, or more pages. In some embodiments, a row of NAND strings comprises a block.

[0056] In one embodiment, a memory cell is erased by raising the p-well to an erase voltage (e.g., 15-20V) for a sufficient period of time and grounding or applying a low bias (e.g., 1V) on the word line of the selected block while the source and bit line are floating. Due to capacitive cross-coupling ("cross" denotes coupling from adjacent storage elements), the bit line, select line, and common source are also raised to a significant fraction of the erase voltage. Thus, a strong electric field is applied to the tunnel oxide layer of the selected memory cell, and as electrons are emitted from the floating gate to the substrate side, the data of the selected memory cell is erased. As electrons pass from the floating gate to the p-well region, the threshold voltage of the selected cell is lowered. Erasing can be performed on the entire memory array, individual blocks, or another unit of cells. In one embodiment, 3D NAND is erased using a different technique. 3D NAND will be discussed further below.

[0057] Figure 5A is a block diagram depicting one embodiment of a sense block 500. Individual sense blocks 500 are partitioned into a core portion, referred to as a sense module 580, and a common portion 590. In one embodiment, there is a separate sense module 580 per bit line and one common portion 590 of a group of multiple sense modules 580. In one example, a sense block 500 will contain one common portion 590 and eight sense modules 580. Each of the sense modules in a group will communicate with the associated common portion via a data bus 572.

[0058] The sense module 580 includes sense circuitry 571 that determines whether the conducted current in the connected bit line is above or below a predetermined threshold level. The sense module 580 also includes a bit line latch 582 that is used to set the voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 582 will result in the connected bit line being pulled to a state that specifies program inhibit (e.g., 1.5-3V). As an example, flag = 0 can inhibit programming, while flag = 1 does not inhibit programming.

[0059] The common portion 590 includes a processor 592, three sets of example data latches 594, and an I / O interface 598 coupled between the sets of data latches 594 and the data bus 521. One set of data latches can be provided for each sense module, and three data latches identified by DLl, DL2, and DL3 can be provided for each set. The use of the data latches is discussed further below.

[0060] The processor 592 performs computations. For example, one of its functions is to determine the data stored in the sensed storage elements and store the determined data in the sets of data latches. At least some of the data latches in a set of data latches (e.g., 594) are used to store data bits determined by the processor 592 during a read operation. At least some of the data latches in a set of data latches are also used to store data bits imported from the data bus 521 during a program operation. The imported data bits represent write data intended to be programmed into the memory. The I / O interface 598 provides the interface between the data latches 594-697 and the data bus 521.

[0061] In one embodiment, at the start of a program operation, data is stored in the DLl and DL2 latches. For example, lower page data can be stored in DLl and upper page data can be stored in DL2. In one embodiment, lower page data read from a memory cell during an IDL is stored in the DLl latch. DL3 can be used to store a verify status, such as a lock status during programming. For example, when the Vt of a memory cell has been verified to reach its target level, the DL3 latch can be set to indicate this condition so that further programming of the memory cell can be inhibited. Note that this describes programming two bits per memory cell. In one embodiment, during a read operation, the DLl and DL2 latches are used to store two bits read from a memory cell. Note that there can be more than two bits per memory cell. There can be one additional latch for each additional bit to be stored per memory cell.

[0062] During a read or other sense, state machine 512 controls the supply of different control gate voltages to the addressed storage elements. As stepped through the various control gate voltages corresponding to the various memory states supported by the memory, sense module 580 can trip at one of these voltages and provide an output from sense module 580 to processor 592 via bus 572. At this point, processor 592 determines the resulting memory state by considering the trip event of the sense module and the information about the control gate voltage being applied from the state machine via input line 593. It then calculates the binary encoding of the memory state and stores the resulting data bits into a data latch (e.g., 594). In another embodiment of the core portion, bit line latches 582 serve as both latches for latching the output of sense module 580 and bit line latches as described above.

[0063] Some embodiments can include multiple processors 592. In one embodiment, each processor 592 will include an output line (not depicted) so that each of the output lines are wired-OR'd together. In some embodiments, the output lines are inverted before being connected to the wired-OR line. This configuration enables a quick determination of when the programming process is complete during a program verify process, as the state machine receiving the wired-OR can determine when all of the bits being programmed have reached the desired level. For example, when each bit has reached its desired level, the logical zero for that bit will be sent to the wired-OR line (or data 1 is inverted). When all of the bit outputs data 0 (or data 1 is inverted), the state machine knows to terminate the programming process. Because each processor is in communication with eight sense modules, the state machine needs to read the wired-OR line eight times, or add logic to the processor 592 to accumulate the results of the associated bit lines so that the state machine only needs to read the wired-OR line once. Similarly, by picking the logic levels correctly, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0064] During programming or verify, the data to be programmed is stored from data bus 521 into the set of data latches 594-597 under the control of the state machine. The programming operation includes a series of programming voltage pulses applied to the control gate of the addressed storage elements under the control of the state machine. Each programming pulse is followed by a read back (verify) to determine if the storage element has programmed to the desired memory state. Processor 592 monitors the read back memory state relative to the desired memory state. When they are in agreement, processor 592 sets bit line latch 582 to cause the bit line to be pulled to a state that specifies program inhibit. This inhibits further programming of the storage elements coupled to the bit line even if a programming pulse appears on its control gate. In other embodiments, the processor initially loads bit line latch 582 and the sense circuitry sets it to the inhibit value during the verify process.

[0065] In one embodiment, each set of data latch stacks 594-597 contains data latch stacks corresponding to a sense module 580. In one embodiment, there are three data latches per sense module 580. All of the DLl and DL2 data latches corresponding to a read / write block of storage elements can be connected together to form a block shift register so that a block of data can be input or output by serial transfer.

[0066] In one embodiment, one purpose of the DLl and DL2 latches is to store data to be programmed into the storage elements. For example, the storage elements can store two bits per storage element. In one embodiment, the lower page data is initially stored into the DLl latches and the upper page data is initially stored into the DL2 latches.

[0067] In one embodiment, the storage elements store three bits per storage element. In this case, there can be an additional data latch (not depicted in Figure 5A In one embodiment, the storage elements store four bits per storage element, in which case there can be two additional data latches (not depicted in Figure 5A In one embodiment, the storage elements store four bits per storage element, in which case there can be two additional data latches (not depicted in

[0068] Additional information regarding read operations and sense amplifiers can be found in: (1) U.S. Patent No. 7,196,931, "Non-Volatile Memory and Method with Reduced Source Line Bias Errors"; (2) U.S. Patent No. 7,023,736, "Non-Volatile Memory and Method with Improved Sensing"; (3) U.S. Patent No. 7,046,568, "Memory Sensing Circuit and Method for Low Voltage Operation"; (4) U.S. Patent No. 7,196,928, "Compensating for Coupling during Read Operations of Non-Volatile Memory"; and (5) U.S. Patent No. 7,327,619, "Reference Sense Amplifier for Non-Volatile Memory". All five of the above-listed patent documents are incorporated herein in their entirety.

[0069] Figure 5B is an array 400 of a non-volatile memory system including Figure 4 A block diagram of a non-volatile memory system of an array 400 including

[0070] According to one embodiment of the technology, a non-volatile memory system includes a memory device 596 having read / write circuits for reading and programming pages of memory cells in parallel. The memory device 596 can include one or more memory dies 598. The memory dies 598 include a two-dimensional array of memory cells 400, control circuitry 510, and read / write circuits 565. The memory array 400 can be addressed by word lines via a row decoder 530 and by bit lines via a column decoder 560. The read / write circuits 565 include a plurality of sense blocks 500 and allow pages of memory cells to be read or programmed in parallel. Typically, a controller 550 is included in the same memory device 596 (e.g., removable memory card) as the one or more memory dies 598. Commands and data are transferred between the host 570 and the controller 550 via lines 520 and between the controller and the one or more memory dies 598 via lines 518.

[0071] The control circuitry 510 cooperates with the read / write circuits 565 to perform memory operations on the memory array 400. The control circuitry 510 includes a state machine 512, memory 513, an on-chip address decoder 514, registers 515, and a power control module 516. The state machine 512 provides chip-level control of memory operations. The memory 513 can store raw write data, modified write data, and status bits for use by the state machine 512. The on-chip address decoder 514 provides an address interface between the hardware address used by the decoders 530 and 560 and the software address used by the host or memory controller. The registers 515 can be used to record the voltages used when programming or erasing the memory device 596. The power control module 516 controls the power and voltages supplied to the word lines and bit lines during memory operations. In another approach, a dual row / column decoder and read / write circuits are used. For example, the control circuitry can be considered to include one or more of components 510, 512, 513, 514, 515, 516, 530, 550, 560, 565.

[0072] Figure 6 is a flowchart describing one embodiment of a method for programming non-volatile memory. At step 640, memory cells to be programmed are erased. Step 640 can include erasing more memory cells (e.g., in blocks or other units) than those to be programmed. At step 642, soft programming is performed to narrow the distribution of erase threshold voltages of the erased memory cells. As a result of the erase process, some memory cells can be in a deeper erase state than necessary. Soft programming can apply small programming pulses to move the threshold voltages of the erased memory cells closer to the erase verify level. In Figure 6At step 650, a "data load" command is issued by the controller 550 and input to the command circuitry, allowing data to be input to the data input / output buffer. At step 652, address data specifying the page address is input from the controller or host to the row controller or decoder 514. The input data is recognized as a page address and latched via the state machine 512, affected by the address latch signal input to the command circuitry. At step 654, the program data page for the addressed page is input to the data input / output buffer for programming. For example, in one embodiment, 512 bytes of data can be input. The data is latched in the appropriate register for the selected bit line. In some embodiments, the data is also latched in a second register for the selected bit line for a verify operation. At step 656, a "program" command is issued by the controller and input to the data input / output buffer. The command is latched by the state machine 512 via the command latch signal input to the command circuitry.

[0073] The data latched in step 654 will be programmed into the selected memory cells controlled by the state machine 512 using stepped pulses applied to the appropriate word line, triggered by the "program" command. At step 658, the program pulse voltage level Vpgm or VPGM applied to the selected sub-line is initialized to a starting pulse (e.g., 12V) and a program counter PC maintained by the state machine 512 is initialized at 0. At step 660, a first Vpgm pulse is applied to the selected sub-line. If a logic "0" is stored in a particular data latch, indicating that the corresponding memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if a logic "1" is stored in the particular latch, indicating that the corresponding memory cell should remain in its current data state, then the corresponding bit line is connected to VDD to inhibit programming.

[0074] At step 662, the state of the selected memory cells is verified. If the target threshold voltage of the selected cells is detected to have reached the appropriate level, then the data stored in the corresponding data latches is changed to a logic "1". If the threshold voltage is detected to have not reached the appropriate level, then the data stored in the corresponding data latches is not changed. In this way, bit lines with a logic "1" stored in their corresponding data latches do not need to be programmed. When all data latches are storing a logic "1", the state machine knows that all selected cells have been programmed. At step 664, it is checked whether all data latches are storing a logic "1". If so, the programming process is complete and successful, as all selected memory cells are programmed and verified to their target state. A status "PASS" is reported at step 666.

[0075] If it is determined at step 664 that not all of the data latches are storing a logical "1", the programming process continues. At step 668, the program counter PC is checked against a program limit value. One example of a program limit value is 20, however, other values can be used in various implementations. If the program counter PC is not less than 20, it is determined at step 669 whether the number of bits that have not been successfully programmed is equal to or less than a predetermined number. If the number of bits that have not been successfully programmed is equal to or less than the predetermined number, the programming process is flagged as passed at step 671 and a pass status is reported. The bits that have not been successfully programmed can be corrected using error correction during a read process. However, if the number of bits that have not been successfully programmed is greater than the predetermined number, the programming process is flagged as failed and a fail status is reported at step 670. If the program counter PC is less than 20, the Vpgm level is increased by a step size and the program counter PC is incremented at step 672. After step 672, the process loops back to step 760 to apply the next Vpgm pulse.

[0076] Figure 6 The flowchart depicts a single pass programming method that can be applied to binary storage. For example, in a two pass programming method that can be applied to multi-level storage, multiple program or verify steps can be used in a single iteration of the flowchart. Steps 658-672 can be performed for each pass of the program operation. In a first pass, one or more program pulses can be applied and their results verified to determine if the cells are in the appropriate intermediate state. In a second pass, one or more program pulses can be applied and their results verified to determine if the cells are in the appropriate final state.

[0077] At the end of a successful program process or operation, the threshold voltage of the memory cell should be within one or more threshold voltage distributions of the programmed memory cell or within the threshold voltage distribution of the erased memory cell.

[0078] Figure 7 A binary memory with a group of cells is shown, where each cell is in one of two possible states. The threshold window of each memory cell is divided by a single split level into two distinct regions. As shown in Figure 7 (a), during a read, a read split level rVl between the lower and upper regions is used to determine in which region the threshold level of the cell is located. If the threshold of the cell is in the lower region, the cell is in the "erased" state and if the threshold of the cell is in the upper region, the cell is in the "programmed" state. Figure 7 (b) shows that all of the cells of the memory are initially in the "erased" state. Figure 7(c) show some cells programmed to a "programmed" state. A one-bit or binary code is used to decode the memory state. For example, a bit value of "1" indicates the "erased" state and "0" indicates the "programmed" state. Typically, programming is performed by applying one or more programming voltage pulses. After each pulse, the cells are sensed to check if the verify threshold has moved beyond a verify boundary level, vVl. Memory with this memory cell partitioning is referred to as "binary" memory or single-level cell ("SLC") memory. It will be seen that binary or SLC memory operates with a wide error margin, as the entire threshold window is occupied by only two regions.

[0079] Simultaneous Multi-Threshold (SMT) sensing can also be employed. During SMT sensing, two or more different bias conditions can be used to sense two different threshold voltages simultaneously. For example, a single verify reference voltage can be applied to the selected sub-line, while one bias condition is used for memory cells that are verifying to a first state and a second bias condition is used for memory cells that are verifying to a second state. One example of different bias conditions is sensing the conduction current of the bit line for different lengths of time. Herein, this sensing time is referred to as "FSENSE". Using two (or more) different FSENSE allows different threshold voltages to be sensed while applying the same verify reference voltage to the selected sub-line. Thus, this can be referred to as "simultaneous multi-threshold" sensing.

[0080] Using SMT sensing saves time during program verify. However, when the memory cells are later read, the bias condition used for each memory cell being read is not known. Thus, all memory cells can be read using the same bias condition. For example, all memory cells can be read using a nominal (e.g., short) FSENSE. Thus, memory cells that were verified using a longer FSENSE will be read using a different FSENSE than was used during verify.

[0081] It should be noted that memory cells can react differently to being read using a bias condition that is different than the bias condition used during verify. For example, they can exhibit different threshold voltage shifts. Ideally, all memory cells would experience the same threshold voltage shift as a result of the different bias condition (e.g., sensing time). However, this can not be the case. This can result in a variation in the threshold voltage shift for memory cells read with a different bias condition than was used for verify.

[0082] As previously discussed, while it is possible to use at least two or three program pulses to determine the correct program voltage (VPGM) level, this solution can not be ideal. In particular, using multiple program pulses to determine the program voltage that should be used can cause the program operation to be slower than if multiple program pulses were not needed. Further, if frequent block jumps are needed, reacquiring the program voltage level also slows the associated program operation.

[0083] Accordingly, described herein is a memory device (e.g., Figure 5B ) that includes a block (e.g., Figure 3 ) of storage elements or memory cells (e.g., Figure 3 ) 301,..., 302-306,..., 307) in Figure 3 ) WL0-WL63) of the memory device. The plurality of word lines can be grouped in word line zones (i.e., groups of word lines). The memory cells are arranged in strings (e.g., Figure 3 ) NS0, NS1,..., NSn-1) and each is configured to hold a threshold voltage Vt or Vth within a common threshold voltage range that defines a threshold window. According to an aspect, the memory cells included in the device are SLC. The device also includes a control circuit (e.g., Figure 5B ) components 510, 512, 513, 514, 515, 516, 530, 550, 560, 565) coupled to the plurality of word lines and the strings and implements a process referred to as "single pulse smart verify" (1PSV).

[0084] In operation, the control circuit can determine whether the at least one of the selected ones of the plurality of word lines associated with the memory cells is a first logical word line of a zone in a first string of the strings in response to determining that a block jump does not yet exist. The control circuit starts a program operation (described in greater detail below) in response to determining that a block jump does exist or determining that the at least one of the selected ones of the plurality of word lines associated with the memory cells is a first logical word line of the zone in the first string of the strings. During the program operation, the control circuit is configured to determine a program low tail voltage of a threshold voltage distribution of the memory cells after a first program pulse of the program operation with a first program voltage (e.g., VPGMSLC). As such, prior to determining the program low tail voltage, a first pulse program is applied to the word line zone of the memory cells in the first string Str0 (e.g., Figure 3 ) NS0) that need to be programmed using the first program voltage VPGMSLC.

[0085] A programmed low tail voltage or low tail Vt is a point near the lower end of the threshold voltage Vt distribution of programmed memory cells (e.g., close to Figure 7 The low tail voltage can be defined based on ignoring a particular number of peripheral Vts. For example, if about 31 memory cells have a Vt to the left of the low tail Vt, the low tail Vt can be defined based on any number other than 31. If counting is performed based on NAND strings, a particular number of NAND strings are ignored. As an example, a NAND string is checked to determine if the given NAND string has at least one memory cell with a Vt above the read reference voltage. Note that there can be about 75,000 NAND strings or more in a block. The low tail Vt can also be defined based on statistics. For example, if the Vt distribution is characterized by a mean and a standard deviation, the low tail Vt can be defined as a particular real number of standard deviations above the mean. Programming the low tail voltage corresponds to a cycling condition for the memory cells.

[0086] According to an aspect, the first program voltage VPGMSLC can be fine-tuned so that the NVT low tail position is 1.4 V (-28 DAC) lower than the desired programmed low tail position or voltage at the regular sense time FSENSE (FSENSE#2). Thus, the control circuit can be configured to select the first program voltage so that the programmed low tail voltage is a predetermined interval voltage lower (e.g., 1.4 volts) than the desired programmed low tail voltage. Figure 8 Distributions of memory cells are shown after applying different first program voltages VPGMSLC. The first program voltage can also be fine-tuned by a die of memory cells to ensure that the low tail is > 0 volts so that it can be detected. As shown in the example data, starting at 15.5 volts, the low tail can be visibly seen and calculated. It is thus recommended to use > 16.0 volts as the starting first pulse program voltage VPGM (VPGMSLC) for SLC. Nonetheless, other values of the first program voltage can be used instead.

[0087] The control circuit is also configured to calculate a second program voltage for a second program pulse of the program operation based on the programmed low tail voltage. The control circuit then applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cell to program the memory cell so that the distribution of threshold voltages of the memory cell has the desired programmed low tail voltage without further program pulses. Figure 9 A cumulative distribution function (CDF) of memory cells is shown conducted after the first program pulse and then after the second program pulse. As shown, the threshold voltages of the memory cells are shifted from the distribution of memory cells after the first program pulse to the desired programmed low tail voltage by approximately 1.4 volts.

[0088] According to one aspect, the control circuit applies at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current. The control circuit is configured to count at least one conduction number of memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse. The control circuit determines the program low tail voltage based on a comparison of the at least one conduction number of memory cells of the selected one of the strings that conducted current during the at least one verify operation to one of a plurality of conduction number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC). As such, one-pulse smart verify ensures that only one program pulse is needed to determine the program low tail location or voltage.

[0089] Figure 10 Test data for a memory device is shown that demonstrates that one or two verify operations can encompass all variations due to word line location, temperature, and cycling. In particular, the test data includes threshold voltage variations from various word lines (e.g., the upper left corner of Figure 10 ), threshold voltage variations for memory cells programmed at a particular voltage (e.g., 17.5 volts) (e.g., the upper right corner of Figure 10 ), conduction cell counts for three conduction number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, and BSPF_1PSV_3_SLC) for various levels of amounts (e.g., the lower left corner of Figure 10 ), and low tail voltages for two sense times (e.g., the lower right corner of Figure 10 ).

[0090] Referring to Figure 11 , the first program pulse is indicated as "Program Pulse" and the at least one verify operation includes a first verify operation and a second verify operation. The at least one conduction number includes a first conduction number associated with the first verify operation and a second conduction number associated with the second verify operation. The control circuit is further configured to apply a first verify pulse of a first verify voltage (Verify #1) to the at least one of the selected ones of the plurality of word lines associated with the memory cells in the first verify operation. The control circuit is also configured to sense whether a selected one of the strings conducts current while applying the first verify pulse after each of a plurality of sense times and count and save the first conduction number of memory cells of the selected one of the strings that conducted current during the first verify operation (indicated as "Scan" after Verify #1). According to one aspect, the plurality of sense times can include a first sense time FSENSE#2 and a second sense time FSENSE#1.

[0091] The control circuit determines in a recursive manner whether the first pass count of memory cells of a selected one of the strings conducting current during the first verify operation is less than one of the plurality of pass count thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC). As such, a verify pulse is applied to determine a low tail location (pass cell count) of memory cells using different sense FSENSE times (e.g., FSENSE#1 and FSENSE#2) and different bit scan pass fail (BSPF) criteria or the plurality of pass count thresholds. For remaining cases where a low tail is not discovered by the first verify, a second verify can be needed. Accordingly, the control circuit then adds one of a plurality of verify offset voltages (e.g., 0.5 volts or 0.55 volts) to the first verify voltage to determine a second verify voltage in response to the first pass count of memory cells of a selected one of the strings conducting current during the first verify operation being less than all of the plurality of pass count thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC). The control circuit is then configured to determine in a recursive manner whether the first pass count of memory cells of a selected one of the strings conducting current during the first verify operation is greater than one of the plurality of pass count thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC) in response to the first pass count of memory cells of a selected one of the strings conducting current during the first verify operation not being less than all of the plurality of pass count thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC). The control circuit subtracts the one of the plurality of verify offset voltages (e.g., 0.5 volts or 0.55 volts) from the first verify voltage to determine a second verify voltage in response to the first pass count of memory cells of a selected one of the strings conducting current during the first verify operation being greater than all of the plurality of pass count thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC). As such, the second verify level can be shifted + / - 0.55V (smaller resolution) or + / - 0.5V (higher resolution).

[0092] Next, for the second verify operation, the control circuit is configured to apply a second verify pulse (verify #2) of a second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The control circuit is also configured to sense whether the selected ones of the strings conduct current while the second verify pulse is applied after each of the plurality of sense times (e.g., FSENSE#1 and FSENSE#2) and to count and save a second pass number of the memory cells of the selected ones of the strings that conduct current during the second verify operation (indicated as “SCAN after verify #2”).

[0093] The control circuit determines in a recursive manner whether the second pass number of the memory cells of the selected ones of the strings that conduct current during the second verify operation is less than one of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC) responsive to the second pass number of the memory cells of the selected ones of the strings that conduct current during the first verify operation not being less than all of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC). The control circuit also determines in a recursive manner whether the second pass number of the memory cells of the selected ones of the strings that conduct current during the second verify operation is greater than one of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC) responsive to the second pass number of the memory cells of the selected ones of the strings that conduct current during the first verify operation not being greater than all of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC). As such, different sense FSENSE times and different BSPFs are applied again to the second verify.

[0094] The control circuit is configured to select one of the plurality of delta program voltages DVPGM based on determining in a recursive manner whether at least one of the first pass number and the second pass number of the memory cells of the selected ones of the strings that conduct current during at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC) responsive to the second pass number of the memory cells of the selected ones of the strings that conduct current during the first verify operation not being greater than all of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC).

[0095] Further, the control circuit is configured to select the one of the plurality of delta programming voltages DVPGM to add to the first programming voltage VPGMSLC to calculate the second programming voltage for the second programming pulse (VPGMSLC + DVPGM) in response to whether the at least one of the first conduction count and the second conduction count of the memory cells of the selected one of the strings conducting current during the at least one of the first verify operation and the second verify operation being determined in a recursive manner is less than or greater than the one of the plurality of conduction count thresholds (e.g., BSPF_1 PSV_1_SLC, BSPF_1 PSV_2_SLC, BSPF_1 PSV_3_SLC, or BSPF_1 PSV_4_SLC).

[0096] After the verify operation, the control circuit applies a second program pulse having a second program voltage (VPGMSLC+DVPGM) to each of the selected ones of the plurality of word lines associated with the memory cell to program the memory cell. A final verify is applied to ensure that the cell is successfully programmed. Thus, the control circuit is also configured to, in a final verify operation, apply at least one final verify pulse to the at least one of the selected ones of the plurality of word lines associated with the memory cell. The control circuit senses whether the selected one of the strings conducts current while the at least one final verify pulse is applied after waiting for at least one sense time, and counts and saves a final pass number of memory cells of the selected one of the strings that conducted current during the final verify operation. The control circuit additionally determines whether the final pass number of memory cells of the selected one of the strings that conducted current during the final verify operation is less than or greater than a final pass number threshold. The control circuit is configured to, in response to determining that the final pass number of memory cells of the selected one of the strings that conducted current during the final verify operation is not less than or greater than the final pass number threshold, add a subsequent delta program voltage to the first program voltage to calculate a subsequent program voltage for a subsequent program pulse. Next, the control circuit applies the subsequent program pulse having the subsequent program voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cell to program the memory cell, and returns to the final verify operation. The control circuit is configured to repeat the applying of the subsequent program pulse and the final verify operation until the threshold voltage distribution of the memory cell has a desired program low tail voltage, and then saves this program voltage VPGM. Thus, the control circuit can also include a program voltage register (e.g., register 515). Thus, the control circuit is further configured to, in another program operation, program memory cells of the strings of memory cell blocks and other strings of memory cells connected to each of the selected ones of the plurality of word lines within one of the word line regions, store an end or new program voltage equal to the first program voltage VPGMSLC plus the second program voltage VPGMSLC+DVPGM in the program voltage register to apply to each of the selected ones of the plurality of word lines. In this way, to program other strings (e.g., strings 1-4) or other word lines in the same region, the new program voltage stored in the program voltage register is applied.

[0097] Figures 12A-12C An example cumulative distribution function (CDF) voltage curve for an example memory cell during a single pulse verify is shown. In more detail, Figure 12AThe distribution of threshold voltages of memory cells that are "fresh" (e.g., in a memory die sort) after being erased is shown. Next, after a first program pulse at a first program voltage VPGMSLC, the programmed low tail voltage from a first verify operation using a first sense time FSENSE#2 is then shown to be 1.4 volts from the desired programmed low tail voltage or final low tail position. A second program pulse using a delta program voltage DVPGM of 2 volts is applied and the distribution of memory cells finally has the desired programmed low tail voltage. Figure 12B The distribution of threshold voltages of memory cells that are highly cycled (i.e., have experienced many program and erase cycles) after being erased is shown. Next, after a first program pulse at a first program voltage VPGMSLC, the programmed low tail voltage from a first verify operation using a first sense time FSENSE#2 is then shown to be 1.4 volts from the desired programmed low tail voltage or final low tail position. A second verify operation is performed using a second verify voltage that is 0.55 volts greater than the first verify voltage used for the first verify operation and using the first sense time FSENSE#2. The distribution of memory cells from the second verify operation is 0.85 volts lower than the desired programmed low tail voltage or final low tail position. A second program pulse using a delta program voltage DVPGM of 1.4 volts is applied and the distribution of memory cells finally has the desired programmed low tail voltage. Figure 12C The distribution of threshold voltages of memory cells that are highly cycled (i.e., have experienced many program and erase cycles) after being erased is shown. Next, after a first program pulse at a first program voltage VPGMSLC, the programmed low tail voltage from a first verify operation using a first sense time FSENSE#2 is then shown to be 1.4 volts from the desired programmed low tail voltage or final low tail position. A second verify operation is performed using a second verify voltage that is 0.55 volts greater than the first verify voltage used for the first verify operation and using the first sense time FSENSE#2. The distribution of memory cells from the second verify operation is 0.85 volts lower than the desired programmed low tail voltage or final low tail position. A second program pulse using a delta program voltage DVPGM of 1.4 volts is applied and the distribution of memory cells finally has the desired programmed low tail voltage.

[0098] In a particular implementation, the plurality of conduction quantity thresholds can include a first conduction quantity threshold BSPF_1PSV_1_SLC and a second conduction quantity threshold BSPF_1PSV_2_SLC and a third conduction quantity threshold BSPF_1PSV_3_SLC. As such, as described above, the control circuit is further configured to apply a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells in a first verify operation. The control circuit is also configured to sense whether the selected ones of the strings conduct current while the first verify pulse is applied after each of a first sense time FSENSE#2 and a second sense time FSENSE#1 and to count and save a first conduction quantity of the memory cells of the selected ones of the strings that conduct current during the first verify operation.

[0099] As such, during the first verify operation, the control circuit determines whether the first conduction count of the memory cells of the selected one of the strings of conduction current is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit then determines whether the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being greater than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Further, the control circuit is configured to select a first primary delta program voltage DVPGM (e.g., 2 volts) in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit determines whether the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is also configured to select a second primary delta program voltage DVPGM (e.g., 2.2 volts) in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit determines whether the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation is greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit then selects a third primary delta program voltage DVPGM (e.g., 2.4 volts) in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1.The control circuit is configured to determine whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than a second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. Next, the control circuit selects a fourth primary delta program voltage DVPGM (e.g., 2.6 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.

[0100] If the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation is less than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2, the control circuit performs a second verify operation using a second verify pulse having a second verify voltage that is higher than the first verify voltage. Thus, the control circuit is configured to add a primary verify offset voltage (e.g., 0.55 volts) to the first verify voltage to determine the second verify voltage in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, similar to the first verify operation, the control circuit applies a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The control circuit is configured to sense whether the selected one of the strings conducts current while applying the second verify pulse after each of the first sense time FSENSE#2 and the second sense time FSENSE#1 and to count and save a second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation.

[0101] During the second verify operation, the control circuit determines whether the second conduction count of the memory cells of the selected one of the strings conducting current is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, the control circuit is configured to select a fifth primary delta program voltage DVPGM (e.g., 0.4 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is additionally configured to determine whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is further configured to select a sixth primary delta program voltage DVPGM (e.g., 1.2 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. Next, the control circuit is configured to determine whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit then selects a seventh primary delta program voltage DVPGM (e.g., 1.4 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit is further configured to determine whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.The control circuit is configured to select an eighth primary delta program voltage DVPGM (e.g., 1.6 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than a second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. Further, the control circuit determines whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit selects a ninth primary delta program voltage DVPGM (e.g., 1.8 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Alternatively, the control circuit selects a tenth primary delta program voltage DVPGM (e.g., 1.8 volts, less likely) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.

[0102] During the first verify operation, if the first conduction count of the memory cells of the selected one of the strings that conducts current is greater than all of the conduction count thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, BSPF_1PSV_4_SLC) using the first and second sense times FSENSE#1, FSENSE#2, the control circuit performs a second verify operation using a second verify pulse having a second verify voltage that is lower than the first verify voltage. Thus, the control circuit is configured to subtract a primary verify offset voltage (e.g., 0.55 volts) from the first verify voltage to determine the second verify voltage in response to the first conduction count of the memory cells of the selected one of the strings that conducts current during the first verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Next, the control circuit applies a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The control circuit is configured to sense whether the selected one of the strings conducts current while applying the second verify pulse after each of a first sense time FSENSE#2 and a second sense time FSENSE#1, and to count and save a second conduction count of the memory cells of the selected one of the strings that conducts current during the second verify operation.

[0103] Thus, during the second verify operation, the control circuit determines whether the second conduction count of the memory cells of the selected one of the strings conducting current is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit selects an eleventh primary delta program voltage DVPGM (e.g., 2.6 volts, less likely) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is also configured to determine whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit selects a twelfth primary delta program voltage DVPGM (e.g., 2.8 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit then determines whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit selects a thirteenth primary delta program voltage DVPGM (e.g., 3 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit then determines whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.The control circuit is configured to select a fourteenth primary delta program voltage DVPGM (e.g., 3.2 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than a second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit is further configured to determine whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit selects a fifteenth primary delta program voltage DVPGM (e.g., 3.4 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Alternatively, the control circuit selects a sixteenth primary delta program voltage DVPGM (e.g., 3.6 volts, less likely) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.

[0104] In another particular implementation, the plurality of conduction count thresholds includes a first conduction count threshold BSPF_1PSV_1_SLC and a second conduction count threshold BSPF_1PSV_2_SLC and a third conduction count threshold BSPF_1PSV_3_SLC and a fourth conduction count threshold BSPF_1PSV_4_SLC. As such, as discussed, the control circuit is further configured to apply a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cell in a first verify operation. The control circuit senses whether the selected one of the strings conducts current while applying the first verify pulse after each of a first sense time FSENSE#2 and a second sense time FSENSE#1 and counts and saves a first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation.

[0105] As such, during the first verify operation, the control circuit is also configured to determine whether the first conduction count of the memory cells of the selected one of the strings of conduction current is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit is configured to determine whether the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being greater than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit selects a first secondary delta program voltage DVPGM (e.g., 2 volts) in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is also configured to determine whether the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is configured to select a second secondary delta program voltage DVPGM (e.g., 2.1 volts) in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit is configured to determine whether the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation is greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the first sense time FSENSE#2 in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit selects a third secondary delta program voltage DVPGM (e.g., 2.2 volts) in response to the first conduction count of the memory cells of the selected one of the strings of conduction current during the first verify operation being less than the fourth conduction count threshold BSPF_1PSV_4_SLC using the first sense time FSENSE#2.The control circuit next determines whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1. The control circuit selects a fourth secondary delta verify voltage DVPGM (e.g., 2.3 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the first conduction count threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1. The control circuit is configured to determine whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit selects a fifth secondary delta verify voltage DVPGM (e.g., 2.4 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit determines whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit then selects a sixth secondary delta verify voltage DVPGM (e.g., 2.5 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.Further, the control circuit is configured to determine whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The control circuit selects a seventh secondary delta verify voltage DVPGM in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1.

[0106] If the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation is less than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2, the control circuit performs a second verify operation using a second verify pulse having a second verify voltage that is higher than the first verify voltage. Thus, the control circuit is configured to add a secondary verify offset voltage (e.g., 0.5 volts) to the first verify voltage to determine the second verify voltage in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit then applies a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The control circuit senses whether the selected one of the strings conducts current while applying the second verify pulse after waiting for each of the first sense time FSENSE#2 and the second sense time FSENSE#1, and counts and saves a second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation.

[0107] As such, during the second verify operation, the control circuit determines whether the second conduction count of the memory cells of the selected one of the strings conducting current is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit selects an eighth secondary delta program voltage DVPGM (e.g., 0.6 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit is configured to determine whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit selects a ninth secondary delta program voltage DVPGM (e.g., 1.3 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is configured to determine whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit selects a tenth secondary delta program voltage DVPGM (e.g., 1.4 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit is further configured to determine whether the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation is greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.The control circuit selects a twelfth delta programming voltage DVPGM (e.g., 1.6 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit is configured to determine whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, the control circuit selects a thirteenth delta programming voltage DVPGM (e.g., 1.7 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit is also configured to determine whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. Next, the control circuit selects a fourteenth delta programming voltage DVPGM (e.g., 1.8 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.The control circuit is additionally configured to determine whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The control circuit selects a fifteenth secondary delta program voltage DVPGM (e.g., 1.9 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1. Alternatively, the control circuit selects a sixteenth secondary delta program voltage DVPGM (e.g., 1.9 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1.

[0108] During the first verify operation, if the first conduction count of the memory cells of the selected one of the strings conducting current is greater than all of the conduction count thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, BSPF_1PSV_4_SLC) using the first and second sense times FSENSE#1, FSENSE#2, the control circuit performs a second verify operation using a second verify pulse having a second verify voltage that is lower than the first verify voltage. Thus, the control circuit is configured to subtract a secondary verify offset voltage (e.g., 0.5 volts) from the first verify voltage to determine the second verify voltage in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The control circuit is also configured to apply the second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The control circuit senses whether the selected one of the strings conducts current while applying the second verify pulse after each of the first sense time FSENSE#2 and the second sense time FSENSE#1 and counts and saves a second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation.

[0109] Thus, during the second verify operation, the control circuit is configured to determine whether the second pass number of memory cells of the selected one of the strings of pass current is greater than a first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, the control circuit selects a seventeenth secondary delta program voltage DVPGM (e.g., 2.6 volts) in response to the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation being less than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit is also configured to determine whether the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation being greater than the first pass number threshold BSPF_1PSV_1_SLC. The control circuit selects an eighteenth secondary delta program voltage DVPGM (e.g., 2.7 volts) in response to the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation being less than the second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The control circuit is additionally configured to determine whether the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation is greater than a third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC. The control circuit next selects a nineteenth secondary delta program voltage DVPGM (e.g., 2.8 volts) in response to the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The control circuit is configured to determine whether the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation is greater than a fourth pass number threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells of the selected one of the strings of pass current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.The control circuit selects a twenty-first primary delta programming voltage DVPGM (e.g., 2.9 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than a fourth conduction count threshold BSPF_1PSV_4_SLC using the first sense time FSENSE#2. Further, the control circuit is configured to determine whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1 in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit selects a twenty-second primary delta programming voltage DVPGM (e.g., 3 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than a first conduction count threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1. The control circuit also determines whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The control circuit selects a twenty-third primary delta programming voltage DVPGM (e.g., 3.1 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than a second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit is configured to determine whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The control circuit then selects a twenty-fourth primary delta programming voltage DVPGM (e.g., 3.2 volts) in response to the second conduction count of the selected one of the strings conducting current during the second verify operation being less than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.Next, the control circuit is configured to determine whether the second conduction count of the memory cells in the selected one of the strings conducting current during the second verify operation is greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second conduction count of the memory cells in the selected one of the strings conducting current during the second verify operation being greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The control circuit selects a twenty-fourth secondary delta program voltage DVPGM (e.g., 3.3 volts) in response to the second conduction count of the memory cells in the selected one of the strings conducting current during the second verify operation being less than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1. Alternatively, the control circuit selects a twenty-fifth secondary delta program voltage DVPGM (e.g., 3.4 volts) in response to the second conduction count of the memory cells in the selected one of the strings conducting current during the second verify operation being greater than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1. While various particular conduction count thresholds, verify offset voltages, and delta program voltages DVPGM have been described above with respect to a single pulse intelligent verify implementation, it should be understood that these are merely examples, and various other thresholds and voltages can alternatively be used.

[0110] According to an aspect, the plurality of word line groups are a plurality of tiers. Thus, the control circuit is further configured to select an amount of the plurality of tiers for applying the at least one verify voltage pulse to the plurality of word lines associated with the selected amount of the plurality of tiers and sensing whether a selected one of the strings conducts current, and counting at least one conduction count of the memory cells in the selected one of the strings conducting current during the at least one verify operation after the first program pulse. The control circuit determines a program low tail voltage based on the at least one conduction count of the memory cells in the selected one of the strings conducting current during the at least one verify operation, the at least one conduction count of the memory cells depending on the selected amount of the plurality of tiers. By looking at a smaller number of tiers (e.g., one tier, rather than 16 tiers), a wider threshold voltage range can be scanned during the at least one verify operation.

[0111] Figure 13is a table showing a comparison between single pulse smart verify, zero pulse smart verify, and smart verify operations. As shown, use of single pulse smart verify as described herein advantageously achieves fewer pulses of the first string (StrO), a relatively low program time (tProg) of the first string (StrO). Moreover, there is no risk of over programming the memory cells, and single pulse smart verify can be implemented "NAND-based" rather than relying on a host or system controller.

[0112] Figure 14A Steps of an exemplary method of measuring a program slope of a memory cell are shown. The method includes a step 600 of starting a measurement of a program slope. Next, 602, the memory cell is erased and programmed using a first program pulse having a first program voltage. The method continues with 604 of sensing the threshold voltage Vth of the cell for a set of data states relative to one or more verify levels (voltages) (e.g., determine low tail voltage or location as described above). The method continues with a step 606 of initializing an incremental program voltage dV to 0 millivolts. Next, 608, it is determined whether the incremental program voltage dV is greater than a predetermined maximum incremental program voltage (e.g., 4 volts). The method continues with a step 610 of erasing the memory cell and programming the memory cell using another first program pulse having a first program voltage (e.g., default program voltage VPGM) in response to the incremental program voltage dV not being greater than the predetermined maximum incremental program voltage. The next step of the method is 612 of calculating a new program voltage as the first program voltage plus the incremental program voltage dV. Next, 614, a second program pulse is applied for the new program voltage. The next step of the method is 616 of sensing the Vth of the cell for a set of data states relative to the one or more verify levels (voltages) (e.g., determine low tail voltage). The method continues with 618 of incrementing the incremental program voltage dV by a predetermined increment (e.g., 0.4 volts) and returning to the step 608 of determining whether the incremental program voltage dV is less than the predetermined maximum incremental program voltage. The method also includes a step 620 of completing the measurement of the program slope in response to the incremental program voltage dV being greater than the predetermined maximum incremental program voltage.

[0113] Figure 14B It is shown that the program slope does not vary with cycle or starting program voltage VPGM. In more detail, if the second program voltage of the second program pulse is less than the first program voltage plus 1 volt (i.e., VPGM > 1 V + first pulse VPGM), then the program slope stabilizes at 0.7. As such, for example, the program slope can be determined via testing of a memory device in advance (e.g., during design engineering), and the differential program voltage DVPGM DVPGM can be selected accordingly based on the program slope and used for single pulse smart verify as described herein.

[0114] Figure 15A low tail position comparison between the first program voltage of the first program pulse and the second program voltage of the second program pulse using the same first program voltage value (e.g., 16 volts) is exhibited. If the second program voltage of the second program pulse is greater than the first program voltage of the first program pulse by 1.5 volts, then the resulting low tail position difference is insignificant (< 100 millivolts).

[0115] Referring first to Figure 16 A method of operating a memory device is also provided. Again, the memory device includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and arranged in a string. Each of the memory cells is also configured to maintain a threshold voltage Vth within a common threshold voltage range defining a threshold window. The method includes a step 700 of determining a program low tail voltage of a distribution of threshold voltages of the memory cells after a first program pulse of a program operation having a first program voltage, the program low tail voltage corresponding to a cycling condition of the memory cells. The method continues with a step 702 of calculating a second program voltage of a second program pulse of the program operation based on the program low tail voltage and applying to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of threshold voltages of the memory cells has a desired program low tail voltage without further program pulses.

[0116] As discussed above, the first program voltage can be selected such that the program low tail voltage is a predetermined amount lower than the desired program low tail voltage. Thus, the method can also include a step of selecting the first program voltage such that the program low tail voltage is a predetermined interval voltage (e.g., 1.4 volts) lower than the desired program low tail voltage. It should be appreciated that other predetermined interval voltages can instead be utilized.

[0117] The method can also include a step of applying at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current and counting at least one conduction number of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse. Next, the program low tail voltage is determined based on a comparison of the at least one conduction number of the memory cells of the selected one of the strings that conducted current during the at least one verify operation to one of a plurality of conduction number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, BSPF_1PSV_4_SLC).

[0118] According to an aspect and with reference to Figure 17The method further includes step 704, receiving a program command that initiates a program operation, and 706, determining whether a block jump has already occurred in response to receiving the program command that initiates the program operation. Next, the method includes step 708, determining whether the at least one of the selected ones of the plurality of word lines associated with the memory cell is a first logical word line of a region in a first string of strings in response to determining that a block jump has not already occurred. The method continues with 710, initiating the program operation (e.g., including Figure 16 and steps 700 and 702 as described above).

[0119] As discussed above, the at least one verify operation can include a first verify operation and a second verify operation. Also, the at least one conduction quantity includes a first conduction quantity associated with the first verify operation and a second conduction quantity associated with the second verify operation. As such, still referring to Figure 17The method includes a step 712 of applying a first program pulse of a first program voltage (VPGMSLC). Next, the method further includes a step 714 of applying a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells in a first verify operation. The method continues with a step 716 of sensing whether the selected ones of the strings conduct current while the first verify pulse is applied after each of a plurality of sense times and counting and saving a first pass number of memory cells of the selected ones of the strings that conducted current during the first verify operation. The method then includes a step 718 of recursively determining whether the first pass number of memory cells of the selected ones of the strings that conducted current during the first verify operation is less than one of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC). The method also includes a step 720 of adding one of a plurality of verify offset voltages (e.g., 0.5 volts or 0.55 volts) to the first verify voltage to determine a second verify voltage in response to the first pass number of memory cells of the selected ones of the strings that conducted current during the first verify operation being less than all of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC). The method also includes a step 722 of recursively determining whether the first pass number of memory cells of the selected ones of the strings that conducted current during the first verify operation is greater than one of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC) in response to the first pass number of memory cells of the selected ones of the strings that conducted current during the first verify operation not being less than all of the plurality of pass number thresholds. The method continues with a step 724 of subtracting the one of the plurality of verify offset voltages (e.g., 0.5 volts or 0.55 volts) from the first verify voltage to determine a second verify voltage in response to the first pass number of memory cells of the selected ones of the strings that conducted current during the first verify operation being greater than all of the plurality of pass number thresholds. The method then includes a step 726 of applying a second verify pulse of the second verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells during a second verify operation.The next step of the method is 728: sensing whether the selected one of the strings conducts current while the second verify pulse is applied after waiting for each of the plurality of sense times, and counting and saving a second pass number of memory cells of the selected one of the strings that conducted current during the second verify operation. The method then includes step 730: recursively determining whether the second pass number of memory cells of the selected one of the strings that conducted current during the second verify operation is less than one of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC). Next, 732 recursively determines whether the second pass number of memory cells of the selected one of the strings that conducted current during the second verify operation is greater than one of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, or BSPF_1PSV_4_SLC) responsive to the second pass number of memory cells of the selected one of the strings that conducted current during the first verify operation not being less than all of the plurality of pass number thresholds (e.g., BSPF_1PSV_1_SLC, BSPF_1PSV_2_SLC, BSPF_1PSV_3_SLC, and BSPF_1PSV_4_SLC). The method also includes step 734: selecting one of a plurality of delta program voltages DVPGM based on recursively determining whether at least one of the first pass number and the second pass number of memory cells of the selected one of the strings that conducted current during at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of pass number thresholds responsive to the first pass number of memory cells of the selected one of the strings that conducted current during the first verify operation not being greater than all of the plurality of pass number thresholds.

[0120] In addition, the method includes step 736: adding the one of the plurality of delta program voltages DVPGM to the first program voltage VPGMSLC to calculate a second program voltage for a second program pulse responsive to selecting the one of the plurality of delta program voltages DVPGM based on recursively determining whether the at least one of the first pass number and the second pass number of memory cells of the selected one of the strings that conducted current during the at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of pass number thresholds. Next, the method includes step 738: applying the second program pulse having the second program voltage to each of the selected ones of the plurality of word lines associated with the memory cells to program the memory cells.

[0121] The method further includes step 740 of applying at least one final verify pulse to the at least one of the selected ones of the plurality of word lines associated with the memory cells in a final verify operation and sensing whether the selected ones of the strings conduct current while the at least one final verify pulse is applied after a wait of at least one sense time and counting and saving a final pass number of memory cells in the selected ones of the strings that conduct current during the final verify operation. The method then includes 742 of determining whether the final pass number of memory cells in the selected ones of the strings that conduct current during the final verify operation is less than or greater than a final pass number threshold. The method continues with step 744 of adding a subsequent delta program voltage DVPGM to the first program voltage to calculate a subsequent program voltage for a subsequent program pulse in response to determining that the final pass number of memory cells in the selected ones of the strings that conduct current during the final verify operation is not less than or greater than the final pass number threshold. The method then includes step 746 of applying the subsequent program pulse with the subsequent program voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells to program the memory cells and returning to the final verify operation. The method continues with 748 of repeating the applying of the subsequent program pulse and the final verify operation until the threshold voltage distribution of the memory cells has a desired program low tail voltage and 750 of ending the one pulse smart verify.

[0122] As discussed above, the plurality of pass number thresholds include a first pass number threshold BSPF_1PSV_1_SLC and a second pass number threshold BSPF_1PSV_2_SLC and a third pass number threshold BSPF_1PSV_3_SLC. Thus, referring to Figure 18The method further includes step 752 of applying a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells in a first verify operation. The method continues with step 754 of sensing whether the selected ones of the strings conduct current concurrently with the application of the first verify pulse after each of a first sense time FSENSE#2 and a second sense time FSENSE#1 and counting and saving a first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation. The method then includes step 756 of determining whether the first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation is greater than a first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The next step of the method is step 758 of determining whether the first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation being greater than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method then includes step 760 of selecting a first primary delta program voltage DVPGM (e.g., 2 volts) in response to the first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The method continues with step 762 of determining whether the first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The method next includes step 764 of selecting a second primary delta program voltage DVPGM (e.g., 2.2 volts) in response to the first conduction count of the memory cells of the selected ones of the strings that conduct current during the first verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.The method continues at step 766 with determining whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a second conduction count threshold BSPF_1PSV_2_SLC using a second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The method continues at 768 with selecting a third primary delta program voltage DVPGM (e.g., 2.4 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The method continues at step 770 with determining whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. Next, 772 selects a fourth primary delta program voltage DVPGM (e.g., 2.6 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.

[0123] If the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation is less than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2, a second verify operation is performed using a second verify pulse having a second verify voltage that is higher than the first verify voltage. Thus, the method includes a step 774 of adding a primary verify offset voltage to the first verify voltage to determine a second verify voltage in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the first conduction count threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method then continues with a step 776 of applying a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during a second verify operation. The method continues with 778 sensing whether the selected one of the strings conducts current while the second verify pulse is applied after each of a first sense time FSENSE#2 and a second sense time FSENSE#1, and counting and saving a second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation.

[0124] As such, the method includes a step 780 of determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method then includes a step 782 of selecting a fifth primary delta program voltage DVPGM (e.g., 0.4 volts, unlikely) in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The method then includes a step 784 of determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. Next, the method includes a step 786 of selecting a sixth primary delta program voltage DVPGM (e.g., 1.2 volts) in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than a third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The method also includes a step 788 of determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. Next, 790 a seventh primary delta program voltage DVPGM (e.g., 1.4 volts) is selected in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The next step of the method is 792 of determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.The method continues at 794 by selecting an eighth primary delta program voltage DVPGM (e.g., 1.6 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than a second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The method continues at step 796 by determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. Next, 798 an ninth primary delta program voltage DVPGM (e.g., 1.8 volts) is selected in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Alternatively, the method includes a step 800 of selecting a tenth primary delta program voltage DVPGM (e.g., 1.8 volts, unlikely) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.

[0125] During the first verify operation, if the first pass number of memory cells in the selected one of the strings conducting current is greater than all of the pass number thresholds using the first and second sense times FSENSE#1, FSENSE#2, then a second verify operation is performed using a second verify pulse having a second verify voltage that is lower than the first verify voltage. Thus, the method includes a step 802 of subtracting a primary verify offset voltage from the first verify voltage to determine the second verify voltage in response to the first pass number of memory cells in the selected one of the strings conducting current during the first verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Next, 804 a second verify pulse of the second verify voltage is applied to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The method also includes a step 806 of sensing whether the selected one of the strings conducts current while the second verify pulse is applied after each of the first sense time FSENSE#2 and the second sense time FSENSE#1, and counting and saving a second pass number of memory cells in the selected one of the strings conducting current during the second verify operation.

[0126] The method continues with 808 by determining whether the second pass number of memory cells of the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1 PSV_2_SLC using the first sense time FSENSE#2. Next, 810 a eleventh primary delta program voltage DVPGM is selected (e.g., 2.6 volts, unlikely) in response to the second pass number of memory cells of the selected one of the strings passing current during the second verify operation being less than the second pass number threshold BSPF_1 PSV_2_SLC using the first sense time FSENSE#2. The method continues with step 812 by determining whether the second pass number of memory cells of the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1 PSV_2_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells of the selected one of the strings passing current during the second verify operation being greater than the second pass number threshold BSPF_1 PSV_2_SLC using the first sense time FSENSE#2. The next step of the method is 814 by selecting a twelfth primary delta program voltage DVPGM (e.g., 2.8 volts) in response to the second pass number of memory cells of the selected one of the strings passing current during the second verify operation being less than a third pass number threshold BSPF_1 PSV_3_SLC using the first sense time FSENSE#2. The method continues with step 816 by determining whether the second pass number of memory cells of the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1 PSV_2_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells of the selected one of the strings passing current during the second verify operation being greater than the third pass number threshold BSPF_1 PSV_3_SLC using the first sense time FSENSE#2. Next, 818 a thirteenth primary delta program voltage DVPGM is selected (e.g., 3 volts) in response to the second pass number of memory cells of the selected one of the strings passing current during the second verify operation being less than the third pass number threshold BSPF_1 PSV_3_SLC using the first sense time FSENSE#2. The method also includes step 820 by determining whether the second pass number of memory cells of the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1 PSV_2_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells of the selected one of the strings passing current during the second verify operation being greater than the third pass number threshold BSPF_1 PSV_3_SLC using the first sense time FSENSE#2.The method also includes a step 822 of selecting a fourteenth primary delta program voltage DVPGM (e.g., 3.2 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than a second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The next step of the method is 824 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. Next, 826 a fifteenth primary delta program voltage DVPGM (e.g., 3.4 volts) is selected in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Alternatively, the method includes a step 828 of selecting a sixteenth primary delta program voltage DVPGM (e.g., 3.6 volts, unlikely) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.

[0127] According to an aspect and as discussed above, the plurality of pass number thresholds includes a first pass number threshold BSPF_1PSV_1_SLC and a second pass number threshold BSPF_1PSV_2_SLC and a third pass number threshold BSPF_1PSV_3_SLC and a fourth pass number threshold BSPF_1PSV_4_SLC. Thus, referring to Figure 19The method further includes step 830 of applying a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells in a first verify operation. Next, 832, sense whether the selected ones of the strings conduct current concurrently with the application of the first verify pulse after each of a first sense time FSENSE#2 and a second sense time FSENSE#1 and count and save a first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation. The method continues with step 834 of determining whether the first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation is greater than a first number of conduction threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method then includes step 836 of determining whether the first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation is greater than a second number of conduction threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation being greater than the first number of conduction threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method continues with step 838 of selecting a first secondary delta program voltage DVPGM (e.g., 2 volts) in response to the first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation being less than the second number of conduction threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The method continues with step 840 of determining whether the first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation is greater than a third number of conduction threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation being greater than the second number of conduction threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. Next, 842, select a second secondary delta program voltage DVPGM (e.g., 2.1 volts) in response to the first number of conduction of memory cells of the selected ones of the strings that conduct current during the first verify operation being less than the third number of conduction threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.A next step of the method is 844: determining whether the first pass number of memory cells in the selected one of strings passing current during the first verify operation is greater than a fourth pass number threshold BSPF_1PSV_4_SLC using the first sense time FSENSE#2 in response to the first pass number of memory cells in the selected one of strings passing current during the first verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The method also includes a step 846: selecting a third secondary delta verify voltage DVPGM (e.g., 2.2 volts) in response to the first pass number of memory cells in the selected one of strings passing current during the first verify operation being less than the fourth pass number threshold BSPF_1PSV_4_SLC using the first sense time FSENSE#2. The method continues with a step 848: determining whether the first pass number of memory cells in the selected one of strings passing current during the first verify operation is greater than a first pass number threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1 in response to the first pass number of memory cells in the selected one of strings passing current during the first verify operation being greater than the fourth pass number threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1. A next step of the method is 850: selecting a fourth secondary delta verify voltage DVPGM (e.g., 2.3 volts) in response to the first pass number of memory cells in the selected one of strings passing current during the first verify operation being less than the first pass number threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1. A next step of the method is 852: determining whether the first pass number of memory cells in the selected one of strings passing current during the first verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the first pass number of memory cells in the selected one of strings passing current during the first verify operation being greater than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, 854 a fifth secondary delta verify voltage DVPGM (e.g., 2.4 volts) is selected in response to the first pass number of memory cells in the selected one of strings passing current during the first verify operation being less than the second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1.The method also includes a step 856 of determining whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than the second conduction count threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The method then includes a step 858 of selecting a sixth secondary delta program voltage DVPGM (e.g., 2.5 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The method continues with a step 860 of determining whether the first conduction count of the selected one of the strings conducting current during the first verify operation is greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being greater than the third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The method then includes a step 862 of selecting a seventh secondary delta program voltage DVPGM (e.g., 2.6 volts) in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1.

[0128] If the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation is less than the first conduction count threshold BSPF_1 PSV_1_SLC using the first sense time FSENSE#2, a second verify operation is performed using a second verify pulse having a second verify voltage that is higher than the first verify voltage. Thus, the method continues at step 864 with adding a secondary verify offset voltage to the first verify voltage to determine a second verify voltage in response to the first conduction count of the memory cells of the selected one of the strings conducting current during the first verify operation being less than the first conduction count threshold BSPF_1 PSV_1_SLC using the first sense time FSENSE#2. Next, 866 a second verify pulse of the second verify voltage is applied to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The method also includes step 868 sensing whether the selected one of the strings conducts current while the second verify pulse is applied after each of the first sense time FSENSE#2 and the second sense time FSENSE#1 is waited for, and counting and saving a second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation.

[0129] As such, the method includes a step 870 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method continues with a step 872 of selecting an eighth secondary delta program voltage DVPGM (e.g., 0.6 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The next step of the method is a step 874 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the first pass number threshold BSPF_1PSV_1_SLC. The method continues with a step 876 of selecting a ninth secondary delta program voltage DVPGM (e.g., 1.3 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. The next step of the method is a step 878 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC. Next, a step 880 selects a tenth secondary delta program voltage DVPGM (e.g., 1.4 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The method continues with a step 882 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a fourth pass number threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2.The method also includes a step 884 of selecting an eleventh secondary delta program voltage DVPGM (e.g., 1.5 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than a fourth pass number threshold BSPF_1PSV_4_SLC using the first sense time FSENSE#2. The next step of the method is 886 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a first pass number threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method also includes a step 888 of selecting a twelfth secondary delta program voltage DVPGM (e.g., 1.6 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method continues with a step 890 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, 892 a thirteenth secondary delta program voltage DVPGM (e.g., 1.7 volts) is selected in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The method also includes a step 894 of determining whether the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation is greater than a third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The next step of the method is 896 of selecting a fourteenth secondary delta program voltage DVPGM (e.g., 1.8 volts) in response to the second pass number of memory cells in the selected one of the strings conducting current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1.The method also includes a step 898 of determining whether the second conduction count of the selected one of the strings conducting current during the second verify operation is greater than a fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than a third conduction count threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Next, 900 a fifteenth secondary delta programming voltage DVPGM (e.g., 1.9 volts) is selected in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being less than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1. Alternatively, the method includes a step 902 of selecting a sixteenth secondary delta programming voltage DVPGM (e.g., 1.9 volts) in response to the second conduction count of the memory cells of the selected one of the strings conducting current during the second verify operation being greater than the fourth conduction count threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1.

[0130] During the first verify operation, if the first pass number of memory cells of the selected one of the strings conducting current is greater than all pass number thresholds using the first and second sense times FSENSE#1, FSENSE#2, a second verify operation is performed using a second verify pulse of a second verify voltage that is lower than the first verify voltage. Thus, the method includes a step 904 of subtracting a secondary verify offset voltage from the first verify voltage to determine the second verify voltage in response to the first pass number of memory cells of the selected one of the strings conducting current during the first verify operation being greater than a third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The method also includes a step 906 of applying a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation. The method also includes a step 908 of sensing whether the selected one of the strings conducts current while the second verify pulse is applied after each of a first sense time FSENSE#2 and a second sense time FSENSE#1 and counting and saving a second pass number of memory cells of the selected one of the strings conducting current during the second verify operation. The method also includes a step 910 of determining whether the second pass number of memory cells of the selected one of the strings conducting current during the second verify operation is greater than a first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, 912 a seventeenth secondary delta program voltage DVPGM (e.g., 2.6 volts) is selected in response to the second pass number of memory cells of the selected one of the strings conducting current during the second verify operation being less than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. The method continues with a step 914 of determining whether the second pass number of memory cells of the selected one of the strings conducting current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells of the selected one of the strings conducting current during the second verify operation being greater than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, the method includes a step 916 of selecting an eighteenth secondary delta program voltage DVPGM (e.g., 2.7 volts) in response to the second pass number of memory cells of the selected one of the strings conducting current during the second verify operation being less than the second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2.The method continues with step 918: determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC using the first sense time FSENSE#2. Next, 920 a nineteenth secondary delta program voltage DVPGM (e.g., 2.8 volts) is selected in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. The method next includes step 922: determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a fourth pass number threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the first sense time FSENSE#2. Next, 924 a twentieth secondary delta program voltage DVPGM (e.g., 2.9 volts) is selected in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the fourth pass number threshold BSPF_1PSV_4_SLC using the first sense time FSENSE#2. The method continues with step 926: determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than the first pass number threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the first pass number threshold BSPF_1PSV_1_SLC using the second sense time FSENSE#1. The method also includes step 928: selecting a twenty-first secondary delta program voltage DVPGM (e.g., 3 volts) in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2.The method continues with step 930 of determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than a first pass number threshold BSPF_1PSV_1_SLC using the first sense time FSENSE#2. Next, 932 a twenty-second secondary delta program voltage DVPGM (e.g., 3.1 volts) is selected in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The method continues with step 934 of determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the second pass number threshold BSPF_1PSV_2_SLC using the second sense time FSENSE#1. The method also includes step 936 of selecting a twenty-third secondary delta program voltage DVPGM (e.g., 3.2 volts) in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. The method next includes step 938 of determining whether the second pass number of memory cells in the selected one of the strings passing current during the second verify operation is greater than a fourth pass number threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1 in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the third pass number threshold BSPF_1PSV_3_SLC using the second sense time FSENSE#1. Next, 940 a twenty-fourth secondary delta program voltage DVPGM (e.g., 3.3 volts) is selected in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being less than the fourth pass number threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1. Alternatively, the method includes step 942 of selecting a twenty-fifth secondary delta program voltage DVPGM (e.g., 3.4 volts) in response to the second pass number of memory cells in the selected one of the strings passing current during the second verify operation being greater than the fourth pass number threshold BSPF_1PSV_4_SLC using the second sense time FSENSE#1.

[0131] As discussed, the plurality of word lines can be grouped into a plurality of tiers. As such, the method further includes the steps of selecting an amount of the plurality of tiers for applying the at least one verify voltage pulse to the plurality of word lines associated with the selected amount of the plurality of tiers and sensing whether the selected one of the strings conducts current, and counting at least one conduction amount of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse. The method then includes the steps of determining a program low tail voltage based on the at least one conduction amount of the memory cells of the selected one of the strings that conducted current during the at least one verify operation, the at least one conduction amount of the memory cells depending on the selected amount of the plurality of tiers.

[0132] As mentioned above, the memory device can include a program voltage register, and the plurality of word lines are grouped into word line zones. Thus, the method includes the steps of storing in the program voltage register an end program voltage equal to the first program voltage plus the second program voltage for application to each of the selected ones of the plurality of word lines when programming the memory cells and memory cell blocks of the other strings of strings connected to each of the selected ones of the plurality of word lines within one of the word line zones in another program operation.

[0133] It will be readily apparent that modifications can be made to the contents of what has been described and illustrated herein, without departing from the scope defined in the appended claims. The foregoing description of embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and other combinations and modifications are possible. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable with other embodiments, as applicable, and can be used in selected embodiments even if not specifically shown or described. Individual elements or features of a particular embodiment can also vary in a multitude of ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure. It is intended that the disclosure be construed as including all such modifications.

[0134] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" can be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having," are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order

[0135] When an element or layer is referred to as being "on," "engaged to," "connected to," or "coupled to" another element or layer, it can be directly on, engaged, connected, or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0136] Although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not connote a sequential or chronological order, unless specifically stated to do so. Accordingly, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

[0137] Spatially relative terms, such as "inner," "outer," "beneath," "below," "lower," "above," "upper," "top," "bottom," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Claims

1. A memory device comprising: a block of memory cells, each of the memory cells connected to one of a plurality of word lines and arranged in a string and configured to hold a threshold voltage within a common threshold voltage range defining a threshold window; control circuitry coupled to the plurality of word lines and the string and configured to: determine a program low tail voltage of a distribution of the threshold voltages of the memory cells after a first program pulse of a program operation having a first program voltage, the program low tail voltage corresponding to a cycling condition of the memory cells, and calculate a second program voltage for a second program pulse of the program operation based on the program low tail voltage, and apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltages of the memory cells has a desired program low tail voltage without further program pulses.

2. The device of claim 1, wherein the control circuitry is further configured to: apply at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current, and count at least one conduction quantity of the memory cells of the selected one of the strings that conducts current during at least one verify operation after the first program pulse, and determine the program low tail voltage based on a comparison of the at least one conduction quantity of the memory cells of the selected one of the strings that conducts current during the at least one verify operation to one of a plurality of conduction quantity thresholds.

3. The device of claim 2, wherein the at least one verify operation includes a first verify operation and a second verify operation, and the at least one conduction quantity includes a first conduction quantity associated with the first verify operation and a second conduction quantity associated with the second verify operation, and the control circuitry is further configured to: apply a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells in the first verify operation, sense whether the selected one of the strings conducts current after waiting for each of a plurality of sense times while applying the first verify pulse, and count and save the first conduction quantity of the memory cells of the selected one of the strings that conducts current during the first verify operation, determine in a recursive manner whether the first conduction quantity of the memory cells of the selected one of the strings that conducts current during the first verify operation is less than one of the plurality of conduction quantity thresholds, add one of a plurality of verify offset voltages to the first verify voltage to determine a second verify voltage in response to the first conduction quantity of the memory cells of the selected one of the strings that conducts current during the first verify operation being less than all of the plurality of conduction quantity thresholds, apply the second verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells in the second verify operation, determining, in a recursive manner, whether the first number of conducting memory cells of the selected one of the strings that conducted current during the first verify operation is greater than one of the plurality of numbers of conducting thresholds in response to the first number of conducting memory cells of the selected one of the strings that conducted current during the first verify operation not being less than all of the plurality of numbers of conducting thresholds, subtracting the one of the plurality of verify offset voltages from the first verify voltage to determine a second verify voltage in response to the first number of conducting memory cells of the selected one of the strings that conducted current during the first verify operation being greater than all of the plurality of numbers of conducting thresholds, applying a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cell during the second verify operation, sensing whether the selected one of the strings conducts current while the second verify pulse is applied after waiting for each of the plurality of sense times and counting and saving the second number of conducting memory cells of the selected one of the strings that conducted current during the second verify operation, determining, in a recursive manner, whether the second number of conducting memory cells of the selected one of the strings that conducted current during the second verify operation is less than one of the plurality of numbers of conducting thresholds, determining, in a recursive manner, whether the first number of conducting memory cells of the selected one of the strings that conducted current during the first verify operation is greater than one of the plurality of numbers of conducting thresholds in response to the first number of conducting memory cells of the selected one of the strings that conducted current during the first verify operation not being less than all of the plurality of numbers of conducting thresholds, selecting one of a plurality of delta program voltages based on determining, in a recursive manner, whether at least one of the first number of conducting memory cells and the second number of conducting memory cells of the selected one of the strings that conducted current during at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of numbers of conducting thresholds in response to the second number of conducting memory cells of the selected one of the strings that conducted current during the second verify operation not being greater than all of the plurality of numbers of conducting thresholds.

4. The apparatus of claim 3, wherein the control circuit is further configured to: determine whether a block jump has already existed in response to receiving a program command to initiate the program operation, determine whether the at least one of the selected ones of the plurality of word lines associated with the memory cell is a first logical word line of a zone in a first string of the strings in response to determining that a block jump has not already existed or determining that the at least one of the selected ones of the plurality of word lines associated with the memory cell is the first logical word line of the zone in the first string of the strings in response to determining that a block jump has already existed, initiate the program operation, selecting one of a plurality of delta program voltages to add to the first program voltage to calculate a second program voltage for a second program pulse in response to whether the at least one of the first conduction count and the second conduction count of the memory cells of the selected one of the strings that conducted current during the at least one of the first verify operation and the second verify operation in the recursive manner is less than or greater than the one of the plurality of conduction count thresholds, applying the second program pulse having the second program voltage to the selected ones of the plurality of word lines associated with the memory cells to program the memory cells, applying at least one final verify pulse to the selected ones of the plurality of word lines associated with the memory cells in a final verify operation, sensing whether the selected one of the strings conducts current while the at least one final verify pulse is applied after waiting for at least one sense time and counting and saving a final conduction count of the memory cells of the selected one of the strings that conducted current during the final verify operation, determining whether the final conduction count of the memory cells of the selected one of the strings that conducted current during the final verify operation is less than or greater than a final conduction count threshold, adding a subsequent delta program voltage to the first program voltage to calculate a subsequent program voltage for a subsequent program pulse in response to determining that the final conduction count of the memory cells of the selected one of the strings that conducted current during the final verify operation is not less than or greater than the final conduction count threshold, applying the subsequent program pulse having the subsequent program voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells to program the memory cells and returning to the final verify operation, and repeating the applying the subsequent program pulse and the final verify operation until the distribution of threshold voltages of the memory cells has the desired program low tail voltage.

5. The apparatus of claim 3, wherein the plurality of sense times includes a first sense time and a second sense time, and the control circuit is further configured to select the first program voltage such that the program low tail voltage is a predetermined margin voltage below the desired program low tail voltage.

6. The apparatus of claim 1, wherein the first program voltage is at least 15.5 volts.

7. The apparatus of claim 2, wherein the plurality of word line groups are in a plurality of tiers, and the control circuit is further configured to: selecting a quantity of the plurality of tiers for applying the at least one verify voltage pulse to the plurality of word lines associated with the quantity of the plurality of tiers selected and sensing whether the selected one of the strings conducts current, and counting at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse, and determining the program low tail voltage based on the at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation, the at least one conducting quantity of the memory cells depending on the quantity of the plurality of tiers selected.

8. The apparatus of claim 1, wherein the control circuit includes a program voltage register, and the plurality of word lines are grouped into word line zones, and the control circuit is further configured to, in another program operation, program memory cells connected to each of the selected ones of the plurality of word lines within one of the word line zones and memory cells of other ones of the strings of the memory cell block, store an end program voltage equal to the first program voltage plus the second program voltage in the program voltage register to apply to each of the selected ones of the plurality of word lines.

9. A controller in communication with a memory apparatus including a block of memory cells, each of the memory cells connected to one of a plurality of word lines and arranged into strings, and configured to maintain a threshold voltage within a common threshold voltage range defining a threshold window, the controller configured to: determine a program low tail voltage of a distribution of the threshold voltages of the memory cells after a first program pulse of a program operation having a first program voltage, the program low tail voltage corresponding to a cycling condition of the memory cells; and calculate a second program voltage for a second program pulse of the program operation based on the program low tail voltage, and instruct the memory apparatus to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltages of the memory cells has a desired program low tail voltage without further program pulses.

10. The controller of claim 9, wherein the controller is further configured to: instruct the memory apparatus to apply at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current, and count at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse; and determine the program low tail voltage based on a comparison of the at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation to one of a plurality of conducting quantity thresholds.

11. The controller of claim 10, wherein the controller is further configured to: instruct the memory apparatus to apply at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current, and count at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse; and determine the program low tail voltage based on a comparison of the at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation to one of a plurality of conducting quantity thresholds.

12. The controller of claim 11, wherein the controller is further configured to: instruct the memory apparatus to apply at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current, and count at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse; and determine the program low tail voltage based on a comparison of the at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation to one of a plurality of conducting quantity thresholds.

13. The controller of claim 12, wherein the controller is further configured to: instruct the memory apparatus to apply at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current, and count at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse; and determine the program low tail voltage based on a comparison of the at least one conducting quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation to one of a plurality of conducting quantity thresholds.

11. The controller of claim 10, wherein the at least one verify operation includes a first verify operation and a second verify operation, and the at least one conduction count includes a first conduction count associated with the first verify operation and a second conduction count associated with the second verify operation, and the controller is further configured to: instruct the memory device to apply a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells in the first verify operation; instruct the memory device to sense whether the selected one of the strings conducts current while the first verify pulse is applied after each of a plurality of sense times, and count and save the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation; determine in a recursive manner whether the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation is less than one of the plurality of conduction count thresholds; in response to the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation being less than all of the plurality of conduction count thresholds, add one of a plurality of verify offset voltages to the first verify voltage to determine a second verify voltage; in response to the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation not being less than all of the plurality of conduction count thresholds, determine in a recursive manner whether the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation is greater than one of the plurality of conduction count thresholds; in response to the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation being greater than all of the plurality of conduction count thresholds, subtract the one of the plurality of verify offset voltages from the first verify voltage to determine the second verify voltage; instruct the memory device to apply a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation; instruct the memory device to sense whether the selected one of the strings conducts current while the second verify pulse is applied after each of the plurality of sense times, and count and save the second conduction count of the memory cells of the selected one of the strings that conducted current during the second verify operation; determine in a recursive manner whether the second conduction count of the memory cells of the selected one of the strings that conducted current during the second verify operation is less than one of the plurality of conduction count thresholds; determining, in a recursive manner, whether the first conduction count and the second conduction count of the memory cells in the selected one of the strings that conducted current during the at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of conduction count thresholds based on selecting the one of the plurality of delta program voltages in response to the second conduction count of the memory cells in the selected one of the strings that conducted current during the second verify operation not being greater than all of the plurality of conduction count thresholds; and selecting the one of the plurality of delta program voltages based on determining, in a recursive manner, whether the first conduction count and the second conduction count of the memory cells in the selected one of the strings that conducted current during the at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of conduction count thresholds in response to the second conduction count of the memory cells in the selected one of the strings that conducted current during the second verify operation not being greater than all of the plurality of conduction count thresholds.

12. The controller of claim 11, wherein the controller is further configured to: determine whether a block jump has existed in response to receiving a program command to initiate the program operation; determine whether the at least one of the selected ones of the plurality of word lines associated with the memory cell is a first logical word line of a zone in a first string of the strings in response to determining that a block jump has not existed; begin the program operation in response to determining that a block jump has existed or determining that the at least one of the selected ones of the plurality of word lines associated with the memory cell is the first logical word line of the zone in the first string of the strings; add the one of the plurality of delta program voltages to the first program voltage to calculate the second program voltage of the second program pulse in response to selecting the one of the plurality of delta program voltages based on determining, in a recursive manner, whether the first conduction count and the second conduction count of the memory cells in the selected one of the strings that conducted current during the at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of conduction count thresholds; instruct the memory device to program the memory cell with the second program pulse having the second program voltage to the selected ones of the plurality of word lines associated with the memory cell; instruct the memory device to apply at least one final verify pulse to the at least one of the selected ones of the plurality of word lines associated with the memory cell in a final verify operation; instruct the memory device to sense whether the selected one of the strings conducted current while the memory device applied the at least one final verify pulse after waiting for at least one sense time and to count and save a final conduction count of the memory cells in the selected one of the strings that conducted current during the final verify operation; determining whether the final number of memory cells in the selected one of the strings that conducted current during the final verify operation is less than or greater than a final number of conduction threshold; in response to determining that the final number of memory cells in the selected one of the strings that conducted current during the final verify operation is not less than or greater than the final number of conduction threshold, adding a subsequent delta program voltage to the first program voltage to calculate a subsequent program voltage for a subsequent program pulse; instructing the memory device to apply the subsequent program pulse having the subsequent program voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cell to program the memory cell, and returning to the final verify operation; and instructing the memory device to repeat the applying the subsequent program pulse and the final verify operation until the distribution of threshold voltages of the memory cell has the desired program low tail voltage.

13. A method of operating a memory device including a block of memory cells, each of the memory cells connected to one of a plurality of word lines and arranged in strings, and configured to maintain a threshold voltage within a common threshold voltage range defining a threshold window, the method comprising the steps of: determining a program low tail voltage of a distribution of threshold voltages of the memory cells after a first program pulse of a program operation having a first program voltage, the program low tail voltage corresponding to a cycling condition of the memory cells; and calculating a second program voltage for a second program pulse of the program operation based on the program low tail voltage, and applying to each of the selected ones of the plurality of word lines associated with the memory cell to program the memory cells such that the distribution of threshold voltages of the memory cells has a desired program low tail voltage without further program pulses.

14. The method of claim 13, further comprising the steps of: applying at least one verify voltage pulse to at least one of the selected ones of the plurality of word lines associated with the memory cells while sensing whether a selected one of the strings conducts current, and counting at least one number of conduction of the memory cells in the selected one of the strings that conducted current during at least one verify operation after the first program pulse; and determining the program low tail voltage based on a comparison of the at least one number of conduction of the memory cells in the selected one of the strings that conducted current during the at least one verify operation to one of a plurality of conduction threshold values.

15. The method of claim 14, wherein the at least one verify operation includes a first verify operation and a second verify operation, and the at least one number of conduction includes a first number of conduction associated with the first verify operation and a second number of conduction associated with the second verify operation, and the method further comprises the steps of: applying a first verify pulse of a first verify voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cells during the first verify operation; sensing whether the selected one of the strings conducts current while the first verify pulse is applied after waiting for each of a plurality of sense times, and counting and saving the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation; determining in a recursive manner whether the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation is less than one of the plurality of conduction count thresholds; in response to the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation being less than all of the plurality of conduction count thresholds, adding one of a plurality of verify offset voltages to the first verify voltage to determine a second verify voltage; in response to the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation not being less than all of the plurality of conduction count thresholds, determining in a recursive manner whether the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation is greater than one of the plurality of conduction count thresholds; in response to the first conduction count of the memory cells of the selected one of the strings that conducted current during the first verify operation being greater than all of the plurality of conduction count thresholds, subtracting the one of the plurality of verify offset voltages from the first verify voltage to determine the second verify voltage; applying a second verify pulse of the second verify voltage to at least one of the selected ones of the plurality of word lines associated with the memory cells during the second verify operation; sensing whether the selected one of the strings conducts current while the second verify pulse is applied after waiting for each of the plurality of sense times, and counting and saving the second conduction count of the memory cells of the selected one of the strings that conducted current during the second verify operation; determining in a recursive manner whether the second conduction count of the memory cells of the selected one of the strings that conducted current during the second verify operation is less than one of the plurality of conduction count thresholds; in response to the second conduction count of the memory cells of the selected one of the strings that conducted current during the second verify operation not being less than all of the plurality of conduction count thresholds, determining in a recursive manner whether the second conduction count of the memory cells of the selected one of the strings that conducted current during the second verify operation is greater than one of the plurality of conduction count thresholds; and ​ determining whether at least one of the first conduction count and the second conduction count of the memory cells of the selected one of the strings that conducted current during at least one of the first verify operation and the second verify operation is less than or greater than the one of the plurality of conduction count thresholds based on the second conduction count of the memory cells of the selected one of the strings that conducted current during the second verify operation being not greater than all of the plurality of conduction count thresholds.

16. The method of claim 15, further comprising: determining whether a block jump already exists in response to receiving a program command to initiate the program operation; determining whether the at least one of the selected ones of the plurality of word lines associated with the memory cell is a first logical word line of a zone in a first string of the strings in response to determining that a block jump does not already exist; starting the program operation in response to determining that a block jump already exists or determining that the at least one of the selected ones of the plurality of word lines associated with the memory cell is the first logical word line of the zone in the first string of the strings; adding the one of the plurality of delta program voltages to the first program voltage to calculate the second program voltage of the second program pulse in response to selecting the one of the plurality of delta program voltages based on the at least one of the first conduction count and the second conduction count of the memory cells of the selected one of the strings that conducted current during the at least one of the first verify operation and the second verify operation being less than or greater than the one of the plurality of conduction count thresholds; applying the second program pulse having the second program voltage to the selected ones of the plurality of word lines associated with the memory cell to program the memory cell; applying at least one final verify pulse to the at least one of the selected ones of the plurality of word lines associated with the memory cell in a final verify operation; sensing whether the selected one of the strings conducted current while the at least one final verify pulse is applied after waiting for at least one sense time and counting and saving a final conduction count of the memory cells of the selected one of the strings that conducted current during the final verify operation; determining whether the final conduction count of the memory cells of the selected one of the strings that conducted current during the final verify operation is less than or greater than a final conduction count threshold; adding a subsequent delta program voltage to the first program voltage to calculate a subsequent program voltage of a subsequent program pulse in response to determining that the final conduction count of the memory cells of the selected one of the strings that conducted current during the final verify operation is not less than or greater than the final conduction count threshold; applying the subsequent program pulse having the subsequent program voltage to the at least one of the selected ones of the plurality of word lines associated with the memory cell to program the memory cell, and returning to the final verify operation; and repeating the applying the subsequent program pulse and the final verify operation until the distribution of the threshold voltages of the memory cell has the desired program low tail voltage.

17. The method of claim 15 wherein the plurality of sense times includes a first sense time and a second sense time, and the method further includes the step of selecting the first program voltage such that the program low tail voltage is a predetermined interval voltage below the desired program low tail voltage.

18. The method of claim 13 wherein the first program voltage is at least 15.5 volts.

19. The method of claim 14 wherein the plurality of word line groups are a plurality of tiers, and the method further includes the steps of: selecting an amount of the plurality of tiers for applying the at least one verify voltage pulse to the plurality of word lines associated with the selected amount of the plurality of tiers and sensing whether the selected one of the strings conducts current during the at least one verify operation, and counting at least one conductive quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation after the first program pulse; and determining the program low tail voltage based on the at least one conductive quantity of the memory cells of the selected one of the strings that conducted current during the at least one verify operation, the at least one conductive quantity of the memory cells depending on the selected amount of the plurality of tiers.

20. The method of claim 13 wherein the memory device includes a program voltage register, and the plurality of word line groups are word line zones, and the method includes the step of storing an end program voltage equal to the first program voltage plus the second program voltage in the program voltage register for application to each of the selected ones of the plurality of word lines when programming memory cells connected to each of the selected ones of the plurality of word lines within one of the word line zones and memory cells of other ones of the strings of the memory cell block in another program operation.

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