Semiconductor device performing loopback test operation

Abstract

This disclosure relates to a semiconductor device for performing loopback test operations. An apparatus is disclosed herein comprising: a memory cell array; data input / output terminals; a read data path and a write data path coupled in parallel between the memory cell array and the data input / output terminals, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

Description

Technical Field

[0001] This disclosure relates to memory, and more particularly, to a semiconductor device for performing loopback test operations. Background Technology

[0002] Various operational tests are performed at the manufacturing steps of semiconductor devices, such as DRAM (Dynamic Random Access Memory). In some operational tests, data output from the output buffer to the data I / O terminals is looped back to the input receiver. This allows test data to be written to the memory cell array without inputting test data from the data I / O terminals. Summary of the Invention

[0003] One aspect of this disclosure provides an apparatus comprising: a memory cell array; data input / output terminals; a read data path and a write data path coupled in parallel between the memory cell array and the data input / output terminals, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

[0004] Another aspect of this disclosure provides an apparatus comprising: a memory cell array; a test register configured to store test data; a read data path transmitting test data supplied from the test register; a write data path transmitting test data to be written into the memory cell array; an external terminal; a first loopback path and a second loopback path configured to loop test data from the read data path back to the write data path, wherein the first loopback path is coupled to the external terminal, and wherein the second loopback path does not contain the external terminal.

[0005] Another aspect of this disclosure provides an apparatus comprising: an external terminal; an output buffer having an input node and an output node coupled to the external terminal; an input receiver having an input node coupled to the external terminal and an output node; and a multiplexer configured to select one of data supplied to the input node of the output buffer and data output from the output node of the input receiver. Attached Figure Description

[0006] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 This is a circuit diagram of the I / O circuit.

[0008] Figure 3 It is a diagram showing the data flow of the I / O circuit during a read operation.

[0009] Figure 4 It is a diagram showing the data flow of the I / O circuitry during a write operation.

[0010] Figure 5 It is a diagram showing the data flow of the I / O circuit during a low-speed write test operation.

[0011] Figure 6 It is a diagram showing the data flow of the I / O circuit during a read test operation.

[0012] Figure 7 It is a diagram showing the data flow of the I / O circuit during a high-speed write test operation. Detailed Implementation

[0013] Various embodiments of the invention will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of the invention that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments can be utilized without departing from the scope of the invention, and structural, logical, and electrical changes can be made. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0014] Figure 1 This is a block diagram of a semiconductor device 10 according to one embodiment of the present disclosure. The semiconductor device 10 may be, for example, a wide I / O DRAM incorporated into a single semiconductor chip. Figure 1 As shown, the semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC respectively disposed at the intersections between word lines WL and bit lines BL. Selection of word lines WL is performed by a row decoder 12, and selection of bit lines BL is performed by a column decoder 13. A sense amplifier 14 is coupled to a corresponding bit line BL and a local I / O line pair LIOT / B. The local I / O line pair LIOT / B is coupled to the main I / O line pair MIOT / B via a transfer gate 15 that acts as a switch. The memory cell array 11 is divided into m+1 memory banks including memory banks BANK0 to BANKm.

[0015] The semiconductor device 10 includes multiple external terminals, including a command address terminal 21, a clock terminal 22, a data terminal 23, power supply terminals 24 and 25, and a test terminal 26. The data terminal 23 is coupled to I / O circuitry 16. The test terminal 26 is coupled to test control circuitry 19.

[0016] The command address signal CA is supplied to command address terminal 21. Signals related to the address in the command address signal CA supplied to command address terminal 21 are transmitted to address decoder 32 via command address input circuit 31, and signals related to the command are transmitted to command decoder 33 via command address input circuit 31. Address decoder 32 decodes the address signals to generate row address XADD and column address YADD. Row address XADD is supplied to row decoder 12, and column address YADD is supplied to column decoder 13. The clock enable signal CKE in the command address signal CA is supplied to internal clock generator 35.

[0017] Complementary external clock signals CK and / or CK are supplied to clock terminal 22. Complementary external clock signals CK and / or CK are input to clock input circuit 34. Clock input circuit 34 generates an internal clock signal ICLK based on the complementary external clock signals CK and / or CK. The internal clock signal ICLK is supplied to at least command decoder 33 and internal clock generator 35. Internal clock generator 35 is activated, for example, by clock enable signal CKE, and generates an internal clock signal LCLK based on internal clock signal ICLK. Internal clock signal LCLK is supplied to I / O circuit 16. Internal clock signal LCLK serves as a timing signal that defines the timing for outputting read data DQ from data terminal 23 during a read operation. During a write operation, write data is input from an external source to data terminal 23. A data mask signal DM may be input from an external source to data terminal 23 during a write operation.

[0018] Power supply potentials VDD and VSS are supplied to power supply terminal 24. These power supply potentials VDD and VSS are supplied to voltage generator 36. Voltage generator 36 generates various internal potentials VPP, VOD, VARY, and VPERI based on the power supply potentials VDD and VSS. Internal potential VPP is mainly used in the line decoder 12, internal potentials VOD and VARY are mainly used in the sense amplifier 14 contained in the memory cell array 11, and internal potential VPERI is used in many other circuit blocks.

[0019] Power supply potentials VDDQ and VSSQ are supplied from power supply terminal 25 to I / O circuit 16. Although power supply potentials VDDQ and VSSQ can be the same as the power supply potentials VDD and VSS supplied to power supply terminal 24, dedicated power supply potentials VDDQ and VSSQ are allocated to I / O circuit 16 to prevent power supply noise occurring in I / O circuit 16 from propagating to other circuit blocks.

[0020] When an activity command is issued, command decoder 33 activates the activity signal ACT. The activity signal ACT is supplied to row decoder 12. When a read command or write command is issued externally after the activity command, command decoder 33 activates the column selection signal CYE. The column selection signal CYE is supplied to column decoder 13, and in response, activates a corresponding one of the sense amplifiers 14. Therefore, in a read operation, data is read from memory cell array 11. The read data read from memory cell array 11 is transferred to I / O circuit 16 via read / write amplifier 17 and FIFO (First-In-First-Out) circuit 18, and output to the outside from data terminal 23. In a write operation, write data that has been input from the outside via data terminal 23 is written into memory cell array 11 via I / O circuit 16, FIFO circuit 18, and read / write amplifier 17.

[0021] When a mode register set command is issued, the command decoder 33 activates the mode register set signal MRS. The mode register set signal MRS is supplied to the mode register 37. When the mode register set signal MRS is activated, various control parameters stored in the mode register 37 are overwritten.

[0022] like Figure 2 As shown, I / O circuit 16 has an output buffer 41 and an input receiver 42. The output node of output buffer 41 and the input node of input receiver 42 are coupled to a corresponding one of data terminals 23. I / O circuit 16 further includes a pre-driver 43, a latch circuit 44, multiplexers 45 and 46, a test register 47, and a comparator 48. Multiplexer 45 couples one of input nodes N1 and N2 to pre-driver 43 based on selection signal SEL1. Multiplexer 46 couples one of input nodes N3 and N4 to latch circuit 44 based on selection signal SEL2. Selection signals SEL1 and SEL2 can be switched via mode register 37 or via test control circuit 19.

[0023] like Figure 3 As shown, during a normal read operation, the input node N1 of the multiplexer 45 is selected via the selection signal SEL1. Therefore, the read data RD read from the memory cell array 11 is supplied to the output buffer 41 via the read data path 51, the multiplexer 45, and the pre-driver 43. This allows the read data RD to be output externally via the data terminal 23. This operation is also performed similarly during a read test operation using the data terminal 23 and during a normal read operation. This read test operation allows evaluation of the proper operation of the memory cell array 11, the read data path 51, the multiplexer 45, the pre-driver 43, and the output buffer 41.

[0024] like Figure 4As shown, during a normal write operation, the input node N3 of the multiplexer 46 is selected via the selection signal SEL2. Therefore, the write data WD from the external input to the data terminal 23 is latched by the latch circuit 44 via the input receiver 42 and the multiplexer 46. The write data WD latched by the latch circuit 44 is transmitted to the memory cell array 11 via the write data path 52 and written into the memory cell array 11. This operation is also performed similarly during the write test operation using the data terminal 23 and during the normal write operation. This write test operation allows evaluation of the proper operation of the input receiver 42, the multiplexer 46, the latch circuit 44, and the write data path 52. The input receiver 42 compares the level of the write data WD supplied to the data terminal 23 with the reference level Vref and generates internal write data based on the comparison result. The latch circuit 44 latches the internal write data synchronously with the write strobe signal WS.

[0025] The semiconductor device 10 according to an embodiment of the present invention can also perform write test operations and read test operations without using the data terminal 23. In this case, test data used in the write test operation is set into the test register 47. The setting of test data into the test register 47 is performed by the test control circuit 19. The test control circuit 19 is coupled to the test terminal 26, and therefore can set the test data without using the data terminal 23. The test data output from the test register 47 loops back in the I / O circuit 16 and is written to the memory cell array 11 via the write data path 52. The semiconductor device 10 according to an embodiment of the present invention has two loopback paths. The first loopback path passes through the output buffer 41 and the input receiver 42. The first loopback path is coupled to the data terminal 23. The first loopback path is selected during low-speed testing. The second loopback path bypasses the output buffer 41 and the input receiver 42. The second loopback path may not contain the data terminal 23. The second loopback path bypasses the first loopback path. The second loopback path is selected during high-speed testing. For example, for a test operation that is executed at a higher speed than the test operation when the first loopback path is selected, the second loopback path is selected.

[0026] During low-speed testing, input node N2 of multiplexer 45 is selected via selection signal SEL1, and input node N3 of multiplexer 46 is selected via selection signal SEL2, such as... Figure 5As shown in the diagram. When test write data TWD is output from test register 47 in this state, the test write data TWD is latched by latch circuit 44 via multiplexer 45, pre-driver 43, output buffer 41, input receiver 42, and multiplexer 46. The test write data TWD latched by latch circuit 44 is transmitted to memory cell array 11 via write data path 52 and written into memory cell array 11. Through this write test operation, the proper operation of multiplexer 45, pre-driver 43, output buffer 41, input receiver 42, multiplexer 46, latch circuit 44, and write data path 52 can be evaluated. Next, test read data TRD is read from memory cell array 11, as shown in the diagram. Figure 6 As shown in the diagram. Comparator 48 compares the test read data TRD with the preset expected value PD in test register 47. Comparator 48 compresses the comparison result to generate a comparison result signal CMP. The comparison result signal CMP is supplied to test control circuit 19. Test control circuit 19 generates a pass / fail signal P / F based on the comparison result signal CMP, and outputs the pass / fail signal P / F to the outside via test terminal 26. Through this read test operation, the normal operation of memory cell array 11 and read data path 51 can be evaluated.

[0027] In this way, during low-speed testing, the circuitry of the data input / output system, including the output buffer 41 and the input receiver 42, can be tested without using the data terminal 23. Therefore, even when the number of data terminals 23 is significantly large, operational testing can be performed in wafer state by probing the test terminal 26 without probing the data terminals 23. However, since the test write data TWD passes through the output buffer 41 and the input receiver 42 during low-speed testing, it is difficult to perform high-speed operations similar to those in normal operation. This is because the floating capacitance of the data terminal 23 is large, and the signal quality of the test write data TWD output from the output buffer 41 differs from the signal quality of the write data WD during normal operation.

[0028] During high-speed testing, input node N2 of multiplexer 45 is selected via selection signal SEL1, and input node N4 of multiplexer 46 is selected via selection signal SEL2, such as... Figure 7As shown in the diagram. This allows the output from pre-driver 43 to reach latch circuit 44 via test path 49. For example, the test path provides a shortcut between pre-driver 43 and latch circuit 44. When test write data TWD is output from test register 47 in this state, the test write data TWD is latched by latch circuit 44 via multiplexer 45, pre-driver 43, and multiplexer 46. The test write data TWD latched by latch circuit 44 is transmitted to memory cell array 11 via write data path 52 and written into memory cell array 11. Through this write test operation, the proper operation of multiplexer 45, pre-driver 43, multiplexer 46, latch circuit 44, and write data path 52 can be evaluated. Subsequently, the test read data TRD read from memory cell array 11 is compared with the expected value PD by comparator 48, and pass / fail signal P / F is generated by test control circuit 19, as shown in the reference. Figure 6 As explained, it can assess whether the memory cell array 11 and the read data path 51 are operating normally.

[0029] In this way, during high-speed testing, the circuitry of the data input / output system, excluding the output buffer 41 and input receiver 42, can be tested without using the data terminals 23. Therefore, even when the number of data terminals 23 is significantly large, operational testing can be performed in the wafer state by probing the test terminals 26 without probing the data terminals 23. Furthermore, since the test write data (TWD) bypasses the output buffer 41 and input receiver 42 during high-speed testing, high-speed operation similar to that in normal operation can be performed.

[0030] While the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the invention and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and will still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form variations of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. An apparatus comprising: Memory cell array; Data input / output terminals; A read data path and a write data path are coupled in parallel between the memory cell array and the data input / output terminals, wherein the read data path includes a pre-driver and an output buffer coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series. A first test path is configured to provide a shortcut between the pre-driver in the read data path and the latch circuitry in the write data path; as well as A second test path is configured to provide a shortcut between the memory cell array and the test control circuitry, wherein, during a read test operation, data output from the memory cell array bypasses the read data path via the second test path.

2. The device of claim 1, wherein in the first test operation, data output from the pre-driver bypasses the output buffer and the input receiver via the first test path.

3. The device of claim 2, wherein in the second test operation, data output from the pre-driver loops back to the latch circuit via the output buffer and the input receiver.

4. The device of claim 3, wherein the first test operation is performed at a higher speed than the second test operation.

5. The device of claim 1, further comprising a first multiplexer coupled between the input receiver and the latch circuit. The first multiplexer has a first input node coupled to the input receiver, a second input node coupled to the pre-driver via the first test path, and an output node coupled to the latch circuit.

6. The device of claim 5, further comprising a comparator, a test register, and a second multiplexer. The comparator has a first input node coupled to the test register, a second input node coupled to the memory cell array via the second test path, and an output node coupled to the test control circuit. The second multiplexer has a first input node coupled to the memory cell array, a second input node coupled to the test register, and an output node coupled to the pre-driver.

7. The apparatus of claim 6, wherein in the third test operation, data output from the memory cell array is supplied to the pre-driver via the second multiplexer.

8. The apparatus of claim 7, wherein in the fourth test operation, data output from the test register is supplied to the pre-driver via the second multiplexer.

9. The apparatus of claim 8, wherein the test control circuit is configured to set the data output from the test register in the test register and generate a pass / fail signal based on the data supplied by the comparator.

10. The device of claim 9, further comprising a test terminal coupled to the test control circuit. The test control circuit is configured to set the data into the test register based on test data supplied from the test terminals, and The test terminal is configured to output the pass / fail signal.

11. An apparatus comprising: Memory cell array; The test register is configured to store test data; Read the data path, which transmits the test data supplied from the test register; A write data path that transmits the test data to be written to the memory cell array; external terminals; A first loopback path and a second loopback path are configured to loop the test data from the read data path back to the write data path. The first loopback path is coupled to the external terminal, and The second loopback path does not include the external terminal; and Test the data reading path, which is configured to bypass the data reading path.

12. The device according to claim 11, further comprising: An output buffer configured to output the test data to the external terminal; as well as An input receiver configured to receive the test data from the external terminal. The first loopback path includes the output buffer and the input receiver.

13. The device of claim 12, wherein the second loopback path is configured to loop the test data from the read data path back to the write data path without passing through the output buffer and the input receiver.

14. The device of claim 13, wherein the first loopback path is selected in the first test operation.

15. The device of claim 14, wherein the second loopback path is selected in the second test operation.

16. The apparatus of claim 15, wherein the second test operation is performed at a higher speed than the first test operation.

17. The apparatus of claim 16, wherein the second test operation is performed in a wafer state.

18. An apparatus comprising: external terminals; An output buffer having a first input node and an output node coupled to the external terminal; An input receiver having an input node coupled to the external terminal and an output node; A multiplexer configured to select one of the data supplied to the first input node of the output buffer and the data output from the output node of the input receiver; as well as Test the data reading path, which is configured to bypass the output buffer, the input receiver, and the multiplexer.

19. The apparatus of claim 18, wherein the multiplexer is configured to select the data supplied to the first input node of the output buffer in a first test operation, and to select the data output from the output node of the input receiver in a second test operation.

20. The apparatus of claim 19, wherein the first test operation is performed at a higher speed than the second test operation.

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