Method for filling a gap and related system and device

Abstract

Methods and related systems for filling gap features included in a substrate are disclosed. The method includes the step of providing a substrate having one or more gap features into a reaction chamber. The one or more gap features includes an upper portion having an upper surface and a lower portion having a lower surface. The method also includes the step of subjecting the substrate to a plasma treatment. As a result, the upper surface is inhibited while the lower surface is substantially unaffected. Then, the method includes the step of selectively depositing a silicon-containing material on the lower surface.

Description

Technical Field

[0001] This disclosure generally relates to methods and systems suitable for forming electronic devices. More specifically, this disclosure relates to methods and systems that can be used to deposit materials in gaps, trenches, etc. Background Technology

[0002] The scaling up of semiconductor devices has led to significant increases in the speed and density of integrated circuits. However, with the miniaturization of wiring pitch in large-scale integrated devices, gapless filling of high aspect ratio gaps or trenches (e.g., trenches with an aspect ratio of 3 or higher) is becoming increasingly common due to limitations in existing deposition processes. Therefore, processes for efficiently filling high aspect ratio features, such as gaps like trenches on semiconductor substrates, are needed, for example, in the case of logic and / or memory devices. In particular, there is a need for processes that efficiently fill high aspect ratio features using silicon-containing materials, such as silicon oxide, capable of withstanding subsequent chemical mechanical polishing (CMP) steps and etching processes.

[0003] Any discussion set forth in this section (including discussions of problems and solutions) is included in this disclosure merely to provide background for this disclosure. Such discussion should not be construed as an admission that any or all information was known at the time of the invention's manufacture or constitutes prior art. Summary of the Invention

[0004] Various embodiments of this disclosure relate to gap-filling methods, structures and devices formed using such methods, and apparatus for performing the method and / or for forming the structure and / or device. The various embodiments of this disclosure address the shortcomings of existing methods and systems in more detail below.

[0005] This document describes a method for filling gap features on a substrate surface. The method includes, in a given sequence, the steps of positioning the substrate on a substrate support in a reaction chamber. The substrate includes one or more gap features. The one or more gap features include an upper portion having an upper surface and a lower portion having a lower surface. The method also includes a step of subjecting the substrate to a plasma pretreatment. The plasma treatment results in the upper surface being suppressed, while the lower surface remains substantially unaffected. The method further includes a step of selectively depositing a silicon-containing material on the lower surface. The step of selectively depositing the silicon-containing material on the lower surface includes a cyclic process. This cyclic process includes multiple sub-cycles. The sub-cycles, in a given sequence, include the step of exposing the substrate to a silicon precursor comprising amine groups and two or more silicon atoms. The substrate is specifically exposed to a silicon precursor pulsed to form a chemisorbed silicon precursor on the lower surface. The sub-cycle also includes a step of exposing the substrate to a post-silicon precursor pulsed plasma treatment, thereby allowing one or more active species included in the plasma to react with the chemisorbed silicon precursor on the lower surface.

[0006] In some embodiments, the amino group is selected from NH2, NHR i and NR i R ii , where R i and R ii At least one of them is a C1 to C4 alkyl group.

[0007] In some embodiments, the silicon precursor includes a compound selected from aminosilanes, silylamines, and cyclosiloxanes.

[0008] In some embodiments, the silicon precursor comprises alkylaminosilane.

[0009] In some embodiments, the silicon precursor includes silicon selected from SiR 1 R 3 R 4 -SiR 2 R 5 R 6 SiR 1 R 3 R 4 -SiR 5 R 6 -SiR 2 R 7 R 8 and SiR 1 R 3 R 4 -SiR 2 R 5 -SiR 6 R 7 R 8 The compound, wherein R 1 and R 2 It is NR 9 R 10 , where R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 Independently selected from H and C1 to C4 alkyl groups.

[0010] In some embodiments, the silicon precursor includes a selection from R 1 -SiH2-SiH3,R 1 -SiH2-SiH2-SiH2-R 2 and R 1 -SiH2-SiHR 2 Compounds of -SiH3, wherein R 1 and R 2 Independently selected from NH2, NHR9 and NR 9 R 10 And R 9 and R 10 Independently selected from H and C1 to C4 alkyl groups.

[0011] In some embodiments, R 3 and R 4 At least one of them is a C1 to C4 alkyl group.

[0012] In some embodiments, the silicon precursor comprises silylamine.

[0013] In some embodiments, the silicon precursor comprises a compound that can be represented by a chemical structure according to formula (1):

[0014]

[0015] Among them, R 11 and R 12 Independently selected from H and C1 to C4 alkyl groups.

[0016] In some embodiments, the silicon precursor comprises a cyclosiloxane having at least one amine group.

[0017] In some embodiments, the cyclosiloxane further includes one or more C1 to C4 alkyl substituents.

[0018] In some embodiments, the amino group is selected from NH2, NHR 13 and NR 13 R 14 , where R 13 and R 14 Independently selected from H and C1 to C4 alkyl groups.

[0019] In some embodiments, plasma pretreatment includes subjecting the substrate to a rare gas plasma.

[0020] In some embodiments, plasma pretreatment includes subjecting the substrate to nitrogen-containing plasma.

[0021] In some embodiments, plasma pretreatment includes subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment.

[0022] In some embodiments, the first plasma treatment includes generating a nitrogen-containing plasma in a reaction chamber.

[0023] In some embodiments, the nitrogen-containing plasma is an N2-containing plasma.

[0024] In some embodiments, the second plasma treatment includes generating a plasma containing rare gases in a reaction chamber.

[0025] In some embodiments, the rare gas plasma is an argon plasma.

[0026] In some embodiments, the substrate is maintained at a temperature of at least 100°C to at most 500°C.

[0027] In some embodiments, the reaction chamber is maintained at a pressure of at least 1 Torr and at most 20 Torr.

[0028] In some embodiments, the method includes performing multiple supercycles. The supercycles include: subjecting the substrate to plasma pretreatment; and selectively depositing a silicon-containing material on the lower surface.

[0029] In some embodiments, the post-silicon precursor pulsed plasma treatment includes generating an oxygen-containing plasma in a reaction chamber, and the silicon-containing material includes silicon oxide.

[0030] In some embodiments, the oxygen-containing plasma is an O2-containing plasma.

[0031] In some embodiments, the step of selectively depositing material on the lower surface is performed at least per sub-cycle. up to each sub-loop The growth rate is completed.

[0032] This document further describes a semiconductor processing apparatus. It includes a reaction chamber, which in turn includes a substrate support for supporting a substrate. The substrate includes one or more gap features. The semiconductor processing apparatus also includes a heater configured and arranged to heat the substrate in the reaction chamber. The semiconductor processing apparatus also includes a first plasma gas source fluidly connected to the reaction chamber via a first plasma gas valve. The semiconductor processing apparatus also includes a second plasma gas source fluidly connected to the reaction chamber via a second plasma gas valve. The semiconductor processing apparatus also includes a third plasma gas source fluidly connected to the reaction chamber via a third plasma gas valve. The semiconductor processing apparatus also includes a plasma module including a radio frequency (RF) power supply configured and arranged to generate plasma in the reaction chamber. The semiconductor processing apparatus also includes one or more silicon precursor sources fluidly connected to the reaction chamber via one or more precursor valves. The semiconductor processing apparatus also includes a controller configured to cause the apparatus to perform the methods described herein.

[0033] These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments, with reference to the accompanying drawings. The invention is not limited to any of the specific embodiments disclosed. Attached Figure Description

[0034] A more complete understanding of embodiments of this disclosure can be obtained by considering the following illustrative drawings and by referring to the detailed description and claims.

[0035] Figure 1 This is a schematic diagram of a plasma-enhanced atomic layer deposition (PEALD) apparatus suitable for depositing structures and / or performing methods according to at least one embodiment of the present disclosure.

[0036] Figure 2 A schematic diagram of a substrate (200) including a gap feature (210) is shown.

[0037] Figure 3 A schematic diagram of an embodiment of the method described herein is shown.

[0038] Figure 4 A schematic diagram of an embodiment of the method described herein is shown.

[0039] Figure 5 A schematic diagram of an embodiment of a method for selectively depositing silicon-containing material on the lower surface of a gap feature included in a substrate is shown.

[0040] Figure 6 A transmission electron microscope (TEM) image of silicon dioxide deposited in the gap features by an embodiment of the method described herein is shown.

[0041] Figure 7 A schematic diagram of an embodiment of a plasma-enhanced atomic layer deposition (PEALD) apparatus (700) is shown.

[0042] In all the figures, the following numbers are followed: 1 – Substrate; 2 – Lower platform / conductive plate electrode; 3 – Reaction chamber; 4 – Upper electrode / conductive plate electrode; 5 – Transfer chamber; 6 – Exhaust line; 11 – Interior of the reaction chamber; 12 – Electrical grounding side; 13 – Circular pipe; 14 – Separation plate; 16 – Interior of the transfer chamber; 7 – Exhaust line; 21 – Gas line; 22 – Gas line; 24 – Gas sealing line; 25 – Power supply; 200 – Substrate; 210 – Gap feature; 211 – Upper part; 212 – Lower part; 311 – Step of positioning the substrate on the substrate support; 312 – Step of subjecting the substrate to plasma treatment; 315 – Post-plasma purging; 316 – Depositing material on the lower surface The steps are as follows: 317 – Post-deposition purging; 318 – End of method; 319 – Repeat; 411 – Positioning the substrate on the substrate support; 412 – Exposing the substrate to a first plasma treatment; 413 – Inter-plasma purging; 414 – Exposing the substrate to a second plasma treatment; 415 – Post-plasma purging; 416 – Depositing silicon-containing material on the lower surface; 417 – Post-deposition purging; 418 – End of method; 419 – Repeat; 511 – Start of method; 512 – Exposing the substrate to the silicon precursor; 513 – Purging; 514 – Exposing the substrate to the post-precursor exposure plasma treatment; 515 – Purging; 516 – End of method; 517 – Repeat.

[0043] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the embodiments illustrated in this disclosure. Detailed Implementation

[0044] The following description of exemplary embodiments of methods, structures, devices, and systems is merely illustrative and for purposes of explanation only; the following description is not intended to limit the scope of this disclosure or the claims. Furthermore, the description of multiple embodiments having the described features is not intended to exclude other embodiments having additional features or other embodiments comprising different combinations of the described features. For example, various embodiments are set forth as exemplary embodiments and may be stated in the dependent claims. Unless otherwise stated, exemplary embodiments or their components may be combined or applied separately from each other.

[0045] In this disclosure, "gas" can include materials that are gaseous at ambient temperature and pressure (NTP), evaporated solids and / or evaporated liquids, and can consist of a single gas or a mixture of gases, depending on the circumstances. Gases other than process gases, i.e., gases introduced without passing through gas distribution components, multi-port injection systems, other gas distribution devices, etc., can be used, for example, to seal the reaction space, and may include sealing gases, such as rare gases. The terms "inert gas" and "rare gas" as used herein are used interchangeably. In some cases, the term "precursor" can refer to a compound that participates in a chemical reaction to produce another compound, particularly a compound constituting the membrane matrix or membrane backbone, or a compound incorporated into the membrane as a component; the term "reactant" is used interchangeably with the term "precursor."

[0046] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or films can be formed. Substrates can include bulk materials such as silicon (e.g., single-crystal silicon), other Group 4 materials such as germanium, or other semiconductor materials such as Group 2-6 or Group 3-5 semiconductor materials, and can include one or more layers on or under the bulk material.

[0047] Furthermore, in this disclosure, any two numbers of a variable may constitute a working range of the variable, and any indicated range may include or exclude endpoints. Additionally, any value of the indicated variable (whether or not it is indicated by “about”) may refer to an exact value or an approximate value and includes equivalents, and may refer to an average, median, representative value, multi-value, etc. Furthermore, in this disclosure, the terms “comprising,” “consisting of,” and “having” independently mean “generally or broadly comprising,” “consisting of,” or “substantially constitutes” in some embodiments. The meaning of any definition in this disclosure does not necessarily exclude the common and customary meaning in some embodiments.

[0048] As used herein, the term "comprising" means that certain features are included, but does not exclude the presence of other features, provided that they do not render the claims or embodiments impractical. In some embodiments, the term "comprising" includes "consisting of". As used herein, the term "consisting of" means that no other features exist in the device / method / product besides the features following the wording. When the term "consisting of" is used to refer to a chemical compound, it means that the chemical compound contains only the listed ingredients.

[0049] As used herein, the term "purging" refers to a process step that removes precursors and / or active species from a reaction chamber. During purging, an inert or substantially inert gas may be supplied to the reaction chamber. Alternatively, the reaction chamber may be evacuated during purging.

[0050] This document describes a method for filling gap features. The gap features are contained within a substrate and may be located at or near the substrate surface. Optionally, the substrate may include multiple gap features, for example, a plurality of gap features. The gap features include an upper portion having an upper surface and a lower portion having a lower surface. Suitable substrates include semiconductor wafers, such as silicon wafers. This method can be used in the fabrication processes of various semiconductor devices and is particularly useful for filling gap features with high aspect ratios and particularly small widths, such as widths less than 10 nm and aspect ratios greater than 2, 5, 10, or 20. The method includes the step of positioning the substrate on a substrate support in a reaction chamber. The method also includes the step of subjecting the substrate to a plasma pretreatment. The plasma pretreatment results in the upper surface being suppressed, while the lower surface is substantially unaffected. After the plasma pretreatment, the method further includes the step of selectively depositing a silicon-containing material on the lower surface. Optionally, purging is performed before the step of selectively depositing material on the lower surface. It should be understood that no plasma is generated in the reaction chamber during the purging process. Furthermore, it should be understood that the step of selectively depositing silicon-containing material on the lower surface includes a cyclic process comprising sub-steps that can be repeated continuously until a desired thickness of silicon-containing material is deposited on the lower surface. Exemplary silicon-containing materials include silicon oxide and silicon carbide. The cyclic process includes multiple cycles, also referred to as sub-cycles. A sub-cycle includes, in the following order: a step of exposing the substrate to a silicon precursor pulsed with silicon precursor, and a step of exposing the substrate to a post-silicon precursor pulsed plasma treatment. Optionally, purging is performed before the step of exposing the substrate to the silicon precursor. Optionally, purging is performed after the step of exposing the substrate to the silicon precursor. It should be understood that no plasma is generated in the reaction chamber during the purging process. The step of exposing the substrate to the silicon precursor results in chemisorption of the silicon precursor on the lower surface. In other words, by exposing the substrate to the silicon precursor, more silicon precursor is chemisorbed on the unpassivated lower surface compared to the plasma-passivated upper surface. The step of exposing the substrate to a post-silicon precursor pulsed plasma treatment results in a reaction between one or more active species contained in the plasma and a silicon precursor that is chemisorbed onto the lower surface during the step of exposing the substrate to the silicon precursor. In some embodiments, the method includes completely filling the interstitial feature with a silicon-containing material. This can be achieved, for example, by repeating the cyclic process until the entire interstitial feature is filled with silicon-containing material.

[0051] Advantageously, this method offers very short cycle times. In fact, the deposition time required to achieve a specific film thickness can be reduced by 50% or more, thus resulting in higher yields and less processing-induced damage to the underlying layers. An example of processing-induced damage is plasma-induced damage.

[0052] In some embodiments, the cyclic process includes from at least two sub-cycles to up to 20,000 sub-cycles. For example, the cyclic deposition process may include two, three, five, ten, twenty, thirty, sixty, one hundred, two hundred, five hundred, ten thousand, twenty thousand, twenty thousand, sixty, one hundred thousand, twenty thousand, twenty thousand, twenty thousand, twenty thousand, ten thousand, or more sub-cycles.

[0053] In some embodiments, the post-silicon precursor pulsed plasma treatment includes generating an oxygen-containing plasma in a reaction chamber, and the silicon-containing material includes silicon oxide. In some embodiments, the oxygen-containing plasma is an O2-containing plasma. Therefore, the methods disclosed herein can be used for various applications, such as filling gap features with seamless SiO2 for shallow trench insulation purposes. Compared to chemical mechanical polishing processes, this seamless shallow trench insulation can advantageously reduce leakage current, improve etch resistance, and enhance resilience. Furthermore, this SiO2 film can have a very low carbon content. Additionally, this SiO2 film can have a very low nitrogen content.

[0054] In some embodiments, the post-silicon precursor pulsed plasma treatment includes exposing the substrate to oxygen plasma, with O2 used as the plasma gas. In some embodiments, O2 is supplied to the reaction chamber at a flow rate of at least 100 sccm to at most 10000 sccm, or at least 200 sccm to at most 5000 sccm, or at least 500 sccm to at most 1000 sccm. In some embodiments, the oxygen plasma is generated by means of an RF generator operating at a plasma power of at least 50 W to at most 200 W. In some embodiments, the oxygen plasma is generated during an oxygen plasma pulse for at least 0.1 s to at most 10 s, or at least 0.2 s to at most 5 s, or at least 0.5 s to at most 2 s. In some embodiments, the substrate is purged after exposure to the oxygen plasma for at least 0.2 s to at most 10 s, or at least 1 s to at most 5 s. It should be understood that no plasma is generated in the reaction chamber during the purging.

[0055] In some embodiments, the step of selectively depositing material on the lower surface is at least / Loop to at most / The growth rate of the cycle proceeds, for example at least / Loop to at most / cycle or at least / Loop to at most / Cycle growth rate. For example, the material at... The growth rate of the cycle is deposited on the lower surface. In some embodiments, the growth rate on the upper surface is at least 2 to at most 20 times slower than that on the lower surface. In some embodiments, the growth rate on the upper surface is at least 2 to at most 5 times slower than that on the upper surface. In some embodiments, the growth rate on the upper surface is at least 5 to at most 10 times slower than that on the upper surface. In some embodiments, the growth rate on the upper surface is at least 10 to at most 20 times slower than that on the upper surface. In some embodiments, the growth rate on the upper surface is less than... / cycle. In some embodiments, the growth rate of the upper surface is / cycle.

[0056] Surprisingly, it was found that high growth rates and bottom-up growth can be achieved using specific silicon precursors. Therefore, in some embodiments, the silicon precursor comprises an amine group and two or more silicon atoms.

[0057] In some embodiments, the silicon precursor comprises a compound selected from aminosilanes, silylamines, and cyclosiloxanes. Exemplary silicon precursors and methods for their preparation are disclosed, for example, in WO2015048237A2, WO2015047914A1, and US10192734B2.

[0058] In some embodiments, the amino group is selected from NH2, NHR i and NR i R ii In some embodiments, R i and R ii It is a hydrocarbon group. In some embodiments, R i and R ii They are the same. In some embodiments, R i and R ii They are different. In some embodiments, R i and R ii Independently selected from C1 to C4 alkyl or alkenyl groups. In some embodiments, R i and R ii At least one of them is a C1 to C4 alkyl group.

[0059] In some embodiments, the silicon precursor comprises an alkylaminosilane. In some embodiments, the silicon precursor is a silane or trisilane containing one or more amino groups.

[0060] In some embodiments, the silicon precursor is selected from SiR 1 R 3 R 4 -SiR 2 R 5 R 6 SiR 1 R 3 R 4-SiR 5 R 6 -SiR 2 R 7 R 8 and SiR 1 R 3 R 4 -SiR 2 R 5 -SiR 6 R 7 R 8 It should be understood that R 1 and R 2 It is NR 9 R 10 , where R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 Independently selected from H and hydrocarbon groups. In some embodiments, R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 Independently selected from H, C1 to C4 alkyl, C1 to C4 alkenyl, and C4 to C8 aryl. In some embodiments, R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 Independently selected from H and C1 to C4 alkyl groups. In some embodiments, R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 At least one of them is H. In some embodiments, R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 At least one of them is methyl. In some embodiments, R 3 ,R4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 At least one of them is ethyl. In some embodiments, R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 At least one of them is propyl. In some embodiments, R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 At least one of them is isopropyl. In some embodiments, R 3 ,R 4 ,R 5 ,R 6 R 7 ,R 8 R 9 and R 10 All are methyl groups. In some embodiments, the silicon precursor comprises dimethylaminopentamethyldisilane.

[0061] In some embodiments, the silicon precursor is selected from R 1 -SiH2-SiH3,R 1 -SiH2-SiH2-SiH2-R 2 and R 1 -SiH2-SiHR 2 -SiH3, where R 1 and R 2 Independently selected from NH2, NHR 9 and NR 9 R 10 And R 9 and R 10 Independently selected from H and C1 to C4 hydrocarbon groups. In some embodiments, R 9 and R 10 Independently selected from H, C1 to C4 alkyl, C1 to C4 alkenyl, and C1 to C4 aryl. In some embodiments, R 9 and R 10 Independently selected from H and C1 to C4 alkyl groups. In some embodiments, R 9 and R 10At least one of them is H. In some embodiments, R 9 and R 10 At least one of them is methyl. In some embodiments, R 9 and R 10 At least one of them is ethyl. In some embodiments, R 9 and R 10 At least one of them is propyl. In some embodiments, R 9 and R 10 At least one of them is isopropyl. In some embodiments, R 9 and R 10 It is methyl. In some embodiments, R 3 and R 4 At least one of them is a C1 to C4 alkyl group. In some embodiments, the silicon precursor comprises an alkylaminosilane selected from diisopropylaminodisilane and di-n-butylaminodisilane.

[0062] In some embodiments, the silicon precursor comprises silylamine.

[0063] In some embodiments, the silicon precursor may be represented by a chemical formula according to formula (i):

[0064]

[0065] Among them, R 11 and R 12 Independently selected from H and C1 to C4 alkyl groups. In some embodiments, R 11 and R 12 At least one of them is H. In some embodiments, R 11 and R 12 At least one of them is methyl. In some embodiments, R 11 and R 12 At least one of them is ethyl. In some embodiments, R 11 and R 12 At least one of them is propyl. In some embodiments, R 11 and R 12 At least one of them is butyl. In some embodiments, R 11 and R 12 At least one of them is isopropyl. In some embodiments, R 11 and R 12 It is isopropyl.

[0066] In some embodiments, the silicon precursor comprises a cyclosiloxane having at least one amino group. In some embodiments, the amino group is selected from NH2, NHR. i and NR i R ii In some embodiments, Ri and R ii It is a hydrocarbon group. In some embodiments, R i and R ii They are the same. In some embodiments, R i and R ii They are different. In some embodiments, R i and R ii Independently selected from C1 to C4 alkyl or alkenyl groups. In some embodiments, R i and R ii At least one of them is a C1 to C4 alkyl group. In some embodiments, the amino group is selected from NH2, NHR 13 and NR 13 R 14 R 13 and R 14 Independently selected from H and C1 to C4 alkyl groups.

[0067] In some embodiments, the cyclosiloxane further comprises one or more C1 to C4 alkyl substituents. In some embodiments, at least one of the C1 to C4 alkyl substituents is methyl. In some embodiments, at least one of the C1 to C4 alkyl substituents is ethyl. In some embodiments, at least one of the C1 to C4 alkyl substituents is propyl. In some embodiments, at least one of the C1 to C4 alkyl substituents is butyl. A suitable siloxane comprises 2-diethylamino-2,4,6,8-tetramethylcyclotetrasiloxane.

[0068] It should be understood that the application of plasma pretreatment results in suppression of the upper surface, while the lower surface is essentially unaffected, or at least less affected than the upper surface. In other words, the reactivity of the upper surface to the silicon precursor that can subsequently be supplied to the reaction chamber can be appropriately reduced. In other words, subjecting the substrate to plasma pretreatment results in a suppression gradient in the gap characteristics. Specifically, the suppression is stronger in the upper part of the gap than in the lower part. In other words, the suppression gradually decreases from the upper part of the gap to the lower part. This invention is not limited to any particular theory or mode of operation; it is believed that the suppression at the upper surface is caused by the depletion of reactive surface groups such as hydroxyl and amino groups near the top of the surface, while reactive surface groups near the lower surface, i.e., near the bottom of the trench, are considered to be fewer or unaffected by plasma pretreatment.

[0069] Plasma pretreatment using no more than one type of plasma advantageously results in short cycle times. Furthermore, when the plasma is maintained for only a short time, such as at least 5 seconds to at most 15 seconds, a dielectric layer, such as SiO2, with advantageous properties such as low leakage and high breakdown voltage can be obtained. When the dielectric layer is deposited on or near the channel region in a transistor (e.g., a silicon transistor or a thin-film transistor), high electron mobility in the transistor channel can be advantageously obtained.

[0070] In some embodiments, plasma pretreatment results in a passivation gradient from the upper surface to the lower surface, i.e., a gradual change in passivation intensity. In this case, the step of exposing the substrate to the precursor causes the density of chemisorbed precursor per unit area to gradually change from the lower surface to the upper surface. Post-silicon precursor pulsed plasma treatment then allows one or more active species contained in the plasma to react with the chemisorbed precursor to form material. Since more precursor is chemisorbed on the lower surface compared to the upper surface, more material is formed on the lower surface compared to the upper surface. In other words, the material is selectively grown in a bottom-up manner.

[0071] In some embodiments, plasma pretreatment includes subjecting the substrate to a rare gas plasma. In some embodiments, the rare gas plasma is an argon plasma.

[0072] In some embodiments, plasma pretreatment includes subjecting the substrate to a nitrogen-containing plasma. In some embodiments, the nitrogen-containing plasma is an N2 plasma. In some embodiments, the nitrogen-containing plasma is an NH3 plasma.

[0073] In some embodiments, plasma pretreatment includes exposing the substrate to H2-N2 plasma. It should be understood that H2-N2 plasma refers to plasma employing a plasma gas comprising H2 and N2. H2-N2 plasma can be advantageously used to fill gaps with silicon-containing materials using alkylaminosilanes, such as bis(diethylamino)silane.

[0074] In some embodiments, plasma pretreatment includes subjecting the substrate to a hydrogen-containing plasma. In some embodiments, the hydrogen-containing plasma is an H2 plasma.

[0075] In some embodiments, plasma pretreatment includes subjecting the substrate to a first plasma treatment and a second plasma treatment. It should be understood that the first and second plasma treatments are different, i.e., not identical. Optionally, the first and second plasma treatments are separated by purging. It should be understood that no plasma is generated in the reaction chamber during purging.

[0076] In some embodiments, the first plasma treatment includes generating a nitrogen-containing plasma in a reaction chamber. In some embodiments, the nitrogen-containing plasma is an N2-containing plasma. In other words, in some embodiments, a plasma gas including N2 is used to generate the nitrogen-containing plasma.

[0077] In some embodiments, the second plasma treatment includes generating a rare gas-containing plasma in a reaction chamber. In some embodiments, the rare gas-containing plasma is an argon-containing plasma.

[0078] In some embodiments, the first plasma treatment includes generating a nitrogen plasma in a reaction chamber, and the second plasma treatment includes generating a rare gas plasma in a reaction chamber. In such embodiments, materials such as silicon oxide shallow trench isolation selectively deposited after the first and second plasma treatments can advantageously have negligible C residue and high-quality film characteristics. Furthermore, when the substrate comprises Si fins, these plasma treatments advantageously limit or avoid oxidation of the silicon fins. Additionally, using a rare gas plasma after the nitrogen plasma can advantageously reduce or eliminate the amount of N-containing surface groups (also known as nitrogen residue) on the substrate.

[0079] In some embodiments, the first plasma treatment includes exposing a substrate to a nitrogen plasma, and the plasma gas comprising N2. In some embodiments, N2 is supplied to the reaction chamber at a flow rate of at least 200 sccm to at most 2000 sccm, or at least 400 sccm to at most 1200 sccm, or at least 600 sccm to at most 1000 sccm. In some embodiments, the nitrogen plasma is generated by an RF generator at a plasma power of at least 100 W to at most 1000 W, for example, at a plasma power of at least 200 W to at most 500 W. In some embodiments, the N2 plasma generation lasts for at least 5 s to at most 50 s, for example, for at least 10 s to at most 20 s. In some embodiments, the N2 plasma generation lasts for at least 0.01 s to at most 50 s, for example, for at least 0.2 s to at most 20 s, for example, for at least 0.5 s to at most 10 s, for example, for at least 1 s to at most 5 s. In some embodiments, the N2 plasma is followed by a purging lasting for at least 1 s to at most 5 s. In some embodiments, a purging process lasting from at least 0.1 s to at most 10 s is performed after the N2 plasma. It should be understood that no plasma is generated in the reaction chamber during the purging. Furthermore, it should be understood that a purging time of at least 1 s may be particularly advantageous when the plasma gas changes between processing steps, such as when the substrate is first subjected to a first plasma treatment and then to a second plasma treatment.

[0080] In some embodiments, the second plasma treatment includes exposing the substrate to argon plasma, and the plasma gas comprising Ar. In some embodiments, Ar is supplied to the reaction chamber at a flow rate of at least 1 slm to at most 10 slm or at a flow rate of at least 2 slm to at most 5 slm. In some embodiments, the argon plasma is generated by an RF generator at a plasma power of at least 100 W to at most 1000 W, for example, at a plasma power of at least 200 W to at most 500 W. In some embodiments, the argon plasma generation lasts for at least 5 s to at most 50 s, for example, at least 10 s to at most 20 s. In some embodiments, the argon plasma is followed by purging, which lasts for at least 0.1 s to at most 2 s, for example, at least 0.2 s to at most 1 s. It should be understood that no plasma is generated in the reaction chamber during purging. Note that the above values ​​are given when a 300 mm wafer is used as the substrate, and these values ​​can be readily applied to different substrate sizes if desired.

[0081] In some embodiments, the substrate is maintained at a temperature of at least 100°C to at most 500°C, or at least 100°C to at most 200°C, or at least 200°C to at most 300°C, or at least 300°C to at most 400°C, or at least 400°C to at most 500°C.

[0082] In some embodiments, the reaction chamber is maintained at a pressure of at least 0.1 Torr to at most 200 Torr, or at least 0.2 Torr to at most 100 Torr, or at least 0.5 Torr to at most 50 Torr, or at least 1 Torr to at most 20 Torr, or at least 2 Torr to at most 10 Torr, for example, the reaction chamber may be maintained at a pressure of 5 Torr.

[0083] In some embodiments, the silicon precursor pulse lasts for at least 1 s to at most 20 s, or at least 2 s to at most 10 s, or at least 3 s to at most 5 s. In some embodiments, the silicon precursor pulse lasts for at least 0.1 s to at most 20 s, or at least 0.2 s to at most 10 s, or at least 0.5 s to at most 5 s, or at least 1 s to at most 2 s. In some embodiments, a purging process is performed after the silicon precursor pulse, lasting for at least 0.2 s to at most 20 s, or at least 0.5 s to at most 10 s, or at least 1 s to at most 5 s. It should be understood that no plasma is generated in the reaction chamber during the purging process.

[0084] In some embodiments, the method includes performing multiple supercycles consecutively. A supercycle includes a step of subjecting a substrate to plasma pretreatment; and a step of selectively depositing a silicon-containing material on a lower surface. In some embodiments, the method includes performing supercycles at least 5 to at most 10,000 times, or at least 10 to at most 5,000 times, or at least 20 to at most 2,000 times, or at least 50 to at most 1,000 times, or at least 100 to at most 500 times. In some embodiments, the method includes performing at least 5 to at most 50 times, or at least 10 to at most 20 times, of supercycles. In some embodiments, consecutive supercycles are separated from each other by purging. It should be understood that no plasma is generated in the reaction chamber during purging.

[0085] This document further describes a semiconductor processing apparatus. The apparatus includes a reaction chamber, a heater, a first plasma gas source, a second plasma gas source, a plasma module, one or more precursor sources, and a controller. Optionally, the apparatus also includes a third plasma gas source. A substrate support suitably allows support of a substrate including one or more gap features. The heater is configured and arranged to heat the substrate in the reaction chamber. The first plasma gas source is in fluid communication with the reaction chamber via a first plasma gas valve. The first plasma gas source may be arranged to, for example, supply a nitrogen-containing gas and / or a rare gas-containing gas to the reaction chamber. The second plasma gas source is in fluid communication with the reaction chamber via a second plasma gas valve. The second plasma gas source may be arranged to, for example, supply an oxygen-containing gas to the reaction chamber. When present, a third plasma gas source may be in fluid communication with the reaction chamber via a third plasma gas valve. The third plasma gas source may be arranged to, for example, supply a nitrogen-containing gas and / or a rare gas-containing gas to the reaction chamber. The plasma module includes a radio frequency power supply configured and arranged to generate plasma in the reaction chamber. One or more precursor sources are in fluid communication with the reaction chamber via one or more precursor valves. Suitable, the semiconductor processing apparatus may further include venting means for discharging reaction products, carrier gas, and unused precursors and co-reactants. The controller includes a processor and one or more memory modules, and is programmed or otherwise configured to cause the apparatus to perform the methods described herein.

[0086] Optionally, the system is configured to provide at least one precursor to the reaction chamber via a carrier gas. Suitable carrier gases include rare gases. In other words, in some embodiments, the semiconductor processing system includes a gas injection system that includes a precursor delivery system that uses a carrier gas to transport the precursor to one or more reaction chambers.

[0087] The currently provided method can be executed on any suitable device, including, for example, Figure 1 An embodiment of the semiconductor processing system shown. Figure 1This is a schematic diagram of a plasma-enhanced atomic layer deposition (PEALD) apparatus that can be used in some embodiments of the present invention. In this diagram, plasma can be generated between the electrodes by providing a pair of parallel and facing conductive plate electrodes (2, 4) in the interior (11) (reaction zone) of the reaction chamber (3), applying RF power (e.g., at 13.56 MHz and / or 27 MHz) from a power source (25) to one side, and electrically grounding the other side (12). Of course, the semiconductor processing apparatus does not need to generate plasma during the step of providing the precursor to the reaction chamber, or during the purging between subsequent processing steps, and it is not necessary to apply RF power to either electrode during these steps or purging. A temperature regulator can be disposed in the lower platform (2), i.e., the lower electrode. A substrate (1) is placed on it, and its temperature is kept constant at a given temperature. The upper electrode (4) can also be used as a spray plate, and various gases such as plasma gas, reactant gas and / or dilution gas (if any) and precursor gas can be introduced into the reaction chamber (3) through gas lines (21) and gas lines (22) and through the spray plate (4), respectively. Furthermore, a circular pipe (13) with an exhaust line (7) is provided in the reaction chamber (3) through which the gas inside the reaction chamber (3) (11) is discharged. In addition, a transfer chamber (5) is provided below the reaction chamber (3) and is provided with a gas sealing line (24) to introduce sealing gas into the interior of the reaction chamber (3) (11) via the interior (16) of the transfer chamber (5), wherein a separation plate (14) for separating the reaction zone and the transfer zone is provided.

[0088] Note that the gate valve, through which the wafer can be transferred to or from the transfer chamber (5), is omitted from the figure. The transfer chamber is also provided with an exhaust line (6). In some embodiments, silicon oxide deposition and surface treatment are performed in the same reaction space, so that all steps can be performed continuously without any intermediate steps of venting the reaction chamber, emptying the reaction chamber, or exposing the substrate to the atmosphere.

[0089] Figure 2 A schematic diagram of a substrate (200) including a gap feature (210) is shown. The gap feature (210) includes an upper portion (211) and a lower portion (212). The upper portion (211) includes an upper surface, and the lower portion (212) includes a lower surface. The upper surface can be substantially suppressed by subjecting the substrate (200) to a first plasma treatment and a second plasma treatment. In other words, the first and second plasma treatments can appropriately reduce the upper surface from reacting with the precursor compared to the lower surface.

[0090] Figure 3A schematic diagram of an embodiment of the method described herein is shown. The method includes the step of positioning a substrate on a substrate support (311). The substrate includes a gap feature. The substrate is then subjected to a plasma treatment (312), as described herein. Optionally, a reaction chamber is then purged using a post-plasma purging (315). For example, purging can be performed using a basic inert gas such as a rare gas. Exemplary rare gases include He, Ne, Ar, Xe, and Kr. The method also includes the step of depositing a silicon-containing material on the lower surface of the gap feature using the techniques described herein (316). Optionally, a post-deposition purging is then used to purge the reaction chamber (317). It should be understood that no plasma is generated in the reaction chamber during the purging process. The steps from subjecting the substrate to plasma treatment (312) to depositing silicon-containing material on the lower surface of the gap feature (316) can optionally be repeated (319) once or more, thereby creating multiple supercycles that include subsequent plasma treatments and subsequent deposition steps. Optionally, the subsequent supercycles are separated by purging. Therefore, silicon-containing material is deposited in the interstitial features. The method ends when the required amount of material has been deposited in the interstitial features (318).

[0091] Figure 4 A schematic diagram of an embodiment of the method described herein is shown. The method includes the step of positioning a substrate on a substrate support (411). The substrate includes a gap feature. The substrate is then subjected to a first plasma treatment (412), as described herein. Optionally, the reaction chamber is then purged using inter-plasma purging (413). For example, purging can be performed using a basic inert gas such as a rare gas. Exemplary rare gases include He, Ne, Ar, Xe, and Kr. The method also includes the step of subjecting the substrate to a second plasma treatment (414), as described herein. Optionally, the reaction chamber is then purged using post-plasma purging (415). The method also includes the step of depositing a silicon-containing material on the lower surface of the gap feature using the techniques described herein (416). Optionally, the reaction chamber is then purged using post-deposition purging (417). It should be understood that no plasma is generated in the reaction chamber during the purging process. The steps from subjecting the substrate to a first plasma treatment (412) to depositing silicon-containing material on the lower surface of the gap feature can optionally be repeated (419) once or multiple times, resulting in multiple supercycles that include subsequent first and second plasma treatments and subsequent deposition steps. Thus, silicon-containing material is deposited in the gap feature. The method ends (418) when the required amount of silicon-containing material has been deposited in the gap.

[0092] Figure 5 A schematic diagram of an embodiment of a method for selectively depositing silicon-containing material on the lower surface of a gap feature included in a substrate is shown. Figure 5The method shown corresponds in part to, for example, Figure 3 The step (316) of depositing silicon-containing material on the lower surface is shown, and / or as shown in the figure. Figure 4 The step of depositing silicon-containing material on the lower surface (416) is shown and begins after a step of subjecting the substrate to plasma treatment, or after a step of subjecting the substrate to a first plasma treatment and a second plasma treatment, or optionally after a purging following any such step (511). As described herein, the substrate is exposed to a silicon precursor chemisorbed on the lower surface (512). Optionally, the reaction chamber is then purged (513). The method then includes a step of subjecting the substrate to a third plasma treatment (514). Optionally, the reaction chamber is then purged (515). It should be understood that no plasma is generated in the reaction chamber during the purging process. The steps from exposing the substrate to the silicon precursor (512) to subjecting the substrate to the third plasma treatment (514) can optionally be repeated (517) once or more, thereby creating multiple sub-cycles. Thus, silicon-containing material is deposited in the gap features. The method ends (516) when the required amount of silicon-containing material has been deposited in the gaps.

[0093] Figure 6 Transmission electron microscopy (TEM) images of silicon oxide deposited in the gap features by an embodiment of the method described herein are shown. Specifically, multiple supercycles were used, comprising sequential plasma pretreatment and selective deposition of silicon oxide on the lower surface. The plasma pretreatment included exposing the substrate to nitrogen plasma, followed by exposing the substrate to argon plasma. During the nitrogen plasma, an N2 flow rate of 800 sccm and a plasma power of 300 W (i.e., radio frequency (RF) power) were used, the N2 plasma was held for 8 seconds, and a 2-second inter-plasma purge time was used. During the argon plasma, an Ar flow rate of 3.7 slm and a plasma power of 500 W (RF power) were used, the argon plasma was used for 8 seconds, and a 5-second post-plasma purge time was used. Diisopropylaminotriisopropylamine was used as the silicon precursor. The post-silicon precursor pulsed plasma treatment included exposing the substrate to O2 plasma. During the O2 plasma, an O2 flow rate of 800 sccm and a plasma power of 100 W (RF power) were used. The O2 plasma was held for 1 second. After the O2 plasma is applied, the reaction chamber is purged for 2 seconds. This process is repeated for 100 supercycles. The reaction chamber is maintained at a pressure of 5 Torr, and the substrate is maintained at a temperature of 300°C. Using this process, the unpassivated lower portion of the gap feature was obtained. / Growth in each cycle, and / Growth per cycle. Therefore, bottom-up growth of interstitial features can be obtained at an astonishingly high growth rate.

[0094] exist Figure 6 In this process, plasma pretreatment, i.e., plasma suppression, is used after each sub-cycle, which includes silicon precursor-post-silicon precursor pulsed plasma treatment. Alternatively, plasma pretreatment can be repeated only every few sub-cycles, such as every 3 sub-cycles, every 5 sub-cycles, every 10 sub-cycles, every 20 sub-cycles, or every 50 sub-cycles. This alternative process can advantageously increase yield and reduce plasma-induced damage, such as Si or Ge oxidation, although this comes at the cost of sacrificing top-bottom selectivity.

[0095] Figure 7 Selected components of an embodiment of a plasma-enhanced atomic layer deposition (PEALD) apparatus (700) for performing the methods described herein are shown. The apparatus (700) includes a gas line (710), a bypass valve (720), a bypass line (730), a reactor (740), and an exhaust line (750). Such an apparatus, including the bypass valve (720), can suitably increase the yield of the methods described herein. In particular, the bypass valve (720) can be used to allow continuous gas flow, even when a specific process gas is not required in the reaction chamber. Therefore, the use of the bypass valve (720) can allow the avoidance of a gas stabilization step during the processing of multiple wafers and can make it easier to switch processing steps to different gas compositions, thereby increasing yield.

[0096] Furthermore, the bypass valve allows for continuous flow of certain gases, thus reducing particulate contamination by avoiding pressure pulsations through the pipeline. Additionally, flow can be initiated in bypass mode, thus preventing initial particles from bursting into the chamber upon startup (first wafer effect, pre-recipe requirements, etc.).

[0097] The gas line (710) can be a line carrying any of the gases described herein, such as a silicon precursor gas line, a rare gas line, a nitrogen line, or an oxygen line. Advantageously, the device (700) includes multiple gas lines, such as a silicon precursor gas line, a rare gas line, a nitrogen line, and an oxygen line.

[0098] Therefore, in some embodiments, the silicon precursor is transferred through a silicon precursor bypass channel during the step of subjecting the substrate to plasma pretreatment.

[0099] Alternatively, during the step of exposing the substrate to the silicon precursor, plasma gas is transferred through a plasma gas bypass channel.

[0100] In some embodiments, during the step of depositing silicon-containing material, a bypass valve is used to transfer the plasma gas used during plasma pretreatment.

[0101] In some embodiments, a bypass valve is used to transfer the silicon precursor during plasma pretreatment and during the step of exposing the substrate to post-silicon precursor pulsed plasma treatment.

[0102] In some embodiments, a bypass valve is used to transfer the plasma gas used in the step of exposing the substrate to plasma pretreatment and the step of exposing the substrate to a silicon precursor.

[0103] The exemplary embodiments described herein do not limit the scope of the invention, as these embodiments are merely examples of embodiments of the invention, which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the invention. In fact, various modifications to this disclosure, such as alternative and useful combinations of the described elements, will become apparent to those skilled in the art from the description, in addition to those shown and described herein. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

[0104] In this disclosure, where conditions and / or structures are not specified, such conditions and / or structures can be readily provided by those skilled in the art in light of this disclosure as matters of routine experimentation.

Claims

1. A method for filling gap features on a substrate surface, the method comprising, in a given order: - The step of positioning a substrate on a substrate support in a reaction chamber, wherein the substrate includes one or more gap features, the one or more gap features including an upper portion having an upper surface and a lower portion having a lower surface; - The step of subjecting the substrate to plasma pretreatment suppresses the reactivity of the upper surface with the silicon precursor subsequently supplied to the reaction chamber, resulting in stronger suppression in the upper part of the gap than in the lower part of the gap; as well as - A step of selectively depositing silicon-containing material on the lower surface; The step of selectively depositing silicon-containing material on the lower surface includes a cyclic process comprising multiple sub-cycles, which include, in a given order: - The step of exposing the substrate to a silicon precursor pulsed with silicon precursor, thereby forming a chemisorbed silicon precursor on the lower surface; and - The step of exposing the substrate to a post-silicon precursor pulsed plasma treatment, thereby allowing one or more active species included in the plasma to react with the chemisorbed silicon precursor on the lower surface; The silicon precursor comprises an amino group and two or more silicon atoms. The plasma pretreatment includes subjecting the substrate to a first plasma treatment and a second plasma treatment, wherein the first plasma and the second plasma are different, and the first and second plasmas are separated by purging. Wherein, the amino group is selected from NHR i and NR i R ii , where R i and R ii At least one of them is a C1 to C4 alkyl group.

2. The method according to claim 1, wherein, The silicon precursor includes compounds selected from aminosilanes, silylamines, and cyclosiloxanes.

3. The method according to claim 1, wherein, The silicon precursor includes alkylaminosilane.

4. The method according to claim 1, wherein, The silicon precursor includes silicon-based precursors selected from SiR. 1 R 3 R 4 -SiR 2 R 5 R 6 SiR 1 R 3 R 4 -SiR 5 R 6 -SiR 2 R 7 R 8 and SiR 1 R 3 R 4 -SiR 2 R 5 -SiR 6 R 7 R 8 The compound, wherein R 1 and R 2 It is NR 9 R 10 , where R 3 , R 4 , R 5 , R 6 R 7 , R 8 R 9 and R 10 Independently selected from H and C1 to C4 alkyl groups.

5. The method according to claim 1, wherein, The silicon precursor includes silylamine.

6. The method according to claim 5, wherein, The silicon precursor comprises a compound whose chemical structure can be represented according to formula (1): (1) Among them, R 11 and R 12 Independently selected from H and C1 to C4 alkyl groups.

7. The method according to claim 1, wherein, The silicon precursor comprises a cyclosiloxane having at least one amine group.

8. The method according to claim 1, wherein, The first plasma treatment includes generating a nitrogen-containing plasma in the reaction chamber.

9. The method according to claim 8, wherein, The nitrogen-containing plasma is an N2-containing plasma.

10. The method according to any one of claims 1 to 7, wherein, The second plasma treatment includes generating a rare gas-containing plasma in the reaction chamber.

11. The method according to any one of claims 1 to 7, comprising executing a plurality of superloops, wherein the superloops include: - A step of subjecting the substrate to plasma pretreatment; as well as - The step of selectively depositing silicon-containing material on the lower surface.

12. The method according to any one of claims 1 to 7, wherein, The post-silicon precursor pulsed plasma treatment includes generating oxygen-containing plasma in the reaction chamber, wherein the silicon-containing material comprises silicon oxide.

13. The method according to any one of claims 1 to 7, wherein, During the step of subjecting the substrate to plasma pretreatment, the silicon precursor is transferred through a silicon precursor bypass channel.

14. The method according to any one of claims 1 to 7, wherein, During the step of exposing the substrate to the silicon precursor, plasma gas is transferred through a plasma gas bypass channel.

15. A semiconductor processing apparatus, comprising: - A reaction chamber, which includes a substrate support for supporting a substrate having one or more gap features; - A heater, constructed and arranged to heat a substrate in a reaction chamber; - A first plasma gas source, which is in fluid communication with the reaction chamber via a first plasma gas valve; - A second plasma gas source, which is fluidly connected to the reaction chamber via a second plasma gas valve; - A third plasma gas source, which is fluidly connected to the reaction chamber via a third plasma gas valve; - A plasma module, which includes a radio frequency power supply configured and arranged to generate plasma in a reaction chamber; - One or more silicon precursor sources, fluidly connected to the reaction chamber via one or more precursor valves; and - A controller configured to cause the device to perform the method according to any one of claims 1 to 14.

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