A stacked packaging method for depletion-type GaNHEMT devices
By stacking and packaging GaN HEMT devices with Si VDMOS chips, the problem of heat management at high temperatures was solved, achieving high heat dissipation and improved reliability, while reducing production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN JINYU SEMICON CO LTD
- Filing Date
- 2022-02-16
- Publication Date
- 2026-06-16
AI Technical Summary
Existing technologies struggle to effectively manage the heat of GaN HEMT devices under high-temperature conditions, leading to reduced device reliability and premature failure. Therefore, there is an urgent need for advancements in packaging technologies and materials.
A stacked packaging method is used to co-package depletion-mode GaN HEMT devices with Si VDMOS chips. By increasing the packaging density and heat dissipation, silver paste or gold-silicon eutectic bonding is used for fixation. Combined with ultrasonic pressure bonding and metal thickening bonding, a stacked structure is formed, and the cutting and baking processes are optimized.
It improves the heat dissipation and reliability of the device, reduces thermal resistance, increases packaging density and product reliability, and reduces production costs.
Smart Images
Figure CN114551249B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power semiconductor chip packaging technology, and particularly relates to a stacking packaging method for depletion-type GaNHEMT devices. Background Technology
[0002] Power electronic devices are evolving towards modularity and intelligence. The emergence of large-scale and very large-scale integrated circuits has led to increasingly higher integration levels in power electronic devices, resulting in a greater number and density of chips assembled on substrates. To reduce the size of power electronic modules and further improve power density, it is required that power modules possess excellent electrical and thermal performance and operational reliability under both steady-state and transient conditions. Conventional GaN HEMTs are inherently depletion-mode, i.e., normally-on devices. The application of GaN HEMT devices as power switching devices means that the chips are subjected to increasingly higher temperatures and temperature drift during use. High temperatures significantly impact the reliability and rapid aging of power electronic products, and excessively high temperatures and temperature cycling often directly lead to premature product failure. Therefore, effective thermal management has become a major challenge for the future development of power electronics, placing higher demands on the research and development of packaging technologies and materials. Effective heat dissipation is a major technical challenge for the future development of high-density, integrated high-power electronic devices. Therefore, in order to significantly increase the maximum output power of power electronic components, reduce the operating temperature of power electronic components to improve their service life, and ensure uniform heat dissipation on the surface of components to prevent excessively high operating temperatures from reducing the reliability of the entire device, the development trend and demand of the electronic packaging industry are to achieve these goals. Summary of the Invention
[0003] In view of this, the present invention provides a stacked packaging method for depletion-mode GaN HEMT devices. Stacked packaging can significantly increase the packaging density of hybrid GaN HEMT devices and Si VDMOS chips, while also enhancing the heat dissipation of the devices. Specifically, the following technical solution is adopted to achieve this:
[0004] This invention provides a method for stacking and packaging depletion-mode GaN HEMT devices, comprising the following steps:
[0005] The depletion-mode GaN HEMT device is mechanically thinned to obtain a chip wafer, and the wafer is then cut to a predetermined size;
[0006] Tape is applied to the back of the wafer and secured with a metal ring. A wafer dicing machine is then used to cut the wafer into individual chips.
[0007] The cut chips are placed on the wafer mount in the lead frame or substrate and fixed by silver paste or gold-silicon eutectic bonding and then sent to baking.
[0008] After baking, the material is fed into the pressure welding machine's material track. First, aluminum wire is used, then copper wire is used for pressure welding to obtain the device to be packaged. The pressure welding parameters are set, and ultrasonic pressure welding is used for aluminum wire pressure welding.
[0009] The gate and source of the device to be packaged are thickened with metal and bonded to form a stacked package structure for depletion-type GaN HEMT devices, wherein the start-up transistor is a Si enhancement-type VDMOS.
[0010] As a further improvement to the above technical solution, the cross-sectional area of the source metal layer of the start-up transistor is larger than the cross-sectional area of the gate metal layer of the device to be packaged.
[0011] As a further improvement to the above technical solution, the metal used is gold or copper, and the thickness is increased to more than 10 micrometers.
[0012] As a further improvement to the above technical solution, the drain of the device to be packaged is used as the input power supply, and the source of the device to be packaged is used as the output power supply.
[0013] As a further improvement to the above technical solution, the gate of the start-up transistor is used to input the start-up signal, and the drain of the start-up transistor is used to input the start-up power supply.
[0014] As a further improvement to the above technical solution, the gate, source, and drain of the device to be packaged are located on the same side of the device. The source and gate of the startup transistor are located on the same side.
[0015] This invention provides a method for stacked packaging of depletion-mode GaN HEMT devices. The method involves mechanically thinning the depletion-mode GaN HEMT device to obtain a wafer, dicing the wafer to a predetermined size, attaching adhesive tape to the back of the wafer and securing it with a metal ring, and then using a wafer dicing machine to cut the wafer into individual chips. The diced chips are placed on a wafer mount in a lead frame or substrate and bonded using silver paste or gold-silicon eutectic bonding. After baking, the chips are fed into a bonding machine's material track and bonded first with aluminum wire and then with copper wire to obtain the device to be packaged. The gate and source of the power transistor are thickened with metal and bonded to form a stacked packaging structure for the depletion-mode GaN HEMT device. By stacking and packaging Si enhancement-mode VDMOS on the chip, the heat dissipation of the power device chip is greatly increased, improving the reliability of the device operation. Heat dissipation structures can be added to both the top and bottom of the stacked packaged chip, improving the chip's heat dissipation speed, reducing thermal resistance, and improving product reliability. Compared with planar packaging, stacked packaging significantly increases packaging density and reduces production and manufacturing costs. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A flowchart of a method for stacking and packaging depletion-type GaN HEMT devices provided in an embodiment of the present invention;
[0018] Figure 2 This is a schematic diagram of the structure of the starter tube provided in an embodiment of the present invention;
[0019] Figure 3 This is a schematic diagram of the structure of a GaN HEMT device provided in an embodiment of the present invention;
[0020] Figure 4 This is a schematic diagram of the stacked packaging structure provided in an embodiment of the present invention. Detailed Implementation
[0021] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0022] It should be noted that when an element is said to be "fixed" to another element, it can be directly on the other element or there may be an intervening element. When an element is said to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is said to be "directly" on another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0023] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0024] See Figure 1 , Figure 2 , Figure 3 and Figure 4 This invention provides a method for stacking and packaging depletion-mode GaN HEMT devices, comprising the following steps:
[0025] S1: The depletion-mode GaN HEMT device is mechanically thinned to obtain a chip wafer, and the wafer is cut to a preset size;
[0026] S2: Apply tape to the back of the wafer and secure it with a metal ring. Use a wafer dicing machine to cut the wafer into individual chips.
[0027] S3: Place the cut chip on the wafer mount in the lead frame or substrate, and fix it with silver paste or gold-silicon eutectic bonding method before baking;
[0028] S4: After baking, the material is fed into the pressure welding machine's material track. First, aluminum wire is used, then copper wire is used for pressure welding to obtain the device to be packaged. The pressure welding parameters are set, and ultrasonic pressure welding is used for aluminum wire pressure welding.
[0029] S5: The gate and source of the device to be packaged are thickened with metal and bonded to form a stacked package structure for depletion-type GaN HEMT devices, wherein the start-up transistor is a Si enhancement-type VDMOS.
[0030] In this embodiment, GaN material exhibits strong spontaneous polarization and piezoelectric polarization effects. In the AlGaN / GaN heterojunction structure composed of AlGaN and GaN, the spontaneous polarization and piezoelectric polarization directions of AlGaN are in the same direction, thereby generating a high polarization electric field and producing a high concentration of two-dimensional electron gas (2DEG) through ionization at the AlGaN / GaN interface. Due to the good confinement of the two-dimensional electron gas and the small amount of scattering it experiences during transport, its mobility is much higher than that of electrons in Si and SiC. Compared with Si-based devices, GaN-based power devices based on this heterojunction structure have higher breakdown voltage, lower on-resistance, and higher power density. The cross-sectional area of the source metal layer of the start-up transistor is larger than that of the gate metal layer of the device to be packaged. The metal used is gold or copper, and the thickness is greater than 10 micrometers. The drain of the device to be packaged is used for input power supply, the source of the device to be packaged is used for output power supply, the gate of the start-up transistor is used for input start-up signal, and the drain of the start-up transistor is used for input start-up power supply. The gate, source, and drain of the device to be packaged are located on the same side of the device to be packaged. The source and gate of the start-up transistor are located on the same side.
[0031] It should be noted that GaN HEMT involves growing aluminum nitride on GaN. The formation of AlGaN from Aluminum nitride and GaN, due to the difference in Fermi levels between aluminum gallium nitride and gallium nitride, and the unique polarization characteristics of gallium nitride, results in two polarization effects during epitaxy: spontaneous polarization and piezoelectric polarization. Spontaneous polarization occurs within a certain temperature range because the centers of mass of nitrogen and gallium atoms cannot coincide at the same point, thus forming dipoles. Piezoelectric polarization occurs due to structural mismatch between the lattice constants of the substrate and the epitaxial layer, typically occurring between two dissimilar materials. Stress is generated between the atoms of the substrate and the epitaxial layer, and this stress gradually accumulates. When the lattice constant of the epitaxial layer is smaller than that of the substrate, expansion deformation occurs; if the lattice constant is larger than that of the substrate, compression deformation occurs, leading to misalignment and thus a polarization effect. Because the coefficient of spontaneous polarization is much smaller than that of piezoelectric polarization, GaN… HEMTs primarily utilize piezoelectric polarization to generate chip characteristics.
[0032] In another feasible embodiment, the first step is to develop a new GaN-on-silicon process node for high-voltage GaN technology. Due to the thicker metal and passivation layers, new design rules must be defined, such as maximum linewidth, metal trench width, and chip chamfer dimensions. Packaging stress directly increases the risk of passivation layer cracking, thus affecting device reliability. Next, the mismatch between stress and thermal expansion coefficients between the GaN epitaxial layer and the silicon substrate makes the wafer more prone to brittleness and cracks in the epitaxial layer during subsequent wafer thinning and dicing. Sometimes, the cut can penetrate the chip circuitry, causing device failure. Therefore, the dicing process needs improvement, and the top and sidewall cutting techniques need to be optimized.
[0033] It should be understood that GaN HEMT devices are epitaxially deposited using metal-organic chemical vapor deposition. Assuming the chip consists of two layers: an upper GaN buffer layer and a lower substrate, the wavy lines represent isotherms. Above the GaN layer is a thin, elongated heat source generated by the gate fingers, while the bottom of the substrate is insulated. The AlGaN layer and other very thin layers are determined by thermal resistance formulas. It can be seen that when the thickness L is extremely small, its thermal resistance can be ignored, thus reducing the burden on the module in terms of calculation and analysis. i T is the contact temperature for chip wire bonding. A For the ambient temperature of the chip substrate, P d This is to consume power. For depletion-type GaN HEMT devices, only a negative voltage can turn them off, which can lead to short-circuit shoot-through. Furthermore, during device operation, the polarities of the gate voltage and drain voltage are always opposite.
[0034] Furthermore, as packaging has gradually evolved towards lighter, thinner, shorter, and smaller packaging structures and process applications, after chip fabrication, the chip needs to be ground to the thickness of the package design to meet the product's structural requirements. The required depletion-mode GaNHEMT power devices are too thick to be diced, so the chip is mechanically thinned to a suitable thickness and then wafer ground. The purpose of chip dicing is to separate each chip on the wafer. Due to the requirements of the packaging process, the wafer is cut to an appropriate size for the next process operation. In addition, tape is attached to the back of the wafer and fixed with a metal ring. The metal ring can support and prevent the tape from breaking and the chips from colliding with each other. Then, the wafer dicing machine cuts the wafer into individual chips. The purpose of chip mounting is to place the cut chips onto the wafer holder in the lead frame or substrate and fix them with silver paste or gold Au-silicon Si eutectic bonding method before sending them to the next process for wire bonding. Baking aims to solidify the silver paste. Since its alternating properties are not yet fully hardened, a special heating curve is required to stabilize its properties. The baking time depends on the characteristics and type of silver paste. Ultrasonic bonding is used to enable the metal material to exhibit strong plastic flow under friction. When metal atoms come into contact, the increased temperature and high-frequency vibrations in the contact area further activate the atoms in the metal lattice. The distance between molecules with covalent bonds is close to nanometers, allowing them to share electrons and form electron bridges, thus achieving metal bonding. Finally, the start-up transistor and the depletion-mode GaN HEMT device are bonded together to form a stacked package structure. The device to be packaged is a depletion-mode GaN HEMT device with a metal layer on the gate. Stacked packaging significantly increases the heat dissipation of the power device chip, improving operational reliability. After stacking, heat dissipation structures can be added to both the top and bottom of the chip, improving heat dissipation speed, reducing thermal resistance, and increasing product reliability. Compared to planar packaging, stacked packaging significantly increases packaging density and reduces production and manufacturing costs.
[0035] In all examples shown and described herein, any specific values should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.
[0036] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0037] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.
Claims
1. A method for stacking and packaging depletion-mode GaN HEMT devices, characterized in that, Includes the following steps: The depletion-mode GaN HEMT device is mechanically thinned to obtain a chip wafer, and the wafer is then cut to a predetermined size; Tape is applied to the back of the wafer and secured with a metal ring. A wafer dicing machine is then used to cut the wafer into individual chips. The cut chips are placed on the wafer mount in the lead frame or substrate and fixed by silver paste or gold-silicon eutectic bonding and then sent to baking. After baking, the material is fed into the pressure welding machine's material track. First, aluminum wire is used, then copper wire is used for pressure welding to obtain the device to be packaged. The pressure welding parameters are set, and ultrasonic pressure welding is used for aluminum wire pressure welding. The gate and source of the device to be packaged are thickened with metal and bonded to form a stacked package structure for depletion-mode GaN HEMT devices, wherein the start-up transistor is a Si enhancement-mode VDMOS. The cross-sectional area of the source metal layer of the start-up transistor is larger than the cross-sectional area of the gate metal layer of the device to be packaged; the gate of the start-up transistor is used to input the start-up signal, and the drain of the start-up transistor is used to input the start-up power supply; the gate, source, and drain of the device to be packaged are located on the same side of the device to be packaged; the source and gate of the start-up transistor are located on the same side; wherein, the polarity of the gate voltage is opposite to that of the drain voltage.
2. The method for stacking and packaging depletion-mode GaN HEMT devices according to claim 1, characterized in that, The metal used is gold or copper, and the thickness is greater than 10 micrometers.
3. The method for stacking and packaging depletion-mode GaN HEMT devices according to claim 1, characterized in that, The drain of the device to be packaged is used for the input power supply, and the source of the device to be packaged is used for the output power supply.