Three-dimensional memory and methods of making the same

Abstract

The present application provides a three-dimensional memory and a preparation method thereof. The preparation method of the three-dimensional memory comprises: alternately stacking an interlayer insulating layer and a sacrificial layer to form a stack structure, and forming a gate gap penetrating through the stack structure; removing the sacrificial layer through the gate gap to form a sacrificial gap; and sequentially forming a first conductive layer, a filling dielectric layer and a second conductive layer in the sacrificial gap to form a gate conductive layer, wherein the first conductive layer and the second conductive layer collectively enclose the filling dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and methods for its fabrication. Background Technology

[0002] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges, such as physical limits and limits on the density of stored electrons. Against this backdrop, three-dimensional memory, which develops vertically, has emerged to address the difficulties encountered by planar flash memory.

[0003] In three-dimensional memory, the gate conductive layer serves as the word line of the memory array, performing operations such as programming, erasing, and reading. Therefore, the stability of the gate conductive layer structure is a crucial factor affecting the performance of three-dimensional memory. However, limitations in actual fabrication processes pose significant challenges to the formation of structures such as the gate conductive layer (which acts as the word line of the memory array) in three-dimensional memory. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory, which includes: alternately stacking an interlayer insulating layer and a sacrificial layer to form a stacked structure and forming a gate gap through the stacked structure; removing the sacrificial layer through the gate gap to form a sacrificial gap; and sequentially forming a first conductive layer, a filling dielectric layer and a second conductive layer in the sacrificial gap to form a gate conductive layer, wherein the first conductive layer and the second conductive layer together surround the filling dielectric layer.

[0005] In one embodiment, forming a first conductive layer, a filling dielectric layer, and a second conductive layer sequentially within the sacrificial gap includes: forming the first conductive layer within the sacrificial gap; filling the remaining portion of the sacrificial gap with a dielectric material to form a filling dielectric layer; etching the filling dielectric layer back through the gate gap to form a sub-gap; and filling the sub-gap with a conductive material to form the second conductive layer.

[0006] In one embodiment, the method further includes: etching back the first conductive layer and the second conductive layer via the gate gap, and filling the etched portion of the gate conductive layer with an insulating material.

[0007] In one embodiment, the method further includes forming a first conductive layer within the sacrificial gap, comprising forming a barrier layer, an adhesive layer, and the first conductive layer sequentially within the sacrificial gap.

[0008] In one embodiment, the method further includes: filling the sub-gap with conductive material to form a second conductive layer, comprising: forming a barrier layer in the sub-gap; and filling the sub-gap with conductive material to form a second conductive layer.

[0009] In one embodiment, the method further includes: etching back the first conductive layer, the barrier layer, and the second conductive layer, and filling the etched portion of the gate conductive layer with an insulating material.

[0010] In one embodiment, the materials of the first conductive layer and the second conductive layer include metallic materials.

[0011] Another aspect of this application provides a three-dimensional memory, including: a stacked structure including alternating interlayer insulating layers and gate conductive layers, wherein the gate conductive layer includes: a filling dielectric layer; and a conductive layer surrounding the filling dielectric layer.

[0012] In one embodiment, the three-dimensional memory further includes a barrier layer located between the gate conductive layer and the interlayer insulating layer.

[0013] In one embodiment, the three-dimensional memory further includes an adhesive layer located between the gate conductive layer and the interlayer insulating layer.

[0014] In one embodiment, the conductive layer includes: a first conductive layer; and a second conductive layer located on one side of the filling dielectric layer near the gate gap structure of the three-dimensional memory.

[0015] In one embodiment, the three-dimensional memory further includes a barrier layer disposed between the second conductive layer and the filling dielectric layer.

[0016] In one embodiment, the three-dimensional memory further includes an insulating material located on the side of the gate conductive layer near the gate gap structure.

[0017] In one embodiment, the materials of the first conductive layer and the second conductive layer include metallic materials.

[0018] The three-dimensional memory and its fabrication method provided according to one or more embodiments of this application may have at least one of the following advantages: 1) Compared to depositing a conductive layer (such as a metallic material layer) within the sacrificial gap using a single deposition process, this application sequentially forms a first conductive layer, a filling dielectric layer, and a second conductive layer within the sacrificial gap. This means that the application can sequentially form the first conductive layer, the filling dielectric layer, and the second conductive layer using a three-stage deposition process, which improves the density and uniformity of the material within the sacrificial gap. Furthermore, this application forms a lower-cost filling dielectric layer within the sacrificial gap, which can reduce material costs while simultaneously improving the density and uniformity of the material within the sacrificial gap. 2) After depositing a conductive layer (such as a metal layer) within the sacrificial gap using a single deposition process, inhomogeneity of the deposited metal often occurs, leading to defects such as gaps within the deposited metal. When using an etch-back process to remove the metal material from the sidewalls, defects such as gaps in the metal often result in complete or excessive etch-back of the deposited metal, causing high impedance or open circuits in the word lines of that layer. However, this application improves the density and uniformity of the material within the sacrificial gap by sequentially forming a first conductive layer, a filling dielectric layer, and a second conductive layer within the sacrificial gap, effectively reducing excessive etch-back due to low material density or poor uniformity during etch-back; and 3) By setting the first conductive layer and the second conductive layer to wrap the filling dielectric layer, the word line contact structure formed subsequently can be electrically connected to the first conductive layer and / or the second conductive layer, reducing the phenomenon of open circuit caused by the word line contact structure being connected to the filling dielectric layer, and ensuring the conductivity of the gate conductive layer. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application; and Figures 2 to 12B This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application. Detailed Implementation

[0020] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0021] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first conductive layer discussed herein may also be referred to as the second conductive layer, and vice versa.

[0022] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0023] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0024] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0025] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0026] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0027] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application.

[0028] like Figure 1 As shown, the fabrication method 1000 of the three-dimensional memory provided in this application may include: S1, alternately stacking an interlayer insulating layer and a sacrificial layer to form a stacked structure and forming a gate gap through the stacked structure; S2, removing the sacrificial layer through the gate gap to form a sacrificial gap; and S3, sequentially forming a first conductive layer, a filling dielectric layer, and a second conductive layer within the sacrificial gap to form a gate conductive layer, wherein the first conductive layer and the second conductive layer together surround the filling dielectric layer. Steps S1 to S3 will be described in detail below.

[0029] Step S1

[0030] like Figure 2 As shown, interlayer insulating layer 110 and sacrificial layer 120 can be alternately stacked to form a stacked structure 100, and a gate gap 200 through the stacked structure 100 can be formed. Exemplarily, interlayer insulating layer 110 and sacrificial layer 120 can be alternately stacked on substrate 300 to form a stacked structure 100, and a gate gap 200 through the stacked structure 100 can be formed. Specifically, the stacked structure 100 can be formed by alternately stacking interlayer insulating layer 110 and sacrificial layer 120 on substrate 300, for example, through a deposition process. Exemplarily, the gate gap 200 through the stacked structure 100 can be formed by processes such as photolithography and dry etching to expose the interlayer insulating layer 110 and sacrificial layer 120.

[0031] In exemplary embodiments of this application, the substrate 300 may be, for example, a polycrystalline silicon (Si) substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 300 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 300 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0032] In an exemplary embodiment of this application, forming a stacked structure 100 on the substrate 300 can be achieved through one or more deposition processes. The deposition processes for forming the stacked structure 100 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the interlayer insulating layer 110 and the sacrificial layer 120 are not limited to... Figure 2 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to provide any number and thickness of interlayer insulating layers 110 and sacrificial layers 120 as needed. Furthermore, the materials of interlayer insulating layers 110 and sacrificial layers 120 may be selected from suitable materials known in the art. For example, interlayer insulating layer 110 may be an oxide layer (such as silicon oxide), and sacrificial layer 120 may be a nitride layer (such as silicon nitride).

[0033] In an exemplary embodiment of this application, a channel structure 400 may also be formed in the stacked structure 100. The channel structure 400 may extend through the stacked structure 100 and into the substrate 300 along the thickness direction of the stack. Exemplarily, the channel structure 400 may include, for example, an epitaxial layer (not shown) located near the substrate 300. It should be understood that the channel structure 400 may have a certain spacing from the gate gap 200.

[0034] Step S2

[0035] like Figure 3 As shown, the sacrificial layer 120 can be removed via the gate gap 200 to form sacrificial gaps 130. Exemplarily, the gate gap 200 can serve as a pathway for providing etchant and chemical precursors, and all of the sacrificial layer 120 in the stacked structure 100 can be removed using processes such as wet etching. Specifically, the sacrificial layer 120 of the stacked structure 100 can be removed using, for example, a wet etching process, thereby forming a concave-convex structure around the channel structure 400 along the stack thickness direction of the stacked structure 100, wherein the concave-convex structure includes a plurality of sacrificial gaps 130 (spaces formed in the stacked structure 100 after the removal of the sacrificial layer 120).

[0036] Step S3

[0037] like Figure 10A and Figure 10B As shown, a first conductive layer 510, a filling dielectric layer 520, and a second conductive layer 530 can be sequentially formed within the sacrificial gap 130 to form a gate conductive layer 500. The first conductive layer 510 and the second conductive layer 530 can together surround the filling dielectric layer 520. Exemplarily, firstly, as... Figure 6 As shown, a first conductive layer 510 can be formed within the sacrificial gap 130; secondly, as Figure 7 As shown, the remaining portion of the sacrificial gap 130 can be filled with a dielectric material to form a filled dielectric layer 520; again, as Figure 8 As shown, the gate gap 200 can be etched back to fill the dielectric layer 520 to form the sub-gap 540; finally, as Figure 9 As shown, conductive material can be filled into the inter-sub-interval 540 to form a second conductive layer 530.

[0038] For example, such as Figure 6 As shown, a first conductive layer 510 can be formed on the inner wall of the sacrificial gap 130 by, for example, a deposition process. Furthermore, the first conductive layer 510 can be formed using, for example, a metallic material such as tungsten. It should be understood that in actual deposition processes, the first conductive layer 510 will also be formed on the interlayer insulating layer 110 and the sidewalls of the channel structure 400, but this does not affect the actual requirements of this application.

[0039] For example, such as Figure 7 As shown, a dielectric material can be filled into the sacrificial gap 130, where the first conductive layer 510 has been formed, using, for example, a deposition process, to form a filled dielectric layer 520. By forming the first conductive layer 510 within the sacrificial gap 130 before filling with the dielectric material, the density and uniformity of the material within the sacrificial gap 130 can be improved, effectively reducing over-etching during the etch-back process due to low material density or poor uniformity. Exemplarily, the dielectric material can be any material with simple and low-cost deposition processes, such as conductive or insulating materials. For example, the dielectric material can be an oxide, such as silicon oxide. It should be understood that in actual deposition processes, the dielectric material may also be formed on the interlayer insulating layer 110, but this does not affect the actual requirements of this application. Exemplarily, a dielectric material can be formed in the sub-gap 540 (… Figure 8 A second conductive layer 530 is formed on the inner wall of the ) Figure 9 Furthermore, a second conductive layer 530 can be formed using, for example, a metallic material such as tungsten.

[0040] In the exemplary embodiments of this application, such as Figure 4As shown, a barrier layer 610 can be formed on the inner wall of the sacrificial gap 130. Exemplarily, the barrier layer 610 can be formed on the inner wall of the sacrificial gap 130 using a deposition process such as CVD, PVD, ALD, or any combination thereof. Specifically, after forming the sacrificial gap 130, a barrier layer 610 covering the interlayer insulation layer 110 can be formed using a deposition process, i.e., forming a barrier layer 610 covering the sidewalls and surface of the interlayer insulation layer 110. Exemplarily, the barrier layer 610 covering the sidewalls of the interlayer insulation layer 110 can be removed using an etch-back process, while retaining the barrier layer 610 covering the surface of the interlayer insulation layer 110 (formed on the inner wall of the sacrificial gap 130). Exemplarily, after forming the barrier layer 610 covering the sidewalls and surface of the interlayer insulation layer 110, the barrier layer 610 covering the sidewalls of the interlayer insulation layer 110 may not be removed.

[0041] In an exemplary embodiment of this application, the barrier layer 610 is made of a high dielectric constant material. Forming the barrier layer 610 (high dielectric constant dielectric layer) on the inner wall of the sacrificial gap 130 effectively prevents charge diffusion from the first conductive layer 510 into the interlayer insulating layer 110. Furthermore, the barrier layer 610 can increase the dielectric constant between the first conductive layer 510 and the interlayer insulating layer 110, thereby enhancing the controllability of the gate conductive layer 500.

[0042] In the exemplary embodiments of this application, such as Figure 5 As shown, an adhesive layer 620 can be formed on the surface of the barrier layer 610. Exemplarily, the adhesive layer 620 can be formed on the surface of the barrier layer 610 using a deposition process such as CVD, PVD, ALD, or any combination thereof. Specifically, after forming the barrier layer 610, a deposition process can be used to form an adhesive layer 620 covering the sidewalls of the interlayer insulation layer 110 and covering the sidewalls and surface of the barrier layer 610. Then, an etch-back process can be used to remove the adhesive layer 620 covering the sidewalls of the interlayer insulation layer 110 and the sidewalls of the barrier layer 610, leaving the adhesive layer 620 covering the surface of the barrier layer 610 (formed on the inner wall of the sacrificial gap 130). Exemplarily, if the barrier layer 610 covering the sidewalls of the interlayer insulation layer 110 is not removed, a deposition process can be used to form an adhesive layer 620 covering the sidewalls and surface of the barrier layer 610. Then, an etching process can be used to remove the adhesive layer 620 covering the sidewalls of the barrier layer 610, while retaining the adhesive layer 620 forming the surface of the barrier layer 610 (formed on the inner wall of the sacrificial gap 130). For example, as... Figure 6 As shown, the first conductive layer 510 can cover the adhesive layer 620.

[0043] In an exemplary embodiment of this application, the material of the adhesive layer 620 includes a nitride. For example... Figure 6As shown, an adhesive layer 620 is formed on the surface of the barrier layer 610, which strengthens the connection between the first conductive layer 510 and the barrier layer 610. The adhesive layer 620 can be made of a material that can block the diffusion of metal ions and has conductivity, such as titanium nitride (TiN), thallium nitride (TaN), or combinations thereof. In some embodiments, the adhesive layer 620 can be in direct contact with both the first conductive layer 510 and the barrier layer 610. In some embodiments, the adhesive layer 620 can be a multilayer structure.

[0044] In the exemplary embodiments of this application, such as Figure 8 As shown, the gate gap 200 can be etched back to fill the dielectric layer 520 to form sub-gap 540. Exemplarily, the gate gap can serve as a pathway for providing etchant and chemical precursors, with a portion of the dielectric material removed using processes such as wet etching. Exemplarily, a wet etching process can be used to remove a portion of the dielectric material, thereby forming an uneven structure around the gate gap 200 along the stack thickness direction of the stack structure 100, wherein the uneven structure includes a plurality of sub-gap 540s (spaces formed in the stack structure 100 after the removal of a portion of the dielectric material).

[0045] In the exemplary embodiments of this application, such as Figure 9 As shown, conductive material can be filled within the sub-interval 540 to form a second conductive layer 530. Exemplarily, the second conductive layer 530 can be formed within the sub-interval 540 by, for example, a deposition process. For example, a metallic material such as tungsten can be used to form the second conductive layer 530. It should be understood that in actual deposition processes, the second conductive layer 530 will also be formed on the interlayer insulating layer 110, but this does not affect the actual requirements of this application. It should also be understood that the materials of the first conductive layer 510 and the second conductive layer 530 can be the same or different. The materials of the first conductive layer 510 and the second conductive layer 530 can be any materials that satisfy the conductivity performance of the gate conductive layer 500. Forming the second conductive layer 530 within the sub-interval 540 can effectively improve the conductivity performance of the gate conductive layer 500.

[0046] In the exemplary embodiments of this application, such as Figure 9As shown, a barrier layer 630 can be formed within the sub-gap 540 before filling it with conductive material to form the second conductive layer 530. Exemplarily, the barrier layer 630 can be formed on the inner wall of the sub-gap 540 by, for example, a deposition process. The barrier layer 630 can be located between the second conductive layer 530 and the filling dielectric layer 520, and between the first conductive layer 510 and the second conductive layer 530. In other words, the barrier layer 630 can be in a "U-shaped" structure located between the first conductive layer 510, the filling dielectric layer 520, and the second conductive layer 530. Exemplarily, the material of the barrier layer 630 can include nitrides, such as titanium nitride (TiN), thallium nitride (TaN), or combinations thereof. Providing the barrier layer 630 on the inner wall of the sub-gap 540 effectively prevents etching solution from entering the filling dielectric layer 520 during subsequent etching back of the second conductive layer 530.

[0047] In the exemplary embodiments of this application, such as Figure 10A As shown, the first conductive layer 510, the barrier layer 630, and the second conductive layer 530 can be etched back. Exemplarily, a portion of the sidewalls of the adhesive layer 620, the first conductive layer 510, the barrier layer 630, and the second conductive layer 530 located on the sidewalls of the gate conductive layer 500 can be removed to disconnect adjacent gate conductive layers 500. Furthermore, as... Figure 11A As shown, insulating material 700 can be filled in a portion of the etched-back gate conductive layer 500. Specifically, during the process of filling the etched-back gate conductive layer 500 with insulating material 700, due to limitations of the actual process (such as deposition process), insulating material 700 will inevitably also be formed on the sidewalls of the interlayer insulating layer 110. However, the interlayer insulating layer 110 can also be an insulating material, so the formation of insulating material 700 on the sidewalls of the interlayer insulating layer 110 does not have an adverse effect on this application. Exemplarily, the adhesive layer 620, the first conductive layer 510, the barrier layer 630, and the second conductive layer 530 located on the sidewalls of the gate conductive layer 500 can be etched away using, for example, an etching solution. It should be understood that in the actual etching process, the first conductive layer 510, the barrier layer 630, and the second conductive layer 530 formed on the interlayer insulating layer 110 will also be etched away, thereby meeting the actual requirements of this application. In this application, by etching back the adhesive layer 620, the first conductive layer 510, the barrier layer 630, and the second conductive layer 530, and filling the etched area with insulating material 700, it is possible to ensure that adjacent gate conductive layers 500 are disconnected, thus avoiding subsequent electrical connections between gate conductive layers 500 of different levels. For example, in the formation of... Figure 11A After the structure shown, dielectric material can be filled into the gate gap 200 to form the gate gap structure 210. Figure 12A The gate gap structure 210 can be used to divide the storage area into multiple storage blocks.

[0048] In the exemplary embodiments of this application, such as Figure 10B As shown, the interlayer insulating layer 110, barrier layer 610, adhesive layer 620, first conductive layer 510, blocking layer 630, and second conductive layer 530 can be etched back. Exemplarily, the sidewalls of the interlayer insulating layer 110, barrier layer 610, and adhesive layer 620, as well as a portion of the first conductive layer 510, blocking layer 630, and second conductive layer 530 located on the sidewall of the gate conductive layer 500, can be removed to disconnect adjacent gate conductive layers 500. In other words, a dry etching process, for example, can be used to remove the sidewalls of the interlayer insulating layer 110, barrier layer 610, and adhesive layer 620, as well as a portion of the first conductive layer 510, blocking layer 630, and second conductive layer 530 located on the sidewall of the gate conductive layer 500 along the stack thickness direction of the stacked structure to disconnect adjacent gate conductive layers 500. Furthermore, as... Figure 11B As shown, insulating material 700 can be filled in a portion of the etched-back gate conductive layer 500. In this application, by etching back the interlayer insulating layer 110, barrier layer 610, adhesive layer 620, first conductive layer 510, barrier layer 630, and second conductive layer 530, and filling the etched-back area with insulating material 700, it is possible to ensure that adjacent gate conductive layers 500 are disconnected, avoiding subsequent electrical connections between gate conductive layers 500 of different levels. For example, in the formation of... Figure 11B After the structure shown, dielectric material can be filled into the gate gap 200 to form the gate gap structure 210. Figure 12B The gate gap structure 210 can be used to divide the storage area into multiple storage blocks.

[0049] This application provides a three-dimensional memory. Figure 12A and Figure 12B A schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application is shown.

[0050] like Figure 12A and Figure 12B As shown, the three-dimensional memory may include a stacked structure, wherein the stacked structure may include alternately stacked interlayer insulating layers 110 and gate conductive layers 500. The gate conductive layer 500 may include a filling dielectric layer 520, a first conductive layer 510, and a second conductive layer 530. The first conductive layer 510 and the second conductive layer 530 may surround the filling dielectric layer 520.

[0051] In an exemplary embodiment of this application, the three-dimensional memory further includes a barrier layer 610 and an adhesive layer 620 located between the gate conductive layer 500 and the interlayer insulating layer 110. Exemplarily, the barrier layer 610 is formed between the first conductive layer 510 and the interlayer insulating layer 110. The material of the barrier layer 610 includes a high dielectric constant material. Providing the barrier layer 610 (high dielectric constant dielectric layer) between the first conductive layer 510 and the interlayer insulating layer 110 effectively prevents charge diffusion from the first conductive layer 510 into the interlayer insulating layer 110. On the other hand, the barrier layer 610 can increase the dielectric constant between the first conductive layer 510 and the interlayer insulating layer 110, enhancing the controllability of the gate conductive layer 500. Exemplarily, the adhesive layer 620 is formed between the first conductive layer 510 and the barrier layer 610. For example, after forming the barrier layer 610, an adhesive layer 620 covering the surface of the barrier layer 610 can be formed within the sacrificial gap 130 using a deposition process. The adhesive layer 620 is made of nitrides. For example... Figure 6 As shown, an adhesive layer 620 is provided between the first conductive layer 510 and the barrier layer 610 to strengthen the connection between them. The adhesive layer 620 can be made of a material that can block the diffusion of metal ions and is conductive, such as titanium nitride (TiN), thallium nitride (TaN), or combinations thereof. In some embodiments, the adhesive layer 620 can be in direct contact with both the first conductive layer 510 and the barrier layer 610. In some embodiments, the adhesive layer 620 can be a multilayer structure.

[0052] In an exemplary embodiment of this application, a barrier layer 630 may be disposed between the second conductive layer 530 and the filling dielectric layer 520. Exemplarily, the barrier layer 630 may be located between the second conductive layer 530 and the filling dielectric layer 520, and between the first conductive layer 510 and the second conductive layer 530. In other words, the barrier layer 630 may have a "U-shaped" structure located between the first conductive layer 510, the filling dielectric layer 520, and the second conductive layer 530. Exemplarily, the material of the barrier layer 630 may include nitrides, such as titanium nitride (TiN), thallium nitride (TaN), or combinations thereof. Distributing the barrier layer 630 between the second conductive layer 530 and the filling dielectric layer 520 can effectively prevent etching solution from entering the filling dielectric layer 520 during subsequent etching back of the second conductive layer 530.

[0053] In an exemplary embodiment of this application, the three-dimensional memory further includes an insulating material 700 formed on the side of the gate conductive layer 500 near the gate gap 200. Providing the insulating material 700 on the side of the gate conductive layer 500 near the gate gap 200 ensures that adjacent gate conductive layers 500 are disconnected, preventing subsequent electrical connections between gate conductive layers 500 of different levels.

[0054] In an exemplary embodiment of this application, the three-dimensional memory further includes a channel structure 400 extending through the stacked structure. The channel structure 400 may extend through the stacked structure along the thickness direction and into the substrate 300. Exemplarily, the channel structure 400 may include, for example, an epitaxial layer (not shown) located near the substrate 300. It should be understood that the channel structure 400 may have a certain spacing from the gate gap 200. The channel structure 400 may include a channel layer (not shown) and a functional layer (not shown) located on the outer wall of the channel layer. The functional layer may include an isolation layer (not shown) located on the inner wall of the channel structure 400 to block charge outflow, a charge trapping layer (not shown) on the surface of the isolation layer to store charge during operation of the three-dimensional memory, and a tunneling layer (not shown) on the surface of the charge trapping layer. The channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon.

[0055] In an exemplary embodiment of this application, the three-dimensional memory further includes a gate gap structure 210 extending along the stack thickness direction of the stacked structure. Exemplarily, the gate gap structure 210 may extend along the stack thickness direction to the interlayer insulating layer 110 closest to the substrate in the stacked structure. The gate gap structure 210 may include a dielectric material 710 and an insulating material 700 formed on the sidewalls of the dielectric material 710. The gate gap structure 210 can be used to divide the memory region into multiple memory blocks. Exemplarily, as... Figure 12A As shown, the insulating material 700 may have an uneven structure along the thickness direction of the stacked structure. Furthermore, as... Figure 12B As shown, the insulating material 700 may also have a quasi-cylindrical structure along the thickness direction of the stacked structure.

[0056] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated here.

[0057] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0058] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Interlayer insulating layers and sacrificial layers are alternately stacked along the thickness direction to form a stacked structure, and a gate gap is formed through the stacked structure; The sacrificial layer is removed via the gate gap to form a sacrificial gap; as well as A first conductive layer, a filling dielectric layer, and a second conductive layer are sequentially formed within the sacrificial gap to form a gate conductive layer. The first conductive layer and the second conductive layer together surround the filling dielectric layer. The second conductive layer is located on the side of the filling dielectric layer near the gate gap along a horizontal direction perpendicular to the stack thickness direction. The first conductive layer protrudes from the filling dielectric layer along the horizontal direction toward the side of the second conductive layer.

2. The preparation method according to claim 1, characterized in that, The formation of a first conductive layer, a filling dielectric layer, and a second conductive layer sequentially within the sacrificial gap includes: A first conductive layer is formed within the sacrificial gap; The remaining portion of the sacrificial gap is filled with a dielectric material to form a filling dielectric layer; The filling dielectric layer is etched back through the gate gap to form a sub-gap; and The space between the sub-spaces is filled with conductive material to form a second conductive layer.

3. The preparation method according to claim 2, characterized in that, The method further includes: etching back the first conductive layer and the second conductive layer via the gate gap, and filling the etched portion of the gate conductive layer with insulating material.

4. The preparation method according to claim 2, characterized in that, Forming the first conductive layer within the sacrificial gap includes: A barrier layer, an adhesive layer, and the first conductive layer are sequentially formed within the sacrificial gap.

5. The preparation method according to claim 2, characterized in that, Filling the interstitial space with conductive material to form a second conductive layer includes: A barrier layer is formed within the sub-gap; and The space between the sub-spaces is filled with conductive material to form a second conductive layer.

6. The preparation method according to claim 5, characterized in that, The method further includes: etching back the first conductive layer, the barrier layer, and the second conductive layer, and filling the etched portion of the gate conductive layer with insulating material.

7. The preparation method according to claim 1, characterized in that, The materials of the first conductive layer and the second conductive layer include metallic materials.

8. A three-dimensional memory, characterized in that, include: A stacked structure includes interlayer insulating layers and a gate conductive layer alternately stacked along the thickness direction of the stack, wherein the gate conductive layer includes: Filling dielectric layer; and A conductive layer surrounds the filling dielectric layer, wherein the conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the filling dielectric layer near the gate gap in a horizontal direction perpendicular to the stack thickness direction, and the first conductive layer protruding from the filling dielectric layer in the horizontal direction toward the side of the second conductive layer.

9. The three-dimensional memory according to claim 8, characterized in that, The three-dimensional memory further includes a barrier layer located between the gate conductive layer and the interlayer insulating layer.

10. The three-dimensional memory according to claim 9, characterized in that, The three-dimensional memory further includes an adhesive layer located between the gate conductive layer and the barrier layer.

11. The three-dimensional memory according to claim 10, characterized in that, The three-dimensional memory further includes a barrier layer disposed between the second conductive layer and the filling dielectric layer.

12. The three-dimensional memory according to claim 10, characterized in that, The three-dimensional memory further includes an insulating material located on the side of the gate conductive layer near the gate gap structure.

13. The three-dimensional memory according to claim 10, characterized in that, The materials of the first conductive layer and the second conductive layer include metallic materials.

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