Semiconductor device package and method and apparatus for manufacturing the same

Abstract

The present disclosure provides a semiconductor device package, a manufacturing method and a manufacturing apparatus thereof. The semiconductor device package includes a substrate having a first surface, a second surface, and a hole extending from the first surface to the second surface; a first electronic component disposed on the second surface of the substrate and covering the hole; and a first encapsulation layer encapsulating the first electronic component, wherein the first encapsulation layer has an extension portion filling a portion of the hole. A substrate having a first surface, a second surface, and a hole extending from the first surface to second surface; a first electronic component disposed on the second surface of the substrate and covering the hole, and a first encapsulation layer encapsulating the first electronic component, wherein the first encapsulation layer having an extension portion filling a portion of the hole. In addition, the present disclosure also provides a method and an apparatus for manufacturing the semiconductor device package.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a method and fixture for manufacturing the semiconductor device package. Background Technology

[0002] In molded underfill (MUF) packaging structures, the problem of voids formed between bumps can be mitigated by adjusting flow rate, mold temperature, and molding pressure. Furthermore, voids can be reduced by creating vents on the substrate at locations where voids might occur, allowing air to be drawn from the packaging material during injection and guiding it towards the vents. However, these methods can cause packaging material to overflow onto the underside of the substrate, affecting solder ball adhesion. Therefore, it is necessary to seek new manufacturing methods and fixtures to address these issues. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor device package includes a substrate having a first surface, a second surface, and a hole extending from the first surface to the second surface; a first electronic component disposed on the second surface of the substrate and covering the hole; and a first encapsulation layer covering the first electronic component, wherein the first encapsulation layer has an extension that fills a portion of the hole.

[0004] According to some embodiments of this disclosure, a fixture includes a carrier plate and a pressure-sensing check valve. The carrier plate is used to support a substrate. The pressure-sensing check valve is configured to be embedded in a hole in the substrate.

[0005] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device package includes: providing a substrate, the substrate including a first surface, a second surface, and a hole extending from the first surface to the second surface; injecting an encapsulation material from the second surface of the substrate, such that the encapsulation material flows from the second surface of the substrate into the hole and stops within the hole. Attached Figure Description

[0006] When with attachment Figure 1 When reading the following detailed description, the contents of this disclosure can be easily understood based on it. It should be noted that the various features may not necessarily be drawn to scale.

[0007] Figure 1 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0008] Figure 2 yes Figure 1 A magnified view of a portion of the image.

[0009] Figure 2A Draw a cross-sectional view of the fill and recess.

[0010] Figure 3 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0011] Figure 4 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0012] Figure 4A yes Figure 4 A partial bottom view.

[0013] Figure 5 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0014] Figure 6 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0015] Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present invention.

[0016] Figure 7A Draw a partial enlarged view of the blocking structure and fixture.

[0017] Figure 12 , Figure 13 and Figure 14 This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present invention.

[0018] Figure 12A Draw the size ratio of the blocking component to the hole.

[0019] Figure 15 and Figure 16 This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present invention.

[0020] The accompanying drawings and detailed description throughout this disclosure use common reference numerals to indicate the same or similar components. This disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming or placing a first feature on or over a second feature may include embodiments in which the first and second features are formed or placed in direct contact, and may also include embodiments in which an additional feature may be formed or placed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself limit the relationship between the various embodiments and / or configurations discussed.

[0022] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0023] Figure 1 This is a cross-sectional view of a semiconductor device package 1a according to some embodiments of the present disclosure. In some embodiments, the semiconductor device package 1a includes a substrate 11, an electronic component 12, a conductive component 13, and a packaging layer 14.

[0024] In some embodiments, substrate 11 may comprise a silicon substrate and / or other suitable materials. For example, substrate 11 may comprise an embedded oxide layer (not shown) formed over the substrate to form a silicon-on-insulator (SOI) structure. In some embodiments, substrate 11 comprises a redistribution layer (not shown). The redistribution layer may comprise a plurality of dielectric layers, conductive layers, and vias formed therein. Substrate 11 comprises a surface 11s1 and a surface 11s2 opposite to surface 11s1.

[0025] Electronic component 12 is disposed on surface 11s2 of substrate 11. Electronic component 12 can be electrically connected to substrate 11 through conductive component 13. Electronic component 12 may include one or more semiconductor chips formed by one or more integrated circuits (ICs). In some embodiments, electronic component 12 may include, but is not limited to, at least one active component.

[0026] The conductive component 13 is disposed on the surface 11s2 of the substrate 11. The conductive component 13 may be a solder bump or a solder ball (e.g., a solder ball).

[0027] An encapsulation layer 14 is disposed on the surface 11s2 of the substrate 11. The encapsulation layer 14 encapsulates the electronic component 12 and the conductive component 13. The encapsulation layer 14 is made of a molding material, which may include, for example, phenolic varnish resin, epoxy resin, polysiloxane resin or other suitable sealants. It may also contain suitable fillers, such as powdered SiO2.

[0028] Figure 2 yes Figure 1 A magnified view of region R.

[0029] In some embodiments, the substrate 11 includes one or more holes 11o. An electronic component 12 is disposed above a surface 11s2 of the substrate 11 and covers the holes 11o. The holes 11o extend from surface 11s1 to surface 11s2. In some embodiments, the encapsulation layer 14 has an extension 14p that fills a portion of the holes 11o. In some embodiments, the encapsulation layer 14 has a recess 14r1. More specifically, the distal end (bottom) of the extension 14p has a recess 14r1. The recess 14r1 extends from surface 11s1 toward surface 11s2 of the substrate 11. Figure 2 As shown, the recess 14r1 is a conical recess. In some embodiments, the aperture of the recess 14r1 at the height of the surface 11s1 is substantially equal to the aperture of the hole 11o. In some embodiments, the extension 14p of the encapsulation layer 14 does not fill the hole 11o. That is, the end of the extension 14p of the encapsulation layer 14 does not extend beyond the surface 11s1 of the substrate 11. In this embodiment, the encapsulation layer 14 is not formed on the surface 11s1 of the substrate 11, which avoids the situation where the encapsulation material overflows and covers the area where the pads or solder balls are to be formed, thus preventing the pads or solder balls from being formed on the surface 11s1 of the substrate 11.

[0030] Figure 2A A cross-sectional view of filler 141 and recess 14r1 is shown. Encapsulation layer 14 may contain a plurality of fillers 141. In some embodiments, filler 141 does not have a cross-section exposed to the recess 14r1 (the reason will be detailed in subsequent flowcharts). In some embodiments, filler 141 has a particle size (or average particle size) D3, which is in the range of 16 μm to 20 μm, for example, it may be 16.3 μm, 16.5 μm, 17 μm, 18 μm, 19 μm, 19.5 μm, or 19.7 μm.

[0031] Figure 3 This is a cross-sectional view of a semiconductor device package 1b according to some embodiments of the present disclosure.

[0032] Figure 3 The structure of the semiconductor device package 1b is similar to Figure 2One difference in the structure of the semiconductor device package 1a is that the distal end of the extension 14p of the semiconductor device package 1b has a surface 14s1 and a recess 14r2, with the recess 14r2 replacing the recess 14r1. In some embodiments, the recess 14r2 is a conical recess. In some embodiments, the aperture of the recess 14r2 at a height position of the surface 11s1 of the substrate 11 is substantially smaller than the aperture of the hole 11o. In such cases... Figure 3 In some embodiments shown, the surface 14s1 of the encapsulation layer 14 may be substantially coplanar with the surface 11s1 of the substrate 11; in other embodiments, the surface 14s1 of the encapsulation layer 14 may be higher than the surface 11s1 of the substrate 11. In the above embodiments, the encapsulation layer 14 is not formed on the surface 11s1 of the substrate 11, which avoids the situation where the encapsulation material overflows and covers the area where the pads or solder balls are to be formed, thus preventing the pads or solder balls from being formed on the surface 11s1 of the substrate 11.

[0033] Figure 4 This is a cross-sectional view of a semiconductor device package 1c according to some embodiments of the present disclosure.

[0034] Figure 4 The structure of the semiconductor device package 1c is similar to Figure 2 One difference in the structure of the semiconductor device package 1a is that the end of the extension 14p of the semiconductor device package 1c has a surface 14s1 and a recess 14r3, with the recess 14r3 replacing the recess 14r1. In some embodiments, the recess 14r3 is a columnar recess (e.g., a cylindrical recess). In some embodiments, the aperture of the recess 14r3 at a height position of the surface 11s1 of the substrate 11 is substantially smaller than the aperture of the hole 11o. Figure 4 In some embodiments shown, the surface 14s1 of the encapsulation layer 14 may be substantially coplanar with the surface 11s1 of the substrate 11; in other embodiments, the surface 14s1 of the encapsulation layer 14 may be higher than the surface 11s1 of the substrate 11. In the above embodiments, the encapsulation layer 14 is not formed on the surface 11s1 of the substrate 11, which avoids the situation where the encapsulation material overflows and covers the area where the pads or solder balls are to be formed, thus preventing the pads or solder balls from being formed on the surface 11s1 of the substrate 11.

[0035] Figure 4A yes Figure 4 A partial bottom view.

[0036] like Figure 4AAs shown, in some embodiments, the hole 11o of the substrate 11 may have a circular profile with a radius D1; ​​the recess 14r3 may have a circular profile with a radius D2. In some embodiments, the ratio of D1 to D2 may be between 2:1 and 5:4, for example, 3:2 or 4:3. The ratio of D1 to D2 may also be other suitable ranges. The ratio of D1 to D2 can be adjusted so that the encapsulation material does not overflow from the hole 11o. In some embodiments, the encapsulation layer 14 contains a filler (such as... Figure 2A The filler 141 has a particle size (or average particle size) D3. In some embodiments, the particle size D3 of the filler is less than the difference between radius D1 and radius D2; in other embodiments, the particle size D3 of the filler may be greater than or equal to the difference between radius D1 and radius D2. In the above embodiments, the encapsulation layer 14 is not formed on the surface 11s1 of the substrate 11, which avoids the situation where the encapsulation material overflows and covers the area where the pads or solder balls are to be formed, thus preventing the pads or solder balls from being formed on the surface 11s1 of the substrate 11. In some embodiments, the particle size D3 of at least one filler is less than the length of the surface 14s1 of the encapsulation layer 14 (which may be defined by the distance from the recess 14r3 to the edge of the hole 11o).

[0037] Figure 5 This is a cross-sectional view of a semiconductor device package 1d according to some embodiments of the present disclosure.

[0038] Figure 5 The structure of the semiconductor device package 1d is similar to Figure 2 One difference in the structure of the semiconductor device package 1a is that the distal end of the extension 14p of the semiconductor device package 1d has a surface 14s1 and a recess 14r4, which replaces the recess 14r1. In some embodiments, the recess 14r4 is a needle-shaped recess. In some embodiments, the aperture of the recess 14r4 at a height position of the surface 11s1 is smaller than the aperture of the hole 11o. In such... Figure 5 In some embodiments shown, the surface 14s1 of the encapsulation layer 14 may be substantially coplanar with the surface 11s1 of the substrate 11; in other embodiments, the surface 14s1 of the encapsulation layer 14 may be higher than the surface 11s1 of the substrate 11. In the above embodiments, the encapsulation layer 14 is not formed on the surface 11s1 of the substrate 11, which avoids the situation where the encapsulation material overflows and covers the area where the pads or solder balls are to be formed, thus preventing the pads or solder balls from being formed on the surface 11s1 of the substrate 11.

[0039] Figure 6 This is a cross-sectional view of a semiconductor device package 1e according to some embodiments of the present disclosure.

[0040] In some embodiments, the semiconductor device package 1e may further include electronic components 15, conductive components 16, and a packaging layer 17.

[0041] Electronic component 15 and electronic component 12 may be disposed on opposite surfaces of substrate 11. For example, electronic component 15 may be disposed on surface 11s1 of substrate 11. Electronic component 15 may be electrically connected to substrate 11 via conductive component 16. Electronic component 15 may be a semiconductor chip containing one or more ICs. In some embodiments, electronic component 15 may include, but is not limited to, at least one active component. In some embodiments, electronic component 15 may include, but is not limited to, at least one passive component, such as a capacitor, resistor, or another passive component.

[0042] A conductive component 16 is disposed on the surface 11s1 of the substrate 11. The conductive component 16 may be a solder bump or a solder ball (e.g., a solder ball).

[0043] An encapsulation layer 17 is disposed on the surface 11s1 of the substrate 11. The encapsulation layer 17 encapsulates the electronic component 15 and the conductive component 16. The encapsulation layer 17 is made of a molding material and may be the same as or different from the encapsulation layer 14. In some embodiments, the encapsulation layer 17 includes an extension 17p. The extension 17p can fill the recess 14r of the encapsulation layer 14. In some embodiments, the extension 17p of the encapsulation layer 17 has a shape corresponding to the recess 14r of the encapsulation layer 14.

[0044] Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 A method for manufacturing a semiconductor device package according to some embodiments of the present invention is described, wherein... Figure 8 , Figure 9 , Figure 10 and Figure 11 A magnified view of a portion of region R1 is shown.

[0045] See Figure 7 A substrate 11 is provided, and an electronic component 12 is disposed on the surface 11s2 of the substrate 11 and connected to the substrate 11 via a conductive component 13. The substrate 11 includes one or more through holes 11o. In some embodiments, the holes 11o are disposed between two conductive components 13. A fixture (or mold) is also provided, the fixture including a fixture 30, a fixture 20a, a suction device 23, and a sensor 24; the substrate 11 is placed on the upper surface of the fixture 20a, with the surface 11s1 of the substrate 11 facing the fixture 20a. In this disclosure, the fixture 30 can be regarded as the upper fixture, and the fixture 20a can be regarded as the lower fixture.

[0046] In some embodiments, the fixture 20a includes a carrier plate 21, a blocking assembly 22a, and a flow channel 25. It should be noted that some components are represented only by blocks or simplified shapes, and the above components may include necessary components and outlines according to actual needs.

[0047] The carrier plate 21 constitutes the main body of the fixture 20a. The carrier plate 21 has a surface 21s1. The surface 21s1 of the carrier plate 21 is adjacent to the surface 11s1 of the substrate 11. A portion of the surface 21s1 of the carrier plate 21 is in contact with the surface 11s1 of the substrate 11, while another portion of the surface 21s1 of the carrier plate 21 is not in contact with the surface 11s1 of the substrate 11 and defines a flow channel 25, which is in fluid communication with the hole 11o. The flow channel 25 is connected to the blocking assembly 22. The carrier plate 21 has an opening for accommodating the blocking assembly 22.

[0048] The blocking component 22 is configured to be embedded in the hole 11o of the substrate 11. Figure 7 In some embodiments shown, the blocking component 22a may be disposed in the carrier plate 21. See also Figure 7A The blocking component 22a includes a movable blocking structure 221 and an actuator 222. In some embodiments, the blocking component 22 is a pressure-sensing check valve used to sense pressure changes and drive the movable blocking structure 221. In some embodiments, the movable blocking structure 221 can move in a longitudinal direction (e.g., a direction perpendicular to the surface 21s1 of the carrier plate 21). In some embodiments, the movable blocking structure 221 can protrude from the surface 21s1 of the carrier plate 21 and pass through the flow channel 25, embedding into the hole 11o of the substrate 11. The movable blocking structure 221 does not fill the hole 11o. The movable blocking structure 221 can be columnar or other shapes. In some embodiments, the top of the movable blocking structure 221 can be cylindrical, conical, or other shapes. In some embodiments, the top of the movable blocking structure 221 is embedded in the hole 11o of the substrate 11. In some embodiments, the movable blocking structure 221 is embedded in the hole 11o of the substrate 11 but does not contact the substrate 11. In some embodiments, the movable blocking structure 221 may initially be embedded in the hole 11o of the substrate 11, and further move upward into the hole 11o of the substrate 11 upon sensing a change in the surrounding environment. The actuator 222 is configured to drive the movable blocking structure 221, enabling the movable blocking structure 221 to move in the longitudinal direction. In some embodiments, the actuator 222 may include a spring. In some embodiments, the actuator 222 may include a solenoid valve. The actuator 222 may be coupled to the sensor 24 and determine whether and in what direction the movable blocking structure 221 moves.

[0049] The suction device 23 can communicate with the flow channel 25. The hole 11o is connected to the suction device 23 via the flow channel 25. The suction device 23 can provide a driving force to attract the encapsulation material, causing the encapsulation material to fill the cavity 31 defined by the fixture 30 and the fixture 20a, flow through the conductive component 13 and toward the hole 11o (see...). Figure 8 , Figure 9 and Figure 10 (See below for explanation). The suction device 23 includes, but is not limited to, a pressure reducing device and a vacuum device.

[0050] Sensor 24 can be coupled to the blocking component 22a. Sensor 24 can detect changes in the surrounding environment of the blocking component 22a. When the change in the surrounding environment of the blocking component 22a exceeds a threshold, sensor 24 can transmit a message to actuator 222, causing actuator 222 to drive the movable blocking structure 221 to move, for example, moving it upward from the carrier plate 21 and embedding it into the hole 11o of the substrate 11. In some embodiments, sensor 24 can be a pressure sensor configured to sense pressure changes on the surface (e.g., the top surface) of the blocking component 22a. When the pressure change on the surface of the blocking component 22a exceeds a threshold, sensor 24 can transmit a message to actuator 222, causing actuator 222 to drive the movable blocking structure 221 to move, for example, moving it upward and embedding it into the hole 11o of the substrate 11.

[0051] A fixture 30 may be placed above the surface 11s2 of the substrate 11. The fixture 30 may cover the substrate 11 and the electronic component 12, and together with the fixture 20a, define a cavity 31. The substrate 11 and the electronic component 12 are located in the cavity 31. The fixture 30 has a surface 30s1 facing the substrate 11 and the electronic component 12. In some embodiments, the fixture 30 does not directly contact the electronic component 12. In some embodiments, the fixture 30 includes an opening 32 and a flow channel 33. The opening 32 extends through the fixture 30. The flow channel 33 may be disposed on the surface 30s1 of the fixture 30 and is in fluid communication with the aperture 11o. The flow channel 33 may be connected to a suction device 23 or other pressure reduction device or vacuum device. Encapsulation material may be injected through the opening 32, and the suction device 23 may provide a driving force to cause the encapsulation material to flow through the conductive component 13 and toward the flow channel 33, substantially filling the cavity 31, and forming an encapsulation layer in the cavity 31 after curing (see Figure 8 , Figure 9 , Figure 10 and Figure 11 (See below for explanation).

[0052] See Figure 8 In some embodiments, a portion (e.g., the top) of the movable blocking structure 221 is embedded in a hole 11o in the substrate 11. At this stage, by means of... Figure 7The suction device 23 shown causes the encapsulation material 14' to fill the cavity 31 and cover the electronic component 12. At this stage, the encapsulation material 14' has not yet filled the holes 11o of the substrate 11, and the change in surface pressure of the blocking component 22a (e.g., the pressure on the top of the movable blocking structure 221) detected by the sensor 24 is not greater than a threshold, so the movable blocking structure 221 is not driven by the driver 222.

[0053] Figure 9 , 10 The illustration shows the movable blocking structure 221 before and after it moves when the change in the surrounding environment of the blocking component 22a exceeds a threshold. (See attached image.) Figure 9 After the encapsulation material 14' fills the holes 11o of the substrate 11, it causes a significant change in the surface pressure of the blocking component 22a. During this stage, the surface pressure change of the blocking component 22a is greater than or equal to a threshold. In some embodiments, when the surface pressure change of the blocking component 22a is greater than or equal to the threshold, or when the encapsulation material 14' contacts the surface of the blocking component 22a, the sensor 24 transmits a message to the actuator 222 to drive the movable blocking structure 221. In some embodiments, when the surface pressure change of the blocking component 22a is greater than or equal to the threshold, the encapsulation material 14' may or may not contact the surface of the blocking component 22a.

[0054] See Figure 10 The driver 222 drives the movable blocking structure 221 to move and embed the encapsulation material 14', forming a recess 14r1. In some embodiments, when the movable blocking structure 221 moves upward, its top is embedded with the encapsulation material 14', and the movable blocking structure 221 seals the hole 11o at the surface 11s1 of the substrate 11, thus preventing the encapsulation material 14' from overflowing from the hole. In some embodiments, when the movable blocking structure 221 moves upward, its top is embedded with the encapsulation material 14', but the movable blocking structure 221 does not completely seal the hole 11o at the surface 11s1 of the substrate 11. Instead, the movable blocking structure 221 slows down the flow of the encapsulation material 14' into the hole 11o (or gradually stops the flow and stops inside the hole 11o), and solidifies into encapsulation material 14 before flowing out of the hole 11o, thus preventing the encapsulation material 14' from overflowing from the hole.

[0055] See Figure 11 The encapsulation material 14' is cured to form the encapsulation layer 14. The fixtures 20a and 30 are removed to manufacture the semiconductor device package 1a. In this embodiment, the recess 14r1 of the encapsulation layer 14 is not cut with a saw or other removal tool, so no cross-section of the filler appears on the surface of the recess 14r1 of the encapsulation layer 14.

[0056] When the encapsulation material 14' is filled into the cavity 31, uneven flow resistance within the cavity 31 causes air to remain in the encapsulation layer, forming voids. In particular, when the spacing between the conductive components 13 is small, voids are more likely to form in the areas between the conductive components 13. In a comparative example, areas where voids may occur are predicted through simulation. Next, corresponding holes are formed on the substrate in the areas where voids may occur, and depressurization or vacuuming is performed at the holes to reduce void formation. However, while this approach facilitates gas venting and prevents void formation, it can easily cause encapsulation material to overflow onto the lower surface of the substrate (11s1), preventing pads or solder balls from forming on the lower surface of the substrate. Therefore, in some embodiments of the present invention, a blocking component 22a is provided below the substrate. The blocking component 22a can be embedded in the hole 11o. Gas is discharged from the hole 11o as the encapsulation material 14' flows through it. When the encapsulation material 14' fills the hole 11o, or even when it is about to overflow through the hole 11o to the surface 11s1, the blocking component 22a blocks the encapsulation material 14' to prevent it from overflowing to the surface 11s1. Therefore, according to the embodiments of this disclosure, not only can gaps be avoided, but also the overflow of encapsulation material can be prevented.

[0057] In another comparative example, encapsulation material overflowing from the lower surface of the substrate is removed using tape. However, this approach may still result in residual adhesive remaining on the lower surface of the substrate, preventing pads or solder balls from forming on the substrate. According to embodiments of this disclosure, the problem of residual adhesive can be effectively mitigated by blocking the flow of encapsulation material 14' with a movable barrier structure 221.

[0058] In this embodiment, the end (top) of the movable blocking structure 221 can be conical, cylindrical, or other suitable shapes. When the end of the movable blocking structure 221 is conical, the margin of positioning error can be increased, and the problem of film pulling is less likely to occur when detaching from the movable blocking structure 221.

[0059] Figure 12 , Figure 13 and Figure 14 A method for manufacturing a semiconductor device package according to some embodiments of the present invention is described, wherein... Figure 13 , Figure 14 A magnified view of a portion of region R1 is shown.

[0060] See Figure 12 It provides a substrate 11, a fixture 20b, a fixture 30, and a suction device 23. Figure 12 The method is similar to Figure 7 One of the differences is that jig 20b is used instead of jig 20a.

[0061] In some embodiments, fixture 20b includes a carrier plate 21 and a blocking assembly 22b.

[0062] The carrier plate 21 constitutes the main body of the fixture 20b. The carrier plate 21 has a surface 21s1. The surface 21s1 of the carrier plate 21 is adjacent to the surface 11s1 of the substrate 11. A portion of the surface 21s1 of the carrier plate 21 is in contact with the surface 11s1 of the substrate 11. Another portion of the surface 21s1 of the carrier plate 21 is not in contact with the surface 11s1 of the substrate 11 and defines a flow channel 25, which is in fluid communication with the hole 11o. The flow channel 25 is connected to the blocking assembly 22.

[0063] The blocking component 22b is configured to embed into the aperture 11o of the substrate 11. For example, the blocking component 22b may protrude from the surface 21s1 of the carrier plate 21, and in some embodiments, the blocking component 22b further extends toward the aperture 11o of the substrate 11, embedding into the aperture 11o of the substrate 11. In some embodiments, the blocking component 22b is integrally formed with the carrier plate 21. In some embodiments, the blocking component 22b is monolithically formed with the carrier plate 21. In some embodiments, the blocking component 22b may be additionally formed on the surface 21s1 of the carrier plate 21. In some embodiments, the blocking component 22b is conical, cylindrical (e.g., cylindrical), or other suitable shape.

[0064] See Figure 12A The diagram illustrates the dimensional proportions of the blocking component 22b and the hole 11o. For example... Figure 12 and Figure 12A As shown, the blocking component 22b is embedded in the hole 11o of the substrate 11, and the portion of the hole 11o not occupied by the blocking component 22b is in fluid communication with the flow channel 25. The hole 11o of the substrate 11 has a radius D1, and the portion of the blocking component 22b embedded in the hole has a radius D2. The ratio of D1 to D2 can be adjusted so that the encapsulation material 14' does not overflow from the hole 11o. Not limited by theory, the blocking component 22b itself can impede the flow of the encapsulation material 14' in the hole 11o. In addition, the blocking component 22b reduces the channel size in the hole 11o, so the encapsulation material 14' slows down (or gradually stops flowing) after flowing into the hole 11o, and solidifies into encapsulation material 14 in the hole 11o. In some embodiments, the ratio of D1 to D2 can be between 2:1 and 5:4, for example, 3:2 or 4:3. The ratio of D1 to D2 can also be other suitable ranges. In some embodiments, the encapsulation material 14' includes fillers (not shown in the figure). Figure 12A For reference Figure 2A The filler 141) has a particle size (or average particle size) D3. In some embodiments, the particle size D3 of the filler is smaller than the difference between radius D1 and radius D2. In other embodiments, the particle size D3 of the filler may be greater than or equal to the difference between radius D1 and radius D2.

[0065] See Figure 13 The encapsulation material 14' is filled into the cavity 31 by the suction device 23 to encapsulate the electronic component 12 and the conductive component 13, and fills the holes 11o of the substrate 11. When the encapsulation material 14' fills part of the hole 11o, or when the encapsulation material 14' is about to fill the hole 11o, the blocking component 22a slows down and stops the flow of the encapsulation material 14', thus preventing the encapsulation material 14' from overflowing onto the surface 11s1.

[0066] See Figure 14 The encapsulation material 14' is cured to form the encapsulation layer 14. Fixtures 20b and 30 are removed to manufacture the semiconductor device package 1c. The encapsulation layer 14 has a surface 14s1 and a recess 14r3. The surface 14s1 and the recess 14r3 of the encapsulation layer 14 are not cut with a saw or other removal tool, therefore no filler cross-section appears on the surface of the recess 14r3 of the encapsulation layer 14.

[0067] Figure 15 and Figure 16 This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present invention.

[0068] See Figure 15 The system provides a substrate 11, a fixture 20c, a fixture 30, and a suction device 23. Electronic components 12 and conductive components 13 are disposed on the surface 11s2 of the substrate 11.

[0069] In some embodiments, the fixture 20c includes a carrier plate 21 and a blocking assembly 22c.

[0070] The carrier plate 21 constitutes the main body of the fixture 20c. The carrier plate 21 has a surface 21s1. The surface 21s1 of the carrier plate 21 is adjacent to the surface 11s1 of the substrate 11.

[0071] In some embodiments, the blocking component 22c is embedded in the carrier plate 21, and a portion of the blocking component 22c protrudes from the surface 21s1 of the carrier plate 21 and is embedded in the hole 11o of the substrate 11. In some embodiments, the blocking component 22c has a needle-like structure. The carrier plate 21 has an opening (not shown) corresponding to the hole 11o of the substrate 11, the diameter of the opening being smaller than the diameter of the hole 11o, and the blocking component 22c is embedded in the hole 11o of the substrate 11 through the opening. Since the surface 21s1 of the carrier plate 21 contacts the surface 11s1 of the substrate 11, it closes the hole 11o of the substrate 11, leaving only an opening for the blocking component 22c to pass through, thus preventing the encapsulation material 14' from overflowing from the hole to the surface 11s1. In some embodiments, the blocking component 22c has a hollow channel that extends through the blocking component 22c. This hollow channel connects the hole 11o of the substrate 11 and the outside of the carrier plate 21. The hole 11o can be connected to other suction devices (not shown) through this hollow tube.

[0072] The encapsulation material 14' is drawn into the cavity 31 through the opening 32 and into the hole 11o by the suction device 23. The operation of the suction device 23 stops when the encapsulation material 14' has partially filled the hole 11o or completely filled the hole 11o. (See also...) Figure 16 The encapsulation material 14' is cured to form the encapsulation layer 14. The blocking component 22c and the fixture 30 are removed to manufacture the semiconductor device package 1d. The encapsulation layer 14 has a surface 14s1 and a recess 14r4. The surface 14s1 and the recess 14r4 of the encapsulation layer 14 are not cut with a saw or other removal tool, so there is no cross-section of filler on the surface of the recess 14r3 of the encapsulation layer 14.

[0073] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include plural referents.

[0074] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials generally refer to those materials that offer little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity exceeding approximately 10. 4 S / m, such as at least 10 5 S / m or at least 10 6 Conductive materials with conductivity of S / m. The conductivity of the material may sometimes vary with temperature. Unless otherwise stated, the conductivity of the material is measured at room temperature.

[0075] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0076] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual installations due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor device package, comprising: A substrate having a first surface, a second surface, and a hole extending from the first surface to the second surface; A first electronic component is disposed on the second surface of the substrate and covers the hole; as well as A first encapsulation layer covers the first electronic component, wherein the first encapsulation layer has an extension that fills a portion of the hole; A second electronic component is disposed on the first surface of the substrate; and A second encapsulation layer covers the second electronic component, wherein the second encapsulation layer has an extension that, together with the extension of the first encapsulation layer, fills the hole.

2. The semiconductor device package of claim 1, wherein the end portion of the extension of the first packaging layer has a recess.

3. The semiconductor device package of claim 2, wherein the recess is a conical recess, a columnar recess, or a needle-shaped recess.

4. The semiconductor device package of claim 1, wherein the first packaging layer has a first surface, the first surface of the first packaging layer being substantially coplanar with the first surface of the substrate.

5. The semiconductor device package of claim 2, wherein the recess extends from a first surface of the first packaging layer toward the second surface of the substrate.

6. The semiconductor device package of claim 2, wherein the first package layer includes a filler, and the filler has no cross-section exposed to the recess.

7. The semiconductor device package according to claim 1, wherein the end portion of the extension of the first packaging layer has a recess, and the extension of the second packaging layer is embedded in the recess.

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