Semiconductor package and method of manufacturing the same

Abstract

The present invention provides a joining method for constructing a joint with high thermal reliability between electrodes and wiring formed on both sides of a semiconductor device. The manufacturing method of a semiconductor package of the present invention includes the steps of joining a semiconductor chip to a first substrate in a manner of sandwiching a joining film, forming a first insulating film on the semiconductor chip, forming a first through-hole in the first insulating film, forming a first wiring on the first insulating film in a manner of electrically connecting with the semiconductor chip through the first through-hole, forming a second through-hole in the joining film, and forming a second wiring under the semiconductor chip in a manner of electrically connecting with the semiconductor chip through the second through-hole.

Description

Technical Field

[0001] This invention relates to semiconductor packages, such as semiconductor packages in which power semiconductor devices are mounted, and methods for manufacturing the same. Background Technology

[0002] Power semiconductor devices are semiconductor devices whose basic functions are power conversion and control. These power semiconductor devices play an important role not only in inverters or small motors used in home appliances or OA (office automation) equipment, but also in power conversion and control in power systems of power plants and motor drive systems of trams or automobiles. Representative power semiconductor devices include rectifier diodes with pn junction diode structures or Schottky barrier diode structures, power transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), and thyristors. As disclosed in Japanese Patent Application Publication Nos. 2012-164817, 2012-164817, 2012-164193, and 2012-164819, conventional power semiconductor devices are supplied as semiconductor chips (hereinafter also referred to as chips) having one or more electrodes (terminals) on the top and bottom surfaces, and wiring is constructed on both the top and bottom surfaces of the chip to electrically connect to an external power supply or other devices. Summary of the Invention

[0003] In one embodiment of the present invention, a semiconductor package includes: a semiconductor chip; a first insulating film for embedding the semiconductor chip and having a first via; a first wiring on the semiconductor chip and electrically connected to the semiconductor chip through the first via; a bonding film below the semiconductor chip and having a second via; and a second wiring below the bonding film and electrically connected to the semiconductor chip through the second via, wherein the material of the first insulating film is different from the material of the bonding film.

[0004] A semiconductor chip may have a first terminal and a second terminal below and above the semiconductor chip, respectively, and the semiconductor chip may be electrically connected to a second wiring and a first wiring through the first terminal and the second terminal, respectively.

[0005] The semiconductor package may have a third via within the first insulating film, or it may have a third wiring located below the first insulating film and electrically connected to the first wiring through the third via. The first wiring and the third wiring may be connected in the third via. The second wiring and the third wiring may exist in the same layer.

[0006] The sizes of the first, second, and third through holes can be different. The bonding membrane can also have multiple through holes.

[0007] The bonding film may include insulating material.

[0008] The semiconductor package may also have a substrate on the first wiring.

[0009] In one embodiment of the present invention, a method for manufacturing a semiconductor package includes the following steps: bonding a semiconductor chip to a first substrate by means of clamping a bonding film; forming a first insulating film on the semiconductor chip; forming a first via in the first insulating film; forming a first wiring on the first insulating film in a manner that is electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip in a manner that is electrically connected to the semiconductor chip through the second via.

[0010] In the manufacturing method of a semiconductor package, a semiconductor chip may have a first terminal and a second terminal below and above the semiconductor chip, respectively, and a first wiring and a second wiring may be formed by electrically connecting the semiconductor chip through the second terminal and the first terminal, respectively.

[0011] In the manufacturing method of a semiconductor package, a third via can be formed simultaneously with a first via in a first insulating film, and a first wiring can be formed by burying the third via. A third wiring can be formed simultaneously with a second wiring under the third via, in a manner electrically connected to the first wiring.

[0012] In the manufacturing method of a semiconductor package, the sizes of the first through-hole, the second through-hole, and the third through-hole can be different. The second through-hole can be formed in a manner that penetrates through the first substrate. The second through-hole can be formed by having multiple through-holes on the bonding film.

[0013] In a method for manufacturing a semiconductor package, the bonding film may include an insulating material. The material comprising the first insulating film may be different from the material comprising the bonding film.

[0014] In a method for manufacturing a semiconductor package, a first substrate may have an opening and wiring through the opening, and the first wiring may be formed by electrically connecting the wiring through a third through-hole. Attached Figure Description

[0015] Figures 1A to 1C This is a cross-sectional schematic diagram of a semiconductor package according to one embodiment of the present invention.

[0016] Figure 2 This is a cross-sectional schematic diagram of a semiconductor package according to one embodiment of the present invention.

[0017] Figures 3A to 3E A diagram illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0018] Figures 4A to 4D A diagram illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0019] Figure 5 A diagram illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0020] Figures 6A to 6D A diagram illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0021] Figures 7A to 7D A diagram illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0022] Figure 8A and Figure 8B A diagram illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0023] (Explanation of reference numerals in the attached diagram)

[0024] 100: First substrate; 105: Second substrate; 110: Bonding film; 120: Semiconductor chip;

[0025] 122: First terminal; 124: Second terminal; 126: Second terminal; 130: First insulating film;

[0026] 135: Second insulating film; 142: First through hole; 144: First through hole; 146: Third through hole;

[0027] 148: Third via; 150: First wiring layer; 152: First wiring; 154: First wiring;

[0028] 156: First wiring; 160: Second through-hole; 170: Second wiring; 172: Third wiring;

[0029] 174: Third wiring layer; 175: Second wiring layer; 180: Resist layer; 200: First substrate;

[0030] 202: Substrate wiring; 204: Substrate wiring; 210: Bonding film; 220: Semiconductor chip;

[0031] 222: First terminal; 224: Second terminal; 226: Second terminal; 230: First insulating film;

[0032] 235: Second insulating film; 242: First through hole; 244: First through hole; 246: Third through hole;

[0033] 248: Third via; 250: First wiring layer; 252: First wiring; 254: First wiring;

[0034] 260: Second through hole; 270: Second wiring; 272: Third wiring; 274: Third wiring;

[0035] 275: Second wiring layer; 280: Anti-corrosion layer Detailed Implementation

[0036] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention can be implemented in various ways without departing from its spirit, and therefore is not limited to the description of the embodiments illustrated below.

[0037] Furthermore, for the purpose of clearer explanation, the accompanying drawings may schematically show the width, thickness, and shape of various parts compared to the actual embodiments. However, the drawings are merely examples and do not limit the interpretation of the present invention. Additionally, in the specification and drawings of the present invention, elements that have the same function as those described in existing drawings are given the same reference numerals, omitting redundant descriptions.

[0038] In this invention, when multiple membranes are formed by processing a single membrane, these multiple membranes can have different functions and effects. However, these multiple membranes originate from membranes formed as the same layer in the same process. Therefore, these multiple membranes are defined as membranes existing in the same layer.

[0039] Even if other effects differ from those of the embodiments described below, effects that are obvious based on the description of this invention, or effects that can be easily predicted by those skilled in the art, should of course be understood as effects of this invention.

[0040] (First Implementation)

[0041] In this embodiment, using Figure 1A The structure of a semiconductor package according to one embodiment of the present invention will be described.

[0042] The semiconductor package includes a semiconductor chip 120. In the semiconductor chip 120, terminals (lead electrodes) are formed on at least one of both sides of the chip. Figure 1A An example of a semiconductor chip 120 having a first terminal 122 and two second terminals 124, 126 is depicted.

[0043] The semiconductor package has a first insulating film 130 on the semiconductor chip 120 and is formed to embed the semiconductor chip 120 and second terminals 124, 126. The first insulating film 130 protects the semiconductor chip 120 and facilitates the handling of the semiconductor package itself by imparting physical strength to the semiconductor package.

[0044] The first insulating film 130 has through holes (openings). Specifically, the first insulating film 130 has first through holes 142 and 144 in the regions overlapping with the second terminals 124 and 126. Furthermore, the first insulating film 130 has third through holes 146 and 148 in the region near the semiconductor chip 120 but not overlapping with it. The first through holes 142 and 144 reach the second terminals 124 and 126 respectively, and the third through holes 146 and 148 penetrate the first insulating film 130.

[0045] The semiconductor package has first wirings 152 and 154 on a first insulating film 130. First wiring 152 is configured to embed a first through-hole 142 and a third through-hole 146, and first wiring 154 is configured to embed a first through-hole 144 and a third through-hole 148. A portion of the first wirings 152 and 154 is in contact with the upper surface of the first insulating film 130. The first wirings 152 and 154 are electrically connected to the semiconductor chip 120 via second terminals 124 and 126, respectively. As described below, the first wirings 152 or 154 can be formed using electroplating or a conductive metal paste (hereinafter referred to as metal paste).

[0046] Figure 1A The semiconductor package shown may also have a substrate (second substrate) 105 over the first wirings 152, 154 via a second insulating film 135. The second insulating film 135 has the function of bonding the second substrate 105 to the first wirings 152, 154. The second substrate 105 has the function of providing physical strength to the semiconductor package while protecting the semiconductor chip 120. In addition, as described below, when the second wiring 170 or the third wirings 172, 174 are formed, the second substrate 105 acts as a supporting substrate. Therefore, the semiconductor package according to this embodiment does not necessarily include the second insulating film 135 or the second substrate 105, and these may be omitted considering the physical strength or ease of operation of the semiconductor package.

[0047] The semiconductor package also has a bonding film 110 beneath the semiconductor chip 120, and the bonding film 110 includes at least one second via 160. Furthermore, a second wiring 170 is disposed beneath the semiconductor chip 120 and the bonding film 110 to bury the second via 160. The second wiring 170 is electrically connected to the semiconductor chip 120 via a first terminal 122. As described below, the first wirings 152 and 154 can be formed using electroplating or metal paste.

[0048] The bonding film 110 and the first insulating film 130 may be made of different materials. That is, the materials included in the bonding film 110 and the materials included in the first insulating film 130 may be different from each other. Therefore, the materials surrounding the first through holes 142 and 144 may be different from the materials surrounding the second through hole 160.

[0049] The semiconductor package also has third wiring 172 and 174 below the third vias 146 and 148. The sizes (cross-sectional areas) of the first vias 142 and 144, the second via 160, and the third vias 146 and 148 can be different. For example, the third vias 146 and 148 can be the largest, while the second via 160 can be the smallest. Alternatively, the first vias 142 and 144 can be the smallest.

[0050] The third wiring 172 is electrically connected to the first wiring 152, and the third wiring 174 is electrically connected to the first wiring 154. Furthermore, the second wiring 170, the third wiring 172, and 174 are not physically connected to each other, but are separate, although they can exist as the same layer. As described below, the second wiring 170 and the third wiring 172 and 174 can be formed using electroplating or metal paste, etc.

[0051] The semiconductor package may also have a resist layer 180 beneath the second wiring 170, the third wiring 172, and 174. The resist layer 180 has the function of protecting the ends of the second wiring 170, the third wiring 172, and 174. In addition, for example, the resist layer 180 may have low affinity with solder, thereby enabling the solder to selectively contact the second wiring 170, the third wiring 172, and 174.

[0052] Using the semiconductor package of this embodiment, wiring can be constructed for terminals disposed on both sides of a chip, and electrical signals can be supplied from one side of the chip for the terminals disposed on both sides of the chip using these wirings. In addition, the same wiring formation method (e.g., electroplating) can be used for the terminals on both sides of the chip.

[0053] Generally, when a chip with terminals on both sides is mounted, wiring is formed on the terminals on the upper surface of the chip using electroplating. On the other hand, the terminals on the lower surface of the chip are bonded to wiring pads on a printed wiring substrate using high-melting-point solder or sintered metal (e.g., sintered silver), a conductive film such as a conductive die-attach film (DAF), or a diffusion-based connection between contacting metals (metal diffusion bonding). In other words, the methods for forming wiring on the upper and lower surfaces of the chip are different. Therefore, devices such as die-attach devices, which are not used when forming wiring on the upper surface terminals, are necessary, leading to increased process complexity and manufacturing costs. Furthermore, bonding using high-melting-point solder or sintered metal, conductive films, or metal diffusion bonding has relatively low thermal reliability, making it prone to delamination at the bonding surface, resulting in voids at or near the bonding surface.

[0054] As described below, in a semiconductor package according to one embodiment of the present invention, wiring can be constructed on the terminals on both sides of the chip using the same method. Therefore, wiring can be formed on the terminals on both sides using the same process and the same manufacturing apparatus. This simplifies the manufacturing process and reduces manufacturing costs. Furthermore, since the wiring can be formed using the same material (e.g., copper) as the terminals on both sides of the chip, a highly thermally reliable connection can be achieved.

[0055] (Second Implementation)

[0056] In this embodiment, using Figure 1B The structure of a semiconductor package according to one embodiment of the present invention will be described. The semiconductor package of this embodiment differs from the first embodiment in aspects where the structure of the second via 160 differs. Descriptions of structures identical to those of the first embodiment are omitted.

[0057] like Figure 1B As shown, in the semiconductor package of this embodiment, a single via (second via 160) can be formed on the bonding film 110. Furthermore, a second wiring 170 can be formed by burying the via 160. By adopting this structure, the connection area between the first terminal 122 and the second wiring 170 is wide, which significantly reduces contact resistance. Additionally, it promotes heat dissipation of the chip.

[0058] (Third Implementation)

[0059] In this embodiment, using Figure 1CThe structure of the semiconductor package according to an embodiment of the present invention will be described. The semiconductor package of this embodiment differs from the first and second embodiments in that the structures of the third vias 146 and 148 are different. Descriptions of structures identical to those of the first and second embodiments will be omitted.

[0060] like Figure 1C As shown, in the semiconductor package of this embodiment, the third vias 146 and 148 have multiple diameters. That is, the third vias 146 and 148 have two or more regions with different opening areas. Therefore, the first wirings 152 and 154 and the third wirings 172 and 174 are connected within the third vias 146 and 148. The third vias 146 and 148 with this shape can be formed, for example, by forming an opening from the upper surface of the first insulating film 130 without penetrating the first insulating film 130, and then forming a larger opening from the lower surface of the first insulating film 130. By adopting the above structure, each via can be embedded more efficiently using electroplating, and the amount of smear (commonly known as glue residue) generated within the vias can be significantly reduced during via formation.

[0061] (Fourth Implementation)

[0062] In this embodiment, using Figure 2 The structure of the semiconductor package according to an embodiment of the present invention will be described. The semiconductor package of this embodiment differs from the first to third embodiments in that it has a plurality of semiconductor chips 120. Furthermore, it differs from the first to third embodiments in that wiring can be constructed on the top and bottom of the chips. Descriptions of structures identical to those in the first to third embodiments will be omitted.

[0063] like Figure 2 As shown, the semiconductor package of this embodiment has two semiconductor chips 120. Furthermore, the number of semiconductor chips 120 is not limited to two; it may have three or more semiconductor chips 120. The semiconductor package also has first wirings 152, 154, 156 disposed on the first insulating film 130 and the second terminals 124, 126 of the semiconductor chips 120, and the two semiconductor chips 120 are electrically connected to each other via the first wirings 154.

[0064] Beneath the two semiconductor chips 120, and separated by a bonding film 110 having a second via 160, second wirings 170 are respectively provided. Furthermore, a resist layer 180 is formed to cover the ends of the first wirings 152, 154, 156 and the second wirings 170. Additionally, the semiconductor package does not necessarily need to have the resist layer 180 on both sides; for example, it may only have the resist layer 180 on the lower surface of the semiconductor package.

[0065] The first wirings 152, 154, 156 and the second wiring 170 are formed using the same method, such as electroplating or metal paste. Therefore, the process can be simplified, enabling the low-cost manufacture of semiconductor packages comprising multiple semiconductor chips. Furthermore, it provides a bonding with higher thermal reliability. In the semiconductor package of this embodiment, the first wirings 152, 154, 156 serve as electrodes opening on the upper surface of the chip, while the second wiring 170 serves as an electrode opening on the lower surface of the chip. Therefore, it is possible to manufacture a high-density chip mounting substrate on which semiconductor packages are stacked.

[0066] (Fifth Implementation)

[0067] In this embodiment, the method for manufacturing a semiconductor package, as an embodiment of the present invention, utilizes... Figures 3A to 3E , Figures 4A to 4D and Figure 5 ,right Figure 1A The manufacturing method of the semiconductor package shown is described.

[0068] The semiconductor chip 120 is bonded to the first substrate 100 using the bonding film 110. The first substrate 100 can be a substrate formed of metal, glass, ceramic, resin, etc. It can also be a substrate in which glass fibers are mixed into a resin such as an epoxy resin. Alternatively, a printed circuit board with pre-formed wiring can be used. Alternatively, a substrate with a film formed by sandwiching a thin insulating film between a metal thin film such as copper on its surface can be used.

[0069] The bonding film 110 only needs to function as a bonding agent for the first substrate 100 and the semiconductor chip 120. Therefore, insulating materials such as epoxy resin, polyimide, and polysiloxane can be used. For example, insulating DAF can be used as an insulating material. However, as described below, since the first substrate 100 is peeled off during the process, it is preferable to use a bonding film 110 that can peel off the first substrate 100 physically or chemically. For example, an adhesive whose bonding strength decreases when exposed to light can be used as the bonding film 110.

[0070] Semiconductor chip 120 can be a device utilizing the semiconductor characteristics of semiconductors such as silicon, gallium, silicon carbide, and gallium nitride. Examples include rectifier diodes or transistors, as well as power semiconductor devices such as power transistors or thyristors driven by high voltage and high current. Terminals (lead electrodes) are formed on at least one of the two sides of the semiconductor chip 120. Figure 3A An example with a first terminal 122 and two second terminals 124, 126 is described.

[0071] The first insulating film 130 is formed by embedding the semiconductor chip 120 and the second terminals 124 and 126. Figure 3B The first insulating film 130 can be formed using epoxy resin or polyimide resin by a wet film-forming method such as inkjet printing, spin coating, or dipping. Alternatively, an insulating film can be disposed on the semiconductor chip 120 and formed by heating and pressing using lamination or similar processes. The material of the first insulating film 130 can be different from the material of the bonding film 110. In other words, the material included in the first insulating film 130 can be different from the material included in the bonding film 110, therefore the material surrounding the first through holes 142 and 144 can be different from the material surrounding the second through hole 160.

[0072] After that, as Figure 3C As shown, first through-holes 142 and 144 are formed in the region of the first insulating film 130 that overlaps with the second terminals 124 and 126, exposing the second terminals 124 and 126. Simultaneously, third through-holes 146 and 148 reaching the first substrate 100 are formed on the first insulating film 130. The third through-holes 146 and 148 can be larger than the first through-holes 142 and 144, thereby enabling the supply of a large current to the semiconductor chip 120. The first through-holes 142 and 144 and the third through-holes 146 and 148 can be formed using photolithography or laser irradiation.

[0073] Next, a first wiring layer 150 is formed on the first insulating film 130 by burying the first through holes 142, 144 and the third through holes 146, 148. Figure 3D The first wiring layer 150 can be formed using electroplating or metal paste. The first wiring layer 150 can contain copper or gold. Etching is performed on the formed first wiring layer 150 to remove unwanted portions, forming first wirings 152 and 154. First wiring 152 embeds first via 142 and third via 146 and is electrically connected to the semiconductor chip 120 via a second terminal 124. On the other hand, first wiring 154 embeds first via 144 and third via 148 and is electrically connected to the semiconductor chip 120 via a second terminal 126. First wirings 152 and 154 are not directly connected but are separate. Furthermore, since first wirings 152 and 154 are formed by processing the first wiring layer 150, these wirings exist within the same layer.

[0074] When the first wiring layer 150 is formed using electroplating, the first vias 142 and 144 and the third vias 146 and 148 may not be sufficiently embedded in the metal. In this case, metal paste can be used as a supplementary material. For example, metal paste can be applied to a portion of the first vias 142 and 144 or the third vias 146 and 148 to form a metal layer before forming the first wiring layer 150, and then the first wiring layer 150 can be formed using electroplating. Alternatively, a metal layer can be formed by applying metal paste after the first wiring layer 150 has been formed.

[0075] Next, the first substrate 100 is peeled off. Figure 4A The substrate can be peeled off by applying physical force or by chemical treatment. Therefore, the first substrate 100 serves as a temporary substrate. After peeling, the surfaces in contact with the first substrate 100 can be cleaned using an etching developer or similar solution as needed.

[0076] Subsequently, a second substrate 105 is formed on the first wirings 152 and 154 through a second insulating film 135. The second substrate 105 can be the same substrate as the first substrate 100. The second substrate 105 can also be the same substrate that was stripped from the first substrate 100, or a new substrate can be used. The second insulating film 135 can be made of the same material as the first insulating film 130.

[0077] Next, the second via 160 is formed by laser irradiation or photolithography on the bonding film 110, exposing the first terminal 122. Figure 4B Here, it is described that a plurality of second through holes 160 are formed and their size is smaller than that of the first through holes 142 and 146, but a single second through hole 160 may also be formed and its size may be larger than that of the first through holes 142 and 146.

[0078] Next, a second wiring layer 175 is formed using, for example, electroplating or metal paste. Figure 4C The second wiring layer 175 is formed to bury the second via 160 and contacts the first terminal 122. The formed second wiring layer 175 is etched to remove unwanted portions, forming the second wiring 170 and the third wirings 172 and 174. Figure 4D The second wiring 170 is separate from the third wirings 172 and 174. The second wiring 170 is electrically connected to the first terminal 122, the third wiring 172 is electrically connected to the first wiring 152, and the third wiring 174 is electrically connected to the first wiring 154. The second wiring 170, the third wirings 172 and 174 are all formed by processing the second wiring layer 175, so these wirings exist in the same layer.

[0079] Similar to the formation of the first wiring layer 150, a metal layer can be formed by applying metal paste to a portion of the second via 160 before forming the second wiring layer 175, and then the second wiring layer 175 can be formed by electroplating. Alternatively, a metal layer can be formed by applying metal paste after the second wiring layer 175 has been formed by electroplating.

[0080] Subsequently, a resist layer 180 may be formed between the second wiring 170 and the third wirings 172, 174. The resist layer 180 functions to protect the ends of the second wiring 170 and the third wirings 172, 174, and can be formed, for example, using resin and a wet film-forming method. Alternatively, if solder is selectively disposed on the second wiring 170 and the third wirings 172, 174, a material with low affinity for solder, such as a solder mask, may be used for the resist layer 180. Afterward, the second substrate 105 may be peeled off, or alternatively, the second substrate 105 may be left intact. When a metal plate is used as the second substrate 105, it can be used as a heat sink by leaving the second substrate 105 in the semiconductor package.

[0081] As described above, in the manufacturing process of the semiconductor package according to an embodiment of the present invention, wiring can be constructed on the terminals on both sides of the chip using the same method (e.g., electroplating). Therefore, wiring can be formed on the terminals on both sides using the same process and the same manufacturing apparatus. Thus, the manufacturing process can be simplified and manufacturing costs reduced. In addition, since the wiring can be formed using the same material (e.g., copper) as the terminals on both sides of the chip, a bonding with high thermal reliability can be achieved.

[0082] (Sixth Implementation Method)

[0083] In this embodiment, a method for manufacturing a semiconductor package according to an embodiment of the present invention will be described. Specifically, using... Figures 6A to 6D , Figures 7A to 7D , Figure 8A , Figure 8B An example of using a substrate with wiring formed on it as the first substrate shown in the fifth embodiment will be described. Descriptions of structures identical to those in the fifth embodiment will be omitted.

[0084] In this embodiment, a substrate (e.g., a printed wiring substrate) with pre-formed wiring (substrate wiring) 202, 204 is used as the first substrate 200. Figure 6A A through-hole 208 is formed on the first substrate 200, and substrate wiring 202 and 204 are provided through the through-hole 208. In addition, a through-hole 206 is provided between the two through-holes 208. There may be at least one through-hole 206, but multiple through-holes may also be provided.

[0085] A semiconductor chip 220, including first terminals 222 and second terminals 224 and 226, is bonded to the first substrate 200 via a bonding film 210. At this time, the semiconductor chip 220 is bonded in a manner that overlaps with the through-hole 206. Figure 6A Next, a first insulating film 230 is formed by embedding the semiconductor chip 220 and the second terminals 224 and 226. Figure 6B The method for fixing the semiconductor chip 220 and the method for forming the first insulating film 230 are the same as in the fifth embodiment.

[0086] Similar to the fifth embodiment, first through-holes 242, 244 and third through-holes 246, 248 are formed in the first insulating film 230. Then, a first wiring layer 250 is formed on the first insulating film 230 by burying the first through-holes 242, 244 and the third through-holes 246, 248 using electroplating or metal paste. Figure 6D Then, the first wiring layer 250 is etched to form the first wirings 252 and 254. Figure 7A Therefore, although the first wirings 252 and 254 are separate from each other, they exist in the same layer. The first wiring 252 is electrically connected to the semiconductor chip 220 through the second terminal 224, and the first wiring 254 is electrically connected to the semiconductor chip 220 through the second terminal 226.

[0087] Subsequently, similarly to the fifth embodiment, a second insulating film 235 is formed on the first wiring 252, 254. Figure 7B Although not illustrated, a substrate can also be formed on the second insulating film 235.

[0088] Subsequently, laser irradiation is performed through the through-hole 206 to form a second through-hole 260 on the bonding film 210, thereby exposing the first terminal 222. Figure 7C Here, multiple second through holes 260 are provided, but a single second through hole 260 can also be formed.

[0089] Subsequently, similarly to the fifth embodiment, an electroplating method or metal paste is used to form a second wiring layer 275, which overlaps with the substrate wirings 202, 204 and the first substrate 200 and buries the second via 260. Figure 7D ), and then perform etching to form the second wiring 270, the third wiring 272, 274 ( Figure 8A Alternatively, an anti-corrosion layer 280 can be formed between the second wiring 270 and the third wirings 272, 274, as needed. Figure 8B ).

[0090] As described above, in the manufacturing process of the semiconductor package according to an embodiment of the present invention, wiring can be constructed on the terminals on both sides of the chip using the same method (e.g., electroplating). Therefore, wiring can be formed on the terminals on both sides using the same process and the same manufacturing apparatus. Thus, the manufacturing process can be simplified and the manufacturing cost reduced. In addition, since the wiring can be formed using the same material (e.g., copper) as the terminals on both sides of the chip, a bonding with high thermal reliability can be achieved. In particular, it is not necessary to peel off the first substrate 200, and it is not necessary to form the second substrate 105 on the first wiring 252, 254 as in the fifth embodiment, thus shortening the process. Furthermore, since the substrate wiring 202, 204 provided in the through-hole 208 can be arbitrarily designed in advance, a substrate suitable for carrying large currents can be used.

Claims

1. A semiconductor package, comprising: A semiconductor chip includes a first terminal located above the semiconductor chip and a second terminal located below the semiconductor chip, wherein the second terminal is wider than the first terminal; A first insulating film includes a first through-hole, wherein the semiconductor chip is covered by and within the first insulating film; The first wiring is located on the semiconductor chip, and the first wiring is coupled to the first terminal through the first through hole; A bonding film having at least one second via and located beneath the semiconductor chip; The second wiring is located under the bonding film, and the second wiring is coupled to the second terminal through the second through hole; A third through-hole is located in the first insulating film; and The third wiring is located below the first insulating film and is coupled to the first wiring through the third through hole; The materials included in the first insulating film are different from those included in the bonding film, and the third wiring is electrically insulated from the second wiring.

2. The semiconductor package according to claim 1, further comprising: A second insulating film above the first wiring.

3. The semiconductor package according to claim 1, further comprising: The third terminal is disposed on the semiconductor chip and is electrically insulated from the second terminal; The fourth wiring is located on the semiconductor chip and is coupled to the third terminal through a fourth through-hole in the first insulating film; The fifth through hole is located in the first insulating film; as well as The fifth wiring is located below the first insulating film and is coupled to the fourth wiring through the fifth through-hole, wherein: The fourth through hole is wider than the first through hole; The fifth wiring, the third wiring, and the second wiring exist in the same layer; and The first wiring and the fourth wiring exist in the same layer.

4. The semiconductor package according to claim 1, wherein: The second wiring has a first width; The semiconductor chip has a second width; and The first width is greater than the second width.

5. The semiconductor package according to claim 1, wherein: The second wiring and the third wiring exist in the same layer.

6. The semiconductor package according to claim 1, wherein: The first wiring includes electroplated wiring.

7. The semiconductor package according to claim 1, wherein: The bonding membrane includes a plurality of the second through-holes; and The second wiring overlaps the bonding film and extends into each of the plurality of second through holes to contact portions of the second terminal.

8. The semiconductor package of claim 1, further comprising: The substrate includes through-holes and substrate wiring, wherein: The semiconductor chip is bonded to the substrate using the bonding film to overlap the through-hole; The bonding membrane further includes a plurality of through holes; The through hole is aligned with the plurality of through holes; The second wiring is located beneath the substrate and is electrically connected to the semiconductor chip via the through-hole and the plurality of vias; and The third wiring is electrically connected to the first wiring through the substrate wiring and the third through-hole.

9. The semiconductor package according to claim 1, wherein: The bonding film is an insulating material.

10. A semiconductor package, comprising: Semiconductor chips; Top surface; The bottom surface is opposite to the top surface; A side surface that extends between the top surface and the bottom surface; The first terminal is located on the top surface; as well as The second terminal is wider than the first terminal on the bottom surface; A first insulating structure is embedded in the semiconductor chip, the first insulating structure comprising: First surface; The second surface is opposite to the first surface; A first through-hole extends from the first surface to the first terminal; and A second through hole extends from the first surface to the second surface, and the second through hole is laterally spaced from the first through hole; A first wiring is in the first through-hole and coupled to the first terminal, the first wiring extending to overlap the first surface of the first insulating structure; A second wiring is provided, adjacent to the second surface of the first insulating structure and coupled to the second terminal; and The third wiring is adjacent to the second surface of the first insulating structure and coupled to the first wiring through a second through-hole.

11. The semiconductor package of claim 10, further comprising: A second insulation structure is placed on top of the first wiring.

12. The semiconductor package of claim 11, further comprising: The substrate is located on the second insulating structure.

13. The semiconductor package of claim 11, wherein: The second insulating structure covers the first wiring, such that no part of the first wiring is exposed outside the semiconductor package.

14. The semiconductor package of claim 10, further comprising: A second insulating structure is provided above the second wiring and the third wiring.

15. The semiconductor package of claim 14, wherein: The second insulation structure electrically insulates the second wiring from the third wiring; The second insulating structure includes a first opening and a second opening; The second wiring is exposed through the first opening; as well as The third wiring is exposed by the second opening.

16. The semiconductor package of claim 10, further comprising: A bonding layer is located between the second terminal and the second wiring.

17. The semiconductor package of claim 16, wherein: The bonding layer includes bonding layer through-holes; and The second wiring is coupled to the second terminal through the bonding layer via.

18. The semiconductor package of claim 10, wherein: The semiconductor chip also includes a third terminal located on the top surface and laterally spaced from the first terminal; The first insulating structure includes a third through hole extending from the upper surface of the first insulating structure to the third terminal; The semiconductor package further includes a fourth wiring, the fourth wiring being disposed in the third via and coupled to the third terminal; and The third terminal is wider than the first terminal.

19. The semiconductor package of claim 18, wherein: The first insulating structure includes a fourth through hole extending from the upper surface to the lower surface of the first insulating structure; The fourth wiring extends to overlap with the upper surface of the first insulating structure; and The fourth wiring includes a plating layer further disposed within the fourth through hole.

20. The semiconductor package of claim 19, further comprising: The fifth wiring is adjacent to the lower surface of the first insulating structure, and the fifth wiring is coupled to the fourth wiring through the fourth through hole.

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