Flip chip module and method of manufacturing the same

Abstract

A flip chip module and method of manufacturing the same are disclosed. The flip chip module includes a carrier having a top surface, a first molding compound on the top surface. A first thinned flip chip die is on a first portion of the first molding compound and has a first set of interconnects extending through the first portion of the first molding compound to the top surface, the first portion of the first molding compound filling an area between the first thinned flip chip die and the top surface; a second molding compound on the carrier and in contact with the first molding compound and providing a first recess over the first thinned flip chip die, the first recess extending to a first die surface of the first thinned flip chip die; a third molding compound in the first recess and covering the first exposed surface of the first thinned flip chip die, the third molding compound including a thermally conductive additive to provide thermal conduction through the third molding compound.

Description

[0001] This application is a divisional application of the Chinese national phase application, filed on August 5, 2016, with international application number PCT / US2016 / 045809 and entitled "Flip Chip Module with Enhanced Properties". The Chinese national phase application entered the national phase on April 4, 2018, with application number 201680058198.6 and entitled "Flip Chip Module with Enhanced Properties".

[0002] Technical field related applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 202,207, filed August 7, 2016, and U.S. Provisional Patent Application No. 62 / 202,967, filed August 10, 2015.

[0004] This application is a continuation-in-part of U.S. Patent Application No. 14 / 959,129, filed December 4, 2015, entitled “ENCAPSULATED DIES WITH ENHANCEDTHERMAL PERFORMANCE”, and claims priority to U.S. Provisional Patent Application No. 62 / 138,177, filed March 25, 2015.

[0005] All the applications listed above are hereby incorporated into this document by reference. Technical Field

[0006] This disclosure relates to a packaging process, and more specifically to a packaging process for enhancing the thermal performance of encapsulated flip-chip dies. Background Technology

[0007] With the widespread adoption of portable communication devices and the advancement of semiconductor manufacturing technology, high-speed and high-performance transistors are being integrated more densely onto semiconductor dies. Consequently, the heat generated by the semiconductor die increases significantly due to the large number of transistors integrated on it, the high power consumption of the transistors, and their high operating speeds. Therefore, it is desirable to package the semiconductor die in configurations that facilitate better heat dissipation.

[0008] Flip-chip assembly technology is widely used in semiconductor packaging due to the preferred solder interconnects between the flip-chip die and the laminate. This eliminates the space required for wire bonding and die surface areas, and substantially reduces the overall package size. Furthermore, eliminating wire connections from the flip-chip die to the laminate and achieving shorter electrical paths reduces unwanted inductance and capacitance.

[0009] In flip chip assembly, molding compounds formulated with epoxy resin containing silica particles are used to encapsulate and underfill flip chip dies to protect them from damage by the external environment. Some molding compounds can act as barriers that resist chemicals such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH) without decomposition; while others with good thermal conductivity can be used for heat dissipation of the die.

[0010] To accommodate the increased heat generation of high-performance dies and take advantage of flip-chip assembly, the purpose of this disclosure is to provide a method for encapsulating flip-chip dies in a configuration for better heat dissipation. Furthermore, there is a need to improve the thermal performance of the encapsulated flip-chip dies without increasing the package size. Summary of the Invention

[0011] Invention Summary

[0012] A flip-chip module having at least one flip-chip die is disclosed. The flip-chip module includes a carrier having a top surface, wherein a first molding compound is located on the top surface. A first thinned flip-chip die is located on a first portion of the first molding compound and has a first set of interconnects extending through the first portion of the first molding compound to the top surface, wherein the first portion of the first molding compound fills a region between the first thinned flip-chip die and the top surface. A second molding compound is located on the carrier and in contact with the first molding compound and provides a first recess on the first thinned flip-chip die, wherein the first recess extends to a first die surface of the first thinned flip-chip die. A third molding compound is located in the first recess and covers a first exposed surface of the first thinned flip-chip die, wherein the third molding compound includes a thermally conductive additive to provide thermal conductivity through the third molding compound.

[0013] Those skilled in the art will understand the scope of this disclosure and recognize its additional aspects after reading the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0015] Figure 1 A flowchart illustrating an exemplary etching and filling process according to one embodiment of the present disclosure is provided.

[0016] Figures 2 to 8 It shows the relationship with Figure 1 The steps associated with the etching and filling processes provided in the document.

[0017] Figure 9An exemplary application of this disclosure is shown.

[0018] Figure 10A The first part of the flowchart shows additional process steps including a first molding compound used as an underfill and a second molding compound used as an encapsulant, which are combined with a selective etching step that removes the substrate of the selected flip chip die.

[0019] Figure 10B yes Figure 10A The second part of the flowchart shows the setting of a dielectric layer and the application of a third molding compound to fill the cavity left by etching the substrate of the selected flip chip die.

[0020] Figure 11 Is using Figure 10A and Figure 10B A cross-sectional view of a flip-chip module manufactured using the process provided in the image.

[0021] Figure 12 It is a specification sheet listing the thermal, mechanical, electrical, and physical properties of exemplary polymer materials that can be used as molding compounds according to this disclosure. Detailed Implementation

[0022] The embodiments described below illustrate the necessary information to enable those skilled in the art to practice this disclosure and demonstrate the best mode of practice. After reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0023] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be named a second element, and similarly, a second element may be named a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0024] It should be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or an intercalation element may also be present. In contrast, when an element is referred to as being "directly on" or "directly" extending onto another element, no intercalation element is present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as extending "above" or "on" another element, it may be directly on or directly extending over the other element, or an intercalation element may also be present. In contrast, when an element is referred to as extending "directly on" or "directly on" another element, no intercalation element is present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or an intercalation element may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intercalation element is present.

[0025] Relative terms such as “below” or “above” or “up” or “down” or “horizontal” or “vertical” are used herein to describe the relationship between one element, layer or region illustrated in the figures and another element, layer or region. It will be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figures.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “described” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” indicate the presence of the said feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein shall be interpreted as having the meaning consistent with their meaning in the context of this specification and the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0028] In this disclosure, thermosetting polymers and thermoplastic polymers are disclosed as molding compounds. Thermosetting polymers crosslink together to form irreversible chemical bonds. Thus, thermosetting polymers cannot be melted and remolded after curing. An advantage of thermosetting polymers is that they offer a relatively high level of dimensional stability compared to thermoplastic polymers. Dimensional stability is desirable for encapsulating interconnects between flip chip dies and carriers.

[0029] In contrast, thermoplastic polymers soften upon heating and become more fluid when heated above their plasticizing temperature. Once cooled below the plasticizing temperature, thermoplastic polymers can be reheated for remolding because there is no chemical bonding as with thermosetting polymers. A benefit of thermoplastic polymers is their chemical resistance. Another benefit is the ability to use additives such as carbon particles and other fillers to provide thermosetting polymers with a wide range of physical properties. These fillers are easily mixed with thermoplastic polymers because there is no chemical bond interference. However, it should be understood that thermosetting polymers can accommodate more additives and fillers than thermoplastic polymers, with particular attention to the proportions and types of additives.

[0030] For the purposes of this disclosure, a thinned flip-chip die, also known as an etched flip-chip die, is a flip-chip die in which at least 95% of the semiconductor substrate has been removed by chemical etching, mechanical polishing, or a combination of chemical etching and mechanical polishing, or by peeling. In contrast, a flip-chip die with a complete semiconductor substrate is a die that has not undergone a substrate removal process. However, it should be understood that some etching of the semiconductor substrate via vias and patterning can occur as long as 95% of the original substrate is retained after etching, and the semiconductor substrate will still be considered a complete semiconductor substrate.

[0031] This disclosure relates to a method for enhancing the thermal performance of encapsulated flip chip dies. Figure 1 A flowchart illustrating an exemplary etching and filling process according to one embodiment of the present disclosure is provided. Figures 2 to 8 It shows the relationship with Figure 1 The etching and filling processes described herein are associated with specific steps. While various types of materials can be used for the substrate, silicon is included as a preferred material in the examples below. First, as... Figure 2As depicted, multiple flip-chip dies 10 are attached to the top surface of a carrier 12 (step 100). The carrier in the described embodiment is formed of a laminate, but it can also be formed of a wafer-level fan-out (WLFO) carrier, lead frame, ceramic carrier, etc. For illustrative purposes, each flip-chip die 10 includes a substrate 14 having a thickness of approximately 150-500 μm, a device layer 16 having a thickness of approximately 4-7 μm, layer contacts 18 on the bottom surface of the device layer 16, and solder interconnects 20 provided on each of the layer contacts 18. The device layer 16 can be formed of silicon dioxide, gallium arsenide, gallium nitride, silicon germanium, etc., and includes various devices such as diodes, transistors, mechanical switches, resonators, etc. The carrier 12 includes a carrier body 22, carrier contacts 24 on the top surface of the carrier 12, and input / output (I / O) pads (not shown) on the bottom surface of the carrier 12. The I / O pads on the bottom surface of the carrier 12 can be formed using a ball grid array (BGA) or planar grid array (LGA) method and selectively connected to the carrier contacts 24 via any number of vias (not shown). Solder interconnects 20 of the flip chip die 10 are used for electrical and physical connection to the carrier contacts 24 of the carrier 12. Thus, the back side of the substrate 14 of the multiple flip chips 10 will typically become the highest component after the attachment process. The height between the device layer 16 and the carrier body 22 typically varies between 15 and 200 μm.

[0032] Then, the first molding compound 26 is applied to the top surface of the carrier 12, so that the flip chip die 10 is encapsulated by the first molding compound 26, such as... Figure 3 As shown in step 102. The first molding compound 26 can be applied through various procedures, such as sheet molding, secondary molding, compression molding, transfer molding, fill encapsulation, and screen printing encapsulation. The first molding compound 26 is an organic epoxy resin system such as Hitachi Chemical Electronic Materials GE-100LFC, which can be used as an etchant barrier to protect the flip chip die 10 from etch chemicals such as KOH, NaOH, and ACH. The first molding compound is then cured using a curing process (step 104).

[0033] refer to Figures 4 to 6 According to one embodiment of this disclosure, a process is provided for substantially etching away the entire substrate 14 of each encapsulated flip-chip die 10. This process begins by forming a protective coating 28 over the bottom surface of the carrier 12, as... Figure 4As shown in step 106. The purpose of the protective coating 28 is to prevent potential damage to the I / O pads (not shown) on the bottom surface of the carrier 12 in subsequent processing steps. The protective coating 28 may be a chemically resistant strip or liquid protective coating that can withstand etching chemicals such as KOH, NaOH, and ACH without decomposition. Alternatively, a rigid carrier may be used as a protective coating 28 to seal the bottom surface of the carrier 12 to prevent the I / O pads (not shown) on the bottom surface of the carrier 12 from coming into contact with destructive etchant materials in subsequent etching processes.

[0034] The next process step is to thin the first molding compound 26 to expose the back side of the flip chip die 10, where the only exposed part of the flip chip die 10 will be the substrate 14, such as... Figure 5 As shown in step 108. The thinning process can be completed using mechanical processes. An alternative process step would be to keep the back side of the flip chip die 10 always exposed during the molding process using the first molding compound 26.

[0035] Next, a wet / dry etchant chemical, such as KOH, ACH, NaOH, etc., is used to substantially etch away the entire substrate 14 of each flip chip die 10 to provide an etched flip chip die 10E having an exposed surface at the bottom of the cavity, such as... Figure 6 As shown in step 110. Here, essentially etching away the entire substrate 14 means removing at least 95% of the entire substrate 14, and possibly a portion of the device layer 16. Therefore, in some applications, a thin substrate 14 is present at the bottom of the cavity of each etched flip chip die 10E, covering the device layer 16 to protect the devices located on the device layer 16. In other cases, the substrate 14 is completely etched away, and the device layer 16 is exposed at the bottom of the cavity of each etched flip chip die 10E.

[0036] refer to Figures 7 to 8 According to one embodiment of this disclosure, a process for filling the remaining cavities of each etched flip chip die 10E is provided. After the etching step is completed, a second molding compound 30 is applied to substantially fill the remaining cavities of each etched flip chip die 10E, such as... Figure 7As shown in step 112. The second molding compound 30 can be applied through various processes, such as sheet molding, secondary molding, compression molding, transfer molding, fill encapsulation, and screen printing encapsulation. The second molding compound 30 is a high thermal conductivity molding compound. Compared to ordinary molding compounds with a thermal conductivity of 1 watt per kelvin (W / m·K), high thermal conductivity molding compounds have a thermal conductivity of 2.5 W / m·K to 10 W / m·K or higher, such as Hitachi Chemical Electronic Materials Co., Ltd. GE-506HT. The higher the thermal conductivity, the better the heat dissipation performance of the encapsulated etched flip chip die 10E. In addition, the second molding compound 30 directly contacts the exposed surface at the bottom of each cavity of each etched flip chip die 10E. If the substrate 14 is completely removed in the etching step (step 110), the second molding compound 30 directly contacts the device layer 16. If a thin substrate 14 remains after the etching step (step 110), the second molding compound 30 directly contacts the thin substrate 14. It is worth noting that the first molding compound 26 can be formed from the same material as the second molding compound 30. However, unlike the second molding compound 30, the first molding compound 26 does not have thermal conductivity requirements in higher performance embodiments. A curing process (step 114) is then provided to harden the second molding compound. The normal curing temperature is 175℉, but it can be higher or lower, depending on which material is used as the second molding compound 30.

[0037] The top surface of the second molding compound 30 is then planarized to ensure that each encapsulated etched flip chip die 10E has a flat top surface, such as... Figure 8 As shown in step 116. The encapsulation polishing process can be used for planarization. Next, the protective coating 28 applied above the bottom surface of the carrier 12 is removed, as shown in step 116. Figure 9 As shown in step 118. Finally, the product can be tagged, segmented, and tested as modules (step 120).

[0038] Figure 10A and Figure 10B A flowchart illustrating the process steps for manufacturing an additional embodiment of this disclosure is provided. Figure 11 It is used as Figure 10A and Figure 10B A cross-sectional view of an additional embodiment of the flip-chip module 32 manufactured using the process provided in the diagram. Combined with... Figure 11 Watch Figure 10A First, multiple flip-chip dies 10 are attached to the top surface of the carrier 12 (step 200). Figure 11In the exemplary embodiment shown, the leftmost flip-chip die 10 includes an integrated passive device (IPD) 34, the middle flip-chip die 10 includes a microelectromechanical system (MEMS) device 36, and the rightmost flip-chip die 10 includes a complementary metal-oxide-semiconductor (CMOS) controller 38. The IPD 34 typically includes passive components such as integrated inductors, capacitors, and resistors. The MEMS device 36 is typically an RF switch controlled by the CMOS controller 38. Solder interconnects 20 of the flip-chip die 10 are used for electrical and physical connection to carrier contacts 24 of the carrier 12. It should be understood that the MEMS device 36 includes mechanical parts that move within a cavity beneath the cover. For example, a MEMS RF switch version of the MEMS device 36 includes a cantilever having a first end attached to an anchor and a second end located above a conductive pad. An actuator plate below the cantilever is charged to attract the second end of the cantilever to contact the conductive pad, providing a low-resistance electrical path between the anchor and the conductive pad. In other words, charging the actuator board closes the MEMS RF switch. Discharging the actuator board allows the second end of the cantilever to pop off the conductive pad, thereby disconnecting the MEMS RF switch and providing virtually unlimited resistance to current flow. Other types of MEMS devices, such as MEMS capacitors, are also envisioned as MEMS devices 36. Such MEMS devices are well known to those skilled in the art and are within the scope of this disclosure.

[0039] Next, a first molding compound 40 is applied to a portion of the top surface of the carrier 12 substantially adjacent to each of the plurality of flip-chip dies 10 to fill the space between the plurality of flip-chip dies 10 and the top surface of the carrier 12 (step 202). The first molding compound 40 is an epoxy resin with an uncured viscosity not exceeding 360 mPa·s when measured by a cone-plate viscometer. This relatively low viscosity, compared to encapsulating epoxy resin, allows the first molding compound 40 to wick between and around the solder interconnects 20 via capillary action. Thus, the first molding compound 40, industrially referred to as a capillary underfill, is designed to cure at approximately 130°C for about eight minutes and at approximately 150°C for about five minutes to minimize stress on the solder interconnects 20. In one embodiment, the first molding compound has a glass transition temperature of 113°C and a coefficient of thermal expansion of 55 parts per million per degree Celsius (ppm / °C) below the glass transition temperature of 113°C. The exemplary material used for the first molding compound 40 is manufactured by Henkel and sold under product number UF3808.

[0040] In one embodiment, the first molding compound 40 includes additive powders to increase magnetic permeability. Suitable additive powders include fully sintered nickel-zinc (Ni-Zn) ferrite, magnesium-zinc (Mg-Zn), and manganese (Mn-Zn) nanoparticles with magnetic saturation between 45 and 80 electromagnetic units per gram (emu / g).

[0041] The first molding compound 40 is cured actively or passively (step 204). Depending on the materials constituting the first molding compound 40, active curing is achieved by exposing the first molding compound 40 to energy such as heat, light, or chemical energy. Examples of adding energy to cure the first molding compound 40 include heating the first molding compound 40 to a predetermined high temperature such as 175℉, exposing the first molding compound 40 to ultraviolet (UV) light, or exposing the first molding compound 40 to activated chemical vapors or sprays. Passive curing of the first molding compound 40 allows it to cure over time without intervention. The first molding compound 40 may include additives that enhance thermal properties such as thermal conductivity, electrical properties such as dielectric constant, and / or magnetic properties such as magnetic permeability.

[0042] Once the first molding compound 40 is cured, a second molding compound 42 is applied over the top surface of the carrier 12 to encapsulate a plurality of flip-chip dies 10 (step 206). The second molding compound 42 is then passively and / or actively cured (step 208). Depending on the material constituting the second molding compound 42, active curing of the second molding compound 42 is achieved by exposing the second molding compound 42 to energy such as thermal energy, light energy, or chemical energy. Passively curing the second molding compound 42 will allow the second molding compound 42 to cure over time without intervention. The second molding compound 42 may include additives that enhance thermal properties such as thermal conductivity, electrical properties such as dielectric constant, and / or magnetic properties such as magnetic permeability. However, it should be understood that the second molding compound 42 does not necessarily include the same additives or the same amount of additives that may be present in the first molding compound 40. Furthermore, the second molding compound 42 does not need to be the same material as the first molding compound 40. Therefore, the second molding compound 42 may be cured in the same manner as the first molding compound 40 or may be cured in a different manner. An exemplary material constituting the second molding compound 42 is a biphenyl thermosetting epoxy resin manufactured by Hitachi and marketed under product number GE100-LFCS. In at least one embodiment, the second molding compound 42 and the first molding compound 40 are identical. For example, in at least one embodiment, the biphenyl thermosetting epoxy resin constitutes both the first molding compound 40 and the second molding compound 42.

[0043] This process involves forming a protective coating 28 (such as...) on the bottom surface of the carrier 12. Figures 4 to 8 (as shown in step 210) and continue. The purpose of the protective coating 28 is to prevent potential damage to the I / O pads (not shown) on the bottom surface of the carrier 12 in subsequent processing steps. The protective coating 28 may be a chemically resistant strip or liquid protective coating that can withstand etching chemicals such as KOH, NaOH, and ACH without decomposition. Alternatively, a rigid carrier may be used as a protective coating 28 to seal the bottom surface of the carrier 12 to prevent the I / O pads (not shown) on the bottom surface of the carrier 12 from coming into contact with destructive etchant materials in subsequent etching processes.

[0044] The next process step is to thin the first molding compound 40 to expose the back side of selected flip chips of the plurality of flip chip dies 10, wherein the only exposed part of the flip chip die 10 will be the substrate 14 (step 212). Figure 11 As depicted, the substrate 14 of the rightmost flip-chip die 10 with CMOS controller 38 is not exposed because its height is lower than that of the substrate 14 of the rightmost flip-chip die 10. Figure 11 The height of the other flip chips in the plurality of flip chips dies 10 depicted. In this exemplary embodiment, it is desirable to remove the substrate 14 from the leftmost and middle ones of the plurality of flip chips dies 10. The thinning process can be performed by a mechanical process. An alternative process step would be to keep the back side of the desired flip chip in the plurality of flip chips dies 10 always exposed during a molding process in which the second molding compound 42 is applied.

[0045] Each of the substrates 14 exposed in the previous step is then etched to provide an etched die 10E, each etched die having an exposed surface at an etch stop layer 44 disposed above each of the IPD 34 and the MEMS device 36 (step 214). Once the etchant reaches the etch stop layer 44, the etching process inherently stops due to the chemical composition of the etch stop layer 44. The etch stop layer 44 is typically a dielectric layer such as a buried oxide (BOX) layer. The etch stop layer 44 is not required and is therefore not disposed above the CMOS controller 38.

[0046] Now go to Figure 10B At the same time, consider Figure 11 The process continues by roughening the surface of the second molding compound 42 using an etchant (step 216). An exemplary way to achieve the roughening produced in this step is by using a wet chemical etchant such as potassium hydroxide and water (KOH: H2O), which causes the surface silica spheres normally present in the second molding compound 42 to dissolve, leaving a pitted surface. The now pitted surface of the second molding compound 42 provides a significant enhancement in the adhesion of materials subsequently applied or applied.

[0047] Next, a dielectric layer 46 is applied over both the second molding compound 42 and the exposed surface at the etch stop layer 44 at the bottom of the cavity left by the etch stop layer 44 at the substrate 14 of each of the etched flip-chip dies 10E (step 218). The dielectric layer 46 provides a moisture barrier not provided by the etch stop layer 44. An exemplary material constituting the etch stop layer 44 is silicon nitride (SiN). The thickness of the dielectric layer 46 can be... to Between, and usually the thickness is and between.

[0048] The process continues by applying a third molding compound 48 to substantially fill each cavity and directly contact the exposed surface of each of the etched flip chips in the plurality of flip chips dies 10 (step 220). In this exemplary embodiment, the exposed surface is the exposed surface of the dielectric layer 46. Moreover, as Figure 11 As shown in the exemplary embodiment, the third molding compound 48 may be disposed over the entire dielectric layer 46.

[0049] The third molding compound 48 is then passively and / or actively cured (step 222). Active curing of the third molding compound 48 is achieved by exposing it to energy such as heat, light, or chemical energy, depending on the materials constituting it. Passively curing the third molding compound 48 allows it to cure over time without intervention. The third molding compound 48 may include additives that enhance thermal properties such as thermal conductivity, electrical properties such as dielectric constant, and / or magnetic properties such as magnetic permeability. However, it should be understood that the third molding compound 48 need not include the same additives or the same amount of additives that may be present in the first molding compound 40 or the second molding compound 42. Furthermore, the third molding compound 48 need not be made of the same material as the first molding compound 40 or the second molding compound 42. Therefore, the third molding compound 48 may be cured in the same manner as the first molding compound 40 or the second molding compound 42, or it may be cured in a different manner.

[0050] Once the third molding compound 48 has cured, its top surface is planarized to ensure that each encapsulated etched flip-chip die 10E has a flat top surface, such as... Figure 11 As shown in step 224. The encapsulation polishing process can be used for planarization. Next, the protective coating 28 applied above the bottom surface of the carrier 12 is removed, as shown in step 224. Figure 9 As shown in step 226. Finally, the flip-chip module 32 is marked, segmented, and tested (step 228).

[0051] Figure 12This is a specification sheet listing the thermal, mechanical, electrical, and physical properties of exemplary polymer materials that can be used as molding compounds according to this disclosure. In at least one embodiment, the exemplary polymer material is a thermoplastic material that can be used as a third molding compound. Furthermore, in at least one embodiment, the second and third molding compounds are identical and include the exemplary polymer material.

[0052] Figure 12 The exemplary polymer material specified in the specification sheet is made by Cool Manufactured and labeled " "D5506 thermally conductive liquid crystal polymer (LCP)" is for sale. It should be understood that... Figure 12 The specification sheet provides only exemplary specifications, and various mechanical and physical properties are available within the scope of this disclosure. Furthermore, Figure 12 The quantitative values ​​of thermal and electrical properties provided in the tables represent only exemplary values ​​within the range of thermal and electrical properties already discussed in the above disclosure.

[0053] Those skilled in the art will recognize improvements and modifications to the embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A flip-chip module, comprising: • Carrier, having a top surface; • A first molding compound is located on the top surface; • A first thinned flip-chip die, which is situated on a first portion of the first molding compound and has a first set of interconnects extending through the first portion of the first molding compound to the top surface, wherein the first thinned flip-chip die substantially excludes a substrate, substantially excluding a substrate means removing at least 95% of the entire substrate, and wherein the first portion of the first molding compound fills the region between the first thinned flip-chip die and the top surface. • A second molding compound, located on the carrier and in contact with the first molding compound, and providing a first recess on the first thinned flip chip die, wherein the first recess extends to a first die surface of the first thinned flip chip die; as well as • A third molding compound, located in the first recess and covering the first exposed surface of the first thinned flip chip die, wherein the first molding compound comprises ferrite nanoparticles to provide magnetic permeability, the second molding compound comprises fillers to provide mechanical strength, and the third molding compound comprises thermally conductive additives to provide thermal conductivity through the third molding compound.

2. The flip-chip module of claim 1, further comprising a second thinned flip-chip die, the second thinned flip-chip die being situated above a second portion of the first molding compound and having a second set of interconnects extending through the second portion to the top surface, wherein: • The second portion of the first molding compound fills the region between the second thinned flip chip die and the top surface; • The second molding compound provides a second recess on the second thinned flip chip die such that the second recess extends to the second exposed surface of the second thinned flip chip die; as well as The third molding compound is located in the second recess and covers the second exposed surface of the second thinned flip chip die.

3. The flip-chip module of claim 2, wherein the first thinned flip-chip die provides a microelectromechanical system (MEMS) component and the second thinned flip-chip die does not provide a microelectromechanical system (MEMS) component.

4. The flip-chip module of claim 2, wherein the first thinned flip-chip die provides an integrated passive device (IPD) and the second thinned flip-chip die does not provide an integrated passive device (IPD).

5. The flip-chip module of claim 1, further comprising a complete flip-chip die having a complete semiconductor substrate, the complete flip-chip die being situated on a second portion of the first molding compound and having a second set of interconnects extending through the first portion to the top surface, wherein: • The second portion of the first molding compound fills the area between the complete flip chip die and the top surface; • The second molding compound covers the entire semiconductor substrate of the complete flip-chip die; as well as • The third molding compound covers the exposed surface of the second molding compound.

6. The flip-chip module of claim 5, wherein the first thinned flip-chip die is a microelectromechanical system (MEMS) device and the complete flip-chip die is a complementary metal-oxide-semiconductor (CMOS) controller.

7. The flip-chip module according to claim 1, wherein the first molding compound, the second molding compound, and the third molding compound are different, each having different physical properties.

8. The flip-chip module of claim 1, wherein both the first molding compound and the second molding compound are thermosetting polymers, wherein the second molding compound is harder than the first molding compound.

9. The flip-chip module of claim 1, wherein the second molding compound is a thermosetting polymer and the third molding compound is a thermoplastic polymer.

10. The flip-chip module of claim 1, wherein the first molding compound and the second molding compound are identical.

11. The flip-chip module of claim 1, wherein the second molding compound and the third molding compound are the same.

12. The flip-chip module of claim 1, wherein the second molding compound has an etched surface to facilitate adhesion to the third molding compound.

13. The flip-chip module of claim 1, wherein the first exposed surface of the first thinned flip-chip die is a surface comprising an etch stop layer of buried oxide (BOX).

14. The flip chip module according to claim 1, further comprising a dielectric layer disposed on the top surface of the second molding compound and the first die surface of the first thinned flip chip die.

15. The flip-chip module of claim 14, wherein the dielectric layer is a silicon nitride (SiN) layer.

16. The flip-chip module of claim 1, wherein the third molding compound has a thermal conductivity greater than 2.5 W / m·K and a thermal conductivity greater than 10 W / m·K. 3 Resistivity in Ohm·cm.

17. A method for manufacturing a flip-chip module, comprising: • Provide a carrier with a top surface; • The flip chip die is attached to the top surface of the carrier by means of an interconnect extending from the flip chip die to the top surface of the carrier; • The space between the flip chip die and the top surface of the carrier is filled with a first molding compound, the first molding compound comprising ferrite nanoparticles to provide magnetic permeability; • A second molding compound is applied to the top surface of the carrier to encapsulate the flip chip die, wherein the second molding compound includes fillers to provide mechanical strength; • Thin the second molding compound to expose the substrate of the flip chip die; • Etching the substrate of the flip chip die such that the substrate is not retained to provide a thinned flip chip die with an exposed surface at the bottom of the cavity; and • A third molding compound is applied to fill the cavity of the thinned flip chip die, wherein the third molding compound includes a thermally conductive additive to provide thermal conductivity through the third molding compound.

18. The method for manufacturing a flip-chip module according to claim 17, further comprising providing a dielectric layer on the exposed surface at the bottom of the cavity prior to applying the third molding compound.

19. The method for manufacturing a flip-chip module according to claim 18, wherein the exposed surface at the bottom of the cavity is the surface of an etch stop layer made of buried oxide (BOX) and the dielectric layer is made of silicon nitride (SiN).

20. The method for manufacturing a flip-chip module according to claim 17, further comprising roughening the top surface of the second molding compound before applying the third molding compound.

21. The method for manufacturing a flip-chip module according to claim 17, wherein the first molding compound is an epoxy resin with an uncured viscosity not exceeding 360 mPa·s when measured by a cone-plate viscometer.

22. The method for manufacturing a flip-chip module according to claim 17, wherein both the first molding compound and the second molding compound are epoxy resins, and the second molding compound is harder than the first molding compound.

23. The method for manufacturing a flip-chip module according to claim 17, wherein the second molding compound is a thermosetting polymer, and the third molding compound has a thermal conductivity greater than 2.5 W / m·K and a thermal conductivity greater than 10 W / m·K. 3 Thermoplastic polymers with resistivity of Ohm·cm.

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