Three-dimensional memory devices and methods of manufacturing the same

Abstract

The present application relates to three-dimensional memory devices and methods of manufacturing the same. A three-dimensional memory device includes a plurality of row lines alternately stacked with a plurality of interlayer dielectric layers in a vertical direction on a substrate, and each of the plurality of row lines has a protrusion protruding from a side surface thereof; and a plurality of vias extending in the vertical direction from the substrate, each via being coupled to the protrusion of a corresponding row line, and the plurality of vias electrically coupling the plurality of row lines to a peripheral circuit defined below the substrate.

Description

Technical Field

[0001] The various implementations generally relate to semiconductor technology, and in particular to three-dimensional memory devices and methods of manufacturing the same. Background Technology

[0002] The advantage of three-dimensional memory devices is that by increasing the number of stacks by stacking memory cells in the vertical direction, a larger capacity can be achieved in the same area, thus providing high performance and excellent power efficiency.

[0003] In three-dimensional memory devices, integration density can be increased by increasing the number of row lines (specifically, word lines) to be stacked. However, if the number of row lines increases, the number of wirings used to connect the row lines and peripheral circuitry (specifically, row decoders) also increases, thus reducing integration density. Therefore, an efficient routing layout method is needed. Summary of the Invention

[0004] Various implementations relate to three-dimensional memory devices with improved integration and methods for manufacturing the same.

[0005] In one embodiment, a three-dimensional memory device may include: a plurality of row lines that are alternately stacked on a substrate in a vertical direction with a plurality of interlayer dielectric layers, and each of the plurality of row lines having a protrusion protruding from its side surface; and a plurality of vias that extend vertically upward from the substrate, each via connecting to the protrusion of a corresponding row line, and the plurality of vias electrically connecting the plurality of row lines to peripheral circuitry defined below the substrate.

[0006] In one embodiment, a method for manufacturing a three-dimensional memory device may include: forming a sacrificial layer on a substrate, the sacrificial layer including a plurality of sacrificial patterns for vias and sacrificial patterns for row lines, the sacrificial patterns for row lines having protrusions connected to corresponding sacrificial patterns for vias among the plurality of sacrificial patterns for vias; forming an interlayer dielectric layer covering the sacrificial patterns for row lines and the sacrificial patterns for vias connected to the sacrificial patterns for row lines, and having a plurality of holes exposing sacrificial patterns for vias among the plurality of sacrificial patterns for vias that are not connected to the sacrificial patterns for row lines; forming a plurality of first conductive patterns in the plurality of holes; repeatedly forming the sacrificial layer, forming the interlayer dielectric layer, and forming the plurality of first conductive patterns to stack a plurality of sacrificial layers, a plurality of interlayer dielectric layers, and a plurality of first conductive patterns on the substrate; and replacing the plurality of sacrificial layers with a conductive material.

[0007] In one embodiment, a three-dimensional memory device may include: a plurality of row lines that are alternately stacked on a substrate in a vertical direction with a plurality of interlayer dielectric layers; a plurality of interconnect lines that are directly connected to the plurality of row lines and each has a protrusion that extends beyond the side surface of the plurality of row lines; and a plurality of through holes that extend vertically from the substrate and are respectively connected to the protrusions of the plurality of interconnect lines, and electrically connect the plurality of row lines to peripheral circuitry defined below the substrate.

[0008] In one embodiment, a method for manufacturing a three-dimensional memory device may include: forming a sacrificial layer on a substrate, the sacrificial layer including sacrificial patterns for row lines and a plurality of sacrificial patterns for vias; forming an interlayer dielectric layer covering the sacrificial patterns for row lines and having a plurality of holes exposing a plurality of sacrificial patterns for vias; stacking a plurality of sacrificial layers and a plurality of interlayer dielectric layers on the substrate by alternately repeating the formation of sacrificial layers and the formation of interlayer dielectric layers; forming a stepped structure exposing a portion of each of the plurality of sacrificial layers; forming a plurality of sacrificial patterns for interconnects corresponding to the plurality of sacrificial layers on the stepped structure, and each of the plurality of sacrificial patterns for interconnects connecting at least one of the sacrificial patterns for row lines and the plurality of sacrificial patterns for vias of the corresponding sacrificial layer; and replacing the plurality of sacrificial layers and the plurality of sacrificial patterns for interconnects with a conductive material.

[0009] In one embodiment, a method for manufacturing a three-dimensional memory device may include: forming a sacrificial layer on a substrate; forming an interlayer dielectric layer on the sacrificial layer covering a portion of the sacrificial layer; stacking a plurality of sacrificial layers and a plurality of interlayer dielectric layers by alternately repeating the formation of sacrificial layers and the formation of interlayer dielectric layers; forming a plurality of supports passing through the plurality of sacrificial layers near the plurality of interlayer dielectric layers; separating sacrificial patterns for row lines and a plurality of sacrificial patterns for vias in each of the plurality of sacrificial layers by forming slits in the plurality of sacrificial layers; forming a stepped structure exposing a portion of each of the plurality of sacrificial layers; forming a plurality of sacrificial patterns for interconnects corresponding to the plurality of sacrificial layers on the stepped structure, wherein each of the plurality of sacrificial patterns for interconnects connects at least one of the sacrificial patterns for row lines and the plurality of sacrificial patterns for vias in the corresponding sacrificial layer; and replacing the plurality of sacrificial layers and the plurality of sacrificial patterns for interconnects with a conductive material. Attached Figure Description

[0010] Figure 1 This is a block diagram schematically illustrating a three-dimensional memory device according to an embodiment of the present disclosure.

[0011] Figure 2 This is a perspective view illustrating a portion of a three-dimensional memory device according to an embodiment of the present disclosure.

[0012] Figure 3 This is an example Figure 2 An exploded 3D view of the lines and through holes.

[0013] Figure 4 This is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.

[0014] Figures 5A to 5F This is a perspective view illustrating a three-dimensional memory device according to an embodiment of the present disclosure through process steps.

[0015] Figures 6A to 6F It is along Figures 5A to 5F The cross-sectional view taken by line AA′.

[0016] Figure 7 This is an example of... Figure 5F A three-dimensional view of the sacrificial layer and the first conductive pattern at the step.

[0017] Figure 8 This is a perspective view illustrating a portion of a three-dimensional memory device according to another embodiment of the present disclosure.

[0018] Figure 9 This is an example Figure 8 An exploded 3D view of the lines, through holes, and connecting lines.

[0019] Figure 10 This is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present disclosure.

[0020] Figures 11A to 11H A perspective view illustrating a three-dimensional memory device according to another embodiment of the present disclosure is provided through process steps.

[0021] Figures 12A to 12D It is along Figures 11A to 11D The cross-sectional view taken from line BB′.

[0022] Figure 13 This is an example Figure 11H A perspective view of the sacrificial layer of the three-dimensional memory device and the sacrificial pattern for the interconnects.

[0023] Figure 14 This is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to yet another embodiment of the present disclosure.

[0024] Figures 15A to 15G The diagram illustrates a perspective view of a three-dimensional memory device according to another embodiment of the present disclosure through process steps.

[0025] Figures 16A to 16C It is along Figures 15A to 15CThe cross-sectional view taken by line CC′.

[0026] Figure 17 This is a perspective view illustrating a three-dimensional memory device that differs from an embodiment of the present disclosure.

[0027] Figure 18 This is a block diagram illustrating a memory system including a three-dimensional memory device according to an embodiment of the present disclosure.

[0028] Figure 19 This is a block diagram illustrating a computing system including a three-dimensional memory device according to an embodiment of the present disclosure. Detailed Implementation

[0029] The advantages and features of this disclosure, as well as methods of implementing them, will become apparent from the following description of exemplary embodiments, taken with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in a variety of different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0030] Because the figures, dimensions, ratios, angles, and quantities of elements given in the accompanying drawings describing embodiments of this disclosure are merely exemplary, this disclosure is not limited to the matters shown. Throughout the specification, similar reference numerals refer to similar components. In describing this disclosure, detailed descriptions of related technologies will be omitted where it is determined that such detailed descriptions may obscure the gist or clarity of the disclosure. It should be understood that the terms “comprising,” “having,” “including,” etc., used in the specification and claims should not be construed as limiting to the means listed thereafter unless otherwise expressly stated. When referring to a singular noun, the use of an indefinite or definite article (e.g., “a,” “an,” or “the”) may include the plural form of the noun unless otherwise expressly stated.

[0031] When interpreting the elements in the embodiments of this disclosure, they should be interpreted as including tolerances, even if not explicitly mentioned.

[0032] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are for the purpose of distinguishing one component from another and are not intended to limit the substance, order, sequence, or quantity of the components. Additionally, the components in embodiments of this disclosure are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, as used herein, within the technical concept of this disclosure, a first component may be a second component.

[0033] If a component is described as "connected," "linked," or "attached" to another component, it can mean that the component is not only directly "connected," "linked," or "attached," but also indirectly "connected," "linked," or "attached" via a third component. When describing positional relationships such as "component A on component B," "component A above component B," "component A below component B," and "component A next to component B," one or more other components may be placed between component A and B unless the terms "directly" or "immediately adjacent" are explicitly used.

[0034] Features of the various exemplary embodiments of this disclosure can be combined, integrated, or separated, in whole or in part. Technically, various interactions and operations are feasible. Various exemplary embodiments can be practiced individually or in combination.

[0035] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a block diagram schematically illustrating a three-dimensional memory device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 The three-dimensional memory device according to embodiments of the present disclosure may include a memory cell array 100 and peripheral circuitry 200. Peripheral circuitry 200 may include a row decoder (X-DEC) 210, a page buffer circuit 220, control logic 230, a voltage generator 240, a column decoder (Y-DEC) 250, and an input / output buffer (IO buffer) 260.

[0038] The memory cell array 100 may include a plurality of memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include a plurality of cell strings. Each cell string may include a plurality of memory cells stacked on a substrate. Although in this specification, memory cells may be described in the example as flash memory cells, the type of memory cells is not limited thereto, and the spirit of this disclosure can be applied to other types of memory cells besides flash memory cells.

[0039] The memory cell array 100 can be connected to the row decoder 210 via row lines RL. The row lines RL can include select lines and word lines, and the select lines can include drain select lines and source select lines. The memory cell array 100 can be connected to the page buffer circuit 220 via bit lines BL. The row lines RL can be connected to corresponding memory blocks BLK1 to BLKn. The bit lines BL can be collectively connected to multiple memory blocks BLK1 to BLKn.

[0040] The row decoder 210 can select any one of the memory blocks BLK1 to BLKn of the memory cell array 100 in response to the row address RADD provided from the control logic 230. The row decoder 210 can transmit operating voltages from the voltage generator 240, such as programming voltage (Vpgm), pass voltage (Vpass), and read voltage (Vread), to the row line RL connected to the selected memory block.

[0041] Page buffer circuit 220 may include multiple page buffers PB connected to memory cell array 100 via bit line BL. Depending on the operating mode, page buffers PB may function as write drivers or sense amplifiers. In programming operations, page buffers PB may latch data DATA received via input / output buffer 260 and column decoder 250, and may apply the voltage required to store data DATA in selected memory cells to bit line BL in response to control signals from control logic 230. In read operations, page buffers PB may read data DATA stored in selected memory cells via bit line BL, and may output the read data DATA to external components via column decoder 250 and input / output buffer 260.

[0042] Control logic 230 can output the row address RADD from the address ADD received through input / output buffer 260 to row decoder 210, and can output the column address CADD from the address ADD received through input / output buffer 260 to column decoder 250. Control logic 230 can control page buffer circuit 220 and voltage generator 240 to access the selected memory cell in response to command CMD received through input / output buffer 260.

[0043] Voltage generator 240 can generate various voltages required in the memory device. For example, voltage generator 240 can generate programming voltage, pass voltage, select read voltage, and unselect read voltage. Column decoder 250 can input programming data into page buffer circuit 220 in response to column address CADD from control logic 230.

[0044] As the size of electronic products containing memory devices decreases, there is a growing demand for smaller memory device sizes. With the increasing number of row lines (RLs) due to the need for high capacity, the number of wires connecting the row lines (RLs) and the row decoder 210 also increases. To mitigate the increase in memory device size caused by the increased number of wires and to increase integration density, an efficient wiring layout method is needed.

[0045] In the following text, and in the accompanying drawings, the direction projecting vertically from the top surface of the substrate is defined as the vertical direction VD, and two directions parallel to the top surface of the substrate and intersecting each other are defined as the first direction FD and the second direction SD, respectively. For example, the first direction FD may correspond to the extension direction of a row line, and the second direction SD may correspond to the extension direction of a bit line. The first direction FD and the second direction SD may intersect each other substantially perpendicularly. In the accompanying drawings, the directions indicated by arrows and their opposites represent the same direction.

[0046] Figure 2 This is a perspective view illustrating a portion of a three-dimensional memory device according to an embodiment of the present disclosure, and Figure 3 This is an example Figure 2 An exploded 3D view of the lines and through holes.

[0047] Reference Figure 2 and Figure 3 A three-dimensional memory device according to an embodiment of the present disclosure may include a plurality of row lines RL alternately stacked on a first substrate 10 in a vertical direction VD with a plurality of interlayer dielectric layers 12. Each of the plurality of row lines RL and the plurality of interlayer dielectric layers has a protrusion PP protruding from its side surface. A plurality of vias VIA extending in the vertical direction VD from the top surface of the first substrate 10 are respectively connected to the protrusions PP of the plurality of row lines RL. The plurality of vias VIA electrically connect the plurality of row lines RL to a peripheral circuitry 200 defined below the first substrate 10.

[0048] More specifically, the three-dimensional memory device according to embodiments of the present disclosure may include a cell section (CELL) and a peripheral circuit section (PERI) disposed below the cell section (CELL). The three-dimensional memory device according to embodiments of the present disclosure may have a PUC (lower peripheral cell) structure.

[0049] The cell section may include a first substrate 10, multiple row lines RL alternately stacked on the first substrate 10 with multiple interlayer dielectric layers 12, a vertical channel CH passing through the multiple interlayer dielectric layers 12 and the multiple row lines RL, and multiple vias VIA respectively connected to the multiple row lines RL.

[0050] The first substrate 10 may include a semiconductor layer on its surface having a dielectric layer formed thereon. The semiconductor layer may include, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The dielectric layer may be used to isolate the lowermost row line RL of the row lines RL from the semiconductor layer, and may include, for example, an oxide.

[0051] Each line RL may extend in a first direction FD and may have a protrusion PP on its side surface. Furthermore, each line RL may have a pair of protrusions PP extending in a second direction SD from both sides of the end of the line in the first direction FD. In this case, for example, the line RL may have a "T" shape.

[0052] The end of the line RL defined by the protrusion PP can be set in a stepped manner in the first direction FD. When viewed from above, the protrusion PP of the line RL can be set at different positions.

[0053] Although this embodiment illustrates a pair of protrusions PP for each row line RL, the disclosure is not limited thereto. Each row line RL may include one or more protrusions PP.

[0054] Within row lines RL, at least one row line RL starting from the bottom can be configured as a source select line, and at least one row line RL starting from the top can be configured as a drain select line. Row lines RL between the source and drain select lines can be configured as word lines.

[0055] The interlayer dielectric layer 12 can be configured with oxide. For simplicity of illustration, Figure 2 The example shows that the interlayer dielectric layer 12 is formed only between adjacent row lines RL, but the interlayer dielectric layer 12 can be formed not only between adjacent row lines RL, but also between row lines RL and vias VIA and between adjacent vias VIA.

[0056] Although not shown in detail, each of the vertical channels (CH) may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon and may include p-type impurities such as boron (B) in some regions therein. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer stacked sequentially from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stacked structure in which oxide layers, nitride layers, and oxide layers are stacked sequentially.

[0057] Source select transistors can be configured in a region or area surrounding the vertical channel CH via source select lines. Memory cells can be configured in a region or area surrounding the vertical channel CH via word lines. Drain select transistors can be configured in a region or area surrounding the vertical channel CH via drain select lines. A string of source select transistors, multiple memory cells, and drain select transistors arranged along a vertical channel CH can be configured.

[0058] The vias VIA can extend vertically in the direction VD from the top surface of the first substrate 10, and each via can be directly connected to the side surface of the protrusion PP of the corresponding row line RL. The top surface of each via VIA can be disposed on the same plane as the top surface of the corresponding row line RL.

[0059] Among multiple vias (VIAs), a via VIA connected to a row line RL stacked n times from the first substrate 10 may include n-1 first conductive patterns 14 and n second conductive patterns 16 (where n is a natural number). For example, in a via VIA, a via VIA connected to the row line RL located at the bottommost layer (n=1) can be configured using one second conductive pattern 16. A via VIA connected to the row line RL immediately above the bottommost row line RL (n=2) can be configured using two second conductive patterns 16 and one first conductive pattern 14.

[0060] The first conductive pattern 14 can be disposed at the same vertical position as the corresponding interlayer dielectric layer in the plurality of interlayer dielectric layers 12, and the second conductive pattern 16 can be disposed at the same vertical position as the corresponding row line in the plurality of row lines RL.

[0061] The second conductive pattern 16 can be formed at the same process step as the row line RL and can be configured with the same conductive material as the row line RL. For example, the row line RL and the second conductive pattern 16 can include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum).

[0062] The peripheral circuit section PERI may include a second substrate 20, peripheral circuitry 200, dielectric layer ILD, and bottom wiring UM. (Refer to the above.) Figure 1 As described, the peripheral circuitry 200 may include a line decoder ( Figure 1 210), page buffer circuit ( Figure 1 220), control logic ( Figure 1 230), voltage generator ( Figure 1 240), column decoder ( Figure 1 250) and input / output buffers ( Figure 1 (of 260).

[0063] Peripheral circuitry 200 may include peripheral circuitry element 22, and peripheral circuitry element 22 may include planar transistors. The planar transistor may include a gate dielectric layer Gox formed on the second substrate 20, a gate GE formed on the gate dielectric layer Gox, and junctions Jn1 and Jn2 defined on both sides of the gate GE in the active region of the second substrate 20. Junctions Jn1 and Jn2 are regions defined by implanting n-type or p-type impurities into the active region of the second substrate 20. One of the junctions (Jn1 or Jn2) may serve as the source region of the planar transistor, and the other may serve as the drain region of the planar transistor. Peripheral circuitry element 22 may be configured to access the line decoder (…). Figure 1 210), page buffer circuit ( Figure 1 220), control logic ( Figure 1 230), voltage generator ( Figure 1 240), column decoder ( Figure 1 250) and input / output buffers ( Figure 1 One of the 260).

[0064] A dielectric layer ILD can be formed on the second substrate 20 to cover the peripheral circuit 200. Bottom wiring UM can be disposed in the dielectric layer ILD and can be electrically connected to the peripheral circuit 200.

[0065] Contact 30 may be defined below each via VIA, may pass through the first substrate 10 and the dielectric layer ILD, and may connect the via VIA to its corresponding bottom wiring UM. Each via VIA may be electrically connected to the peripheral circuit 200 through contact 30 and bottom wiring UM, and may also electrically connect the corresponding row line RL to the peripheral circuit 200.

[0066] In the following text, reference will be made to Figures 4 to 7 Description for manufacturing Figure 2 The method of the cell section of the three-dimensional memory device shown.

[0067] Figure 4 This is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure. Figures 5A to 5F A perspective view illustrating a three-dimensional memory device according to an embodiment of the present disclosure is provided through process steps. Figures 6A to 6F It is along Figures 5A to 5F The cross-sectional view taken by line AA′, and Figure 7 This is an example Figure 5F A three-dimensional view of the sacrificial layer and the first conductive pattern at the step.

[0068] Reference Figures 4 to 7A method for manufacturing a three-dimensional memory device according to embodiments of the present disclosure may include step S401: forming a sacrificial layer 11 on a first substrate 10, comprising a plurality of sacrificial patterns 11B for vias and sacrificial patterns 11A for row lines. The sacrificial pattern 11A has a protrusion PA connected to a corresponding sacrificial pattern 11B for a via. The method then includes step S402: forming an interlayer dielectric layer 12 covering the sacrificial patterns 11A and 11B and having a plurality of holes H exposing the remaining sacrificial patterns 11B for vias not connected to the sacrificial patterns 11A. The method further includes step S403: forming a plurality of first conductive patterns 14 in the plurality of holes H. Subsequently, in step S404, the plurality of sacrificial layers 11, the plurality of interlayer dielectric layers 12, and the plurality of first conductive patterns 14 are stacked by repeating steps S401 (forming the sacrificial layer 11), S402 (forming the interlayer dielectric layer 12), and S403 (forming the plurality of first conductive patterns 14). The method also includes step S405 of replacing the plurality of sacrificial layers 11 with a conductive material.

[0069] For details, refer to Figure 5A and Figure 6A A sacrificial layer 11-1 (11) can be formed on the first substrate 10, and by patterning the sacrificial layer 11-1 via a photolithography process, a sacrificial pattern 11A-1 (11A) for row lines and a plurality of sacrificial patterns 11B-1 (11B) for vias can be formed. The sacrificial layer 11-1 can be configured with nitride.

[0070] The sacrificial pattern 11A-1 for the running line can extend in the first direction FD and can have a protrusion PA on its side surface. A plurality of sacrificial patterns 11B-1 for through holes can be arranged near the sacrificial pattern 11A-1 in the first direction FD, which is the extension direction of the sacrificial pattern 11A-1 for the running line.

[0071] The protrusion PA of the sacrificial pattern 11A-1 for the line can be connected to at least one of the multiple sacrificial patterns 11B-1 for the through hole. For example, in Figure 5A In this design, the sacrificial pattern 11A-1 for the row lines may have a pair of protrusions PA at its ends in the first direction FD, protruding from its two side surfaces. The protrusions PA of the sacrificial pattern 11A-1 for the row lines may be respectively connected to a pair of sacrificial patterns 11B-1 for through holes, which are disposed on the first substrate 10 and located at the outermost position in the first direction FD among the plurality of sacrificial patterns 11B-1 for through holes.

[0072] Reference Figure 5B and Figure 6BAn interlayer dielectric layer 12-1 (12) covering the sacrificial layer 11-1 can be formed on the first substrate 10. The interlayer dielectric layer 12-1 can be configured with a dielectric material that has etch selectivity relative to the sacrificial layer 11-1. For example, if the sacrificial layer 11-1 is configured with a nitride, the interlayer dielectric layer 12-1 can be configured with an oxide.

[0073] Multiple vias H can be formed in the interlayer dielectric layer 12-1, exposing sacrificial patterns 11B-1 that are not connected to sacrificial patterns 11A-1 for vias. For example, as Figure 5A As shown, if the sacrificial pattern 11A-1 for the line is connected to a pair of sacrificial patterns 11B-1 for through holes located at the outermost end in the first direction FD, then as Figure 5B As shown, a plurality of vias H can be formed in the interlayer dielectric layer 12-1 (12), the plurality of vias H exposing the remaining via sacrificial patterns 11B-1 except for a pair of via sacrificial patterns 11B-1 located at the outermost end and connected to the sacrificial pattern 11A-1. The via sacrificial pattern 11A-1 for the row lines and the via sacrificial pattern 11B-1 connected thereto can be covered by the interlayer dielectric layer 12-1.

[0074] Reference Figure 5C and Figure 6C A first conductive pattern 14-1 (14) can be formed in each of the multiple holes H. For example, after filling the multiple holes H with conductive material and covering the interlayer dielectric layer 12-1, the conductive material formed on the interlayer dielectric layer 12-1 can be removed by CMP (chemical mechanical polishing) process, so that the conductive material is retained only in the multiple holes H.

[0075] Reference Figure 5D and Figure 6D A sacrificial layer 11-2 (11) can be formed covering the first conductive pattern 14-1 and the interlayer dielectric layer 12-1. The sacrificial layer 11-2 can be configured with the same material (e.g., nitride) as the underlying sacrificial layer 11-1.

[0076] When the sacrificial layer 11-2 is patterned by photolithography, a sacrificial pattern 11A-2 (11A) for line lines and a plurality of sacrificial patterns 11B-2 (11B) for vias can be formed.

[0077] The sacrificial pattern 11A-2 for the running line may extend in the first direction FD and may have a protrusion PA on its side surface. The length of the sacrificial pattern 11A-2 for the running line in the first direction FD may be greater than the length of the sacrificial pattern 11A-1 for the running line in the first direction FD (see [link]). Figure 5A )short.

[0078] In addition to the protrusion PA, the sacrificial pattern 11A-2 for the running line may overlap with the sacrificial pattern 11A-1 for the running line in the vertical direction VD. The protrusion PA of the sacrificial pattern 11A-2 for the running line may be connected to at least one of the plurality of sacrificial patterns 11B-2 for the through hole. For example, the sacrificial pattern 11A-2 for the running line may have a pair of protrusions PA at its end in the first direction FD, and the protrusions PA of the sacrificial pattern 11A-2 for the running line may be connected to the pair of sacrificial patterns 11B-2 located at the outermost end in the first direction FD, respectively.

[0079] Reference Figure 5E and Figure 6E An interlayer dielectric layer 12-2(12) covering the sacrificial layer 11-2 can be formed on the interlayer dielectric layer 12-1(12). The interlayer dielectric layer 12-2 can be configured with the same material (e.g., oxide) as the underlying interlayer dielectric layer 12-1.

[0080] Multiple vias (not shown) can be formed in the interlayer dielectric layer 12-2, exposing sacrificial patterns 11B-2 for vias that are not connected to sacrificial patterns 11A-2 for line traces. For example, if the sacrificial patterns 11A-2 for line traces are connected to a pair of sacrificial patterns 11B-2 for vias located at the outermost ends in the first direction FD, multiple vias can be formed in the interlayer dielectric layer 12-2 (12) to expose the remaining sacrificial patterns 11B-2 for vias other than the pair of sacrificial patterns 11B-2 for vias located at the outermost ends in the first direction FD. The sacrificial patterns 11A-2 for line traces and the sacrificial patterns 11B-2 for vias connected thereto can be covered by the interlayer dielectric layer 12-2.

[0081] The first conductive pattern 14-2(14) can be formed in multiple holes respectively.

[0082] Reference Figure 5F and Figure 6F As the steps of forming the sacrificial layer 11, forming the interlayer dielectric layer 12 and forming the first conductive pattern 14 are repeated, multiple sacrificial layers 11-1 to 11-5 (11), multiple interlayer dielectric layers 12-1 to 12-4 (12) and multiple first conductive patterns 14-1 to 14-4 (14) can be stacked.

[0083] Reference Figure 7 The ends of the sacrificial patterns 11A-1 to 11A-5 used for the running lines, defined by the protrusion PA, can be set in a stepped structure in the first direction FD.

[0084] Vertical pillars I can be respectively connected to the protrusions PA of the sacrificial patterns 11A-1 to 11A-5 for the row lines. Vertical pillars I can extend from the top surface of the first substrate 10 in the vertical direction VD, and can each be connected to the side surface of the corresponding sacrificial pattern (one of 11A-1 to 11A-5) for the row lines. The top surface of each vertical pillar I can be disposed on the same plane as the top surface of the corresponding sacrificial pattern (one of 11A-1 to 11A-5) for the row lines.

[0085] In the vertical pillar I, the vertical pillar I connected to the sacrificial pattern 11A for the row lines stacked n times from the first substrate 10 can be configured by n sacrificial patterns 11B for through holes and n-1 first conductive patterns 14. For example, the vertical pillar I connected to the sacrificial pattern 11A-1 for the row lines located at the bottom layer (n=1) can be configured by one sacrificial pattern 11B for the through hole. Furthermore, the vertical pillar I connected to the sacrificial pattern 11A-2 (n=2) for the row lines stacked immediately above the sacrificial pattern 11A-1 for the row lines can be configured by two sacrificial patterns 11B for through holes and one first conductive pattern 14.

[0086] Subsequently, by replacing the sacrificial patterns 11A-1 to 11A-5 used for the row lines and the sacrificial patterns 11B-1 to 11B-5 used for the vias with conductive material, multiple row lines can be formed. Figure 2 RL) and multiple second conductive patterns ( Figure 2 16), such as Figure 2 As shown. (Referring to...) Figures 4 to 7 In the described embodiment, the ends of the sacrificial patterns 11A-1 to 11A-5 that share a common structure with the protrusion PA are shown to be provided in a stepped structure, but this disclosure is not limited thereto. Although not shown in the drawings, in another embodiment, the ends of the sacrificial patterns 11A-1 to 11A-5 may not be provided in a stepped structure.

[0087] In the following text, reference will be made to Figures 8 to 16C A three-dimensional memory device and a method for manufacturing the same according to another embodiment of the present disclosure are described below. In the following description, repeated descriptions of components identical to those described in the above embodiments will be omitted.

[0088] Figure 8 This is a perspective view illustrating a portion of a three-dimensional memory device according to another embodiment of the present disclosure, and Figure 9 This is an example Figure 8 An exploded 3D view of the lines, through holes, and connecting lines.

[0089] Reference Figure 8 and Figure 9A three-dimensional memory device according to an embodiment of the present disclosure may include: a plurality of row lines RL, which are alternately stacked with a plurality of interlayer dielectric layers 12 on a first substrate 10 in a vertical direction VD; a plurality of interconnect lines CL, which are respectively directly connected to the plurality of row lines RL; and a plurality of vias VIA, which extend from the first substrate 10 in the vertical direction VD. The plurality of vias VIA are respectively connected to protrusions of the plurality of interconnect lines CL extending beyond the side surfaces of the plurality of row lines RL. The plurality of vias VIA electrically connect the plurality of row lines RL and peripheral circuitry 200 defined below the first substrate 10.

[0090] For more details, see the above references. Figure 2 and Figure 3 As described, the three-dimensional memory device according to embodiments of the present disclosure may include a cell section (CELL) and a peripheral circuit section (PERI) disposed below the cell section (CELL).

[0091] The cell section may include a first substrate 10, multiple row lines RL, multiple vertical channels CH, multiple connecting lines CL, and multiple through holes VIA.

[0092] The line RL can extend at different lengths in the first direction FD, and the ends of the line RL can be set in a stepped structure in the first direction FD.

[0093] The interlayer dielectric layer 12 can be configured with oxide. For simplicity of illustration, Figure 8 The example illustrates that the interlayer dielectric layer 12 is formed only between adjacent row lines RL, but this disclosure is not limited thereto. In some embodiments, the interlayer dielectric layer 12 may be configured to fill the space between the row line RL and the via VIA, as well as to fill the space between adjacent via VIAs.

[0094] In some other embodiments, the interlayer dielectric layer 12 may be formed only between adjacent row lines RL. Slit dielectric layer (e.g., Figure 15F 40) can be set in the space between the line RL and the through hole VIA, and the support (e.g., Figure 15F 19) can be positioned in the space between adjacent through-holes VIA. Multiple supports ( Figure 15F 19) can be alternately set with multiple through holes VIA on the first direction FD.

[0095] The connecting line CL can correspond to multiple row lines RL respectively, and each can be directly connected to the end of the corresponding row line RL. Each connecting line CL can have a protrusion that extends beyond the side surface of the corresponding row line RL in the second direction SD.

[0096] Each via VIA can be configured to be adjacent to the end of the corresponding row line RL in the second direction SD. For example, a pair of via VIAs can be configured to be located on both sides of the end of the corresponding row line RL in the second direction SD. Although this embodiment illustrates a pair of via VIAs corresponding to one row line RL, this disclosure is not limited thereto. The number of via VIAs corresponding to one row line RL can be one.

[0097] The vias VIA can extend vertically in the direction VD from the top surface of the first substrate 10, and the top surface of each via VIA can be disposed on the same plane as the top surface of the corresponding row line RL. Each via VIA can be directly connected to the bottom surface of the protrusion of the corresponding connecting line CL, and can be connected to the corresponding row line RL through the connecting line CL.

[0098] Row lines RL, vias VIA, and connector lines CL can be formed at the same process step and can be configured from the same materials. For example, row lines RL, vias VIA, and connector lines CL can include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum).

[0099] Contact 30 may be defined below each via VIA, may pass through the first substrate 10 and the dielectric layer ILD, and may connect the via VIA and its corresponding bottom wiring UM. Each via VIA may be electrically connected to the peripheral circuit 200 through contact 30 and bottom wiring UM, and the corresponding row line RL may be electrically connected to the peripheral circuit 200.

[0100] Figure 10 This is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present disclosure. Figures 11A to 11H A perspective view illustrating a three-dimensional memory device according to another embodiment of the present disclosure is provided through process steps. Figures 12A to 12D It is along Figures 11A to 11D The cross-sectional view of line BB′, and Figure 13 This is an example Figure 11H A perspective view of the sacrificial layer of the three-dimensional memory device and the sacrificial pattern for the interconnects.

[0101] Reference Figures 10 to 13A method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure may include: step S1001: forming a sacrificial layer 11 on a first substrate 10, including a sacrificial pattern 11A for row lines and a plurality of sacrificial patterns 11B for vias; step S1002: forming an interlayer dielectric layer 12, the interlayer dielectric layer 12 covering the sacrificial patterns 11A for row lines and having a plurality of holes H exposing the plurality of sacrificial patterns 11B for vias; step S1003: alternatingly repeating step S1001 of forming the sacrificial layer 11 and forming the interlayer dielectric layer. Step S1002 of step 12: stacking multiple sacrificial layers 11 and multiple interlayer dielectric layers 12; Step S1004: forming a stepped structure that exposes corresponding portions of the sacrificial layers 11; Step S1005: forming multiple sacrificial patterns 18 for interconnecting lines corresponding to the sacrificial layers 11 on the stepped structure, wherein each sacrificial pattern for interconnecting lines is connected to a sacrificial pattern 11A for line traces and a sacrificial pattern 11B for vias of the corresponding sacrificial layers 11; and Step S1006: replacing the multiple sacrificial layers 11 and the multiple sacrificial patterns 18 for interconnecting lines with a conductive material.

[0102] For details, refer to Figure 11A and Figure 12A A sacrificial layer 11-1 (11) can be formed on the first substrate 10, and by patterning the sacrificial layer 11-1 via a photolithography process, a sacrificial pattern 11A-1 (11A) for row lines and a plurality of sacrificial patterns 11B-1 (11B) for vias can be formed. The sacrificial layer 11-1 can be configured with nitride.

[0103] The sacrificial pattern 11A-1 for the line can have a line shape extending in the first direction FD. A plurality of sacrificial patterns 11B-1 for the through holes can be arranged near the sacrificial pattern 11A-1 for the line in the first direction FD, which is the extension direction of the sacrificial pattern 11A-1 for the line.

[0104] Reference Figure 11B and Figure 12B An interlayer dielectric layer 12-1 (12) covering the sacrificial layer 11-1 can be formed on the first substrate 10. The interlayer dielectric layer 12-1 can be configured with a dielectric material that has etch selectivity relative to the sacrificial layer 11-1. For example, if the sacrificial layer 11-1 is configured with a nitride, the interlayer dielectric layer 12-1 can be configured with an oxide.

[0105] Multiple vias H can be formed in the interlayer dielectric layer 12-1 to expose multiple sacrificial patterns 11B-1 for vias. The interlayer dielectric layer 12-1 can be used to cover the sacrificial patterns 11A-1 for row lines.

[0106] Reference Figure 11C and Figure 12CA sacrificial layer 11-2 (11) can be formed to fill multiple pores H and cover the interlayer dielectric layer 12-1. The sacrificial layer 11-2 can be formed of the same material (e.g., nitride) as the underlying sacrificial layer 11-1.

[0107] By patterning the sacrificial layer 11-2 using a photolithography process, a sacrificial pattern 11A-2 (11A) for row lines and multiple sacrificial patterns 11B-2 (11B) for vias can be formed. In the photolithography process for patterning the sacrificial layer 11-2, a mask pattern with the same structure as the mask pattern used in the photolithography process for patterning the lower sacrificial layer 11-1 can be used. Therefore, the sacrificial pattern 11A-2 for row lines can have the same layout structure as the lower sacrificial pattern 11A-1 for row lines. The sacrificial pattern 11A-2 can be configured to overlap with the sacrificial pattern 11A-1 for row lines in the vertical direction VD. Furthermore, the multiple sacrificial patterns 11B-2 for vias can have the same layout structure as the multiple sacrificial patterns 11B-1 for vias in the lower layer, and can be configured to overlap with the multiple sacrificial patterns 11B-1 for vias in the vertical direction VD.

[0108] Reference Figure 11D and Figure 12D As the steps of forming the sacrificial layer 11 and forming the interlayer dielectric layer 12 are repeated alternately, multiple sacrificial layers 11-1 to 11-5 (11) and multiple interlayer dielectric layers 12-1 to 12-4 (12) can be stacked.

[0109] Reference Figure 11E After the interlayer dielectric layer 12-5 covering the sacrificial layer 11-5 is formed on the interlayer dielectric layer 12-4, a mask pattern PR can be formed on the interlayer dielectric layer 12-5. The mask pattern PR can expose a portion of the top surface of the interlayer dielectric layer 12-5.

[0110] A pad etching process can be performed by using a mask pattern PR as an etching mask to etch a portion of a stack comprising multiple sacrificial layers 11-1 to 11-5 (11) and multiple interlayer dielectric layers 12-1 to 12-5 (12). In the pad etching process, the stack can be etched to the depth exposing the sacrificial layers 11-5.

[0111] Reference Figure 11F A trimming process can be performed to reduce the area of ​​the mask pattern PR. By performing the trimming process, the area exposed by the mask pattern PR can be increased, and thus a portion of the top surface of the sacrificial layer 11-5 can be additionally exposed.

[0112] The trimming process can cause the sidewalls of the mask pattern PR to move horizontally a predetermined distance in the first direction FD. The horizontal movement distance of the sidewalls of the mask pattern PR can correspond to the above reference. Figure 8 The width of a step included in the described stepped structure in the first direction FD. For example, as a trimming process, an isotropic dry etching or wet etching method can be used. During the trimming process, as the entire surface of the mask pattern PR is etched, the top surface of the mask pattern PR can be recessed. That is, the area and thickness of the mask pattern PR can be reduced by the trimming process.

[0113] A pad etching process can be performed by using a modified mask pattern PR as an etching mask to etch a portion of the stack. In the pad etching process, the stack can be etched to the depth of the sacrificial layer 11-4.

[0114] The trimming process and the pad etching process can be performed alternately and repeatedly. The number of repetitions of the trimming process and the pad etching process can vary depending on the number of layers of the sacrificial layer 11. For example, when the number of layers of the sacrificial layer 11 is m (m is a natural number of 2 or greater), the number of repetitions can be m-1. This embodiment illustrates five stacked sacrificial layers 11, and in this case, the number of repetitions can be four.

[0115] like Figure 11G As shown, by repeatedly performing etching and finishing processes, a stepped structure can be formed that exposes the ends of the sacrificial layers 11-1 to 11-5.

[0116] The mask pattern PR can be configured using a photoresist. The mask pattern PR left after the formation of the stepped structure can be removed by a stripping process.

[0117] Reference Figure 11H Multiple sacrificial patterns 18 for connecting lines can be formed on the stepped structure.

[0118] Multiple sacrificial patterns 18 for connecting lines may correspond to multiple sacrificial layers 11-1 to 11-5 (11) (see) Figure 11G ), and each can be connected to its corresponding sacrifice layer 11 (see Figure 11G Sacrificial pattern 11A for the line (see) Figure 11G ) and sacrificial pattern 11B for through holes (see Figure 11G Each sacrificial pattern 18 used for connecting lines can be directly connected to the corresponding sacrificial pattern 11A used for row lines (see...). Figure 11G ) and the corresponding sacrificial pattern 11B for through holes (see Figure 11G The top surface of ).

[0119] Reference Figure 13The ends of the sacrificial patterns 11A-1 to 11A-5 used for the line can be set as a stepped structure in the first direction FD.

[0120] When viewed from above, the vertical pillars I′ can be respectively positioned in the second direction SD at positions adjacent to the ends of the sacrificial patterns 11A-1 to 11A-5 for the row lines. Each vertical pillar I′ can extend from the top surface of the first substrate 10 in the vertical direction VD, and the top surface of the vertical pillar I′ can be disposed on the same plane as the top surface of the corresponding sacrificial pattern (one of 11A-1 to 11A-5) for the row lines.

[0121] Each of the vertical pillars I′ can be configured as at least one sacrificial pattern 11B for through holes or more stacked sacrificial patterns 11B. The number of sacrificial patterns 11B for through holes can vary depending on the stacking position of the sacrificial patterns 11A for row lines corresponding to the vertical pillar I′. For example, if the sacrificial pattern 11A for row lines corresponding to the vertical pillar I′ is stacked k times (k is a natural number) from the first substrate 10, the number of stacked sacrificial patterns 11B for through holes configured in the vertical pillar I′ can be k.

[0122] By replacing the sacrificial patterns 11A-1 to 11A-5 (11A) for the row lines, the sacrificial patterns 11B-1 to 11B-5 (11B) for the vias, and the sacrificial pattern 18 for the connecting lines with conductive materials, multiple row lines RL, multiple vias VIA, and multiple connecting lines CL can be formed, such as Figure 8 As shown.

[0123] Figure 14 This is a flowchart illustrating a method for manufacturing a three-dimensional memory device according to yet another embodiment of the present disclosure. Figures 15A to 15G A perspective view illustrating a three-dimensional memory device according to another embodiment of the present disclosure is provided through process steps. Figures 16A to 16C It is along Figures 15A to 15C The cross-sectional view taken by line CC′.

[0124] Reference Figures 14 to 16CA method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure may include: step S1401: forming a sacrificial layer 11 on a first substrate 10; step S1402: forming an interlayer dielectric layer 12 covering a portion of the sacrificial layer 11 on the sacrificial layer 11; step S1403: stacking a plurality of sacrificial layers 11 and a plurality of interlayer dielectric layers 12 by alternately repeating the steps of forming the sacrificial layer 11 and forming the interlayer dielectric layer 12; step S1404: forming a plurality of supports 19 passing through the plurality of sacrificial layers 11 near the plurality of interlayer dielectric layers 12; step S1405: forming a plurality of supports 19 in the sacrificial layer 11... Step S1406: Forming a slit to separate the sacrificial pattern 11A for line traces and the plurality of sacrificial patterns 11B for vias included in each sacrificial layer 11; Step S1407: Forming a stepped structure that exposes a portion of each sacrificial layer 11; Step S1408: Forming a plurality of sacrificial patterns 18 for connecting lines corresponding to the sacrificial layer 11 on the stepped structure, the sacrificial patterns for connecting lines each connecting to the sacrificial pattern 11A for line traces and the sacrificial pattern 11B for vias of the corresponding sacrificial layer 11; and Step S1409: Replacing the sacrificial layer 11 and the sacrificial patterns 18 for connecting lines with a conductive material.

[0125] For details, refer to Figure 15A and Figure 16A A sacrificial layer 11-1 (11) can be formed on the first substrate 10, and an interlayer dielectric layer 12-1 (12) can be formed on a local area of ​​the sacrificial layer 11-1.

[0126] By alternately repeating the steps of forming the sacrificial layer 11 and forming the interlayer dielectric layer 12, multiple sacrificial layers 11-1 to 11-5 (11) and multiple interlayer dielectric layers 12-1 to 12-4 (12) can be stacked. The multiple interlayer dielectric layers 12-1 to 12-4 (12) can each have a line shape extending in the first direction FD and can be configured to overlap each other in the vertical direction VD.

[0127] The multiple sacrificial layers 11-1 to 11-5 (11) and the multiple interlayer dielectric layers 12-1 to 12-4 (12) can be configured with dielectric materials having different etch selectivity. For example, the multiple sacrificial layers 11-1 to 11-5 (11) can be configured with nitrides, and the multiple interlayer dielectric layers 12-1 to 12-4 (12) can be configured with oxides.

[0128] Reference Figure 15B and Figure 16BMultiple supports 19 can be formed on both sides of the multiple interlayer dielectric layers 12-1 to 12-4 (12) and pass through the multiple sacrificial layers 11-1 to 11-5 (11) in the vertical direction VD. When viewed from the top, the multiple supports 19 can be provided or arranged in a row on each side of the interlayer dielectric layers 12-1 to 12-4 (12) in a first direction FD, which is the extension direction of the multiple interlayer dielectric layers 12-1 to 12-4 (12).

[0129] The support 19 may be configured with a dielectric material whose etching selectivity differs from that of the sacrificial layers 11-1 to 11-5 (11). For example, if the sacrificial layers 11-1 to 11-5 (11) are configured with nitrides, the support 19 may be configured with oxides.

[0130] Reference Figure 15C and Figure 16C A slit can be formed on both sides of the support members 19 arranged in a row along the first direction, passing through a plurality of sacrificial layers 11-1 to 11-5 (11) in the vertical direction VD and extending in the first direction FD. Through the slit, each of the plurality of sacrificial layers 11-1 to 11-5 (11) can be divided into a sacrificial pattern 11A for line traces and a plurality of sacrificial patterns 11B for vias. The sacrificial patterns 11A-1 to 11A-5 (11A) for line traces can be alternated with a plurality of interlayer dielectric layers 12-1 to 12-4 (12) in the vertical direction VD, and the sacrificial pattern 11B for vias can be alternated with a plurality of support members 19 in the first direction FD.

[0131] The slit dielectric layer 40 can fill the slit. The slit dielectric layer 40 can be configured with a dielectric material whose etch selectivity is different from that of the plurality of sacrificial layers 11-1 to 11-5 (11). For example, if the plurality of sacrificial layers 11-1 to 11-5 (11) are configured with nitrides, the slit dielectric layer 40 can be configured with oxides.

[0132] Reference Figure 15D A mask pattern PR can be formed on the uppermost sacrificial layer 11-5, which exposes a portion of the top surface of the uppermost sacrificial layer 11-5.

[0133] A pad etching process can be performed to etch a portion of a structure comprising multiple sacrificial layers 11-1 to 11-5 (11), multiple interlayer dielectric layers 12-1 to 12-4 (12), a support 19, and a slot dielectric layer 40 by using a mask pattern PR as an etching mask. In the pad etching process, the structure can be etched to the depth exposing the sacrificial layers 11-4.

[0134] Reference Figure 15EA trimming process can be performed to reduce the area of ​​the mask pattern PR. This trimming process can increase the area exposed by the mask pattern PR.

[0135] The trimming process can cause the sidewalls of the mask pattern PR to move horizontally a predetermined distance in the first direction FD. The horizontal movement distance of the sidewalls of the mask pattern PR can correspond to the configuration of the above reference. Figure 8 The width of a step in the first direction FD of the described stepped structure.

[0136] A pad etching process can be performed by using a modified mask pattern PR as an etching mask to etch a portion of the structure. In the pad etching process, the structure can be etched to the depth of the sacrificial layer 11-3.

[0137] In turn, the trimming process and the pad etching process can be performed alternately and repeatedly. As the trimming process and the pad etching process are repeated, such as... Figure 15F As shown, a stepped structure can be formed that exposes the ends of the sacrificial layers 11-1 to 11-5.

[0138] The mask pattern PR can be configured using a photoresist. The mask pattern PR left after the formation of the stepped structure can be removed by a stripping process.

[0139] Reference Figure 15G Multiple sacrificial patterns 18 for connecting wires can be formed on the stepped structure. The sacrificial patterns 18 for connecting wires can correspond to sacrificial layers 11-1 to 11-5 (11) respectively (see...) Figure 15F ), and each can be connected to its corresponding sacrifice layer 11 (see Figure 15F Sacrificial pattern 11A for the line (see) Figure 15F ) and sacrificial pattern 11B for through holes (see Figure 15F The sacrificial pattern 18 used for connecting lines can be directly connected to the corresponding sacrificial layer 11 (see...). Figure 15F Sacrificial pattern 11A for the line (see) Figure 15F ) and sacrificial pattern 11B for through holes (see Figure 15F The top surface of ).

[0140] The sacrificial layers 11-1 to 11-5(11) formed by the above process (see also) Figure 15F The sacrificial pattern 18 for connecting lines can have, for example, Figure 13 The shape shown.

[0141] Subsequently, by replacing the sacrificial patterns 11A-1 to 11A-5 for the row lines, the sacrificial patterns 11B-1 to 11B-5 for the vias, and the sacrificial pattern 18 for the connecting lines with conductive material, multiple row lines RL, multiple vias VIA, and multiple connecting lines CL can be formed, such as... Figure 8 As shown.

[0142] Figure 17 This is a perspective view illustrating a three-dimensional memory device that differs from an embodiment of the present disclosure.

[0143] Reference Figure 17 Row lines RL can be connected to peripheral circuitry 200 via top wiring TM. In this case, if the number of row lines RL increases, the number of top wiring TM required to connect row lines RL and peripheral circuitry 200 increases, and the area occupied by top wiring TM increases, thereby increasing the size of the memory device.

[0144] In addition, since the row line RL is connected to the peripheral circuit 200 through the first through hole VIA1, the top wiring TM, the second through hole VIA2 and the bottom wiring UM, the length of the electrical path connecting the row line RL and the peripheral circuit 200 is increased. Therefore, the probability of functional error due to RC delay is high.

[0145] According to the embodiments of this disclosure described above, since top wiring is not used to connect the row line RL and the peripheral circuit 200, the number of top wirings can be reduced, thereby contributing to improved integration. Furthermore, the length of the electrical path connecting the row line RL and the peripheral circuit 200 can be shortened, thereby helping to reduce RC delay.

[0146] Return to reference Figure 17 To form the first via VIA1, a deep hole can be etched using a single etching process. In this case, due to the etching load, tilting may occur on the sidewalls of the hole, resulting in each first via VIA1 potentially having a downwardly decreasing dimension. When the depth of the first via VIA1 is deep, an open-circuit fault may occur, where the first via VIA1 is not connected to the row line RL.

[0147] Furthermore, in order to form the first via VIA1 connected to the row lines RL at different vertical positions, multiple holes of different depths should be formed by etching. If the etching cannot be precisely controlled, a short circuit fault may occur where one of the first vias VIA1 is connected to at least two row lines RL, or an open circuit fault may occur where the first via VIA1 is not connected to any row line RL.

[0148] According to embodiments of this disclosure, vias can be formed by stacking sacrificial patterns for vias and replacing the stacked sacrificial patterns for vias with conductive material. Therefore, individual vias can be formed with uniform dimensions, and this helps reduce open-circuit faults in the vias. Furthermore, since the vias are not connected to the row lines, the aforementioned short-circuit or open-circuit faults can be prevented.

[0149] Figure 18 This is a block diagram illustrating a memory system including a three-dimensional memory device according to an embodiment of the present disclosure.

[0150] Reference Figure 18 The memory system 600 according to the embodiment may include a non-volatile memory device (NVM device) 610 and a memory controller 620.

[0151] The non-volatile memory device 610 can be constructed from the aforementioned semiconductor memory device and can operate in the manner described above. The memory controller 620 can be configured to control the non-volatile memory device (NVM device) 610. The combination of the non-volatile memory device (NVM device) 610 and the memory controller 620 can provide a memory card or a solid-state drive (SSD). SRAM 621 is used as the working memory of the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol for a host connected to the memory system 600.

[0152] Error correction code block (ECC) 624 detects and corrects errors included in data read from non-volatile memory device 610.

[0153] The memory interface (memory I / F) 625 is interfaced with the non-volatile memory device 610 of this embodiment. The processing unit 622 performs general control operations for data exchange with the memory controller 620.

[0154] Although not shown in the accompanying drawings, it will be apparent to those skilled in the art that the memory system 600 according to the embodiment may additionally include a ROM storing code data for interfacing with a host. The non-volatile memory device (NVM device) 610 may be configured as a multi-chip package comprising multiple flash memory chips.

[0155] As described above, the memory system 600 according to the embodiment can be configured as a highly reliable storage medium with a low probability of error. Specifically, the non-volatile memory device of this embodiment can be included in a memory system such as a solid-state drive (SSD), which is currently under active research. In this case, the memory controller 620 can be configured to communicate with an external (e.g., a host) via one of various interface protocols such as USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI-E (Rapid Peripheral Component Interconnect) protocol, SATA (Serial Advanced Technology Attached) protocol, PATA (Parallel Advanced Technology Attached) protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Data Center Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

[0156] Figure 19 This is a block diagram illustrating a computing system including a three-dimensional memory device according to an embodiment of the present disclosure.

[0157] Reference Figure 19 The computing system 700 according to an embodiment may include a memory system 710, a microprocessor (CPU) 720, RAM 730, a user interface 740, and a modem 750 (such as a baseband chipset) electrically connected to a system bus 760. In the case where the computing system 700 according to an embodiment is a mobile device, a battery (not shown) may be additionally provided to supply the operating voltage of the computing system 700. Although not shown in the figures, it will be apparent to those skilled in the art that the computing system 700 according to this embodiment may additionally include an application chipset, a camera image processor (CIS), mobile DRAM, etc. The memory system 710 may be configured, for example, to use a non-volatile memory to store data, such as an SSD (solid-state drive / disk). Alternatively, the memory system 710 may be configured as a converged flash memory (e.g., OneNAND flash memory).

[0158] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in a descriptive sense only and not as limiting the scope of the technology. The scope of this disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted by the appended claims, and the spirit and scope of this disclosure cover all equivalent forms falling within the scope of the appended claims.

[0159] Cross-references to related applications

[0160] This application claims priority to Korean Patent Application No. 10-2020-0161361, filed with the Korean Intellectual Property Office on November 26, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: Multiple rows of lines are alternately stacked on a substrate in a vertical direction with multiple interlayer dielectric layers, each of the multiple rows of lines having a protrusion protruding from its side surface; as well as A plurality of through-holes extend from the substrate in the vertical direction, each of the through-holes connecting to a protrusion of a corresponding row line, and the plurality of through-holes electrically connecting the plurality of row lines to a peripheral circuit defined below the substrate. Among these, the vias connected to the corresponding row lines of the nth stacked layer from the substrate include n-1 first conductive patterns and n second conductive patterns, where n is a natural number of 1 or greater. Each of the n-1 first conductive patterns is positioned at the same vertical position as the corresponding interlayer dielectric layer in the plurality of interlayer dielectric layers, and each of the n second conductive patterns is positioned at the same vertical position as the corresponding row line in the plurality of row lines.

2. The three-dimensional memory device according to claim 1, wherein, Each of the plurality of through holes is directly connected to the side surface of the protrusion of the corresponding row.

3. The three-dimensional memory device according to claim 1, in, The protruding portions are respectively disposed at the end of each of the plurality of rows in a first direction, and extend from the side surface in a second direction intersecting the first direction, the first direction and the second direction being parallel to the top surface of the substrate.

4. The three-dimensional memory device according to claim 3, in, The ends of the multiple rows that are common to the protrusion are arranged in a stepped structure in the first direction.

5. The three-dimensional memory device according to claim 3, wherein, The top surface of each of the plurality of through holes is disposed on the same plane as the top surface of the corresponding row line in the plurality of row lines.

6. The three-dimensional memory device according to claim 1, wherein, The n second conductive patterns are made of the same conductive material as the multiple row lines.

7. A method for manufacturing a three-dimensional memory device, the method comprising the following steps: A sacrificial layer is formed on a substrate. The sacrificial layer includes a plurality of sacrificial patterns for vias and a sacrificial pattern for lines. The sacrificial pattern for lines has a protrusion that connects to a corresponding sacrificial pattern for a via among the plurality of sacrificial patterns for vias. An interlayer dielectric layer is formed, which covers the sacrificial pattern for the row lines and the sacrificial pattern for the via connected to the sacrificial pattern for the row lines, and has a plurality of holes that expose the sacrificial pattern for the via that is not connected to the sacrificial pattern for the row lines. Multiple first conductive patterns are formed in the plurality of holes; The sacrificial layer, the interlayer dielectric layer, and the plurality of first conductive patterns are repeatedly formed to stack a plurality of sacrificial layers, a plurality of interlayer dielectric layers, and a plurality of first conductive patterns on the substrate. as well as Replace the plurality of sacrificial layers with a conductive material. During the formation of the sacrificial layer, The plurality of sacrificial patterns for through holes are formed to be arranged in a first direction, which is the extending direction of the sacrificial patterns for line lines, and The protrusion of the sacrificial pattern for the line is formed to be connected to the outermost sacrificial pattern for the through hole in the first direction among the plurality of sacrificial patterns for the through hole.

8. The method according to claim 7, wherein, The plurality of sacrificial layers are configured with dielectric materials that have etch selectivity relative to the plurality of interlayer dielectric layers.

9. A three-dimensional memory device, the three-dimensional memory device comprising: Multiple row lines are alternately stacked on a substrate in a vertical direction with multiple interlayer dielectric layers and extend in a first direction. The ends of the multiple row lines are configured with a stepped structure in the first direction. Multiple connecting lines extend in a second direction intersecting the first direction, respectively contacting the top surface of the ends of the multiple lines, and each having a protrusion that protrudes beyond the side surface of the multiple lines in the second direction, wherein the first direction and the second direction are parallel to the top surface of the substrate. Multiple through holes extend from the substrate in the vertical direction and are respectively connected to the protrusions of the multiple connecting lines, and electrically connect the multiple lines to the peripheral circuitry defined below the substrate. A slit dielectric layer extending in the first direction and disposed between the plurality of row lines and the plurality of vias; as well as Multiple support members are alternately arranged with the multiple through holes in the first direction.

10. The three-dimensional memory device according to claim 9, wherein, The top surface of each of the plurality of through holes is disposed on the same plane as the top surface of the corresponding row line in the plurality of row lines.

11. The three-dimensional memory device according to claim 9, wherein, The plurality of interlayer dielectric layers fill the space between the plurality of row lines and the plurality of vias, and also fill the space between the plurality of vias.

12. The three-dimensional memory device according to claim 9, in, The slit dielectric layer is configured with a dielectric material whose etch selectivity differs from that of the multiple sacrificial layers.

13. The three-dimensional memory device according to claim 9, wherein, The plurality of supports are configured with dielectric materials having different etching selectivity than the plurality of sacrificial layers.

14. The three-dimensional memory device according to claim 9, wherein, The plurality of through holes are made of the same material as the plurality of rows.

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